File logging started to /mnt/config/bcm_dump.txt
>/usr/bin/bcmcmd version
Broadcom Command Monitor: Copyright (c) 1998-2022 Broadcom
Release: sdk-6.5.22 built 20220312 (Sat Mar 12 22:51:31 2022)
From autouser@ip-10-78-122-9.ec2.internal:/localdisk/yocto/builds-0/valimar/cn-container-hal-dnx-docker-aarch64/tmp/work/aarch64-evernight-linux/bcm-sdk-all/1.0.0+gitAUTOINC+16dfff56fb-r0/git
Platform: unknown
OS: Unix (Posix)
Chips:
      
      
      
      
      
       BCM88660_A0, BCM88675_A0,
       BCM88790_A0,
      
      
      
       BCM88375_A0, BCM88470_A0,
       BCM88470_B0, BCM88270_A0, BCM88675_B0, BCM88375_B0,
       BCM88680_A0, BCM88690_A0, BCM88690_B0, BCM88800_A0,
       BCM88850_A0, BCM88480_A0, BCM88480_B0,
      
      
      
      
      
PHYs: 
>/usr/bin/bcmcmd show unit
Unit 0 chip BCM88483_B1 (current)
>/usr/bin/bcmcmd show patches
Current version installed: sdk-6.5.22
===============================================================================
|                           Patches installed info                            |
===============================================================================
| Patch ID | Patch String                                                     |
===============================================================================
| 1        | AE Patch SDK-210372 L2 show fix(wrong encap_id) CS00012183982    |
-------------------------------------------------------------------------------
| 2        | AE Patch L2 show/traverse fix  CS00012183982                     |
-------------------------------------------------------------------------------
| 3        | SDK-252734 - MACT flush FIFO DMA check reply FIFO CS00012188266  |
-------------------------------------------------------------------------------
| 4        | SDK-261287 L2 traverse issues duplicate|wrong entries CS00012192 |
-------------------------------------------------------------------------------
| 5        | SDK-263455 soc_ndev_attached in soc_dnx_attach/detach CS00012196 |
-------------------------------------------------------------------------------
| 6        | SDK-251899 - Add new Incoming Tag Structure of type S-Priority T |
-------------------------------------------------------------------------------
| 7        | SDK-251390 add support for GDDR6 16GB from Micron - CS0001220379 |
-------------------------------------------------------------------------------
| 8        | SDK-251401 Support configurable FlexE OH/OAM packet MAC - CS0001 |
-------------------------------------------------------------------------------
| 11       | SDK-270618 fix Dt2PMF1 result signal - CS00012208540             |
-------------------------------------------------------------------------------
| 12       | SDK-279322 fixes j2p etpp latency - CS00012216194                |
-------------------------------------------------------------------------------
| 13       | SDK-244638 SDK-252242 Skip CDMAC access - CS00012228949          |
-------------------------------------------------------------------------------
| 14       | SDK-257969 fix bcm_dnx_mpls_tunnel_initiator_clear - CS000122300 |
===============================================================================
>/usr/bin/bcmcmd show pvt
============================================================
|                                    PVT                   |
============================================================
| Monitor | Current Temperature (C) | Peak Temperature (C) |
============================================================
| 0       |                    34.4 |                 35.4 |
| 1       |                    30.1 |                 30.1 |
| 2       |                    29.6 |                 30.6 |
| 3       |                    32.2 |                 32.8 |
============================================================
>/usr/bin/bcmcmd show volt
Command:"volt" is not supported for current device and/or configuration
>/usr/bin/bcmcmd show int
======================================================================================================
|                                                        Interrupt                                   |
======================================================================================================
| Interrupt Name#                                               | ID   | UnMask(Enable) | On | Count |
======================================================================================================
| SPB_REASSEMBLY_ReassemblyErrorGeneralMop[0]                   | 102  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesHeaderSizeErrInt[0]                            | 145  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesQualifierSizeErrInt2[0]                        | 152  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesQualifierSizeErrInt3[0]                        | 153  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesQualifierSizeErrInt4[0]                        | 154  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_SrcEqualDestInt[0]                          | 190  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesHeaderSizeErrInt[0]                    | 235  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt2[0]                | 249  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt3[0]                | 250  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt4[0]                | 251  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt5[0]                | 252  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_DiscardInt[0]                             | 255  | 0              | 1  | 0     |
| TCAM_TcamQueryFailureValid[0]                                 | 322  | 0              | 1  | 0     |
| IPPE_QualifierSizeError2[0]                                   | 430  | 0              | 1  | 0     |
| IPPE_QualifierSizeError7[0]                                   | 435  | 0              | 1  | 0     |
| IPPE_QualifierSizeError8[0]                                   | 436  | 0              | 1  | 0     |
| IPPE_QualifierSizeError9[0]                                   | 437  | 0              | 1  | 0     |
| IPPE_QualifierSizeError10[0]                                  | 438  | 0              | 1  | 0     |
| IPPE_QualifierSizeError11[0]                                  | 439  | 0              | 1  | 0     |
| CDU_TxFifoOverflowInt[0]                                      | 453  | 0              | 1  | 0     |
| CDU_TxFifoOverflowInt[1]                                      | 453  | 0              | 1  | 0     |
| SCH_SmpFullLevel1[0]                                          | 657  | 0              | 1  | 0     |
| ETPPB_ETPPB_PortMtuTrapInt[0]                                 | 679  | 0              | 1  | 0     |
| ETPPB_BTC_PopBeforeFifoReady[0]                               | 691  | 0              | 1  | 0     |
| IRE_NIF_ERROR_NifErrDataArrived[0]                            | 914  | 0              | 1  | 0     |
| IPPD_SameInteraceInt[0]                                       | 987  | 0              | 1  | 0     |
| ECGM_DroppedUcPdInt[0]                                        | 1038 | 0              | 1  | 0     |
| CRPS_DMA_0_FULLNESS_Dma0NotEmptyEvent[0]                      | 1186 | 0              | 1  | 0     |
| CRPS_DMA_1_FULLNESS_Dma1NotEmptyEvent[0]                      | 1189 | 0              | 1  | 0     |
| CLU_TxFifoOverflowInt[0]                                      | 1303 | 0              | 1  | 0     |
| CLU_TxFifoOverflowInt[1]                                      | 1303 | 0              | 1  | 0     |
| CLU_TxFifoOverflowInt[2]                                      | 1303 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_0[0] | 1313 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_1[0] | 1314 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_4[0] | 1317 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_5[0] | 1318 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_7[2] | 1320 | 0              | 1  | 0     |
| MDB_Lem_EmpPulseScanDone[0]                                   | 1434 | 0              | 1  | 0     |
======================================================================================================
>/usr/bin/bcmcmd soc
==========================================================
|                         Device General Info            |
|   UNIT 0 Driver Control Structure                      |
==========================================================
| Chip        | Rev  | Driver      | Family | Board type |
==========================================================
| BCM88483_B1 | 0x12 | BCM88480_B0 | q2a    | 0x0        |
==========================================================
========================
| Device Status        |
========================
| Flags = 0x40207      |
========================
| attached             |
------------------------
| initialized          |
------------------------
| link-scan            |
========================
===============================================================================
|                           Device Additional Info                            |
===============================================================================
| Feature  | Values                                                           |
===============================================================================
| CM       | Base=0x7f04ae7000                                                |
-------------------------------------------------------------------------------
| Disabled | reg_flags=0x0 mem_flags=0x0                                      |
-------------------------------------------------------------------------------
| Debug    | SchanOps=-597838116                                              |
-------------------------------------------------------------------------------
| Counter  | int=1000000us                                                    |
-------------------------------------------------------------------------------
| Timeout  | Schan=300000us MIIM=0(300000us)                                  |
-------------------------------------------------------------------------------
| Intr     | Total=919592706 Sc=0 ScErr=0 MMU/ARLErr=0                        |
-------------------------------------------------------------------------------
| PCI      | LinkStat=0 PCIfatal=0 PCIparity=0                                |
-------------------------------------------------------------------------------
| ARL      | ARLdrop=0 ARLmbuf=0 ARLxfer=0 ARLcnt0=0                          |
-------------------------------------------------------------------------------
| DMA      | TableDMA=0 TSLAM-DMA=186                                         |
-------------------------------------------------------------------------------
| Mem      | TMemCmd[BSE]=0 MemCmd[CSE]=0 MemCmd[HSE]=0                       |
-------------------------------------------------------------------------------
| ChipFunc | ChipFunc[0]=0 ChipFunc[1]=0 ChipFunc[2]=0 ChipFunc[3]=0          |
|          | ChipFunc[4]=0                                                    |
-------------------------------------------------------------------------------
| I2C      | I2C=0 MII=0 StatsDMA=0 Desc=928199580 Chain=469998412            |
===============================================================================
>/usr/bin/bcmcmd d chg soc
BDM_BDB_CONFIG.BDM0[0x104]=0x1001
BDM_BDB_STATUS.BDM0[0x105]=0
BDM_BD_DATA_DEBUG.BDM0[0x10d]=0
BDM_ECC_1B_ERR_CNT.BDM0[0x94]=0
BDM_ECC_2B_ERR_CNT.BDM0[0x96]=0
BDM_ECC_ERR_1B_MONITOR_MEM_MASK.BDM0[0x9a]=0xfff
BDM_ECC_ERR_2B_MONITOR_MEM_MASK.BDM0[0x9c]=0xfff
BDM_ECC_INTERRUPT_REGISTER.BDM0[0x7]=0
BDM_ECC_INTERRUPT_REGISTER_MASK.BDM0[0x17]=0
BDM_ECC_INTERRUPT_REGISTER_TEST.BDM0[0x1f]=0
BDM_FPC_CONFIG.BDM0[0x106]=0
BDM_FPC_CONTROL(0).BDM0[0x112]=0xfffc000
BDM_FPC_CONTROL(1).BDM0[0x113]=0xfffc000
BDM_FPC_CONTROL(2).BDM0[0x114]=0xfffc000
BDM_FPC_CONTROL(3).BDM0[0x115]=0xfffc000
BDM_FPC_DELETE.BDM0[0x111]=0
BDM_FPC_MODULE_STATUS(0).BDM0[0x116]=0x1ffe3ffc7ff8
BDM_FPC_MODULE_STATUS(1).BDM0[0x117]=0x1ffe3ffc7ff8
BDM_FPC_MODULE_STATUS(2).BDM0[0x118]=0x1ffe3ffc7ff8
BDM_FPC_MODULE_STATUS(3).BDM0[0x119]=0x1ffebffd7ffa
BDM_FPC_STATUS.BDM0[0x107]=0x150803ffc5ffe2fff1
BDM_GTIMER_CONFIGURATION.BDM0[0x89]=0
BDM_GTIMER_CYCLE.BDM0[0x88]=0x3b9aca00
BDM_INTERRUPT_MASK_REGISTER.BDM0[0x10]=0
BDM_INTERRUPT_REGISTER.BDM0[0x0]=0
BDM_INTERRUPT_REGISTER_TEST.BDM0[0x18]=0
BDM_PCMI_0.BDM0[0xb0]=0x3b9aca00
BDM_PCMI_1.BDM0[0xb3]=0x3b9aca00
BDM_PCMI_2.BDM0[0xb6]=0x3b9aca00
BDM_PCMI_3.BDM0[0xb9]=0x3b9aca00
BDM_PCMI_4.BDM0[0xbc]=0x3b9aca00
BDM_PCMI_0_S.BDM0[0xb1]=0
BDM_PCMI_0_T.BDM0[0xb2]=0
BDM_PCMI_1_S.BDM0[0xb4]=0
BDM_PCMI_1_T.BDM0[0xb5]=0
BDM_PCMI_2_S.BDM0[0xb7]=0
BDM_PCMI_2_T.BDM0[0xb8]=0
BDM_PCMI_3_S.BDM0[0xba]=0
BDM_PCMI_3_T.BDM0[0xbb]=0
BDM_PCMI_4_S.BDM0[0xbd]=0
BDM_PCMI_4_T.BDM0[0xbe]=0
BDM_REG_00C2.BDM0[0xc2]=0x10
BDM_RESERVED_MTCD.BDM0[0xae]=0x30
BDM_RESERVED_MTCP.BDM0[0xad]=0x300000600000000
BDM_RESERVED_SPARE_0.BDM0[0x90]=0xffffffff
BDM_RESERVED_SPARE_1.BDM0[0x91]=0xffffffff
BDM_RESERVED_SPARE_2.BDM0[0x92]=0
BDM_RESERVED_SPARE_3.BDM0[0x93]=0
BDM_SBUS_BROADCAST_ID.BDM0[0x86]=0x7ff
BDM_SBUS_LAST_IN_CHAIN.BDM0[0x87]=0
BDM_SPECIAL_CLOCK_CONTROLS.BDM0[0xc1]=2
CDMAC_CLOCK_CTRL.CDMAC0[0x6010600]=0
CDMAC_CLOCK_CTRL.CDMAC1[0x6010600]=0
CDMAC_CTRL.eth33[0x4010c00]=0x5041
CDMAC_CTRL.eth34[0x4010c00]=0x5041
CDMAC_CTRL.eth35[0x4010c00]=0x5041
CDMAC_CTRL.eth36[0x4010c00]=0x5041
CDMAC_ECC_CTRL.CDMAC0[0x6010300]=9
CDMAC_ECC_CTRL.CDMAC1[0x6010300]=9
CDMAC_ECC_STATUS.CDMAC0[0x6010400]=0
CDMAC_ECC_STATUS.CDMAC1[0x6010400]=0
CDMAC_FIFO_STATUS.eth33[0x4011b00]=4
CDMAC_FIFO_STATUS.eth34[0x4011b00]=4
CDMAC_FIFO_STATUS.eth35[0x4011b00]=4
CDMAC_FIFO_STATUS.eth36[0x4011b00]=4
CDMAC_INTR_ENABLE.eth33[0x4011e00]=0
CDMAC_INTR_ENABLE.eth34[0x4011e00]=0
CDMAC_INTR_ENABLE.eth35[0x4011e00]=0
CDMAC_INTR_ENABLE.eth36[0x4011e00]=0
CDMAC_INTR_STATUS.eth33[0x4011f00]=4
CDMAC_INTR_STATUS.eth34[0x4011f00]=4
CDMAC_INTR_STATUS.eth35[0x4011f00]=4
CDMAC_INTR_STATUS.eth36[0x4011f00]=4
CDMAC_LAG_FAILOVER_STATUS.eth33[0x4011c00]=0
CDMAC_LAG_FAILOVER_STATUS.eth34[0x4011c00]=0
CDMAC_LAG_FAILOVER_STATUS.eth35[0x4011c00]=0
CDMAC_LAG_FAILOVER_STATUS.eth36[0x4011c00]=0
CDMAC_LINK_INTR_CTRL.CDMAC0[0x6010100]=0
CDMAC_LINK_INTR_CTRL.CDMAC1[0x6010100]=0
CDMAC_LINK_INTR_STATUS.CDMAC0[0x6010200]=0
CDMAC_LINK_INTR_STATUS.CDMAC1[0x6010200]=0
CDMAC_MEM_CTRL.CDMAC0[0x6010500]=0
CDMAC_MEM_CTRL.CDMAC1[0x6010500]=0
CDMAC_MIB_COUNTER_CTRL.eth33[0x4012100]=0x17b9
CDMAC_MIB_COUNTER_CTRL.eth34[0x4012100]=0x17b9
CDMAC_MIB_COUNTER_CTRL.eth35[0x4012100]=0x17b9
CDMAC_MIB_COUNTER_CTRL.eth36[0x4012100]=0x17b9
CDMAC_MIB_COUNTER_MODE.CDMAC0[0x6010b00]=0
CDMAC_MIB_COUNTER_MODE.CDMAC1[0x6010b00]=0
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR0.CDMAC0[0x6010700]=0x4f0040
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR0.CDMAC1[0x6010700]=0x4f0040
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR1.CDMAC0[0x6010800]=0x5f0050
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR1.CDMAC1[0x6010800]=0x5f0050
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR2.CDMAC0[0x6010900]=0x6f0060
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR2.CDMAC1[0x6010900]=0x6f0060
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR3.CDMAC0[0x6010a00]=0x7f0070
CDMAC_MIB_COUNTER_PROG_RANGE_CNTR3.CDMAC1[0x6010a00]=0x7f0070
CDMAC_MODE.eth33[0x4010d00]=0
CDMAC_MODE.eth34[0x4010d00]=0
CDMAC_MODE.eth35[0x4010d00]=0
CDMAC_MODE.eth36[0x4010d00]=0
CDMAC_PAUSE_CTRL.eth33[0x4011600]=0xffff3c000
CDMAC_PAUSE_CTRL.eth34[0x4011600]=0xffff3c000
CDMAC_PAUSE_CTRL.eth35[0x4011600]=0xffff3c000
CDMAC_PAUSE_CTRL.eth36[0x4011600]=0xffff3c000
CDMAC_PFC_CTRL.eth33[0x4011700]=2
CDMAC_PFC_CTRL.eth34[0x4011700]=2
CDMAC_PFC_CTRL.eth35[0x4011700]=2
CDMAC_PFC_CTRL.eth36[0x4011700]=2
CDMAC_PFC_DA.eth33[0x4011a00]=0x180c2000001
CDMAC_PFC_DA.eth34[0x4011a00]=0x180c2000001
CDMAC_PFC_DA.eth35[0x4011a00]=0x180c2000001
CDMAC_PFC_DA.eth36[0x4011a00]=0x180c2000001
CDMAC_PFC_OPCODE.eth33[0x4011900]=0x101
CDMAC_PFC_OPCODE.eth34[0x4011900]=0x101
CDMAC_PFC_OPCODE.eth35[0x4011900]=0x101
CDMAC_PFC_OPCODE.eth36[0x4011900]=0x101
CDMAC_PFC_TYPE.eth33[0x4011800]=0x8808
CDMAC_PFC_TYPE.eth34[0x4011800]=0x8808
CDMAC_PFC_TYPE.eth35[0x4011800]=0x8808
CDMAC_PFC_TYPE.eth36[0x4011800]=0x8808
CDMAC_RSV_MASK.eth33[0x4012000]=0x20858
CDMAC_RSV_MASK.eth34[0x4012000]=0x20858
CDMAC_RSV_MASK.eth35[0x4012000]=0x20858
CDMAC_RSV_MASK.eth36[0x4012000]=0x20858
CDMAC_RX_CTRL.eth33[0x4011000]=0x40c
CDMAC_RX_CTRL.eth34[0x4011000]=0x40c
CDMAC_RX_CTRL.eth35[0x4011000]=0x40c
CDMAC_RX_CTRL.eth36[0x4011000]=0x40c
CDMAC_RX_LSS_CTRL.eth33[0x4011400]=0x30
CDMAC_RX_LSS_CTRL.eth34[0x4011400]=0x30
CDMAC_RX_LSS_CTRL.eth35[0x4011400]=0x30
CDMAC_RX_LSS_CTRL.eth36[0x4011400]=0x30
CDMAC_RX_LSS_STATUS.eth33[0x4011500]=9
CDMAC_RX_LSS_STATUS.eth34[0x4011500]=9
CDMAC_RX_LSS_STATUS.eth35[0x4011500]=9
CDMAC_RX_LSS_STATUS.eth36[0x4011500]=9
CDMAC_RX_MAC_SA.eth33[0x4011100]=0
CDMAC_RX_MAC_SA.eth34[0x4011100]=0
CDMAC_RX_MAC_SA.eth35[0x4011100]=0
CDMAC_RX_MAC_SA.eth36[0x4011100]=0
CDMAC_RX_MAX_SIZE.eth33[0x4011200]=0x5f2
CDMAC_RX_MAX_SIZE.eth34[0x4011200]=0x5f2
CDMAC_RX_MAX_SIZE.eth35[0x4011200]=0x5f2
CDMAC_RX_MAX_SIZE.eth36[0x4011200]=0x5f2
CDMAC_RX_VLAN_TAG.eth33[0x4011300]=0x381008100
CDMAC_RX_VLAN_TAG.eth34[0x4011300]=0x381008100
CDMAC_RX_VLAN_TAG.eth35[0x4011300]=0x381008100
CDMAC_RX_VLAN_TAG.eth36[0x4011300]=0x381008100
CDMAC_SPARE.eth33[0x4012200]=0
CDMAC_SPARE.eth34[0x4012200]=0
CDMAC_SPARE.eth35[0x4012200]=0
CDMAC_SPARE.eth36[0x4012200]=0
CDMAC_TXFIFO_STATUS.eth33[0x4011d00]=0
CDMAC_TXFIFO_STATUS.eth34[0x4011d00]=0
CDMAC_TXFIFO_STATUS.eth35[0x4011d00]=0
CDMAC_TXFIFO_STATUS.eth36[0x4011d00]=0
CDMAC_TX_CTRL.eth33[0x4010e00]=0x18c81b
CDMAC_TX_CTRL.eth34[0x4010e00]=0x18c81b
CDMAC_TX_CTRL.eth35[0x4010e00]=0x18c81b
CDMAC_TX_CTRL.eth36[0x4010e00]=0x18c81b
CDMAC_TX_MAC_SA.eth33[0x4010f00]=0
CDMAC_TX_MAC_SA.eth34[0x4010f00]=0
CDMAC_TX_MAC_SA.eth35[0x4010f00]=0
CDMAC_TX_MAC_SA.eth36[0x4010f00]=0
CDMAC_VERSION_ID.CDMAC0[0x6010000]=0x8000a011
CDMAC_VERSION_ID.CDMAC1[0x6010000]=0x8000a011
CDPORT_FAULT_LINK_STATUS.eth33[0x100]=3
CDPORT_FAULT_LINK_STATUS.eth34[0x100]=3
CDPORT_FAULT_LINK_STATUS.eth35[0x100]=3
CDPORT_FAULT_LINK_STATUS.eth36[0x100]=3
CDPORT_FLOW_CONTROL_CONFIG.eth33[0x300]=0
CDPORT_FLOW_CONTROL_CONFIG.eth34[0x300]=0
CDPORT_FLOW_CONTROL_CONFIG.eth35[0x300]=0
CDPORT_FLOW_CONTROL_CONFIG.eth36[0x300]=0
CDPORT_GENERAL_SPARE0_REG.CDPORT0[0x2001a00]=0
CDPORT_GENERAL_SPARE0_REG.CDPORT1[0x2001a00]=0
CDPORT_GENERAL_SPARE1_REG.CDPORT0[0x2001b00]=0
CDPORT_GENERAL_SPARE1_REG.CDPORT1[0x2001b00]=0
CDPORT_GENERAL_SPARE2_REG.CDPORT0[0x2001c00]=0
CDPORT_GENERAL_SPARE2_REG.CDPORT1[0x2001c00]=0
CDPORT_GENERAL_SPARE3_REG.CDPORT0[0x2001d00]=0
CDPORT_GENERAL_SPARE3_REG.CDPORT1[0x2001d00]=0
CDPORT_INTR_ENABLE.CDPORT0[0x2001800]=0
CDPORT_INTR_ENABLE.CDPORT1[0x2001800]=0
CDPORT_INTR_STATUS.CDPORT0[0x2001700]=0
CDPORT_INTR_STATUS.CDPORT1[0x2001700]=0
CDPORT_LAG_FAILOVER_CONFIG.eth33[0x0]=0
CDPORT_LAG_FAILOVER_CONFIG.eth34[0x0]=0
CDPORT_LAG_FAILOVER_CONFIG.eth35[0x0]=0
CDPORT_LAG_FAILOVER_CONFIG.eth36[0x0]=0
CDPORT_LED_CONTROL.eth33[0x400]=0
CDPORT_LED_CONTROL.eth34[0x400]=0
CDPORT_LED_CONTROL.eth35[0x400]=0
CDPORT_LED_CONTROL.eth36[0x400]=0
CDPORT_LINKSTATUS_DOWN.CDPORT0[0x2001600]=0
CDPORT_LINKSTATUS_DOWN.CDPORT1[0x2001600]=0
CDPORT_MAC_CONTROL.CDPORT0[0x2000a00]=0
CDPORT_MAC_CONTROL.CDPORT1[0x2000a00]=0
CDPORT_MODE_REG.CDPORT0[0x2000900]=0x24
CDPORT_MODE_REG.CDPORT1[0x2000900]=0x24
CDPORT_PM_VERSION_ID.CDPORT0[0x2001e00]=0x18
CDPORT_PM_VERSION_ID.CDPORT1[0x2001e00]=0x18
CDPORT_SBUS_CONTROL.CDPORT0[0x2001900]=0x7f
CDPORT_SBUS_CONTROL.CDPORT1[0x2001900]=0x7f
CDPORT_SPARE0_REG.eth33[0x500]=0
CDPORT_SPARE0_REG.eth34[0x500]=0
CDPORT_SPARE0_REG.eth35[0x500]=0
CDPORT_SPARE0_REG.eth36[0x500]=0
CDPORT_SPARE1_REG.eth33[0x600]=0
CDPORT_SPARE1_REG.eth34[0x600]=0
CDPORT_SPARE1_REG.eth35[0x600]=0
CDPORT_SPARE1_REG.eth36[0x600]=0
CDPORT_SPARE2_REG.eth33[0x700]=0
CDPORT_SPARE2_REG.eth34[0x700]=0
CDPORT_SPARE2_REG.eth35[0x700]=0
CDPORT_SPARE2_REG.eth36[0x700]=0
CDPORT_SPARE3_REG.eth33[0x800]=0
CDPORT_SPARE3_REG.eth34[0x800]=0
CDPORT_SPARE3_REG.eth35[0x800]=0
CDPORT_SPARE3_REG.eth36[0x800]=0
CDPORT_SW_FLOW_CONTROL.eth33[0x200]=0
CDPORT_SW_FLOW_CONTROL.eth34[0x200]=0
CDPORT_SW_FLOW_CONTROL.eth35[0x200]=0
CDPORT_SW_FLOW_CONTROL.eth36[0x200]=0
CDPORT_TSC_INTR_STATUS.CDPORT0[0x2001f00]=0
CDPORT_TSC_INTR_STATUS.CDPORT1[0x2001f00]=0
CDPORT_TSC_MEM_CTRL.CDPORT0[0x2001500]=0
CDPORT_TSC_MEM_CTRL.CDPORT1[0x2001500]=0
CDPORT_TSC_PLL_LOCK_STATUS.CDPORT0[0x2000b00]=5
CDPORT_TSC_PLL_LOCK_STATUS.CDPORT1[0x2000b00]=4
CDPORT_XGXS0_CTRL_REG.CDPORT0[0x2000c00]=5
CDPORT_XGXS0_CTRL_REG.CDPORT1[0x2000c00]=5
CDPORT_XGXS0_LN0_STATUS_REG.CDPORT0[0x2000d00]=0
CDPORT_XGXS0_LN0_STATUS_REG.CDPORT1[0x2000d00]=0
CDPORT_XGXS0_LN1_STATUS_REG.CDPORT0[0x2000e00]=0
CDPORT_XGXS0_LN1_STATUS_REG.CDPORT1[0x2000e00]=0
CDPORT_XGXS0_LN2_STATUS_REG.CDPORT0[0x2000f00]=0
CDPORT_XGXS0_LN2_STATUS_REG.CDPORT1[0x2000f00]=0
CDPORT_XGXS0_LN3_STATUS_REG.CDPORT0[0x2001000]=0
CDPORT_XGXS0_LN3_STATUS_REG.CDPORT1[0x2001000]=0
CDPORT_XGXS0_LN4_STATUS_REG.CDPORT0[0x2001100]=0
CDPORT_XGXS0_LN4_STATUS_REG.CDPORT1[0x2001100]=0
CDPORT_XGXS0_LN5_STATUS_REG.CDPORT0[0x2001200]=0
CDPORT_XGXS0_LN5_STATUS_REG.CDPORT1[0x2001200]=0
CDPORT_XGXS0_LN6_STATUS_REG.CDPORT0[0x2001300]=0
CDPORT_XGXS0_LN6_STATUS_REG.CDPORT1[0x2001300]=0
CDPORT_XGXS0_LN7_STATUS_REG.CDPORT0[0x2001400]=0
CDPORT_XGXS0_LN7_STATUS_REG.CDPORT1[0x2001400]=0
CDU_ALIGNER_ASYNC_FIFO_CONFIG.CDU0[0x523]=1
CDU_ALIGNER_ASYNC_FIFO_CONFIG.CDU1[0x523]=1
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(0).CDU0[0x519]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(1).CDU0[0x51a]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(2).CDU0[0x51b]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(3).CDU0[0x51c]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(4).CDU0[0x51d]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(5).CDU0[0x51e]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(6).CDU0[0x51f]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(7).CDU0[0x520]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(0).CDU1[0x519]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(1).CDU1[0x51a]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(2).CDU1[0x51b]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(3).CDU1[0x51c]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(4).CDU1[0x51d]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(5).CDU1[0x51e]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(6).CDU1[0x51f]=0
CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS(7).CDU1[0x520]=0
CDU_ALIGNER_DEBUG_FIFO_WR_STATUS_MAX_OCCUPANCY.CDU0[0x522]=0
CDU_ALIGNER_DEBUG_FIFO_WR_STATUS_MAX_OCCUPANCY.CDU1[0x522]=0
CDU_ALIGNER_DEBUG_REG.CDU0[0x521]=0
CDU_ALIGNER_DEBUG_REG.CDU1[0x521]=0
CDU_ALIGNER_MEMS_RESET.CDU0[0x47a]=1
CDU_ALIGNER_MEMS_RESET.CDU1[0x47a]=1
CDU_CLK_POWER_DOWN_2.CDU0[0x3fe]=0
CDU_CLK_POWER_DOWN_2.CDU1[0x3fe]=0
CDU_CONTROL_FRAME_CONFIG.CDU0[0x19c]=0
CDU_CONTROL_FRAME_CONFIG.CDU1[0x19c]=0
CDU_ECC_1B_ERR_CNT.CDU0[0x94]=0
CDU_ECC_1B_ERR_CNT.CDU1[0x94]=0
CDU_ECC_2B_ERR_CNT.CDU0[0x96]=0
CDU_ECC_2B_ERR_CNT.CDU1[0x96]=0
CDU_ECC_ERR_1B_MONITOR_MEM_MASK.CDU0[0x9a]=0x1fff
CDU_ECC_ERR_1B_MONITOR_MEM_MASK.CDU1[0x9a]=0x1fff
CDU_ECC_ERR_2B_MONITOR_MEM_MASK.CDU0[0x9c]=0x1fff
CDU_ECC_ERR_2B_MONITOR_MEM_MASK.CDU1[0x9c]=0x1fff
CDU_ECC_INTERRUPT_REGISTER.CDU0[0x7]=0
CDU_ECC_INTERRUPT_REGISTER.CDU1[0x7]=0
CDU_ECC_INTERRUPT_REGISTER_MASK.CDU0[0x17]=0
CDU_ECC_INTERRUPT_REGISTER_MASK.CDU1[0x17]=0
CDU_ECC_INTERRUPT_REGISTER_TEST.CDU0[0x1f]=0
CDU_ECC_INTERRUPT_REGISTER_TEST.CDU1[0x1f]=0
CDU_EGQ_CRDT_CONFIG.CDU0[0x24d]=0x320320320320320320320320
CDU_EGQ_CRDT_CONFIG.CDU1[0x24d]=0x320320320320320320320320
CDU_ENABLE_DYNAMIC_MEMORY_ACCESS.CDU0[0x84]=0
CDU_ENABLE_DYNAMIC_MEMORY_ACCESS.CDU1[0x84]=0
CDU_ETH_TX_GEN_LLFC_CNT.CDU0[0x4b5]=0
CDU_ETH_TX_GEN_LLFC_CNT.CDU1[0x4b5]=0
CDU_ETH_TX_LLFC_STOP_TX_CNT.CDU0[0x4b4]=0
CDU_ETH_TX_LLFC_STOP_TX_CNT.CDU1[0x4b4]=0
CDU_FC_CHAIN_RX_LLFC_SYNC_DBG.CDU0[0x543]=0
CDU_FC_CHAIN_RX_LLFC_SYNC_DBG.CDU1[0x543]=0
CDU_FC_CHAIN_RX_PFC_SYNC_DBG.CDU0[0x544]=1
CDU_FC_CHAIN_RX_PFC_SYNC_DBG.CDU1[0x544]=1
CDU_FC_CHOOSE_PORT_FOR_ETH_TX.CDU0[0x4b3]=0
CDU_FC_CHOOSE_PORT_FOR_ETH_TX.CDU1[0x4b3]=0
CDU_FC_CHOOSE_PORT_FOR_PFC.CDU0[0x4b1]=0
CDU_FC_CHOOSE_PORT_FOR_PFC.CDU1[0x4b1]=0
CDU_FC_GEN_SAFC_REFRESH_TIMER(0).CDU0[0x49c]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(1).CDU0[0x49d]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(2).CDU0[0x49e]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(3).CDU0[0x49f]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(4).CDU0[0x4a0]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(5).CDU0[0x4a1]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(6).CDU0[0x4a2]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(7).CDU0[0x4a3]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(0).CDU1[0x49c]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(1).CDU1[0x49d]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(2).CDU1[0x49e]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(3).CDU1[0x49f]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(4).CDU1[0x4a0]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(5).CDU1[0x4a1]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(6).CDU1[0x4a2]=0x1000000
CDU_FC_GEN_SAFC_REFRESH_TIMER(7).CDU1[0x4a3]=0x1000000
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(0).CDU0[0x4b6]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(1).CDU0[0x4b7]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(2).CDU0[0x4b8]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(3).CDU0[0x4b9]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(4).CDU0[0x4ba]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(5).CDU0[0x4bb]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(6).CDU0[0x4bc]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(7).CDU0[0x4bd]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(0).CDU1[0x4b6]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(1).CDU1[0x4b7]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(2).CDU1[0x4b8]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(3).CDU1[0x4b9]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(4).CDU1[0x4ba]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(5).CDU1[0x4bb]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(6).CDU1[0x4bc]=0
CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(7).CDU1[0x4bd]=0
CDU_FC_LLFC_STOP_TX_FORCE.CDU0[0x47e]=0
CDU_FC_LLFC_STOP_TX_FORCE.CDU1[0x47e]=0
CDU_FC_LLFC_STOP_TX_FROM_CFC_MASK.CDU0[0x482]=0
CDU_FC_LLFC_STOP_TX_FROM_CFC_MASK.CDU1[0x482]=0
CDU_FC_MASK_FC_WHEN_LINK_FAIL.CDU0[0x49a]=0xff
CDU_FC_MASK_FC_WHEN_LINK_FAIL.CDU1[0x49a]=0xff
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(0).CDU0[0x4ce]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(1).CDU0[0x4cf]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(2).CDU0[0x4d0]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(3).CDU0[0x4d1]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(4).CDU0[0x4d2]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(5).CDU0[0x4d3]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(6).CDU0[0x4d4]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(7).CDU0[0x4d5]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(8).CDU0[0x4d6]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(9).CDU0[0x4d7]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(10).CDU0[0x4d8]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(11).CDU0[0x4d9]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(12).CDU0[0x4da]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(13).CDU0[0x4db]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(14).CDU0[0x4dc]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(15).CDU0[0x4dd]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(0).CDU1[0x4ce]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(1).CDU1[0x4cf]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(2).CDU1[0x4d0]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(3).CDU1[0x4d1]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(4).CDU1[0x4d2]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(5).CDU1[0x4d3]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(6).CDU1[0x4d4]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(7).CDU1[0x4d5]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(8).CDU1[0x4d6]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(9).CDU1[0x4d7]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(10).CDU1[0x4d8]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(11).CDU1[0x4d9]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(12).CDU1[0x4da]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(13).CDU1[0x4db]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(14).CDU1[0x4dc]=0
CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(15).CDU1[0x4dd]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(0).CDU0[0x4be]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(1).CDU0[0x4bf]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(2).CDU0[0x4c0]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(3).CDU0[0x4c1]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(4).CDU0[0x4c2]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(5).CDU0[0x4c3]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(6).CDU0[0x4c4]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(7).CDU0[0x4c5]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(8).CDU0[0x4c6]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(9).CDU0[0x4c7]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(10).CDU0[0x4c8]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(11).CDU0[0x4c9]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(12).CDU0[0x4ca]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(13).CDU0[0x4cb]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(14).CDU0[0x4cc]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(15).CDU0[0x4cd]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(0).CDU1[0x4be]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(1).CDU1[0x4bf]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(2).CDU1[0x4c0]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(3).CDU1[0x4c1]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(4).CDU1[0x4c2]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(5).CDU1[0x4c3]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(6).CDU1[0x4c4]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(7).CDU1[0x4c5]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(8).CDU1[0x4c6]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(9).CDU1[0x4c7]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(10).CDU1[0x4c8]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(11).CDU1[0x4c9]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(12).CDU1[0x4ca]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(13).CDU1[0x4cb]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(14).CDU1[0x4cc]=0
CDU_FC_MASK_PFC_PRIO_OF_RMC(15).CDU1[0x4cd]=0
CDU_FC_PFC_CFG.CDU0[0x47c]=0x25
CDU_FC_PFC_CFG.CDU1[0x47c]=0x25
CDU_FC_PFC_DEBUG_INDICATIONS.CDU0[0x4b2]=0
CDU_FC_PFC_DEBUG_INDICATIONS.CDU1[0x4b2]=0
CDU_FC_PFC_RX_BITMAP_MAP_FORCE_EN.CDU0[0x48b]=0xff
CDU_FC_PFC_RX_BITMAP_MAP_FORCE_EN.CDU1[0x48b]=0xff
CDU_FC_PFC_RX_BITMAP_TYPE_A.CDU0[0x485]=0xff008040201008040201
CDU_FC_PFC_RX_BITMAP_TYPE_A.CDU1[0x485]=0xff008040201008040201
CDU_FC_PFC_RX_BITMAP_TYPE_B.CDU0[0x488]=0xff008040201008040201
CDU_FC_PFC_RX_BITMAP_TYPE_B.CDU1[0x488]=0xff008040201008040201
CDU_FC_PFC_RX_BITMAP_TYPE_PER_PORT.CDU0[0x48c]=0
CDU_FC_PFC_RX_BITMAP_TYPE_PER_PORT.CDU1[0x48c]=0
CDU_FC_PFC_TX_BITMAP_TYPE_A.CDU0[0x48d]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_A.CDU1[0x48d]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_B.CDU0[0x490]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_B.CDU1[0x490]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_C.CDU0[0x493]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_C.CDU1[0x493]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_D.CDU0[0x496]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_D.CDU1[0x496]=0xfff8040201008040201
CDU_FC_PFC_TX_BITMAP_TYPE_PER_PORT.CDU0[0x499]=0
CDU_FC_PFC_TX_BITMAP_TYPE_PER_PORT.CDU1[0x499]=0
CDU_FC_RESET.CDU0[0x47b]=0
CDU_FC_RESET.CDU1[0x47b]=0
CDU_FC_RX_GEN_LLFC_FROM_QMLF.CDU0[0x4a4]=0
CDU_FC_RX_GEN_LLFC_FROM_QMLF.CDU1[0x4a4]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(0).CDU0[0x4a5]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(1).CDU0[0x4a6]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(2).CDU0[0x4a7]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(3).CDU0[0x4a8]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(4).CDU0[0x4a9]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(5).CDU0[0x4aa]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(6).CDU0[0x4ab]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(7).CDU0[0x4ac]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(0).CDU1[0x4a5]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(1).CDU1[0x4a6]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(2).CDU1[0x4a7]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(3).CDU1[0x4a8]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(4).CDU1[0x4a9]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(5).CDU1[0x4aa]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(6).CDU1[0x4ab]=0
CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT(7).CDU1[0x4ac]=0
CDU_FC_TX_GEN_LLFC_FORCE.CDU0[0x47d]=0
CDU_FC_TX_GEN_LLFC_FORCE.CDU1[0x47d]=0
CDU_FC_TX_GEN_LLFC_FROM_CFC.CDU0[0x4ad]=0
CDU_FC_TX_GEN_LLFC_FROM_CFC.CDU1[0x4ad]=0
CDU_FC_TX_GEN_LLFC_FROM_CFC_MASK.CDU0[0x480]=0xff
CDU_FC_TX_GEN_LLFC_FROM_CFC_MASK.CDU1[0x480]=0xff
CDU_FC_TX_GEN_LLFC_FROM_CFC_OCB_MASK.CDU0[0x481]=0
CDU_FC_TX_GEN_LLFC_FROM_CFC_OCB_MASK.CDU1[0x481]=0
CDU_FC_TX_GEN_LLFC_FROM_CFC_PD_MASK.CDU0[0x483]=0
CDU_FC_TX_GEN_LLFC_FROM_CFC_PD_MASK.CDU1[0x483]=0
CDU_FC_TX_GEN_LLFC_TO_PM.CDU0[0x4ae]=0
CDU_FC_TX_GEN_LLFC_TO_PM.CDU1[0x4ae]=0
CDU_FC_TX_GEN_PFC_FORCE.CDU0[0x47f]=0
CDU_FC_TX_GEN_PFC_FORCE.CDU1[0x47f]=0
CDU_FC_TX_GEN_PFC_FORCE_MASK.CDU0[0x484]=0
CDU_FC_TX_GEN_PFC_FORCE_MASK.CDU1[0x484]=0
CDU_FC_TX_LLFC_STOP_TX_FROM_CFC.CDU0[0x4af]=0
CDU_FC_TX_LLFC_STOP_TX_FROM_CFC.CDU1[0x4af]=0
CDU_FC_TX_LLFC_STOP_TX_TO_PM.CDU0[0x4b0]=0
CDU_FC_TX_LLFC_STOP_TX_TO_PM.CDU1[0x4b0]=0
CDU_FC_TX_LOW_PASS_FILTER.CDU0[0x49b]=0x10100
CDU_FC_TX_LOW_PASS_FILTER.CDU1[0x49b]=0x10100
CDU_FE_PORTID_COLLISION_ERR_PORTID.CDU0[0x55a]=7
CDU_FE_PORTID_COLLISION_ERR_PORTID.CDU1[0x55a]=5
CDU_FIFO_WRITE_POINTER_QMLF_SELECT.CDU0[0x3e6]=0
CDU_FIFO_WRITE_POINTER_QMLF_SELECT.CDU1[0x3e6]=0
CDU_FIFO_WRITE_POINTER_RESULT.CDU0[0x3e7]=0x118000
CDU_FIFO_WRITE_POINTER_RESULT.CDU1[0x3e7]=0x109000
CDU_FLUSH_OR_STOP_RX_FIFO.CDU0[0x53b]=0x1fffe
CDU_FLUSH_OR_STOP_RX_FIFO.CDU1[0x53b]=0x1fffe
CDU_FLUSH_SOP_WITH_ERR_CONFIG.CDU0[0x24c]=0xffff
CDU_FLUSH_SOP_WITH_ERR_CONFIG.CDU1[0x24c]=0xffff
CDU_GTIMER_CONFIGURATION.CDU0[0x89]=0
CDU_GTIMER_CONFIGURATION.CDU1[0x89]=0
CDU_GTIMER_CYCLE.CDU0[0x88]=0x3b9aca00
CDU_GTIMER_CYCLE.CDU1[0x88]=0x3b9aca00
CDU_ILKN_ALIGNER_RX(0).CDU0[0x545]=0
CDU_ILKN_ALIGNER_RX(1).CDU0[0x546]=0
CDU_ILKN_ALIGNER_RX(2).CDU0[0x547]=0
CDU_ILKN_ALIGNER_RX(3).CDU0[0x548]=0
CDU_ILKN_ALIGNER_RX(4).CDU0[0x549]=0
CDU_ILKN_ALIGNER_RX(5).CDU0[0x54a]=0
CDU_ILKN_ALIGNER_RX(6).CDU0[0x54b]=0
CDU_ILKN_ALIGNER_RX(7).CDU0[0x54c]=0
CDU_ILKN_ALIGNER_RX(0).CDU1[0x545]=0
CDU_ILKN_ALIGNER_RX(1).CDU1[0x546]=0
CDU_ILKN_ALIGNER_RX(2).CDU1[0x547]=0
CDU_ILKN_ALIGNER_RX(3).CDU1[0x548]=0
CDU_ILKN_ALIGNER_RX(4).CDU1[0x549]=0
CDU_ILKN_ALIGNER_RX(5).CDU1[0x54a]=0
CDU_ILKN_ALIGNER_RX(6).CDU1[0x54b]=0
CDU_ILKN_ALIGNER_RX(7).CDU1[0x54c]=0
CDU_ILKN_ALIGNER_TX(0).CDU0[0x54d]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(1).CDU0[0x54e]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(2).CDU0[0x54f]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(3).CDU0[0x550]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(4).CDU0[0x551]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(5).CDU0[0x552]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(6).CDU0[0x553]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(7).CDU0[0x554]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(0).CDU1[0x54d]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(1).CDU1[0x54e]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(2).CDU1[0x54f]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(3).CDU1[0x550]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(4).CDU1[0x551]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(5).CDU1[0x552]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(6).CDU1[0x553]=0x7c000000c0
CDU_ILKN_ALIGNER_TX(7).CDU1[0x554]=0x7c000000c0
CDU_ILKN_ALIGNER_TX_FT_FIFO(0).CDU0[0x55b]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(1).CDU0[0x55c]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(2).CDU0[0x55d]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(3).CDU0[0x55e]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(4).CDU0[0x55f]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(5).CDU0[0x560]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(6).CDU0[0x561]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(7).CDU0[0x562]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(0).CDU1[0x55b]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(1).CDU1[0x55c]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(2).CDU1[0x55d]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(3).CDU1[0x55e]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(4).CDU1[0x55f]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(5).CDU1[0x560]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(6).CDU1[0x561]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO(7).CDU1[0x562]=0
CDU_ILKN_ALIGNER_TX_FT_FIFO_INPUT_READY_TH.CDU0[0x563]=4
CDU_ILKN_ALIGNER_TX_FT_FIFO_INPUT_READY_TH.CDU1[0x563]=4
CDU_INDIRECT_COMMAND.CDU0[0x80]=0xe000000
CDU_INDIRECT_COMMAND.CDU1[0x80]=0xe000000
CDU_INDIRECT_COMMAND_ADDRESS.CDU0[0x81]=0
CDU_INDIRECT_COMMAND_ADDRESS.CDU1[0x81]=0
CDU_INDIRECT_COMMAND_RD_DATA.CDU0[0x60]=0xd92c565920ac9c44c19c0812091cad20c0e910328c8c48168c6358133ff9a12c549ff520d6ebe4ce7f5fdfb3ebdffecbc4
CDU_INDIRECT_COMMAND_RD_DATA.CDU1[0x60]=0x10000001180002e0c210400c000240000874dc0c008002188200000104200300a0280080800000000001202000041100
CDU_INDIRECT_COMMAND_WR_DATA.CDU0[0x20]=0
CDU_INDIRECT_COMMAND_WR_DATA.CDU1[0x20]=0
CDU_INDIRECT_FORCE_BUBBLE.CDU0[0x83]=0x1020019
CDU_INDIRECT_FORCE_BUBBLE.CDU1[0x83]=0x1020019
CDU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION.CDU0[0x517]=0
CDU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION.CDU1[0x517]=0
CDU_INSTRUMENTATION_DEBUG_WRAP_AROUND.CDU0[0x511]=0
CDU_INSTRUMENTATION_DEBUG_WRAP_AROUND.CDU1[0x511]=0
CDU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.CDU0[0x3e5]=0
CDU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.CDU1[0x3e5]=0
CDU_INSTRUMENTATION_INTERVALS_COUNTER.CDU0[0x513]=0
CDU_INSTRUMENTATION_INTERVALS_COUNTER.CDU1[0x513]=0
CDU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN.CDU0[0x512]=0
CDU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN.CDU1[0x512]=0
CDU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED.CDU0[0x50f]=0xf
CDU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED.CDU1[0x50f]=0xf
CDU_INSTRUMENTATION_OVERRIDE_MODE.CDU0[0x510]=1
CDU_INSTRUMENTATION_OVERRIDE_MODE.CDU1[0x510]=1
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(0).CDU0[0x4ee]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(1).CDU0[0x4ef]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(2).CDU0[0x4f0]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(3).CDU0[0x4f1]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(4).CDU0[0x4f2]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(5).CDU0[0x4f3]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(6).CDU0[0x4f4]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(7).CDU0[0x4f5]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(0).CDU1[0x4ee]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(1).CDU1[0x4ef]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(2).CDU1[0x4f0]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(3).CDU1[0x4f1]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(4).CDU1[0x4f2]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(5).CDU1[0x4f3]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(6).CDU1[0x4f4]=0
CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(7).CDU1[0x4f5]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(0).CDU0[0x4f6]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(1).CDU0[0x4f7]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(2).CDU0[0x4f8]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(3).CDU0[0x4f9]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(4).CDU0[0x4fa]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(5).CDU0[0x4fb]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(6).CDU0[0x4fc]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(7).CDU0[0x4fd]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(0).CDU1[0x4f6]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(1).CDU1[0x4f7]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(2).CDU1[0x4f8]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(3).CDU1[0x4f9]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(4).CDU1[0x4fa]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(5).CDU1[0x4fb]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(6).CDU1[0x4fc]=0
CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(7).CDU1[0x4fd]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(0).CDU0[0x4fe]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(1).CDU0[0x4ff]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(2).CDU0[0x500]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(3).CDU0[0x501]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(4).CDU0[0x502]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(5).CDU0[0x503]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(6).CDU0[0x504]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(7).CDU0[0x505]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(0).CDU1[0x4fe]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(1).CDU1[0x4ff]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(2).CDU1[0x500]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(3).CDU1[0x501]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(4).CDU1[0x502]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(5).CDU1[0x503]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(6).CDU1[0x504]=0
CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(7).CDU1[0x505]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(0).CDU0[0x506]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(1).CDU0[0x507]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(2).CDU0[0x508]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(3).CDU0[0x509]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(4).CDU0[0x50a]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(5).CDU0[0x50b]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(6).CDU0[0x50c]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(7).CDU0[0x50d]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(0).CDU1[0x506]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(1).CDU1[0x507]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(2).CDU1[0x508]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(3).CDU1[0x509]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(4).CDU1[0x50a]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(5).CDU1[0x50b]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(6).CDU1[0x50c]=0
CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(7).CDU1[0x50d]=0
CDU_INSTRUMENTATION_PFC_DEBUG_AND_BREAKING_MECHANISM.CDU0[0x518]=0
CDU_INSTRUMENTATION_PFC_DEBUG_AND_BREAKING_MECHANISM.CDU1[0x518]=0
CDU_INSTRUMENTATION_RESET_LOW.CDU0[0x514]=1
CDU_INSTRUMENTATION_RESET_LOW.CDU1[0x514]=1
CDU_INSTRUMENTATION_RSTN_PFC_CNTS.CDU0[0x516]=0xff
CDU_INSTRUMENTATION_RSTN_PFC_CNTS.CDU1[0x516]=0xff
CDU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS.CDU0[0x515]=0xff
CDU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS.CDU1[0x515]=0xff
CDU_INSTRUMENTATION_TIME_FACTOR_FOR_PFC_CNTS.CDU0[0x50e]=0xa00000000
CDU_INSTRUMENTATION_TIME_FACTOR_FOR_PFC_CNTS.CDU1[0x50e]=0xa00000000
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(0).CDU0[0x4de]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(1).CDU0[0x4df]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(2).CDU0[0x4e0]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(3).CDU0[0x4e1]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(4).CDU0[0x4e2]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(5).CDU0[0x4e3]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(6).CDU0[0x4e4]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(7).CDU0[0x4e5]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(0).CDU1[0x4de]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(1).CDU1[0x4df]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(2).CDU1[0x4e0]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(3).CDU1[0x4e1]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(4).CDU1[0x4e2]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(5).CDU1[0x4e3]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(6).CDU1[0x4e4]=0
CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(7).CDU1[0x4e5]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(0).CDU0[0x4e6]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(1).CDU0[0x4e7]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(2).CDU0[0x4e8]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(3).CDU0[0x4e9]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(4).CDU0[0x4ea]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(5).CDU0[0x4eb]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(6).CDU0[0x4ec]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(7).CDU0[0x4ed]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(0).CDU1[0x4e6]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(1).CDU1[0x4e7]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(2).CDU1[0x4e8]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(3).CDU1[0x4e9]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(4).CDU1[0x4ea]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(5).CDU1[0x4eb]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(6).CDU1[0x4ec]=0
CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(7).CDU1[0x4ed]=0
CDU_INTERRUPT_MASK_REGISTER.CDU0[0x10]=0
CDU_INTERRUPT_MASK_REGISTER.CDU1[0x10]=0
CDU_INTERRUPT_REGISTER.CDU0[0x0]=2
CDU_INTERRUPT_REGISTER.CDU1[0x0]=2
CDU_INTERRUPT_REGISTER_TEST.CDU0[0x18]=0
CDU_INTERRUPT_REGISTER_TEST.CDU1[0x18]=0
CDU_LAST_RECEIVED_FROM_EGQ_CONTROLS.CDU0[0x2f1]=0x79e0647
CDU_LAST_RECEIVED_FROM_EGQ_CONTROLS.CDU1[0x2f1]=0x7d205ed
CDU_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP.CDU0[0x2f2]=0xbe7ba7791f55ead84260f2e777d87fdbac3fbeb7d733af19d4d22a25ff6f677df5bb8cdc54ae52fa9edebd95a9c0be9fd2961d2c5cd96351dd6fd7223b7a5fef
CDU_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP.CDU1[0x2f2]=0xc5dfa1c1bfd377d1718efaa7bea1aebeec6e532c38b9addfeeee465ba26eeb9b83b7ffec3875f3e34d577bf12fcbffac8bcc881136becfe37dcfefe63b572e7c
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(0).CDU0[0x269]=0xf1af99f9afb6e9fff3eacb4af4d8fdfcf866e35febed6c7d4df7eeadc73bfebb5afeeff5ffbaef5f7dbe5be96bd3ad678fbff57243bad3cdf1eb4d8adbf4d7e46
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(1).CDU0[0x26a]=0xaac8eefffd71dbd686bcbe616bddbe4fd4b9fe9dfedfff8fcb9efef2ddbb33444fdfd49b5fff71ffbf7d939c7361a6571a2fdd7dd8dfb7fc8816ffd3c8ffbff8e
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(2).CDU0[0x26b]=0x9692865e64cdf4f9ebd79ddf2afefd74cb2773aa5ddd67fd3315817fe923f3f25bf3e35db257fbc6d935e0e4ba09aa9bf3db83966fe7fdbbe7fe3637fab5ddb98
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(3).CDU0[0x26c]=0x4e1b8bf9fbf7ef66ce7fb87cbff4ea673d63e7fc2dad6ba79f90eb7f8bedffdf147fd775f716fcadafbe9bda449ef17feb63cad7cb9cacb2fbfbfd1ee1abefcee
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(4).CDU0[0x26d]=0xc743e33367b669defcf63ab7bf5cc1e865a6c85fa9bb773bb8df35fb251ff4998abffe77f98bbdff7aaaedb877e7d7de4f73c56ff50f99feed16ca52bc1e67fee
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(5).CDU0[0x26e]=0xca7ba9f97aeedf9c03fb6ddf76b5dcf1babf5b4d4befe57f6dbcdaabdceadbd9bdfe583f8bf2fc6a9dad86f1ef100e1e377d6df7f7c673775d547ebf5d5eefa8c
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(6).CDU0[0x26f]=0x6afe3825bbffebff6fbf8fffe5d35f65cb87ab23f1ddd52feccffd98e6abef751c1d171cb9b8bdb54df5f77279a6ff7ae61f5da32f757551aeaf1efebd19794fe
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(7).CDU0[0x270]=0xd7d3bd77917fe65c57df27b9a4ffde677d0efde7ceefbbb3dffb4a3fedbabfdf7be7defc08ee7fbf7c5dd4da74fddfefdfddbf9ffb47676f9bff7cfdeb7ed6df2
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(0).CDU1[0x269]=0x6d6f34dec8eb6d5f7ff4fdbbffbe61ceecb3dbdf65b5c5eec65fdf1aa9f7e7f901b8fda73bf3daf9b5cbf4dcffaac37dfe8ff87f6e64ad74f77df5cab9db4adbe
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(1).CDU1[0x26a]=0x3977a7e69d7e6b4fd6e7aff7f82e6b5bddba97bf26fce9effbef3edfa4fbedb68cee7291fdb794457e4e756bec5fd463ebf55b7afbfff3c6e2f6f8cf7484edace
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(2).CDU1[0x26b]=0x67d9c352a4d7e8d8d73af6edf9a32b707f32fde37cd48c5cae3efe92e35b05ffd77eee16f3ef97dd36b9b05be797f75eaf58bbb82df934f7abae5f73997dfca70
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(3).CDU1[0x26c]=0xbdfdef57c7eefff6f9b9fe9fdffff5fe77e2edffd2d9ad0e1fbfb0c1cddf7bfde7e09ffdfb3d7b5e26d669cb65d7f68aeffb4fd6db66ffaffffefdf8dfbfd7fbe
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(4).CDU1[0x26d]=0xe96fe54dbf4ee7e5e7bf579ba5abc1d7e93da93e1558a45cebbb7fdddb76b73bbfe35bd739a3fb836627eeedc0213ef63457e8d23f8df7723f36e5df0d99dfbce
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(5).CDU1[0x26e]=0x343ef51aa5da3f5cb1d5fffd197ed3f77fd0ef5af3be9a715ff7fb3fffe2b51756b793743bf7bf1f76cde9c77797feca7fadeefdfb578345db7fdbc3dfdec39c6
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(6).CDU1[0x26f]=0xaffdffbcfeeeffffbd4ec7de811dbabfc4f8bf6ed76f77ba677e7f3f9bfffffff3ffe9cfeffebffbffd7effbd93f6e9afea7edf6ffefd7bffff7ffd1ffef7fbf0
CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT(7).CDU1[0x270]=0xbffdffbcffeffffffd4fcfdf9fbffebfe6ffbf7fd7fff7aaef7e7fbfdffffffffbfffdeffffffffbffffefffdfff7ffefef7eff7fffff7bffff7fff5ffff7fbf0
CDU_LAST_RECEIVED_FROM_PM_CONTROLS.CDU0[0x325]=0x3ffbfffffbffdc
CDU_LAST_RECEIVED_FROM_PM_CONTROLS.CDU1[0x325]=0xa0b5d1d2498b6
CDU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP.CDU0[0x327]=0x7fe33037f4aabed2490f106c515fdff93bfbab43affb9f3ffdde9ebfc1f487e9d5eaffdfefdd7d5c4fd7feb018555c363b1c01d47dbf20fecdd3abc2f7957e2b
CDU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP.CDU1[0x327]=0x5bb51b2b07767cfb22942037ddff2496d7b2d6b3e9ee63cadbe3530f672bfd4ffed7d77be1efc6f6dea567a69655de9266fdd4fed17eec7d2eb93f37ff5fef7c
CDU_LAST_SENT_TO_IRE_CONTROLS.CDU0[0x302]=0x60dd1569469bff4
CDU_LAST_SENT_TO_IRE_CONTROLS.CDU1[0x302]=0x221315e77f719abe
CDU_LAST_SENT_TO_IRE_DATA_ON_SOP.CDU0[0x304]=0xfff7efcff6f6430b8f6637f5da91e4c4f3373fa62f6eeff6c00ed7b83dc1351e9fc6b2667b6bbdcbf920d5ed9eb53fd6d6e0fdb75d797ebdd5e7b3ddcde7cefd
CDU_LAST_SENT_TO_IRE_DATA_ON_SOP.CDU1[0x304]=0xdb7f7dd94af25bfffcdb6edaf9afa5d5e11be8ae67d8fb3c6f1577ebf9f436cdaef562f6d2fdfffe3d9c8bd2d7b0ded332dbaafd0d9e853f61dd9ff2ecdfcfda
CDU_LAST_SENT_TO_PM_CONTROLS.CDU0[0x314]=0x4f0caf2
CDU_LAST_SENT_TO_PM_CONTROLS.CDU1[0x314]=0x975dffe
CDU_LAST_SENT_TO_PM_DATA_ON_SOP.CDU0[0x315]=0xf7d67f23f78499f21bde6f0bdf41efac9f7d47ff3c7934cdfe17e9b1bc6f736bb7bfddc33e6ddf10938bbccf5f2cad9760e63cd064120486803a1d542eaf2aee
CDU_LAST_SENT_TO_PM_DATA_ON_SOP.CDU1[0x315]=0x7bd3b1defff2df7fcb7fbcef7dfdf4bff2fafff53df4e58f7e5d5dbff77eacacb2597bd17f53afeef2ddd98bddee06ffefc3fa62ef7f7e7dfd7affeffadd2e9f
CDU_LINK_ACTIVE.CDU0[0x264]=0
CDU_LINK_ACTIVE.CDU1[0x264]=0
CDU_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER.CDU0[0x11]=0
CDU_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER.CDU1[0x11]=0
CDU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER.CDU0[0x1]=0
CDU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER.CDU1[0x1]=0
CDU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST.CDU0[0x19]=0
CDU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST.CDU1[0x19]=0
CDU_MAC_RESET.CDU0[0x479]=0
CDU_MAC_RESET.CDU1[0x479]=0
CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER.CDU0[0x12]=0
CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER.CDU1[0x12]=0
CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER.CDU0[0x2]=0
CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER.CDU1[0x2]=0
CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST.CDU0[0x1a]=0
CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST.CDU1[0x1a]=0
CDU_NBI_TX_DATA_PATH_ASYNC_FIFO_DEBUG.CDU0[0x559]=0
CDU_NBI_TX_DATA_PATH_ASYNC_FIFO_DEBUG.CDU1[0x559]=0
CDU_NIF_ILKN_CFG.CDU0[0x3f0]=0
CDU_NIF_ILKN_CFG.CDU1[0x3f0]=0
CDU_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION.CDU0[0x3ef]=0
CDU_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION.CDU1[0x3ef]=0
CDU_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION.CDU0[0x3ed]=0
CDU_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION.CDU1[0x3ed]=0
CDU_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION.CDU0[0x3ee]=0
CDU_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION.CDU1[0x3ee]=0
CDU_NIF_PM_EXTRA_SAMPLES.CDU0[0x3fd]=0x20
CDU_NIF_PM_EXTRA_SAMPLES.CDU1[0x3fd]=0x20
CDU_NIF_PM_RESOLVED_SPEED.CDU0[0x3ea]=0x3c3c3c3c38383838
CDU_NIF_PM_RESOLVED_SPEED.CDU1[0x3ea]=0x3c3c3c3c38383838
CDU_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS.CDU0[0x3eb]=0
CDU_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS.CDU1[0x3eb]=0
CDU_NIF_TSC_LANE_STATUS.CDU0[0x3e8]=0
CDU_NIF_TSC_LANE_STATUS.CDU1[0x3e8]=0
CDU_PARITY_ERR_CNT.CDU0[0x98]=0
CDU_PARITY_ERR_CNT.CDU1[0x98]=0
CDU_PARSER_HARD_CONTROL.CDU0[0x108]=0xdc0c523819c
CDU_PARSER_HARD_CONTROL.CDU1[0x108]=0xdc0c523819c
CDU_PARSER_HARD_CONTROL_PLANE(0).CDU0[0x123]=0
CDU_PARSER_HARD_CONTROL_PLANE(1).CDU0[0x124]=0
CDU_PARSER_HARD_CONTROL_PLANE(2).CDU0[0x125]=0
CDU_PARSER_HARD_CONTROL_PLANE(3).CDU0[0x126]=0
CDU_PARSER_HARD_CONTROL_PLANE(0).CDU1[0x123]=0
CDU_PARSER_HARD_CONTROL_PLANE(1).CDU1[0x124]=0
CDU_PARSER_HARD_CONTROL_PLANE(2).CDU1[0x125]=0
CDU_PARSER_HARD_CONTROL_PLANE(3).CDU1[0x126]=0
CDU_PARSER_HARD_ETHER_TYPE.CDU0[0x122]=0
CDU_PARSER_HARD_ETHER_TYPE.CDU1[0x122]=0
CDU_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.CDU0[0x129]=0x6db492249000
CDU_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.CDU1[0x129]=0x6db492249000
CDU_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.CDU0[0x128]=0x6db6db6db6db492492492492249249249249000000000000
CDU_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.CDU1[0x128]=0x6db6db6db6db492492492492249249249249000000000000
CDU_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.CDU0[0x12a]=0x6d2240
CDU_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.CDU1[0x12a]=0x6d2240
CDU_PARSER_HARD_PORT_ETH_TPID(0).CDU0[0x10a]=0
CDU_PARSER_HARD_PORT_ETH_TPID(1).CDU0[0x10b]=0
CDU_PARSER_HARD_PORT_ETH_TPID(2).CDU0[0x10c]=0
CDU_PARSER_HARD_PORT_ETH_TPID(3).CDU0[0x10d]=0
CDU_PARSER_HARD_PORT_ETH_TPID(4).CDU0[0x10e]=0
CDU_PARSER_HARD_PORT_ETH_TPID(5).CDU0[0x10f]=0
CDU_PARSER_HARD_PORT_ETH_TPID(6).CDU0[0x110]=0
CDU_PARSER_HARD_PORT_ETH_TPID(7).CDU0[0x111]=0
CDU_PARSER_HARD_PORT_ETH_TPID(0).CDU1[0x10a]=0
CDU_PARSER_HARD_PORT_ETH_TPID(1).CDU1[0x10b]=0
CDU_PARSER_HARD_PORT_ETH_TPID(2).CDU1[0x10c]=0
CDU_PARSER_HARD_PORT_ETH_TPID(3).CDU1[0x10d]=0
CDU_PARSER_HARD_PORT_ETH_TPID(4).CDU1[0x10e]=0
CDU_PARSER_HARD_PORT_ETH_TPID(5).CDU1[0x10f]=0
CDU_PARSER_HARD_PORT_ETH_TPID(6).CDU1[0x110]=0
CDU_PARSER_HARD_PORT_ETH_TPID(7).CDU1[0x111]=0
CDU_PARSER_HARD_PORT_PROPERTIES(0).CDU0[0x11a]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(1).CDU0[0x11b]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(2).CDU0[0x11c]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(3).CDU0[0x11d]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(4).CDU0[0x11e]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(5).CDU0[0x11f]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(6).CDU0[0x120]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(7).CDU0[0x121]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(0).CDU1[0x11a]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(1).CDU1[0x11b]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(2).CDU1[0x11c]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(3).CDU1[0x11d]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(4).CDU1[0x11e]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(5).CDU1[0x11f]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(6).CDU1[0x120]=0xf
CDU_PARSER_HARD_PORT_PROPERTIES(7).CDU1[0x121]=0xf
CDU_PARSER_HARD_PORT_TYPE(0).CDU0[0x112]=7
CDU_PARSER_HARD_PORT_TYPE(1).CDU0[0x113]=7
CDU_PARSER_HARD_PORT_TYPE(2).CDU0[0x114]=7
CDU_PARSER_HARD_PORT_TYPE(3).CDU0[0x115]=7
CDU_PARSER_HARD_PORT_TYPE(4).CDU0[0x116]=7
CDU_PARSER_HARD_PORT_TYPE(5).CDU0[0x117]=7
CDU_PARSER_HARD_PORT_TYPE(6).CDU0[0x118]=7
CDU_PARSER_HARD_PORT_TYPE(7).CDU0[0x119]=7
CDU_PARSER_HARD_PORT_TYPE(0).CDU1[0x112]=7
CDU_PARSER_HARD_PORT_TYPE(1).CDU1[0x113]=7
CDU_PARSER_HARD_PORT_TYPE(2).CDU1[0x114]=7
CDU_PARSER_HARD_PORT_TYPE(3).CDU1[0x115]=7
CDU_PARSER_HARD_PORT_TYPE(4).CDU1[0x116]=7
CDU_PARSER_HARD_PORT_TYPE(5).CDU1[0x117]=7
CDU_PARSER_HARD_PORT_TYPE(6).CDU1[0x118]=7
CDU_PARSER_HARD_PORT_TYPE(7).CDU1[0x119]=7
CDU_PARSER_HARD_SPECIAL_LABEL(0).CDU0[0x12b]=0x30
CDU_PARSER_HARD_SPECIAL_LABEL(1).CDU0[0x12c]=0x30
CDU_PARSER_HARD_SPECIAL_LABEL(2).CDU0[0x12d]=0x30
CDU_PARSER_HARD_SPECIAL_LABEL(3).CDU0[0x12e]=0x30
CDU_PARSER_HARD_SPECIAL_LABEL(0).CDU1[0x12b]=0x30
CDU_PARSER_HARD_SPECIAL_LABEL(1).CDU1[0x12c]=0x30
CDU_PARSER_HARD_SPECIAL_LABEL(2).CDU1[0x12d]=0x30
CDU_PARSER_HARD_SPECIAL_LABEL(3).CDU1[0x12e]=0x30
CDU_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.CDU0[0x127]=0x6db6db6db6db492492492492249249249249000000000000
CDU_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.CDU1[0x127]=0x6db6db6db6db492492492492249249249249000000000000
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).CDU0[0x147]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).CDU0[0x148]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).CDU0[0x149]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).CDU0[0x14a]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).CDU0[0x14b]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).CDU0[0x14c]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).CDU0[0x14d]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).CDU0[0x14e]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).CDU0[0x14f]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).CDU0[0x150]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).CDU0[0x151]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).CDU0[0x152]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).CDU0[0x153]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).CDU0[0x154]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).CDU0[0x155]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).CDU1[0x147]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).CDU1[0x148]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).CDU1[0x149]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).CDU1[0x14a]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).CDU1[0x14b]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).CDU1[0x14c]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).CDU1[0x14d]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).CDU1[0x14e]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).CDU1[0x14f]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).CDU1[0x150]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).CDU1[0x151]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).CDU1[0x152]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).CDU1[0x153]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).CDU1[0x154]=0x20
CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).CDU1[0x155]=0x20
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).CDU0[0x12f]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).CDU0[0x130]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(2).CDU0[0x131]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(3).CDU0[0x132]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(4).CDU0[0x133]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(5).CDU0[0x134]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(6).CDU0[0x135]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(7).CDU0[0x136]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).CDU1[0x12f]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).CDU1[0x130]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(2).CDU1[0x131]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(3).CDU1[0x132]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(4).CDU1[0x133]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(5).CDU1[0x134]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(6).CDU1[0x135]=1
CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(7).CDU1[0x136]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).CDU0[0x137]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).CDU0[0x138]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).CDU0[0x139]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).CDU0[0x13a]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).CDU0[0x13b]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).CDU0[0x13c]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).CDU0[0x13d]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).CDU0[0x13e]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).CDU0[0x13f]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).CDU0[0x140]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).CDU0[0x141]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).CDU0[0x142]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).CDU0[0x143]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).CDU0[0x144]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).CDU0[0x145]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).CDU0[0x146]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).CDU1[0x137]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).CDU1[0x138]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).CDU1[0x139]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).CDU1[0x13a]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).CDU1[0x13b]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).CDU1[0x13c]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).CDU1[0x13d]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).CDU1[0x13e]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).CDU1[0x13f]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).CDU1[0x140]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).CDU1[0x141]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).CDU1[0x142]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).CDU1[0x143]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).CDU1[0x144]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).CDU1[0x145]=1
CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).CDU1[0x146]=1
CDU_PARSER_SOFT_TCAM_0_TO_7.CDU0[0x156]=0
CDU_PARSER_SOFT_TCAM_0_TO_7.CDU1[0x156]=0
CDU_PARSER_SOFT_TCAM_16_TO_23.CDU0[0x158]=0
CDU_PARSER_SOFT_TCAM_16_TO_23.CDU1[0x158]=0
CDU_PARSER_SOFT_TCAM_24_TO_31.CDU0[0x159]=0
CDU_PARSER_SOFT_TCAM_24_TO_31.CDU1[0x159]=0
CDU_PARSER_SOFT_TCAM_8_TO_15.CDU0[0x157]=0
CDU_PARSER_SOFT_TCAM_8_TO_15.CDU1[0x157]=0
CDU_PAR_ERR_MEM_MASK.CDU0[0xa0]=0x3f
CDU_PAR_ERR_MEM_MASK.CDU1[0xa0]=0x3f
CDU_PCMI_0.CDU0[0xb0]=0x3b9aca00
CDU_PCMI_0.CDU1[0xb0]=0x3b9aca00
CDU_PCMI_1.CDU0[0xb3]=0x3b9aca00
CDU_PCMI_1.CDU1[0xb3]=0x3b9aca00
CDU_PCMI_2.CDU0[0xb6]=0x3b9aca00
CDU_PCMI_2.CDU1[0xb6]=0x3b9aca00
CDU_PCMI_3.CDU0[0xb9]=0x3b9aca00
CDU_PCMI_3.CDU1[0xb9]=0x3b9aca00
CDU_PCMI_4.CDU0[0xbc]=0x3b9aca00
CDU_PCMI_4.CDU1[0xbc]=0x3b9aca00
CDU_PCMI_0_S.CDU0[0xb1]=0
CDU_PCMI_0_S.CDU1[0xb1]=0
CDU_PCMI_0_T.CDU0[0xb2]=0
CDU_PCMI_0_T.CDU1[0xb2]=0
CDU_PCMI_1_S.CDU0[0xb4]=0
CDU_PCMI_1_S.CDU1[0xb4]=0
CDU_PCMI_1_T.CDU0[0xb5]=0
CDU_PCMI_1_T.CDU1[0xb5]=0
CDU_PCMI_2_S.CDU0[0xb7]=0
CDU_PCMI_2_S.CDU1[0xb7]=0
CDU_PCMI_2_T.CDU0[0xb8]=0
CDU_PCMI_2_T.CDU1[0xb8]=0
CDU_PCMI_3_S.CDU0[0xba]=0
CDU_PCMI_3_S.CDU1[0xba]=0
CDU_PCMI_3_T.CDU0[0xbb]=0
CDU_PCMI_3_T.CDU1[0xbb]=0
CDU_PCMI_4_S.CDU0[0xbd]=0
CDU_PCMI_4_S.CDU1[0xbd]=0
CDU_PCMI_4_T.CDU0[0xbe]=0
CDU_PCMI_4_T.CDU1[0xbe]=0
CDU_PHY_LED_SAMP_CFG.CDU0[0x556]=2
CDU_PHY_LED_SAMP_CFG.CDU1[0x556]=2
CDU_PM_BYPASS_CONFIG.CDU0[0x187]=0
CDU_PM_BYPASS_CONFIG.CDU1[0x187]=0
CDU_PM_MEM_TEST_CTL_MANUALLY_ADDED.CDU0[0x3fb]=0
CDU_PM_MEM_TEST_CTL_MANUALLY_ADDED.CDU1[0x3fb]=0
CDU_PM_TX_PLL_LOCK_STATUS.CDU0[0x3ec]=3
CDU_PM_TX_PLL_LOCK_STATUS.CDU1[0x3ec]=2
CDU_PORTS_CONFIG.CDU0[0x24f]=0
CDU_PORTS_CONFIG.CDU1[0x24f]=0
CDU_PORTS_INDICATIONS.CDU0[0x261]=0
CDU_PORTS_INDICATIONS.CDU1[0x261]=0
CDU_PRD_BYPASS.CDU0[0x185]=0
CDU_PRD_BYPASS.CDU1[0x185]=0
CDU_PRD_CONFIG.CDU0[0x102]=3
CDU_PRD_CONFIG.CDU1[0x102]=3
CDU_PRD_EN.CDU0[0x107]=0
CDU_PRD_EN.CDU1[0x107]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(0).CDU0[0x175]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(1).CDU0[0x176]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(2).CDU0[0x177]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(3).CDU0[0x178]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(4).CDU0[0x179]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(5).CDU0[0x17a]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(6).CDU0[0x17b]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(7).CDU0[0x17c]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(8).CDU0[0x17d]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(9).CDU0[0x17e]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(10).CDU0[0x17f]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(11).CDU0[0x180]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(12).CDU0[0x181]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(13).CDU0[0x182]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(14).CDU0[0x183]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(15).CDU0[0x184]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(0).CDU1[0x175]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(1).CDU1[0x176]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(2).CDU1[0x177]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(3).CDU1[0x178]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(4).CDU1[0x179]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(5).CDU1[0x17a]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(6).CDU1[0x17b]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(7).CDU1[0x17c]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(8).CDU1[0x17d]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(9).CDU1[0x17e]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(10).CDU1[0x17f]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(11).CDU1[0x180]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(12).CDU1[0x181]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(13).CDU1[0x182]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(14).CDU1[0x183]=0
CDU_PRD_ERR_PKT_DROP_CNT_PORT(15).CDU1[0x184]=0
CDU_PRD_OVERRIDES.CDU0[0x186]=0
CDU_PRD_OVERRIDES.CDU1[0x186]=0
CDU_PRD_PKT_DROP_CNT_PORT(0).CDU0[0x165]=0
CDU_PRD_PKT_DROP_CNT_PORT(1).CDU0[0x166]=0
CDU_PRD_PKT_DROP_CNT_PORT(2).CDU0[0x167]=0
CDU_PRD_PKT_DROP_CNT_PORT(3).CDU0[0x168]=0
CDU_PRD_PKT_DROP_CNT_PORT(4).CDU0[0x169]=0
CDU_PRD_PKT_DROP_CNT_PORT(5).CDU0[0x16a]=0
CDU_PRD_PKT_DROP_CNT_PORT(6).CDU0[0x16b]=0
CDU_PRD_PKT_DROP_CNT_PORT(7).CDU0[0x16c]=0
CDU_PRD_PKT_DROP_CNT_PORT(8).CDU0[0x16d]=0
CDU_PRD_PKT_DROP_CNT_PORT(9).CDU0[0x16e]=0
CDU_PRD_PKT_DROP_CNT_PORT(10).CDU0[0x16f]=0
CDU_PRD_PKT_DROP_CNT_PORT(11).CDU0[0x170]=0
CDU_PRD_PKT_DROP_CNT_PORT(12).CDU0[0x171]=0
CDU_PRD_PKT_DROP_CNT_PORT(13).CDU0[0x172]=0
CDU_PRD_PKT_DROP_CNT_PORT(14).CDU0[0x173]=0
CDU_PRD_PKT_DROP_CNT_PORT(15).CDU0[0x174]=0
CDU_PRD_PKT_DROP_CNT_PORT(0).CDU1[0x165]=0
CDU_PRD_PKT_DROP_CNT_PORT(1).CDU1[0x166]=0
CDU_PRD_PKT_DROP_CNT_PORT(2).CDU1[0x167]=0
CDU_PRD_PKT_DROP_CNT_PORT(3).CDU1[0x168]=0
CDU_PRD_PKT_DROP_CNT_PORT(4).CDU1[0x169]=0
CDU_PRD_PKT_DROP_CNT_PORT(5).CDU1[0x16a]=0
CDU_PRD_PKT_DROP_CNT_PORT(6).CDU1[0x16b]=0
CDU_PRD_PKT_DROP_CNT_PORT(7).CDU1[0x16c]=0
CDU_PRD_PKT_DROP_CNT_PORT(8).CDU1[0x16d]=0
CDU_PRD_PKT_DROP_CNT_PORT(9).CDU1[0x16e]=0
CDU_PRD_PKT_DROP_CNT_PORT(10).CDU1[0x16f]=0
CDU_PRD_PKT_DROP_CNT_PORT(11).CDU1[0x170]=0
CDU_PRD_PKT_DROP_CNT_PORT(12).CDU1[0x171]=0
CDU_PRD_PKT_DROP_CNT_PORT(13).CDU1[0x172]=0
CDU_PRD_PKT_DROP_CNT_PORT(14).CDU1[0x173]=0
CDU_PRD_PKT_DROP_CNT_PORT(15).CDU1[0x174]=0
CDU_REG_0041.CDU0[0x41]=0
CDU_REG_0041.CDU1[0x41]=0
CDU_REG_00C2.CDU0[0xc2]=0x10
CDU_REG_00C2.CDU1[0xc2]=0x10
CDU_REG_00C4.CDU0[0xc4]=0
CDU_REG_00C4.CDU1[0xc4]=0
CDU_REG_03E9.CDU0[0x3e9]=0x2f40100
CDU_REG_03E9.CDU1[0x3e9]=0x2f40100
CDU_REG_03FC.CDU0[0x3fc]=0
CDU_REG_03FC.CDU1[0x3fc]=0
CDU_RESERVED_MTCD.CDU0[0xae]=0x30
CDU_RESERVED_MTCD.CDU1[0xae]=0x30
CDU_RESERVED_MTCP.CDU0[0xad]=0x300000600000000
CDU_RESERVED_MTCP.CDU1[0xad]=0x300000600000000
CDU_RESERVED_SPARE_0.CDU0[0x90]=0xffffffff
CDU_RESERVED_SPARE_0.CDU1[0x90]=0xffffffff
CDU_RESERVED_SPARE_1.CDU0[0x91]=0xffffffff
CDU_RESERVED_SPARE_1.CDU1[0x91]=0xffffffff
CDU_RESERVED_SPARE_2.CDU0[0x92]=0
CDU_RESERVED_SPARE_2.CDU1[0x92]=0
CDU_RESERVED_SPARE_3.CDU0[0x93]=0
CDU_RESERVED_SPARE_3.CDU1[0x93]=0
CDU_RE_EN_SAMP_CFG.CDU0[0x555]=2
CDU_RE_EN_SAMP_CFG.CDU1[0x555]=2
CDU_RUNT_PKT_CONFIG.CDU0[0x1ad]=3
CDU_RUNT_PKT_CONFIG.CDU1[0x1ad]=3
CDU_RX_FIFOS_SRSTN.CDU0[0x100]=0
CDU_RX_FIFOS_SRSTN.CDU1[0x100]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(0).CDU0[0x470]=1
CDU_RX_FIFOS_VECTOR_PER_PORT(1).CDU0[0x471]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(2).CDU0[0x472]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(3).CDU0[0x473]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(4).CDU0[0x474]=2
CDU_RX_FIFOS_VECTOR_PER_PORT(5).CDU0[0x475]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(6).CDU0[0x476]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(7).CDU0[0x477]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(0).CDU1[0x470]=2
CDU_RX_FIFOS_VECTOR_PER_PORT(1).CDU1[0x471]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(2).CDU1[0x472]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(3).CDU1[0x473]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(4).CDU1[0x474]=1
CDU_RX_FIFOS_VECTOR_PER_PORT(5).CDU1[0x475]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(6).CDU1[0x476]=0
CDU_RX_FIFOS_VECTOR_PER_PORT(7).CDU1[0x477]=0
CDU_RX_FIFO_RANGE_RMC_0.CDU0[0x460]=0xff000
CDU_RX_FIFO_RANGE_RMC_0.CDU1[0x460]=0x1ff100
CDU_RX_FIFO_RANGE_RMC_1.CDU0[0x461]=0x1ff100
CDU_RX_FIFO_RANGE_RMC_1.CDU1[0x461]=0xff000
CDU_RX_FIFO_RANGE_RMC_2.CDU0[0x462]=0x2ff200
CDU_RX_FIFO_RANGE_RMC_2.CDU1[0x462]=0x2ff200
CDU_RX_FIFO_RANGE_RMC_3.CDU0[0x463]=0x3ff300
CDU_RX_FIFO_RANGE_RMC_3.CDU1[0x463]=0x3ff300
CDU_RX_FIFO_RANGE_RMC_4.CDU0[0x464]=0x4ff400
CDU_RX_FIFO_RANGE_RMC_4.CDU1[0x464]=0x4ff400
CDU_RX_FIFO_RANGE_RMC_5.CDU0[0x465]=0x5ff500
CDU_RX_FIFO_RANGE_RMC_5.CDU1[0x465]=0x5ff500
CDU_RX_FIFO_RANGE_RMC_6.CDU0[0x466]=0x6ff600
CDU_RX_FIFO_RANGE_RMC_6.CDU1[0x466]=0x6ff600
CDU_RX_FIFO_RANGE_RMC_7.CDU0[0x467]=0x7ff700
CDU_RX_FIFO_RANGE_RMC_7.CDU1[0x467]=0x7ff700
CDU_RX_FIFO_RANGE_RMC_8.CDU0[0x468]=0x8ff800
CDU_RX_FIFO_RANGE_RMC_8.CDU1[0x468]=0x8ff800
CDU_RX_FIFO_RANGE_RMC_9.CDU0[0x469]=0x9ff900
CDU_RX_FIFO_RANGE_RMC_9.CDU1[0x469]=0x9ff900
CDU_RX_FIFO_RANGE_RMC_10.CDU0[0x46a]=0xaffa00
CDU_RX_FIFO_RANGE_RMC_10.CDU1[0x46a]=0xaffa00
CDU_RX_FIFO_RANGE_RMC_11.CDU0[0x46b]=0xbffb00
CDU_RX_FIFO_RANGE_RMC_11.CDU1[0x46b]=0xbffb00
CDU_RX_FIFO_RANGE_RMC_12.CDU0[0x46c]=0xcffc00
CDU_RX_FIFO_RANGE_RMC_12.CDU1[0x46c]=0xcffc00
CDU_RX_FIFO_RANGE_RMC_13.CDU0[0x46d]=0xdffd00
CDU_RX_FIFO_RANGE_RMC_13.CDU1[0x46d]=0xdffd00
CDU_RX_FIFO_RANGE_RMC_14.CDU0[0x46e]=0xeffe00
CDU_RX_FIFO_RANGE_RMC_14.CDU1[0x46e]=0xeffe00
CDU_RX_FIFO_RANGE_RMC_15.CDU0[0x46f]=0xffff00
CDU_RX_FIFO_RANGE_RMC_15.CDU1[0x46f]=0xffff00
CDU_RX_FLEXE_L_1_RATE_MISMATCH_CONFIG.CDU0[0x1af]=0x1e003c007800f001e003c007800f001e003c007800f001e003c007800f0000000000000000
CDU_RX_FLEXE_L_1_RATE_MISMATCH_CONFIG.CDU1[0x1af]=0x1e003c007800f001e003c007800f001e003c007800f001e003c007800f0000000000000000
CDU_RX_FLEXE_L_1_RATE_MISMATCH_DEBUG.CDU0[0x1b0]=0x438000000000000000
CDU_RX_FLEXE_L_1_RATE_MISMATCH_DEBUG.CDU1[0x1b0]=0x438000000000000000
CDU_RX_MISS_EOP_ERR_COUNTER(0).CDU0[0x3b9]=0
CDU_RX_MISS_EOP_ERR_COUNTER(1).CDU0[0x3ba]=0
CDU_RX_MISS_EOP_ERR_COUNTER(2).CDU0[0x3bb]=0
CDU_RX_MISS_EOP_ERR_COUNTER(3).CDU0[0x3bc]=0
CDU_RX_MISS_EOP_ERR_COUNTER(4).CDU0[0x3bd]=0
CDU_RX_MISS_EOP_ERR_COUNTER(5).CDU0[0x3be]=0
CDU_RX_MISS_EOP_ERR_COUNTER(6).CDU0[0x3bf]=0
CDU_RX_MISS_EOP_ERR_COUNTER(7).CDU0[0x3c0]=0
CDU_RX_MISS_EOP_ERR_COUNTER(8).CDU0[0x3c1]=0
CDU_RX_MISS_EOP_ERR_COUNTER(9).CDU0[0x3c2]=0
CDU_RX_MISS_EOP_ERR_COUNTER(10).CDU0[0x3c3]=0
CDU_RX_MISS_EOP_ERR_COUNTER(11).CDU0[0x3c4]=0
CDU_RX_MISS_EOP_ERR_COUNTER(12).CDU0[0x3c5]=0
CDU_RX_MISS_EOP_ERR_COUNTER(13).CDU0[0x3c6]=0
CDU_RX_MISS_EOP_ERR_COUNTER(14).CDU0[0x3c7]=0
CDU_RX_MISS_EOP_ERR_COUNTER(15).CDU0[0x3c8]=0
CDU_RX_MISS_EOP_ERR_COUNTER(0).CDU1[0x3b9]=0
CDU_RX_MISS_EOP_ERR_COUNTER(1).CDU1[0x3ba]=0
CDU_RX_MISS_EOP_ERR_COUNTER(2).CDU1[0x3bb]=0
CDU_RX_MISS_EOP_ERR_COUNTER(3).CDU1[0x3bc]=0
CDU_RX_MISS_EOP_ERR_COUNTER(4).CDU1[0x3bd]=0
CDU_RX_MISS_EOP_ERR_COUNTER(5).CDU1[0x3be]=0
CDU_RX_MISS_EOP_ERR_COUNTER(6).CDU1[0x3bf]=0
CDU_RX_MISS_EOP_ERR_COUNTER(7).CDU1[0x3c0]=0
CDU_RX_MISS_EOP_ERR_COUNTER(8).CDU1[0x3c1]=0
CDU_RX_MISS_EOP_ERR_COUNTER(9).CDU1[0x3c2]=0
CDU_RX_MISS_EOP_ERR_COUNTER(10).CDU1[0x3c3]=0
CDU_RX_MISS_EOP_ERR_COUNTER(11).CDU1[0x3c4]=0
CDU_RX_MISS_EOP_ERR_COUNTER(12).CDU1[0x3c5]=0
CDU_RX_MISS_EOP_ERR_COUNTER(13).CDU1[0x3c6]=0
CDU_RX_MISS_EOP_ERR_COUNTER(14).CDU1[0x3c7]=0
CDU_RX_MISS_EOP_ERR_COUNTER(15).CDU1[0x3c8]=0
CDU_RX_MISS_SOP_ERR_COUNTER(0).CDU0[0x3a9]=0
CDU_RX_MISS_SOP_ERR_COUNTER(1).CDU0[0x3aa]=0
CDU_RX_MISS_SOP_ERR_COUNTER(2).CDU0[0x3ab]=0
CDU_RX_MISS_SOP_ERR_COUNTER(3).CDU0[0x3ac]=0
CDU_RX_MISS_SOP_ERR_COUNTER(4).CDU0[0x3ad]=0
CDU_RX_MISS_SOP_ERR_COUNTER(5).CDU0[0x3ae]=0
CDU_RX_MISS_SOP_ERR_COUNTER(6).CDU0[0x3af]=0
CDU_RX_MISS_SOP_ERR_COUNTER(7).CDU0[0x3b0]=0
CDU_RX_MISS_SOP_ERR_COUNTER(8).CDU0[0x3b1]=0
CDU_RX_MISS_SOP_ERR_COUNTER(9).CDU0[0x3b2]=0
CDU_RX_MISS_SOP_ERR_COUNTER(10).CDU0[0x3b3]=0
CDU_RX_MISS_SOP_ERR_COUNTER(11).CDU0[0x3b4]=0
CDU_RX_MISS_SOP_ERR_COUNTER(12).CDU0[0x3b5]=0
CDU_RX_MISS_SOP_ERR_COUNTER(13).CDU0[0x3b6]=0
CDU_RX_MISS_SOP_ERR_COUNTER(14).CDU0[0x3b7]=0
CDU_RX_MISS_SOP_ERR_COUNTER(15).CDU0[0x3b8]=0
CDU_RX_MISS_SOP_ERR_COUNTER(0).CDU1[0x3a9]=0
CDU_RX_MISS_SOP_ERR_COUNTER(1).CDU1[0x3aa]=0
CDU_RX_MISS_SOP_ERR_COUNTER(2).CDU1[0x3ab]=0
CDU_RX_MISS_SOP_ERR_COUNTER(3).CDU1[0x3ac]=0
CDU_RX_MISS_SOP_ERR_COUNTER(4).CDU1[0x3ad]=0
CDU_RX_MISS_SOP_ERR_COUNTER(5).CDU1[0x3ae]=0
CDU_RX_MISS_SOP_ERR_COUNTER(6).CDU1[0x3af]=0
CDU_RX_MISS_SOP_ERR_COUNTER(7).CDU1[0x3b0]=0
CDU_RX_MISS_SOP_ERR_COUNTER(8).CDU1[0x3b1]=0
CDU_RX_MISS_SOP_ERR_COUNTER(9).CDU1[0x3b2]=0
CDU_RX_MISS_SOP_ERR_COUNTER(10).CDU1[0x3b3]=0
CDU_RX_MISS_SOP_ERR_COUNTER(11).CDU1[0x3b4]=0
CDU_RX_MISS_SOP_ERR_COUNTER(12).CDU1[0x3b5]=0
CDU_RX_MISS_SOP_ERR_COUNTER(13).CDU1[0x3b6]=0
CDU_RX_MISS_SOP_ERR_COUNTER(14).CDU1[0x3b7]=0
CDU_RX_MISS_SOP_ERR_COUNTER(15).CDU1[0x3b8]=0
CDU_RX_MLF_CONFIG.CDU0[0x1ae]=3
CDU_RX_MLF_CONFIG.CDU1[0x1ae]=3
CDU_RX_MLF_CTRL_PKT_DROP(0).CDU0[0x18c]=0
CDU_RX_MLF_CTRL_PKT_DROP(1).CDU0[0x18d]=0
CDU_RX_MLF_CTRL_PKT_DROP(2).CDU0[0x18e]=0
CDU_RX_MLF_CTRL_PKT_DROP(3).CDU0[0x18f]=0
CDU_RX_MLF_CTRL_PKT_DROP(4).CDU0[0x190]=0
CDU_RX_MLF_CTRL_PKT_DROP(5).CDU0[0x191]=0
CDU_RX_MLF_CTRL_PKT_DROP(6).CDU0[0x192]=0
CDU_RX_MLF_CTRL_PKT_DROP(7).CDU0[0x193]=0
CDU_RX_MLF_CTRL_PKT_DROP(8).CDU0[0x194]=0
CDU_RX_MLF_CTRL_PKT_DROP(9).CDU0[0x195]=0
CDU_RX_MLF_CTRL_PKT_DROP(10).CDU0[0x196]=0
CDU_RX_MLF_CTRL_PKT_DROP(11).CDU0[0x197]=0
CDU_RX_MLF_CTRL_PKT_DROP(12).CDU0[0x198]=0
CDU_RX_MLF_CTRL_PKT_DROP(13).CDU0[0x199]=0
CDU_RX_MLF_CTRL_PKT_DROP(14).CDU0[0x19a]=0
CDU_RX_MLF_CTRL_PKT_DROP(15).CDU0[0x19b]=0
CDU_RX_MLF_CTRL_PKT_DROP(0).CDU1[0x18c]=0
CDU_RX_MLF_CTRL_PKT_DROP(1).CDU1[0x18d]=0
CDU_RX_MLF_CTRL_PKT_DROP(2).CDU1[0x18e]=0
CDU_RX_MLF_CTRL_PKT_DROP(3).CDU1[0x18f]=0
CDU_RX_MLF_CTRL_PKT_DROP(4).CDU1[0x190]=0
CDU_RX_MLF_CTRL_PKT_DROP(5).CDU1[0x191]=0
CDU_RX_MLF_CTRL_PKT_DROP(6).CDU1[0x192]=0
CDU_RX_MLF_CTRL_PKT_DROP(7).CDU1[0x193]=0
CDU_RX_MLF_CTRL_PKT_DROP(8).CDU1[0x194]=0
CDU_RX_MLF_CTRL_PKT_DROP(9).CDU1[0x195]=0
CDU_RX_MLF_CTRL_PKT_DROP(10).CDU1[0x196]=0
CDU_RX_MLF_CTRL_PKT_DROP(11).CDU1[0x197]=0
CDU_RX_MLF_CTRL_PKT_DROP(12).CDU1[0x198]=0
CDU_RX_MLF_CTRL_PKT_DROP(13).CDU1[0x199]=0
CDU_RX_MLF_CTRL_PKT_DROP(14).CDU1[0x19a]=0
CDU_RX_MLF_CTRL_PKT_DROP(15).CDU1[0x19b]=0
CDU_RX_MLF_DROP_ALL_DATA(0).CDU0[0x19d]=0
CDU_RX_MLF_DROP_ALL_DATA(1).CDU0[0x19e]=0
CDU_RX_MLF_DROP_ALL_DATA(2).CDU0[0x19f]=0
CDU_RX_MLF_DROP_ALL_DATA(3).CDU0[0x1a0]=0
CDU_RX_MLF_DROP_ALL_DATA(4).CDU0[0x1a1]=0
CDU_RX_MLF_DROP_ALL_DATA(5).CDU0[0x1a2]=0
CDU_RX_MLF_DROP_ALL_DATA(6).CDU0[0x1a3]=0
CDU_RX_MLF_DROP_ALL_DATA(7).CDU0[0x1a4]=0
CDU_RX_MLF_DROP_ALL_DATA(8).CDU0[0x1a5]=0
CDU_RX_MLF_DROP_ALL_DATA(9).CDU0[0x1a6]=0
CDU_RX_MLF_DROP_ALL_DATA(10).CDU0[0x1a7]=0
CDU_RX_MLF_DROP_ALL_DATA(11).CDU0[0x1a8]=0
CDU_RX_MLF_DROP_ALL_DATA(12).CDU0[0x1a9]=0
CDU_RX_MLF_DROP_ALL_DATA(13).CDU0[0x1aa]=0
CDU_RX_MLF_DROP_ALL_DATA(14).CDU0[0x1ab]=0
CDU_RX_MLF_DROP_ALL_DATA(15).CDU0[0x1ac]=0
CDU_RX_MLF_DROP_ALL_DATA(0).CDU1[0x19d]=0
CDU_RX_MLF_DROP_ALL_DATA(1).CDU1[0x19e]=0
CDU_RX_MLF_DROP_ALL_DATA(2).CDU1[0x19f]=0
CDU_RX_MLF_DROP_ALL_DATA(3).CDU1[0x1a0]=0
CDU_RX_MLF_DROP_ALL_DATA(4).CDU1[0x1a1]=0
CDU_RX_MLF_DROP_ALL_DATA(5).CDU1[0x1a2]=0
CDU_RX_MLF_DROP_ALL_DATA(6).CDU1[0x1a3]=0
CDU_RX_MLF_DROP_ALL_DATA(7).CDU1[0x1a4]=0
CDU_RX_MLF_DROP_ALL_DATA(8).CDU1[0x1a5]=0
CDU_RX_MLF_DROP_ALL_DATA(9).CDU1[0x1a6]=0
CDU_RX_MLF_DROP_ALL_DATA(10).CDU1[0x1a7]=0
CDU_RX_MLF_DROP_ALL_DATA(11).CDU1[0x1a8]=0
CDU_RX_MLF_DROP_ALL_DATA(12).CDU1[0x1a9]=0
CDU_RX_MLF_DROP_ALL_DATA(13).CDU1[0x1aa]=0
CDU_RX_MLF_DROP_ALL_DATA(14).CDU1[0x1ab]=0
CDU_RX_MLF_DROP_ALL_DATA(15).CDU1[0x1ac]=0
CDU_RX_MLF_LEVEL(0).CDU0[0x20a]=0
CDU_RX_MLF_LEVEL(1).CDU0[0x20c]=0
CDU_RX_MLF_LEVEL(2).CDU0[0x20e]=0
CDU_RX_MLF_LEVEL(3).CDU0[0x210]=0
CDU_RX_MLF_LEVEL(4).CDU0[0x212]=0
CDU_RX_MLF_LEVEL(5).CDU0[0x214]=0
CDU_RX_MLF_LEVEL(6).CDU0[0x216]=0
CDU_RX_MLF_LEVEL(7).CDU0[0x218]=0
CDU_RX_MLF_LEVEL(8).CDU0[0x21a]=0
CDU_RX_MLF_LEVEL(9).CDU0[0x21c]=0
CDU_RX_MLF_LEVEL(10).CDU0[0x21e]=0
CDU_RX_MLF_LEVEL(11).CDU0[0x220]=0
CDU_RX_MLF_LEVEL(12).CDU0[0x222]=0
CDU_RX_MLF_LEVEL(13).CDU0[0x224]=0
CDU_RX_MLF_LEVEL(14).CDU0[0x226]=0
CDU_RX_MLF_LEVEL(15).CDU0[0x228]=0
CDU_RX_MLF_LEVEL(0).CDU1[0x20a]=0
CDU_RX_MLF_LEVEL(1).CDU1[0x20c]=0
CDU_RX_MLF_LEVEL(2).CDU1[0x20e]=0
CDU_RX_MLF_LEVEL(3).CDU1[0x210]=0
CDU_RX_MLF_LEVEL(4).CDU1[0x212]=0
CDU_RX_MLF_LEVEL(5).CDU1[0x214]=0
CDU_RX_MLF_LEVEL(6).CDU1[0x216]=0
CDU_RX_MLF_LEVEL(7).CDU1[0x218]=0
CDU_RX_MLF_LEVEL(8).CDU1[0x21a]=0
CDU_RX_MLF_LEVEL(9).CDU1[0x21c]=0
CDU_RX_MLF_LEVEL(10).CDU1[0x21e]=0
CDU_RX_MLF_LEVEL(11).CDU1[0x220]=0
CDU_RX_MLF_LEVEL(12).CDU1[0x222]=0
CDU_RX_MLF_LEVEL(13).CDU1[0x224]=0
CDU_RX_MLF_LEVEL(14).CDU1[0x226]=0
CDU_RX_MLF_LEVEL(15).CDU1[0x228]=0
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(0).CDU0[0x1ca]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(1).CDU0[0x1cb]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(2).CDU0[0x1cc]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(3).CDU0[0x1cd]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(4).CDU0[0x1ce]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(5).CDU0[0x1cf]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(6).CDU0[0x1d0]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(7).CDU0[0x1d1]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(8).CDU0[0x1d2]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(9).CDU0[0x1d3]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(10).CDU0[0x1d4]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(11).CDU0[0x1d5]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(12).CDU0[0x1d6]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(13).CDU0[0x1d7]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(14).CDU0[0x1d8]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(15).CDU0[0x1d9]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(0).CDU1[0x1ca]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(1).CDU1[0x1cb]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(2).CDU1[0x1cc]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(3).CDU1[0x1cd]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(4).CDU1[0x1ce]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(5).CDU1[0x1cf]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(6).CDU1[0x1d0]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(7).CDU1[0x1d1]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(8).CDU1[0x1d2]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(9).CDU1[0x1d3]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(10).CDU1[0x1d4]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(11).CDU1[0x1d5]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(12).CDU1[0x1d6]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(13).CDU1[0x1d7]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(14).CDU1[0x1d8]=0x7e0200
CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(15).CDU1[0x1d9]=0x7e0200
CDU_RX_MLF_MAX_OCCUPANCY.CDU0[0x22a]=0
CDU_RX_MLF_MAX_OCCUPANCY.CDU1[0x22a]=0
CDU_RX_MLF_OVERFLOW(0).CDU0[0x1fa]=0
CDU_RX_MLF_OVERFLOW(1).CDU0[0x1fb]=0
CDU_RX_MLF_OVERFLOW(2).CDU0[0x1fc]=0
CDU_RX_MLF_OVERFLOW(3).CDU0[0x1fd]=0
CDU_RX_MLF_OVERFLOW(4).CDU0[0x1fe]=0
CDU_RX_MLF_OVERFLOW(5).CDU0[0x1ff]=0
CDU_RX_MLF_OVERFLOW(6).CDU0[0x200]=0
CDU_RX_MLF_OVERFLOW(7).CDU0[0x201]=0
CDU_RX_MLF_OVERFLOW(8).CDU0[0x202]=0
CDU_RX_MLF_OVERFLOW(9).CDU0[0x203]=0
CDU_RX_MLF_OVERFLOW(10).CDU0[0x204]=0
CDU_RX_MLF_OVERFLOW(11).CDU0[0x205]=0
CDU_RX_MLF_OVERFLOW(12).CDU0[0x206]=0
CDU_RX_MLF_OVERFLOW(13).CDU0[0x207]=0
CDU_RX_MLF_OVERFLOW(14).CDU0[0x208]=0
CDU_RX_MLF_OVERFLOW(15).CDU0[0x209]=0
CDU_RX_MLF_OVERFLOW(0).CDU1[0x1fa]=0
CDU_RX_MLF_OVERFLOW(1).CDU1[0x1fb]=0
CDU_RX_MLF_OVERFLOW(2).CDU1[0x1fc]=0
CDU_RX_MLF_OVERFLOW(3).CDU1[0x1fd]=0
CDU_RX_MLF_OVERFLOW(4).CDU1[0x1fe]=0
CDU_RX_MLF_OVERFLOW(5).CDU1[0x1ff]=0
CDU_RX_MLF_OVERFLOW(6).CDU1[0x200]=0
CDU_RX_MLF_OVERFLOW(7).CDU1[0x201]=0
CDU_RX_MLF_OVERFLOW(8).CDU1[0x202]=0
CDU_RX_MLF_OVERFLOW(9).CDU1[0x203]=0
CDU_RX_MLF_OVERFLOW(10).CDU1[0x204]=0
CDU_RX_MLF_OVERFLOW(11).CDU1[0x205]=0
CDU_RX_MLF_OVERFLOW(12).CDU1[0x206]=0
CDU_RX_MLF_OVERFLOW(13).CDU1[0x207]=0
CDU_RX_MLF_OVERFLOW(14).CDU1[0x208]=0
CDU_RX_MLF_OVERFLOW(15).CDU1[0x209]=0
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(0).CDU0[0x1da]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(1).CDU0[0x1db]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(2).CDU0[0x1dc]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(3).CDU0[0x1dd]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(4).CDU0[0x1de]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(5).CDU0[0x1df]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(6).CDU0[0x1e0]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(7).CDU0[0x1e1]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(8).CDU0[0x1e2]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(9).CDU0[0x1e3]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(10).CDU0[0x1e4]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(11).CDU0[0x1e5]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(12).CDU0[0x1e6]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(13).CDU0[0x1e7]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(14).CDU0[0x1e8]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(15).CDU0[0x1e9]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(0).CDU1[0x1da]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(1).CDU1[0x1db]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(2).CDU1[0x1dc]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(3).CDU1[0x1dd]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(4).CDU1[0x1de]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(5).CDU1[0x1df]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(6).CDU1[0x1e0]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(7).CDU1[0x1e1]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(8).CDU1[0x1e2]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(9).CDU1[0x1e3]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(10).CDU1[0x1e4]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(11).CDU1[0x1e5]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(12).CDU1[0x1e6]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(13).CDU1[0x1e7]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(14).CDU1[0x1e8]=0x49012c
CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(15).CDU1[0x1e9]=0x49012c
CDU_RX_MLF_UNDERFLOW(0).CDU0[0x1ea]=0
CDU_RX_MLF_UNDERFLOW(1).CDU0[0x1eb]=0
CDU_RX_MLF_UNDERFLOW(2).CDU0[0x1ec]=0
CDU_RX_MLF_UNDERFLOW(3).CDU0[0x1ed]=0
CDU_RX_MLF_UNDERFLOW(4).CDU0[0x1ee]=0
CDU_RX_MLF_UNDERFLOW(5).CDU0[0x1ef]=0
CDU_RX_MLF_UNDERFLOW(6).CDU0[0x1f0]=0
CDU_RX_MLF_UNDERFLOW(7).CDU0[0x1f1]=0
CDU_RX_MLF_UNDERFLOW(8).CDU0[0x1f2]=0
CDU_RX_MLF_UNDERFLOW(9).CDU0[0x1f3]=0
CDU_RX_MLF_UNDERFLOW(10).CDU0[0x1f4]=0
CDU_RX_MLF_UNDERFLOW(11).CDU0[0x1f5]=0
CDU_RX_MLF_UNDERFLOW(12).CDU0[0x1f6]=0
CDU_RX_MLF_UNDERFLOW(13).CDU0[0x1f7]=0
CDU_RX_MLF_UNDERFLOW(14).CDU0[0x1f8]=0
CDU_RX_MLF_UNDERFLOW(15).CDU0[0x1f9]=0
CDU_RX_MLF_UNDERFLOW(0).CDU1[0x1ea]=0
CDU_RX_MLF_UNDERFLOW(1).CDU1[0x1eb]=0
CDU_RX_MLF_UNDERFLOW(2).CDU1[0x1ec]=0
CDU_RX_MLF_UNDERFLOW(3).CDU1[0x1ed]=0
CDU_RX_MLF_UNDERFLOW(4).CDU1[0x1ee]=0
CDU_RX_MLF_UNDERFLOW(5).CDU1[0x1ef]=0
CDU_RX_MLF_UNDERFLOW(6).CDU1[0x1f0]=0
CDU_RX_MLF_UNDERFLOW(7).CDU1[0x1f1]=0
CDU_RX_MLF_UNDERFLOW(8).CDU1[0x1f2]=0
CDU_RX_MLF_UNDERFLOW(9).CDU1[0x1f3]=0
CDU_RX_MLF_UNDERFLOW(10).CDU1[0x1f4]=0
CDU_RX_MLF_UNDERFLOW(11).CDU1[0x1f5]=0
CDU_RX_MLF_UNDERFLOW(12).CDU1[0x1f6]=0
CDU_RX_MLF_UNDERFLOW(13).CDU1[0x1f7]=0
CDU_RX_MLF_UNDERFLOW(14).CDU1[0x1f8]=0
CDU_RX_MLF_UNDERFLOW(15).CDU1[0x1f9]=0
CDU_RX_NUM_TOTAL_DROPPED_EOPS.CDU0[0x337]=0
CDU_RX_NUM_TOTAL_DROPPED_EOPS.CDU1[0x337]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(0).CDU0[0x379]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(1).CDU0[0x37a]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(2).CDU0[0x37b]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(3).CDU0[0x37c]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(4).CDU0[0x37d]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(5).CDU0[0x37e]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(6).CDU0[0x37f]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(7).CDU0[0x380]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(8).CDU0[0x381]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(9).CDU0[0x382]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(10).CDU0[0x383]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(11).CDU0[0x384]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(12).CDU0[0x385]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(13).CDU0[0x386]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(14).CDU0[0x387]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(15).CDU0[0x388]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(0).CDU1[0x379]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(1).CDU1[0x37a]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(2).CDU1[0x37b]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(3).CDU1[0x37c]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(4).CDU1[0x37d]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(5).CDU1[0x37e]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(6).CDU1[0x37f]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(7).CDU1[0x380]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(8).CDU1[0x381]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(9).CDU1[0x382]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(10).CDU1[0x383]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(11).CDU1[0x384]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(12).CDU1[0x385]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(13).CDU1[0x386]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(14).CDU1[0x387]=0
CDU_RX_PKT_CTRL_DROP_COUNTER(15).CDU1[0x388]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(0).CDU0[0x389]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(1).CDU0[0x38a]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(2).CDU0[0x38b]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(3).CDU0[0x38c]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(4).CDU0[0x38d]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(5).CDU0[0x38e]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(6).CDU0[0x38f]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(7).CDU0[0x390]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(8).CDU0[0x391]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(9).CDU0[0x392]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(10).CDU0[0x393]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(11).CDU0[0x394]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(12).CDU0[0x395]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(13).CDU0[0x396]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(14).CDU0[0x397]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(15).CDU0[0x398]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(0).CDU1[0x389]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(1).CDU1[0x38a]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(2).CDU1[0x38b]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(3).CDU1[0x38c]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(4).CDU1[0x38d]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(5).CDU1[0x38e]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(6).CDU1[0x38f]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(7).CDU1[0x390]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(8).CDU1[0x391]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(9).CDU1[0x392]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(10).CDU1[0x393]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(11).CDU1[0x394]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(12).CDU1[0x395]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(13).CDU1[0x396]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(14).CDU1[0x397]=0
CDU_RX_PKT_CTRL_NON_DROP_COUNTER(15).CDU1[0x398]=0
CDU_RX_PKT_DROP_COUNTER(0).CDU0[0x339]=0
CDU_RX_PKT_DROP_COUNTER(1).CDU0[0x33a]=0
CDU_RX_PKT_DROP_COUNTER(2).CDU0[0x33b]=0
CDU_RX_PKT_DROP_COUNTER(3).CDU0[0x33c]=0
CDU_RX_PKT_DROP_COUNTER(4).CDU0[0x33d]=0
CDU_RX_PKT_DROP_COUNTER(5).CDU0[0x33e]=0
CDU_RX_PKT_DROP_COUNTER(6).CDU0[0x33f]=0
CDU_RX_PKT_DROP_COUNTER(7).CDU0[0x340]=0
CDU_RX_PKT_DROP_COUNTER(8).CDU0[0x341]=0
CDU_RX_PKT_DROP_COUNTER(9).CDU0[0x342]=0
CDU_RX_PKT_DROP_COUNTER(10).CDU0[0x343]=0
CDU_RX_PKT_DROP_COUNTER(11).CDU0[0x344]=0
CDU_RX_PKT_DROP_COUNTER(12).CDU0[0x345]=0
CDU_RX_PKT_DROP_COUNTER(13).CDU0[0x346]=0
CDU_RX_PKT_DROP_COUNTER(14).CDU0[0x347]=0
CDU_RX_PKT_DROP_COUNTER(15).CDU0[0x348]=0
CDU_RX_PKT_DROP_COUNTER(0).CDU1[0x339]=0
CDU_RX_PKT_DROP_COUNTER(1).CDU1[0x33a]=0
CDU_RX_PKT_DROP_COUNTER(2).CDU1[0x33b]=0
CDU_RX_PKT_DROP_COUNTER(3).CDU1[0x33c]=0
CDU_RX_PKT_DROP_COUNTER(4).CDU1[0x33d]=0
CDU_RX_PKT_DROP_COUNTER(5).CDU1[0x33e]=0
CDU_RX_PKT_DROP_COUNTER(6).CDU1[0x33f]=0
CDU_RX_PKT_DROP_COUNTER(7).CDU1[0x340]=0
CDU_RX_PKT_DROP_COUNTER(8).CDU1[0x341]=0
CDU_RX_PKT_DROP_COUNTER(9).CDU1[0x342]=0
CDU_RX_PKT_DROP_COUNTER(10).CDU1[0x343]=0
CDU_RX_PKT_DROP_COUNTER(11).CDU1[0x344]=0
CDU_RX_PKT_DROP_COUNTER(12).CDU1[0x345]=0
CDU_RX_PKT_DROP_COUNTER(13).CDU1[0x346]=0
CDU_RX_PKT_DROP_COUNTER(14).CDU1[0x347]=0
CDU_RX_PKT_DROP_COUNTER(15).CDU1[0x348]=0
CDU_RX_PKT_OVF_DROP_COUNTER(0).CDU0[0x369]=0
CDU_RX_PKT_OVF_DROP_COUNTER(1).CDU0[0x36a]=0
CDU_RX_PKT_OVF_DROP_COUNTER(2).CDU0[0x36b]=0
CDU_RX_PKT_OVF_DROP_COUNTER(3).CDU0[0x36c]=0
CDU_RX_PKT_OVF_DROP_COUNTER(4).CDU0[0x36d]=0
CDU_RX_PKT_OVF_DROP_COUNTER(5).CDU0[0x36e]=0
CDU_RX_PKT_OVF_DROP_COUNTER(6).CDU0[0x36f]=0
CDU_RX_PKT_OVF_DROP_COUNTER(7).CDU0[0x370]=0
CDU_RX_PKT_OVF_DROP_COUNTER(8).CDU0[0x371]=0
CDU_RX_PKT_OVF_DROP_COUNTER(9).CDU0[0x372]=0
CDU_RX_PKT_OVF_DROP_COUNTER(10).CDU0[0x373]=0
CDU_RX_PKT_OVF_DROP_COUNTER(11).CDU0[0x374]=0
CDU_RX_PKT_OVF_DROP_COUNTER(12).CDU0[0x375]=0
CDU_RX_PKT_OVF_DROP_COUNTER(13).CDU0[0x376]=0
CDU_RX_PKT_OVF_DROP_COUNTER(14).CDU0[0x377]=0
CDU_RX_PKT_OVF_DROP_COUNTER(15).CDU0[0x378]=0
CDU_RX_PKT_OVF_DROP_COUNTER(0).CDU1[0x369]=0
CDU_RX_PKT_OVF_DROP_COUNTER(1).CDU1[0x36a]=0
CDU_RX_PKT_OVF_DROP_COUNTER(2).CDU1[0x36b]=0
CDU_RX_PKT_OVF_DROP_COUNTER(3).CDU1[0x36c]=0
CDU_RX_PKT_OVF_DROP_COUNTER(4).CDU1[0x36d]=0
CDU_RX_PKT_OVF_DROP_COUNTER(5).CDU1[0x36e]=0
CDU_RX_PKT_OVF_DROP_COUNTER(6).CDU1[0x36f]=0
CDU_RX_PKT_OVF_DROP_COUNTER(7).CDU1[0x370]=0
CDU_RX_PKT_OVF_DROP_COUNTER(8).CDU1[0x371]=0
CDU_RX_PKT_OVF_DROP_COUNTER(9).CDU1[0x372]=0
CDU_RX_PKT_OVF_DROP_COUNTER(10).CDU1[0x373]=0
CDU_RX_PKT_OVF_DROP_COUNTER(11).CDU1[0x374]=0
CDU_RX_PKT_OVF_DROP_COUNTER(12).CDU1[0x375]=0
CDU_RX_PKT_OVF_DROP_COUNTER(13).CDU1[0x376]=0
CDU_RX_PKT_OVF_DROP_COUNTER(14).CDU1[0x377]=0
CDU_RX_PKT_OVF_DROP_COUNTER(15).CDU1[0x378]=0
CDU_RX_PKT_PRD_DROP_COUNTER(0).CDU0[0x359]=0
CDU_RX_PKT_PRD_DROP_COUNTER(1).CDU0[0x35a]=0
CDU_RX_PKT_PRD_DROP_COUNTER(2).CDU0[0x35b]=0
CDU_RX_PKT_PRD_DROP_COUNTER(3).CDU0[0x35c]=0
CDU_RX_PKT_PRD_DROP_COUNTER(4).CDU0[0x35d]=0
CDU_RX_PKT_PRD_DROP_COUNTER(5).CDU0[0x35e]=0
CDU_RX_PKT_PRD_DROP_COUNTER(6).CDU0[0x35f]=0
CDU_RX_PKT_PRD_DROP_COUNTER(7).CDU0[0x360]=0
CDU_RX_PKT_PRD_DROP_COUNTER(8).CDU0[0x361]=0
CDU_RX_PKT_PRD_DROP_COUNTER(9).CDU0[0x362]=0
CDU_RX_PKT_PRD_DROP_COUNTER(10).CDU0[0x363]=0
CDU_RX_PKT_PRD_DROP_COUNTER(11).CDU0[0x364]=0
CDU_RX_PKT_PRD_DROP_COUNTER(12).CDU0[0x365]=0
CDU_RX_PKT_PRD_DROP_COUNTER(13).CDU0[0x366]=0
CDU_RX_PKT_PRD_DROP_COUNTER(14).CDU0[0x367]=0
CDU_RX_PKT_PRD_DROP_COUNTER(15).CDU0[0x368]=0
CDU_RX_PKT_PRD_DROP_COUNTER(0).CDU1[0x359]=0
CDU_RX_PKT_PRD_DROP_COUNTER(1).CDU1[0x35a]=0
CDU_RX_PKT_PRD_DROP_COUNTER(2).CDU1[0x35b]=0
CDU_RX_PKT_PRD_DROP_COUNTER(3).CDU1[0x35c]=0
CDU_RX_PKT_PRD_DROP_COUNTER(4).CDU1[0x35d]=0
CDU_RX_PKT_PRD_DROP_COUNTER(5).CDU1[0x35e]=0
CDU_RX_PKT_PRD_DROP_COUNTER(6).CDU1[0x35f]=0
CDU_RX_PKT_PRD_DROP_COUNTER(7).CDU1[0x360]=0
CDU_RX_PKT_PRD_DROP_COUNTER(8).CDU1[0x361]=0
CDU_RX_PKT_PRD_DROP_COUNTER(9).CDU1[0x362]=0
CDU_RX_PKT_PRD_DROP_COUNTER(10).CDU1[0x363]=0
CDU_RX_PKT_PRD_DROP_COUNTER(11).CDU1[0x364]=0
CDU_RX_PKT_PRD_DROP_COUNTER(12).CDU1[0x365]=0
CDU_RX_PKT_PRD_DROP_COUNTER(13).CDU1[0x366]=0
CDU_RX_PKT_PRD_DROP_COUNTER(14).CDU1[0x367]=0
CDU_RX_PKT_PRD_DROP_COUNTER(15).CDU1[0x368]=0
CDU_RX_PORT_0_MAP_TO_RMC.CDU0[0x448]=0x1084210
CDU_RX_PORT_0_MAP_TO_RMC.CDU1[0x448]=0x118c631
CDU_RX_PORT_1_MAP_TO_RMC.CDU0[0x449]=0x210842
CDU_RX_PORT_1_MAP_TO_RMC.CDU1[0x449]=0x210842
CDU_RX_PORT_2_MAP_TO_RMC.CDU0[0x44a]=0x421084
CDU_RX_PORT_2_MAP_TO_RMC.CDU1[0x44a]=0x421084
CDU_RX_PORT_3_MAP_TO_RMC.CDU0[0x44b]=0x6318c6
CDU_RX_PORT_3_MAP_TO_RMC.CDU1[0x44b]=0x6318c6
CDU_RX_PORT_4_MAP_TO_RMC.CDU0[0x44c]=0x118c631
CDU_RX_PORT_4_MAP_TO_RMC.CDU1[0x44c]=0x1084210
CDU_RX_PORT_5_MAP_TO_RMC.CDU0[0x44d]=0xa5294a
CDU_RX_PORT_5_MAP_TO_RMC.CDU1[0x44d]=0xa5294a
CDU_RX_PORT_6_MAP_TO_RMC.CDU0[0x44e]=0xc6318c
CDU_RX_PORT_6_MAP_TO_RMC.CDU1[0x44e]=0xc6318c
CDU_RX_PORT_7_MAP_TO_RMC.CDU0[0x44f]=0xe739ce
CDU_RX_PORT_7_MAP_TO_RMC.CDU1[0x44f]=0xe739ce
CDU_RX_PORT_MAP_IS_INVALID(0).CDU0[0x3ff]=0
CDU_RX_PORT_MAP_IS_INVALID(1).CDU0[0x400]=0
CDU_RX_PORT_MAP_IS_INVALID(2).CDU0[0x401]=0
CDU_RX_PORT_MAP_IS_INVALID(3).CDU0[0x402]=0
CDU_RX_PORT_MAP_IS_INVALID(4).CDU0[0x403]=0
CDU_RX_PORT_MAP_IS_INVALID(5).CDU0[0x404]=0
CDU_RX_PORT_MAP_IS_INVALID(6).CDU0[0x405]=0
CDU_RX_PORT_MAP_IS_INVALID(7).CDU0[0x406]=0
CDU_RX_PORT_MAP_IS_INVALID(0).CDU1[0x3ff]=0
CDU_RX_PORT_MAP_IS_INVALID(1).CDU1[0x400]=0
CDU_RX_PORT_MAP_IS_INVALID(2).CDU1[0x401]=0
CDU_RX_PORT_MAP_IS_INVALID(3).CDU1[0x402]=0
CDU_RX_PORT_MAP_IS_INVALID(4).CDU1[0x403]=0
CDU_RX_PORT_MAP_IS_INVALID(5).CDU1[0x404]=0
CDU_RX_PORT_MAP_IS_INVALID(6).CDU1[0x405]=0
CDU_RX_PORT_MAP_IS_INVALID(7).CDU1[0x406]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(0).CDU0[0x41f]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(1).CDU0[0x420]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(2).CDU0[0x421]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(3).CDU0[0x422]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(4).CDU0[0x423]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(5).CDU0[0x424]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(6).CDU0[0x425]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(7).CDU0[0x426]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(0).CDU1[0x41f]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(1).CDU1[0x420]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(2).CDU1[0x421]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(3).CDU1[0x422]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(4).CDU1[0x423]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(5).CDU1[0x424]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(6).CDU1[0x425]=0
CDU_RX_PORT_MAP_IS_INVALID_PARAM(7).CDU1[0x426]=0
CDU_RX_PORT_MAP_MASK_PARSER_TDM.CDU0[0x447]=6
CDU_RX_PORT_MAP_MASK_PARSER_TDM.CDU1[0x447]=6
CDU_RX_PORT_OVF.CDU0[0x262]=0
CDU_RX_PORT_OVF.CDU1[0x262]=0
CDU_RX_REQ_LOW_RMC_EN.CDU0[0x53d]=0x3ffff
CDU_RX_REQ_LOW_RMC_EN.CDU1[0x53d]=0x3ffff
CDU_RX_RMC_0_MAP.CDU0[0x450]=0
CDU_RX_RMC_0_MAP.CDU1[0x450]=4
CDU_RX_RMC_0_PRD_THRESHOLDS_CONFIG.CDU0[0x22c]=0x7ffefffdfffbfff
CDU_RX_RMC_0_PRD_THRESHOLDS_CONFIG.CDU1[0x22c]=0x7ffefffdfffbfff
CDU_RX_RMC_10_MAP.CDU0[0x45a]=5
CDU_RX_RMC_10_MAP.CDU1[0x45a]=5
CDU_RX_RMC_10_PRD_THRESHOLDS_CONFIG.CDU0[0x240]=0x7ffefffdfffbfff
CDU_RX_RMC_10_PRD_THRESHOLDS_CONFIG.CDU1[0x240]=0x7ffefffdfffbfff
CDU_RX_RMC_11_MAP.CDU0[0x45b]=5
CDU_RX_RMC_11_MAP.CDU1[0x45b]=5
CDU_RX_RMC_11_PRD_THRESHOLDS_CONFIG.CDU0[0x242]=0x7ffefffdfffbfff
CDU_RX_RMC_11_PRD_THRESHOLDS_CONFIG.CDU1[0x242]=0x7ffefffdfffbfff
CDU_RX_RMC_12_MAP.CDU0[0x45c]=6
CDU_RX_RMC_12_MAP.CDU1[0x45c]=6
CDU_RX_RMC_12_PRD_THRESHOLDS_CONFIG.CDU0[0x244]=0x7ffefffdfffbfff
CDU_RX_RMC_12_PRD_THRESHOLDS_CONFIG.CDU1[0x244]=0x7ffefffdfffbfff
CDU_RX_RMC_13_MAP.CDU0[0x45d]=6
CDU_RX_RMC_13_MAP.CDU1[0x45d]=6
CDU_RX_RMC_13_PRD_THRESHOLDS_CONFIG.CDU0[0x246]=0x7ffefffdfffbfff
CDU_RX_RMC_13_PRD_THRESHOLDS_CONFIG.CDU1[0x246]=0x7ffefffdfffbfff
CDU_RX_RMC_14_MAP.CDU0[0x45e]=7
CDU_RX_RMC_14_MAP.CDU1[0x45e]=7
CDU_RX_RMC_14_PRD_THRESHOLDS_CONFIG.CDU0[0x248]=0x7ffefffdfffbfff
CDU_RX_RMC_14_PRD_THRESHOLDS_CONFIG.CDU1[0x248]=0x7ffefffdfffbfff
CDU_RX_RMC_15_MAP.CDU0[0x45f]=7
CDU_RX_RMC_15_MAP.CDU1[0x45f]=7
CDU_RX_RMC_15_PRD_THRESHOLDS_CONFIG.CDU0[0x24a]=0x7ffefffdfffbfff
CDU_RX_RMC_15_PRD_THRESHOLDS_CONFIG.CDU1[0x24a]=0x7ffefffdfffbfff
CDU_RX_RMC_1_MAP.CDU0[0x451]=4
CDU_RX_RMC_1_MAP.CDU1[0x451]=0
CDU_RX_RMC_1_PRD_THRESHOLDS_CONFIG.CDU0[0x22e]=0x7ffefffdfffbfff
CDU_RX_RMC_1_PRD_THRESHOLDS_CONFIG.CDU1[0x22e]=0x7ffefffdfffbfff
CDU_RX_RMC_2_MAP.CDU0[0x452]=1
CDU_RX_RMC_2_MAP.CDU1[0x452]=1
CDU_RX_RMC_2_PRD_THRESHOLDS_CONFIG.CDU0[0x230]=0x7ffefffdfffbfff
CDU_RX_RMC_2_PRD_THRESHOLDS_CONFIG.CDU1[0x230]=0x7ffefffdfffbfff
CDU_RX_RMC_3_MAP.CDU0[0x453]=1
CDU_RX_RMC_3_MAP.CDU1[0x453]=1
CDU_RX_RMC_3_PRD_THRESHOLDS_CONFIG.CDU0[0x232]=0x7ffefffdfffbfff
CDU_RX_RMC_3_PRD_THRESHOLDS_CONFIG.CDU1[0x232]=0x7ffefffdfffbfff
CDU_RX_RMC_4_MAP.CDU0[0x454]=2
CDU_RX_RMC_4_MAP.CDU1[0x454]=2
CDU_RX_RMC_4_PRD_THRESHOLDS_CONFIG.CDU0[0x234]=0x7ffefffdfffbfff
CDU_RX_RMC_4_PRD_THRESHOLDS_CONFIG.CDU1[0x234]=0x7ffefffdfffbfff
CDU_RX_RMC_5_MAP.CDU0[0x455]=2
CDU_RX_RMC_5_MAP.CDU1[0x455]=2
CDU_RX_RMC_5_PRD_THRESHOLDS_CONFIG.CDU0[0x236]=0x7ffefffdfffbfff
CDU_RX_RMC_5_PRD_THRESHOLDS_CONFIG.CDU1[0x236]=0x7ffefffdfffbfff
CDU_RX_RMC_6_MAP.CDU0[0x456]=3
CDU_RX_RMC_6_MAP.CDU1[0x456]=3
CDU_RX_RMC_6_PRD_THRESHOLDS_CONFIG.CDU0[0x238]=0x7ffefffdfffbfff
CDU_RX_RMC_6_PRD_THRESHOLDS_CONFIG.CDU1[0x238]=0x7ffefffdfffbfff
CDU_RX_RMC_7_MAP.CDU0[0x457]=3
CDU_RX_RMC_7_MAP.CDU1[0x457]=3
CDU_RX_RMC_7_PRD_THRESHOLDS_CONFIG.CDU0[0x23a]=0x7ffefffdfffbfff
CDU_RX_RMC_7_PRD_THRESHOLDS_CONFIG.CDU1[0x23a]=0x7ffefffdfffbfff
CDU_RX_RMC_8_MAP.CDU0[0x458]=4
CDU_RX_RMC_8_MAP.CDU1[0x458]=4
CDU_RX_RMC_8_PRD_THRESHOLDS_CONFIG.CDU0[0x23c]=0x7ffefffdfffbfff
CDU_RX_RMC_8_PRD_THRESHOLDS_CONFIG.CDU1[0x23c]=0x7ffefffdfffbfff
CDU_RX_RMC_9_MAP.CDU0[0x459]=4
CDU_RX_RMC_9_MAP.CDU1[0x459]=4
CDU_RX_RMC_9_PRD_THRESHOLDS_CONFIG.CDU0[0x23e]=0x7ffefffdfffbfff
CDU_RX_RMC_9_PRD_THRESHOLDS_CONFIG.CDU1[0x23e]=0x7ffefffdfffbfff
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(0).CDU0[0x427]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(1).CDU0[0x428]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(2).CDU0[0x429]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(3).CDU0[0x42a]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(4).CDU0[0x42b]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(5).CDU0[0x42c]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(6).CDU0[0x42d]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(7).CDU0[0x42e]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(0).CDU1[0x427]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(1).CDU1[0x428]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(2).CDU1[0x429]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(3).CDU1[0x42a]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(4).CDU1[0x42b]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(5).CDU1[0x42c]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(6).CDU1[0x42d]=0
CDU_RX_RMC_MAP_TO_PORT_IS_INVALID(7).CDU1[0x42e]=0
CDU_RX_RMC_PRIORITY_MAP.CDU0[0x478]=0xffff00000000
CDU_RX_RMC_PRIORITY_MAP.CDU1[0x478]=0xffff00000000
CDU_RX_RUNT_PKT_COUNTER(0).CDU0[0x399]=0
CDU_RX_RUNT_PKT_COUNTER(1).CDU0[0x39a]=0
CDU_RX_RUNT_PKT_COUNTER(2).CDU0[0x39b]=0
CDU_RX_RUNT_PKT_COUNTER(3).CDU0[0x39c]=0
CDU_RX_RUNT_PKT_COUNTER(4).CDU0[0x39d]=0
CDU_RX_RUNT_PKT_COUNTER(5).CDU0[0x39e]=0
CDU_RX_RUNT_PKT_COUNTER(6).CDU0[0x39f]=0
CDU_RX_RUNT_PKT_COUNTER(7).CDU0[0x3a0]=0
CDU_RX_RUNT_PKT_COUNTER(8).CDU0[0x3a1]=0
CDU_RX_RUNT_PKT_COUNTER(9).CDU0[0x3a2]=0
CDU_RX_RUNT_PKT_COUNTER(10).CDU0[0x3a3]=0
CDU_RX_RUNT_PKT_COUNTER(11).CDU0[0x3a4]=0
CDU_RX_RUNT_PKT_COUNTER(12).CDU0[0x3a5]=0
CDU_RX_RUNT_PKT_COUNTER(13).CDU0[0x3a6]=0
CDU_RX_RUNT_PKT_COUNTER(14).CDU0[0x3a7]=0
CDU_RX_RUNT_PKT_COUNTER(15).CDU0[0x3a8]=0
CDU_RX_RUNT_PKT_COUNTER(0).CDU1[0x399]=0
CDU_RX_RUNT_PKT_COUNTER(1).CDU1[0x39a]=0
CDU_RX_RUNT_PKT_COUNTER(2).CDU1[0x39b]=0
CDU_RX_RUNT_PKT_COUNTER(3).CDU1[0x39c]=0
CDU_RX_RUNT_PKT_COUNTER(4).CDU1[0x39d]=0
CDU_RX_RUNT_PKT_COUNTER(5).CDU1[0x39e]=0
CDU_RX_RUNT_PKT_COUNTER(6).CDU1[0x39f]=0
CDU_RX_RUNT_PKT_COUNTER(7).CDU1[0x3a0]=0
CDU_RX_RUNT_PKT_COUNTER(8).CDU1[0x3a1]=0
CDU_RX_RUNT_PKT_COUNTER(9).CDU1[0x3a2]=0
CDU_RX_RUNT_PKT_COUNTER(10).CDU1[0x3a3]=0
CDU_RX_RUNT_PKT_COUNTER(11).CDU1[0x3a4]=0
CDU_RX_RUNT_PKT_COUNTER(12).CDU1[0x3a5]=0
CDU_RX_RUNT_PKT_COUNTER(13).CDU1[0x3a6]=0
CDU_RX_RUNT_PKT_COUNTER(14).CDU1[0x3a7]=0
CDU_RX_RUNT_PKT_COUNTER(15).CDU1[0x3a8]=0
CDU_RX_SCH_DEBUG_CONF.CDU0[0x53a]=1
CDU_RX_SCH_DEBUG_CONF.CDU1[0x53a]=1
CDU_RX_SCH_DEBUG_RESULT.CDU0[0x535]=0xf0000000
CDU_RX_SCH_DEBUG_RESULT.CDU1[0x535]=0xf0000000
CDU_RX_SCH_MORE_THAN_ONE_RD_FROM_MAIN_SCH.CDU0[0x53f]=0
CDU_RX_SCH_MORE_THAN_ONE_RD_FROM_MAIN_SCH.CDU1[0x53f]=0
CDU_RX_SCH_WIN_PRIOR_HIGH_WITH_NO_WIN_RMC_CNT.CDU0[0x541]=0
CDU_RX_SCH_WIN_PRIOR_HIGH_WITH_NO_WIN_RMC_CNT.CDU1[0x541]=0
CDU_RX_SCH_WIN_PRIOR_LOW_WITH_NO_WIN_RMC_CNT.CDU0[0x542]=0
CDU_RX_SCH_WIN_PRIOR_LOW_WITH_NO_WIN_RMC_CNT.CDU1[0x542]=0
CDU_RX_SCH_WIN_PRIOR_TDM_WITH_NO_WIN_RMC_CNT.CDU0[0x540]=0
CDU_RX_SCH_WIN_PRIOR_TDM_WITH_NO_WIN_RMC_CNT.CDU1[0x540]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(0).CDU0[0x349]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(1).CDU0[0x34a]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(2).CDU0[0x34b]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(3).CDU0[0x34c]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(4).CDU0[0x34d]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(5).CDU0[0x34e]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(6).CDU0[0x34f]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(7).CDU0[0x350]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(8).CDU0[0x351]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(9).CDU0[0x352]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(10).CDU0[0x353]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(11).CDU0[0x354]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(12).CDU0[0x355]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(13).CDU0[0x356]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(14).CDU0[0x357]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(15).CDU0[0x358]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(0).CDU1[0x349]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(1).CDU1[0x34a]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(2).CDU1[0x34b]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(3).CDU1[0x34c]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(4).CDU1[0x34d]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(5).CDU1[0x34e]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(6).CDU1[0x34f]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(7).CDU1[0x350]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(8).CDU1[0x351]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(9).CDU1[0x352]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(10).CDU1[0x353]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(11).CDU1[0x354]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(12).CDU1[0x355]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(13).CDU1[0x356]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(14).CDU1[0x357]=0
CDU_RX_SMALL_PKT_ERR_DROP_COUNTER(15).CDU1[0x358]=0
CDU_RX_TDM_BYTE_COUNTER.CDU0[0x3d3]=0
CDU_RX_TDM_BYTE_COUNTER.CDU1[0x3d3]=0
CDU_RX_TDM_PKT_COUNTER.CDU0[0x3d1]=0
CDU_RX_TDM_PKT_COUNTER.CDU1[0x3d1]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(0).CDU0[0x1ba]=0xcc
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(1).CDU0[0x1bb]=0xcc
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(2).CDU0[0x1bc]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(3).CDU0[0x1bd]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(4).CDU0[0x1be]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(5).CDU0[0x1bf]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(6).CDU0[0x1c0]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(7).CDU0[0x1c1]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(8).CDU0[0x1c2]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(9).CDU0[0x1c3]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(10).CDU0[0x1c4]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(11).CDU0[0x1c5]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(12).CDU0[0x1c6]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(13).CDU0[0x1c7]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(14).CDU0[0x1c8]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(15).CDU0[0x1c9]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(0).CDU1[0x1ba]=0xcc
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(1).CDU1[0x1bb]=0xcc
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(2).CDU1[0x1bc]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(3).CDU1[0x1bd]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(4).CDU1[0x1be]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(5).CDU1[0x1bf]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(6).CDU1[0x1c0]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(7).CDU1[0x1c1]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(8).CDU1[0x1c2]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(9).CDU1[0x1c3]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(10).CDU1[0x1c4]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(11).CDU1[0x1c5]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(12).CDU1[0x1c6]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(13).CDU1[0x1c7]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(14).CDU1[0x1c8]=0
CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(15).CDU1[0x1c9]=0
CDU_RX_TOTAL_BYTE_COUNTER.CDU0[0x3cb]=0
CDU_RX_TOTAL_BYTE_COUNTER.CDU1[0x3cb]=0
CDU_RX_TOTAL_BYTE_WITH_ERR_COUNTER.CDU0[0x3d0]=0
CDU_RX_TOTAL_BYTE_WITH_ERR_COUNTER.CDU1[0x3d0]=0
CDU_RX_TOTAL_PKT_COUNTER.CDU0[0x3c9]=0
CDU_RX_TOTAL_PKT_COUNTER.CDU1[0x3c9]=0
CDU_RX_TOTAL_PKT_WITH_ERR_COUNTER.CDU0[0x3cf]=0
CDU_RX_TOTAL_PKT_WITH_ERR_COUNTER.CDU1[0x3cf]=0
CDU_SBUS_BROADCAST_ID.CDU0[0x86]=0x7ff
CDU_SBUS_BROADCAST_ID.CDU1[0x86]=0x7ff
CDU_SBUS_LAST_IN_CHAIN.CDU0[0x87]=0
CDU_SBUS_LAST_IN_CHAIN.CDU1[0x87]=0
CDU_SCH_CNT_DEC_TH.CDU0[0x534]=0
CDU_SCH_CNT_DEC_TH.CDU1[0x534]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(0).CDU0[0x524]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(1).CDU0[0x525]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(2).CDU0[0x526]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(3).CDU0[0x527]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(4).CDU0[0x528]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(5).CDU0[0x529]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(6).CDU0[0x52a]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(7).CDU0[0x52b]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(8).CDU0[0x52c]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(9).CDU0[0x52d]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(10).CDU0[0x52e]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(11).CDU0[0x52f]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(12).CDU0[0x530]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(13).CDU0[0x531]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(14).CDU0[0x532]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(15).CDU0[0x533]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(0).CDU1[0x524]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(1).CDU1[0x525]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(2).CDU1[0x526]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(3).CDU1[0x527]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(4).CDU1[0x528]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(5).CDU1[0x529]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(6).CDU1[0x52a]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(7).CDU1[0x52b]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(8).CDU1[0x52c]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(9).CDU1[0x52d]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(10).CDU1[0x52e]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(11).CDU1[0x52f]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(12).CDU1[0x530]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(13).CDU1[0x531]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(14).CDU1[0x532]=0
CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(15).CDU1[0x533]=0
CDU_SPECIAL_CLOCK_CONTROLS.CDU0[0xc1]=2
CDU_SPECIAL_CLOCK_CONTROLS.CDU1[0xc1]=2
CDU_SW_PROPAGATE_RESET.CDU0[0x557]=0
CDU_SW_PROPAGATE_RESET.CDU1[0x557]=0
CDU_SYNC_ETH_CFG(0).CDU0[0x3f1]=0
CDU_SYNC_ETH_CFG(1).CDU0[0x3f2]=0
CDU_SYNC_ETH_CFG(0).CDU1[0x3f1]=0
CDU_SYNC_ETH_CFG(1).CDU1[0x3f2]=0
CDU_SYNC_ETH_DEBUG(0).CDU0[0x3f3]=0
CDU_SYNC_ETH_DEBUG(1).CDU0[0x3f4]=0
CDU_SYNC_ETH_DEBUG(2).CDU0[0x3f5]=0
CDU_SYNC_ETH_DEBUG(3).CDU0[0x3f6]=0
CDU_SYNC_ETH_DEBUG(4).CDU0[0x3f7]=0
CDU_SYNC_ETH_DEBUG(5).CDU0[0x3f8]=0
CDU_SYNC_ETH_DEBUG(6).CDU0[0x3f9]=0
CDU_SYNC_ETH_DEBUG(7).CDU0[0x3fa]=0
CDU_SYNC_ETH_DEBUG(0).CDU1[0x3f3]=0
CDU_SYNC_ETH_DEBUG(1).CDU1[0x3f4]=0
CDU_SYNC_ETH_DEBUG(2).CDU1[0x3f5]=0
CDU_SYNC_ETH_DEBUG(3).CDU1[0x3f6]=0
CDU_SYNC_ETH_DEBUG(4).CDU1[0x3f7]=0
CDU_SYNC_ETH_DEBUG(5).CDU1[0x3f8]=0
CDU_SYNC_ETH_DEBUG(6).CDU1[0x3f9]=0
CDU_SYNC_ETH_DEBUG(7).CDU1[0x3fa]=0
CDU_TX_EGRESS_CREDITS_DEBUG_PM.CDU0[0x256]=0x101
CDU_TX_EGRESS_CREDITS_DEBUG_PM.CDU1[0x256]=0x101
CDU_TX_FIFO_FLUSH_AND_STOP_TOOL.CDU0[0x251]=0
CDU_TX_FIFO_FLUSH_AND_STOP_TOOL.CDU1[0x251]=0
CDU_TX_MEM_SER_ASYNC_FIFO_DEBUG.CDU0[0x558]=0
CDU_TX_MEM_SER_ASYNC_FIFO_DEBUG.CDU1[0x558]=0
CDU_TX_MLF_CONFIG.CDU0[0x1b9]=0x24090240d024090240d
CDU_TX_MLF_CONFIG.CDU1[0x1b9]=0x24090240d024090240d
CDU_TX_MLF_ERR_ON_MOP_FROM_EGQ.CDU0[0x25f]=0
CDU_TX_MLF_ERR_ON_MOP_FROM_EGQ.CDU1[0x25f]=0
CDU_TX_MLF_FIFO_FLUSH(0).CDU0[0x1b1]=0
CDU_TX_MLF_FIFO_FLUSH(1).CDU0[0x1b2]=0
CDU_TX_MLF_FIFO_FLUSH(2).CDU0[0x1b3]=0
CDU_TX_MLF_FIFO_FLUSH(3).CDU0[0x1b4]=0
CDU_TX_MLF_FIFO_FLUSH(4).CDU0[0x1b5]=0
CDU_TX_MLF_FIFO_FLUSH(5).CDU0[0x1b6]=0
CDU_TX_MLF_FIFO_FLUSH(6).CDU0[0x1b7]=0
CDU_TX_MLF_FIFO_FLUSH(7).CDU0[0x1b8]=0
CDU_TX_MLF_FIFO_FLUSH(0).CDU1[0x1b1]=0
CDU_TX_MLF_FIFO_FLUSH(1).CDU1[0x1b2]=0
CDU_TX_MLF_FIFO_FLUSH(2).CDU1[0x1b3]=0
CDU_TX_MLF_FIFO_FLUSH(3).CDU1[0x1b4]=0
CDU_TX_MLF_FIFO_FLUSH(4).CDU1[0x1b5]=0
CDU_TX_MLF_FIFO_FLUSH(5).CDU1[0x1b6]=0
CDU_TX_MLF_FIFO_FLUSH(6).CDU1[0x1b7]=0
CDU_TX_MLF_FIFO_FLUSH(7).CDU1[0x1b8]=0
CDU_TX_MLF_LEVEL_PM.CDU0[0x258]=0x8b0000008d
CDU_TX_MLF_LEVEL_PM.CDU1[0x258]=0x8b0000008b
CDU_TX_MLF_MAX_OCCUPANCY.CDU0[0x25a]=0x8b0000008d
CDU_TX_MLF_MAX_OCCUPANCY.CDU1[0x25a]=0x8b0000008b
CDU_TX_MLF_NUM_CREDITS_FROM_PM.CDU0[0x25c]=0x80000000
CDU_TX_MLF_NUM_CREDITS_FROM_PM.CDU1[0x25c]=0x80000002
CDU_TX_MLF_OVERFLOW_PM.CDU0[0x257]=0x1111
CDU_TX_MLF_OVERFLOW_PM.CDU1[0x257]=0x1111
CDU_TX_NO_DATA_IN_BUFFER.CDU0[0x25d]=0
CDU_TX_NO_DATA_IN_BUFFER.CDU1[0x25d]=0
CDU_TX_PORTS_CONFIG.CDU0[0x253]=2
CDU_TX_PORTS_CONFIG.CDU1[0x253]=2
CDU_TX_PORTS_SRSTN.CDU0[0x101]=0x11
CDU_TX_PORTS_SRSTN.CDU1[0x101]=0x11
CDU_TX_PORT_OVF.CDU0[0x263]=0
CDU_TX_PORT_OVF.CDU1[0x263]=0
CDU_TX_QMLF_CONFIG.CDU0[0x254]=0x3b8000
CDU_TX_QMLF_CONFIG.CDU1[0x254]=0x3b8000
CDU_TX_TMC_RATE_LIMITER_LEVEL.CDU0[0x265]=0
CDU_TX_TMC_RATE_LIMITER_LEVEL.CDU1[0x265]=0
CDU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY.CDU0[0x267]=0
CDU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY.CDU1[0x267]=0
CDU_TX_TOTAL_BYTE_COUNTER.CDU0[0x3d9]=0x1709670
CDU_TX_TOTAL_BYTE_COUNTER.CDU1[0x3d9]=0x1709670
CDU_TX_TOTAL_BYTE_WITH_ERR_COUNTER.CDU0[0x3e4]=0
CDU_TX_TOTAL_BYTE_WITH_ERR_COUNTER.CDU1[0x3e4]=0
CDU_TX_TOTAL_ERR_ON_SOP_BYTE_COUNTER.CDU0[0x3df]=0
CDU_TX_TOTAL_ERR_ON_SOP_BYTE_COUNTER.CDU1[0x3df]=0
CDU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER.CDU0[0x3dd]=0
CDU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER.CDU1[0x3dd]=0
CDU_TX_TOTAL_PKT_COUNTER.CDU0[0x3d7]=0x11c04
CDU_TX_TOTAL_PKT_COUNTER.CDU1[0x3d7]=0x11c04
CDU_TX_TOTAL_PKT_WITH_ERR_COUNTER.CDU0[0x3e3]=0
CDU_TX_TOTAL_PKT_WITH_ERR_COUNTER.CDU1[0x3e3]=0
CDU_TX_WRONG_PORT_FROM_EGQ_QMLF.CDU0[0x25e]=0
CDU_TX_WRONG_PORT_FROM_EGQ_QMLF.CDU1[0x25e]=0
CDU_UNIT_LOW_RMC_EN_IS_ALL_MASKED.CDU0[0x53c]=0
CDU_UNIT_LOW_RMC_EN_IS_ALL_MASKED.CDU1[0x53c]=0
CFC_CAT_2_TC_MAP_NIF_ENA.CFC0[0x104]=0xff
CFC_CFC_ENABLERS.CFC0[0x100]=0x1ffbfffeffff555f
CFC_CGM_2_NIF_LLFC_SEL_ILKN_OR_FLEXE.CFC0[0x147]=0
CFC_CGM_GLBL_FC_STATUS.CFC0[0x143]=0
CFC_CGM_VSQ_FC_STATUS_SEL.CFC0[0x142]=0
CFC_CGM_VSQ_GRPS_ABCD_FC_STATUS.CFC0[0x144]=0
CFC_CGM_VSQ_LLFC_STATUS.CFC0[0x145]=0
CFC_CGM_VSQ_PFC_STATUS.CFC0[0x146]=0
CFC_CLR_CMIC_TX_FC.CFC0[0x16b]=0
CFC_CLR_EGQ_PFC.CFC0[0x15e]=0
CFC_CLR_NIF_ETH_GEN_LLFC.CFC0[0x160]=0
CFC_CLR_NIF_ETH_LLFC_STOP.CFC0[0x15f]=0
CFC_CLR_NIF_ETH_PFC.CFC0[0x165]=0
CFC_CLR_NIF_FLEXE_GEN_LLFC.CFC0[0x164]=0
CFC_CLR_NIF_FLEXE_LLFC_STOP.CFC0[0x163]=0
CFC_CLR_NIF_FLEXE_PFC.CFC0[0x166]=0
CFC_CLR_NIF_ILU_GEN_CHFC(0).CFC0[0x167]=0
CFC_CLR_NIF_ILU_GEN_CHFC(1).CFC0[0x168]=0
CFC_CLR_NIF_ILU_GEN_CHFC(2).CFC0[0x169]=0
CFC_CLR_NIF_ILU_GEN_CHFC(3).CFC0[0x16a]=0
CFC_CLR_NIF_ILU_GEN_LLFC.CFC0[0x162]=0
CFC_CLR_NIF_ILU_LLFC_STOP.CFC0[0x161]=0
CFC_CMIC_RX_FC_MAP.CFC0[0x103]=0xa040000000000000006022b958aa5429948a250000000000000000200
CFC_CMIC_RX_FC_MASK.CFC0[0x102]=0
CFC_CMIC_RX_FC_STATUS.CFC0[0x16c]=0xfffffffffcffffff
CFC_CMIC_TX_FC.CFC0[0x101]=0
CFC_CMIC_TX_FC_STATUS.CFC0[0x16d]=0
CFC_ECC_1B_ERR_CNT.CFC0[0x94]=0
CFC_ECC_2B_ERR_CNT.CFC0[0x96]=0
CFC_ECC_ERR_1B_MONITOR_MEM_MASK.CFC0[0x9a]=0xffff
CFC_ECC_ERR_2B_MONITOR_MEM_MASK.CFC0[0x9c]=0xffff
CFC_ECC_INTERRUPT_REGISTER.CFC0[0x7]=0
CFC_ECC_INTERRUPT_REGISTER_MASK.CFC0[0x17]=0
CFC_ECC_INTERRUPT_REGISTER_TEST.CFC0[0x1f]=0
CFC_EGQ_PFC_STATUS.CFC0[0x136]=0
CFC_EGQ_PFC_STATUS_SEL.CFC0[0x135]=0
CFC_ENABLE_DYNAMIC_MEMORY_ACCESS.CFC0[0x84]=0
CFC_FRC_CMIC_TX_FC.CFC0[0x15d]=0
CFC_FRC_EGQ_PFC.CFC0[0x150]=0
CFC_FRC_NIF_ETH_GEN_LLFC.CFC0[0x153]=0
CFC_FRC_NIF_ETH_LLFC_STOP.CFC0[0x156]=0
CFC_FRC_NIF_ETH_PFC.CFC0[0x151]=0
CFC_FRC_NIF_FLEXE_GEN_LLFC.CFC0[0x155]=0
CFC_FRC_NIF_FLEXE_LLFC_STOP.CFC0[0x158]=0
CFC_FRC_NIF_FLEXE_PFC.CFC0[0x152]=0
CFC_FRC_NIF_ILU_GEN_CHFC(0).CFC0[0x159]=0
CFC_FRC_NIF_ILU_GEN_CHFC(1).CFC0[0x15a]=0
CFC_FRC_NIF_ILU_GEN_CHFC(2).CFC0[0x15b]=0
CFC_FRC_NIF_ILU_GEN_CHFC(3).CFC0[0x15c]=0
CFC_FRC_NIF_ILU_GEN_LLFC.CFC0[0x154]=0
CFC_FRC_NIF_ILU_LLFC_STOP.CFC0[0x157]=0
CFC_GLB_RSC_CGM_MASK.CFC0[0x105]=0x2fff
CFC_GLB_RSC_DRAM_CGM_TO_NIF_LLFC_MAP.CFC0[0x106]=0
CFC_GLB_RSC_HDRM_CGM_TO_NIF_LLFC_HP_MAP.CFC0[0x10a]=0
CFC_GLB_RSC_POOL_CGM_TO_NIF_LLFC_MAP(0).CFC0[0x108]=0
CFC_GLB_RSC_POOL_CGM_TO_NIF_LLFC_MAP(1).CFC0[0x109]=0
CFC_GLB_RSC_SRAM_CGM_TO_NIF_LLFC_MAP.CFC0[0x107]=0
CFC_GTIMER_CONFIGURATION.CFC0[0x89]=0
CFC_GTIMER_CYCLE.CFC0[0x88]=0x3b9aca00
CFC_ILKN_OOB_CONFIG(0).CFC0[0x16e]=0
CFC_ILKN_OOB_CONFIG(1).CFC0[0x16f]=0
CFC_ILKN_OOB_INDICATIONS(0).CFC0[0x170]=0xf0000000000f00
CFC_ILKN_OOB_INDICATIONS(1).CFC0[0x171]=0xf0000000000f00
CFC_ILKN_OOB_POLARITY_CFG(0).CFC0[0x10f]=0
CFC_ILKN_OOB_POLARITY_CFG(1).CFC0[0x110]=0
CFC_ILKN_OOB_RSTN(0).CFC0[0x172]=0
CFC_ILKN_OOB_RSTN(1).CFC0[0x173]=0
CFC_ILKN_OOB_RX_FC_STATUS(0).CFC0[0x117]=0
CFC_ILKN_OOB_RX_FC_STATUS(1).CFC0[0x118]=0
CFC_ILKN_OOB_TX_CONFIGURATION(0).CFC0[0x111]=0
CFC_ILKN_OOB_TX_CONFIGURATION(1).CFC0[0x112]=0
CFC_INDIRECT_COMMAND.CFC0[0x80]=0xe000002
CFC_INDIRECT_COMMAND_ADDRESS.CFC0[0x81]=0x3500
CFC_INDIRECT_COMMAND_RD_DATA.CFC0[0x60]=0x57fbde15eff9ff757f37fbf9fdfedfff5fd57f745efffffed1bab7aebfebefffffefd85fef57fdffffefef5dfef9febefdffbffdefdb7fdb1cff66fb376defd7efb
CFC_INDIRECT_COMMAND_WR_DATA.CFC0[0x20]=0x1ffbfffe00003000
CFC_INDIRECT_FORCE_BUBBLE.CFC0[0x83]=0x20019
CFC_INTERRUPT_MASK_REGISTER.CFC0[0x10]=0
CFC_INTERRUPT_REGISTER.CFC0[0x0]=0
CFC_INTERRUPT_REGISTER_TEST.CFC0[0x18]=0
CFC_NIF_ETH_RX_LLFC_STATUS.CFC0[0x137]=0
CFC_NIF_ETH_RX_PFC_STATUS.CFC0[0x13d]=0
CFC_NIF_ETH_RX_PFC_STATUS_SEL.CFC0[0x13e]=0
CFC_NIF_ETH_TX_GEN_LLFC_STATUS.CFC0[0x11d]=0
CFC_NIF_ETH_TX_GEN_PFC_STATUS.CFC0[0x140]=0
CFC_NIF_ETH_TX_GEN_PFC_STATUS_SEL.CFC0[0x13f]=0
CFC_NIF_ETH_TX_LLFC_STOP_STATUS.CFC0[0x11e]=0
CFC_NIF_FLEXE_RX_CHFC_STATUS(0).CFC0[0x13b]=0
CFC_NIF_FLEXE_RX_CHFC_STATUS(1).CFC0[0x13c]=0
CFC_NIF_FLEXE_RX_LLFC_STATUS.CFC0[0x139]=0
CFC_NIF_FLEXE_RX_PFC_STATUS.CFC0[0x13a]=0xce53793fdbfaeff7
CFC_NIF_FLEXE_TX_GEN_LLFC_STATUS.CFC0[0x11f]=0
CFC_NIF_FLEXE_TX_GEN_PFC_STATUS.CFC0[0x141]=0
CFC_NIF_FLEXE_TX_LLFC_STOP_STATUS.CFC0[0x120]=0
CFC_NIF_ILU_RX_CHFC_STATUS(0).CFC0[0x119]=0
CFC_NIF_ILU_RX_CHFC_STATUS(1).CFC0[0x11a]=0
CFC_NIF_ILU_RX_CHFC_STATUS(2).CFC0[0x11b]=0
CFC_NIF_ILU_RX_CHFC_STATUS(3).CFC0[0x11c]=0
CFC_NIF_ILU_RX_LLFC_STATUS.CFC0[0x138]=0
CFC_NIF_ILU_TX_CHFC_STATUS(0).CFC0[0x123]=0
CFC_NIF_ILU_TX_CHFC_STATUS(1).CFC0[0x124]=0
CFC_NIF_ILU_TX_CHFC_STATUS(2).CFC0[0x125]=0
CFC_NIF_ILU_TX_CHFC_STATUS(3).CFC0[0x126]=0
CFC_NIF_ILU_TX_CONFIGURATION(0).CFC0[0x113]=0xff
CFC_NIF_ILU_TX_CONFIGURATION(1).CFC0[0x114]=0xff
CFC_NIF_ILU_TX_CONFIGURATION(2).CFC0[0x115]=0xff
CFC_NIF_ILU_TX_CONFIGURATION(3).CFC0[0x116]=0xff
CFC_NIF_ILU_TX_GEN_LLFC_STATUS.CFC0[0x121]=0
CFC_NIF_ILU_TX_LLFC_STOP_STATUS.CFC0[0x122]=0
CFC_OOB_PAD_CONFIGURATION(0).CFC0[0x10d]=0x100041
CFC_OOB_PAD_CONFIGURATION(1).CFC0[0x10e]=0x100041
CFC_PFC_GENERIC_BITMAP(0).CFC0[0x175]=0
CFC_PFC_GENERIC_BITMAP(1).CFC0[0x176]=0
CFC_PFC_GENERIC_BITMAP(2).CFC0[0x177]=0
CFC_PFC_GENERIC_BITMAP(3).CFC0[0x178]=0
CFC_PFC_GENERIC_BITMAP(4).CFC0[0x179]=0
CFC_PFC_GENERIC_BITMAP(5).CFC0[0x17a]=0
CFC_PFC_GENERIC_BITMAP(6).CFC0[0x17b]=0
CFC_PFC_GENERIC_BITMAP(7).CFC0[0x17c]=0
CFC_PFC_GENERIC_BITMAP(8).CFC0[0x17d]=0
CFC_PFC_GENERIC_BITMAP(9).CFC0[0x17e]=0
CFC_PFC_GENERIC_BITMAP(10).CFC0[0x17f]=0
CFC_PFC_GENERIC_BITMAP(11).CFC0[0x180]=0
CFC_PFC_GENERIC_BITMAP(12).CFC0[0x181]=0
CFC_PFC_GENERIC_BITMAP(13).CFC0[0x182]=0
CFC_PFC_GENERIC_BITMAP(14).CFC0[0x183]=0
CFC_PFC_GENERIC_BITMAP(15).CFC0[0x184]=0
CFC_PFC_GENERIC_BITMAP(16).CFC0[0x185]=0
CFC_PFC_GENERIC_BITMAP(17).CFC0[0x186]=0
CFC_PFC_GENERIC_BITMAP(18).CFC0[0x187]=0
CFC_PFC_GENERIC_BITMAP(19).CFC0[0x188]=0
CFC_PFC_GENERIC_BITMAP(20).CFC0[0x189]=0
CFC_PFC_GENERIC_BITMAP(21).CFC0[0x18a]=0
CFC_PFC_GENERIC_BITMAP(22).CFC0[0x18b]=0
CFC_PFC_GENERIC_BITMAP(23).CFC0[0x18c]=0
CFC_PFC_GENERIC_BITMAP(24).CFC0[0x18d]=0
CFC_PFC_GENERIC_BITMAP(25).CFC0[0x18e]=0
CFC_PFC_GENERIC_BITMAP(26).CFC0[0x18f]=0
CFC_PFC_GENERIC_BITMAP(27).CFC0[0x190]=0
CFC_PFC_GENERIC_BITMAP(28).CFC0[0x191]=0
CFC_PFC_GENERIC_BITMAP(29).CFC0[0x192]=0
CFC_PFC_GENERIC_BITMAP(30).CFC0[0x193]=0
CFC_PFC_GENERIC_BITMAP(31).CFC0[0x194]=0
CFC_PP_INBAND.CFC0[0x134]=0x1ff
CFC_PP_RX_4_FC_STATUS.CFC0[0x127]=0
CFC_REG_0041.CFC0[0x41]=0
CFC_REG_00C2.CFC0[0xc2]=0x10
CFC_RESERVED_MTCD.CFC0[0xae]=0x30
CFC_RESERVED_MTCP.CFC0[0xad]=0x300000600000000
CFC_RESERVED_SPARE_0.CFC0[0x90]=0xffffffff
CFC_RESERVED_SPARE_1.CFC0[0x91]=0xffffffff
CFC_RESERVED_SPARE_2.CFC0[0x92]=0
CFC_RESERVED_SPARE_3.CFC0[0x93]=0
CFC_RING_OSCILATOR.CFC0[0x174]=0
CFC_SBUS_BROADCAST_ID.CFC0[0x86]=0x7ff
CFC_SBUS_LAST_IN_CHAIN.CFC0[0x87]=0
CFC_SPECIAL_CLOCK_CONTROLS.CFC0[0xc1]=2
CFC_SPI_OOB_RX_CONFIGURATION(0).CFC0[0x128]=0x6060606060c00
CFC_SPI_OOB_RX_CONFIGURATION(1).CFC0[0x129]=0x6060606060c00
CFC_SPI_OOB_RX_ERR(0).CFC0[0x10b]=0xf
CFC_SPI_OOB_RX_ERR(1).CFC0[0x10c]=0xf
CFC_SPI_OOB_RX_ERROR_COUNTER(0).CFC0[0x130]=0
CFC_SPI_OOB_RX_ERROR_COUNTER(1).CFC0[0x131]=0
CFC_SPI_OOB_RX_ERR_CFG(0).CFC0[0x12a]=0x1e
CFC_SPI_OOB_RX_ERR_CFG(1).CFC0[0x12b]=0x1e
CFC_SPI_OOB_RX_GEN_PFC_STATUS(0).CFC0[0x14e]=0x8000000
CFC_SPI_OOB_RX_GEN_PFC_STATUS(1).CFC0[0x14f]=0x200000000000
CFC_SPI_OOB_RX_LLFC_STATUS(0).CFC0[0x14c]=0
CFC_SPI_OOB_RX_LLFC_STATUS(1).CFC0[0x14d]=0
CFC_SPI_OOB_RX_PFC_SEL(0).CFC0[0x148]=0
CFC_SPI_OOB_RX_PFC_SEL(1).CFC0[0x149]=0
CFC_SPI_OOB_RX_PFC_STATUS(0).CFC0[0x14a]=0
CFC_SPI_OOB_RX_PFC_STATUS(1).CFC0[0x14b]=0
CFC_SPI_OOB_RX_WD_EN_CFG(0).CFC0[0x12c]=0
CFC_SPI_OOB_RX_WD_EN_CFG(1).CFC0[0x12d]=0
CFC_SPI_OOB_RX_WD_PERIOD_CFG(0).CFC0[0x12e]=0xffff
CFC_SPI_OOB_RX_WD_PERIOD_CFG(1).CFC0[0x12f]=0xffff
CFC_SPI_OOB_TX_CONFIGURATION(0).CFC0[0x132]=0xc00
CFC_SPI_OOB_TX_CONFIGURATION(1).CFC0[0x133]=0xc00
CFC_SYNC_ETH_0_REF_CLK_CNT.CFC0[0x197]=0
CFC_SYNC_ETH_1_REF_CLK_CNT.CFC0[0x198]=0
CFC_SYNC_ETH_ENABLE_FORCE.CFC0[0x195]=3
CFC_SYNC_ETH_REF_CLK_CNT_RESET_N.CFC0[0x196]=0
CGM_CGM_INIT.CGM0[0x200]=0
CGM_CONGESTION_INTERRUPT_ENABLERS.CGM0[0x203]=4
CGM_CONGESTION_INTERRUPT_MASK_REGISTER.CGM0[0x151]=0
CGM_CONGESTION_INTERRUPT_REGISTER.CGM0[0x150]=0
CGM_CONGESTION_INTERRUPT_REGISTER_TEST.CGM0[0x152]=0
CGM_CRPS_ILM_BUBBLE_REQ_CTR.CGM0[0x303]=0
CGM_CRPS_IRPP_CTR_BUBBLE_REQ_CTR.CGM0[0x2f9]=0
CGM_CRPS_TM_CTR_BUBBLE_REQ_CTR.CGM0[0x2f8]=0
CGM_DEL_CTR.CGM0[0x31a]=0
CGM_DEL_CTR_SETTINGS.CGM0[0x319]=0x1535265
CGM_DEST_REQUESTS_CTR.CGM0[0x2ee]=0xe1d17b2d
CGM_DP_LEVEL_RJCT_PKT_CTR.CGM0[0x2bf]=0
CGM_DRAM_BDBS_FREE_MIN_STATUS.CGM0[0x297]=0xfff1
CGM_DRAM_BDBS_FREE_STATUS.CGM0[0x296]=0xfff1
CGM_DRAM_BDBS_RJCT_PKT_CTR.CGM0[0x2bc]=0
CGM_DRAM_BOUND_RECOVERY_MAX_STATUS.CGM0[0x22a]=0
CGM_DRAM_BOUND_RECOVERY_STATUS.CGM0[0x229]=0
CGM_DRAM_BOUND_STATE_LFSR_MASKS.CGM0[0x227]=0
CGM_DRAM_BOUND_STATE_TH.CGM0[0x226]=0x72002000010010018000010
CGM_ECC_1B_ERR_CNT.CGM0[0x94]=0x8000
CGM_ECC_2B_ERR_CNT.CGM0[0x96]=0x8000
CGM_ECC_ERR_1B_MONITOR_MEM_MASK.CGM0[0x9a]=0x7fffffffffffffffffffffff
CGM_ECC_ERR_2B_MONITOR_MEM_MASK.CGM0[0x9c]=0x7fffffffffffffffffffffff
CGM_ECC_INTERRUPT_REGISTER.CGM0[0x7]=0
CGM_ECC_INTERRUPT_REGISTER_MASK.CGM0[0x17]=0
CGM_ECC_INTERRUPT_REGISTER_TEST.CGM0[0x1f]=0
CGM_ENABLERS.CGM0[0x202]=0xff
CGM_ENABLE_DYNAMIC_MEMORY_ACCESS.CGM0[0x84]=0
CGM_EXTERNAL_ERR_PKT_CTR.CGM0[0x2c7]=0
CGM_EXT_STAT_BILL_SETTINGS.CGM0[0x232]=0
CGM_EXT_STAT_BILL_STAMP.CGM0[0x233]=0
CGM_EXT_STAT_QNUM_RANGE_FILTER.CGM0[0x22f]=0xfffe0003fff8000
CGM_EXT_STAT_SCRB_SETTINGS.CGM0[0x231]=0x3fff8000
CGM_EXT_STAT_SETTINGS.CGM0[0x230]=0
CGM_FABRIC_MC_BASE_QUEUE.CGM0[0x209]=0
CGM_FIFO_SIZES.CGM0[0x208]=0x150040100
CGM_FLOW_AGR_SETTINGS.CGM0[0x20e]=0x8000
CGM_FLOW_BASE_QUEUE.CGM0[0x20a]=0
CGM_FR_GLBL_RSRC_RJCT_STATUS.CGM0[0x304]=0
CGM_GLBL_RJCT_PRMS.CGM0[0x210]=2
CGM_GLOBAL_FC_STATUS.CGM0[0x29a]=0
CGM_GTIMER_CONFIGURATION.CGM0[0x89]=2
CGM_GTIMER_CYCLE.CGM0[0x88]=0x23c34600
CGM_INDIRECT_COMMAND.CGM0[0x80]=0xe000002
CGM_INDIRECT_COMMAND_ADDRESS.CGM0[0x81]=0x80b8800d
CGM_INDIRECT_COMMAND_RD_DATA.CGM0[0x60]=0x600000c0042
CGM_INDIRECT_COMMAND_WR_DATA.CGM0[0x20]=0x100000000000000000000000000000000000000000000000000000000000000000000008000000000007c0000000050000000000000
CGM_INDIRECT_FORCE_BUBBLE.CGM0[0x83]=0x20019
CGM_INIT.CGM0[0x205]=0
CGM_INSTRUMENTATION_SETTINGS.CGM0[0x239]=0x3f
CGM_INSTRUMENTATION_STATUS.CGM0[0x23a]=0xf
CGM_INTERRUPT_MASK_REGISTER.CGM0[0x10]=0
CGM_INTERRUPT_REGISTER.CGM0[0x0]=0
CGM_INTERRUPT_REGISTER_TEST.CGM0[0x18]=0
CGM_INT_IRPP_STAT_SETTINGS.CGM0[0x234]=0x5abff00000000000000000000
CGM_INT_TM_STAT_SETTINGS.CGM0[0x235]=0x2ffff80002ffe400000000
CGM_INVALID_CUD.CGM0[0x20d]=0x3ffffe
CGM_INVALID_DESTINATION_QUEUE.CGM0[0x20c]=0x7fff
CGM_IPT_SRAM_TO_DRAM_CMD_NRDY_CTR.CGM0[0x2fe]=0
CGM_IPT_TX_CMD_NRDY_CTR.CGM0[0x2ff]=0
CGM_LM_CTR_CMD_FILTER.CGM0[0x20f]=0xe8
CGM_LOW_PRIORITY_CONGESTION_INTERRUPT_ENABLERS.CGM0[0x204]=0
CGM_LOW_PRIORITY_INTERRUPT_MASK_REGISTER.CGM0[0x161]=0
CGM_LOW_PRIORITY_INTERRUPT_REGISTER.CGM0[0x160]=0
CGM_LOW_PRIORITY_INTERRUPT_REGISTER_TEST.CGM0[0x162]=0
CGM_MAX_PB_VSQ_QSIZE_TRACK_SETTINGS.CGM0[0x246]=0x3ffff
CGM_MAX_PB_VSQ_SRAM_BUFFERS_QSIZE_TRACK.CGM0[0x248]=0xff3f0000000000000000000000000000000000000000000000000000000000
CGM_MAX_PB_VSQ_SRAM_PDS_QSIZE_TRACK.CGM0[0x249]=0x6b1f8000000000000000000000000000000000000000000000
CGM_MAX_PB_VSQ_WORDS_QSIZE_TRACK.CGM0[0x247]=0xec03f00000000000000000000000000000000000000000000000000000000000000000
CGM_MAX_QB_VSQ_QSIZE_TRACK_SETTINGS.CGM0[0x242]=0xff00
CGM_MAX_QB_VSQ_SRAM_BUFFERS_QSIZE_TRACK.CGM0[0x244]=0xff02000000000000000000000000
CGM_MAX_QB_VSQ_SRAM_PDS_QSIZE_TRACK.CGM0[0x245]=0x6b010000000000000000000
CGM_MAX_QB_VSQ_WORDS_QSIZE_TRACK.CGM0[0x243]=0xec002000000000000000000000000000
CGM_MAX_VOQ_QSIZE_TRACK_SETTINGS.CGM0[0x23d]=0x3fffffff
CGM_MAX_VOQ_SRAM_BUFFERS_QSIZE_TRACK.CGM0[0x240]=0xff023000ac08b0012401c001b8020002a0060004600a0000809b8001002f
CGM_MAX_VOQ_SRAM_PDS_QSIZE_TRACK.CGM0[0x241]=0x378118002b022c00240038001b80200003003000028028000080370000803f
CGM_MAX_VOQ_SRAM_WORDS_QSIZE_TRACK.CGM0[0x23f]=0xec00230004b408b0009300180012600380021e0040003d400a00006c09b8000d802f
CGM_MAX_VOQ_WORDS_QSIZE_TRACK.CGM0[0x23e]=0xec0023000004b408b0000093001800001260038000021e004000003d400a0000006c09b800000d802f
CGM_MCH_FWD_RX_REP_CTR.CGM0[0x2e6]=0x11e9964
CGM_MCH_SNIF_0_PKT_DROP_CTR.CGM0[0x2f2]=0
CGM_MCH_SNIF_0_RX_REP_CTR.CGM0[0x2e7]=0x9c33f
CGM_MCH_SNIF_1_PKT_DROP_CTR.CGM0[0x2f3]=0
CGM_MCH_SNIF_1_RX_REP_CTR.CGM0[0x2e8]=0
CGM_MCH_SNIF_2_PKT_DROP_CTR.CGM0[0x2f4]=0
CGM_MCH_SNIF_2_RX_REP_CTR.CGM0[0x2e9]=0
CGM_MCL_FWD_RX_REP_CTR.CGM0[0x2ea]=0
CGM_MCL_SNIF_0_PKT_DROP_CTR.CGM0[0x2f5]=0
CGM_MCL_SNIF_0_RX_REP_CTR.CGM0[0x2eb]=0
CGM_MCL_SNIF_1_PKT_DROP_CTR.CGM0[0x2f6]=0
CGM_MCL_SNIF_1_RX_REP_CTR.CGM0[0x2ec]=0
CGM_MCL_SNIF_2_PKT_DROP_CTR.CGM0[0x2f7]=0
CGM_MCL_SNIF_2_RX_REP_CTR.CGM0[0x2ed]=0
CGM_MC_FIFO_FULL_PKT_CTR.CGM0[0x2c3]=0
CGM_MC_REP_ERR_PKT_CTR.CGM0[0x2c2]=0
CGM_MC_TC_PRIORITY_MAP.CGM0[0x207]=0xff
CGM_MICRO_BURST_SETTINGS.CGM0[0x23b]=0xfffffffc00040007
CGM_MICRO_BURST_STATUS.CGM0[0x23c]=0
CGM_MIRROR_RJCT_ACTION.CGM0[0x22e]=0
CGM_MIRROR_RJCT_REASON_MASK.CGM0[0x22c]=0
CGM_MIRROR_RJCT_SETTINGS.CGM0[0x22d]=0x20ffffffc0003fffffff
CGM_MRPS_METER_CMD_NRDY_CTR.CGM0[0x302]=0
CGM_PB_VSQ_FC_STATUS.CGM0[0x29d]=0
CGM_PB_VSQ_GLOBAL_FC_STATUS.CGM0[0x29b]=0
CGM_PB_VSQ_LLFC_CONGESTION_FIFO_DATA.CGM0[0x29f]=0
CGM_PB_VSQ_PG_CONGESTION_FIFO_DATA.CGM0[0x29e]=0
CGM_PB_VSQ_RJCT_SETTINGS.CGM0[0x221]=0
CGM_PB_VSQ_SHRD_FR_RJCT_STATUS.CGM0[0x306]=0
CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_0_MAX_OC.CGM0[0x278]=0
CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_0_OC.CGM0[0x26c]=0
CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_1_MAX_OC.CGM0[0x279]=0
CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_1_OC.CGM0[0x26d]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_0_FR.CGM0[0x276]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_0_MAX_OC.CGM0[0x27d]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_0_OC.CGM0[0x271]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_1_FR.CGM0[0x277]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_1_MAX_OC.CGM0[0x27e]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_1_OC.CGM0[0x272]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_FR.CGM0[0x275]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_MAX_OC.CGM0[0x27c]=0
CGM_PB_VSQ_SRAM_BUFFERS_HDRM_OC.CGM0[0x270]=0
CGM_PB_VSQ_SRAM_BUFFERS_OC_TH.CGM0[0x216]=0x7ff
CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_0_FR.CGM0[0x273]=0x7ff0
CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_0_MAX_OC.CGM0[0x27a]=0xff
CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_0_OC.CGM0[0x26e]=0
CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_1_FR.CGM0[0x274]=0
CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_1_MAX_OC.CGM0[0x27b]=0
CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_1_OC.CGM0[0x26f]=0
CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_0_MAX_OC.CGM0[0x28b]=0
CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_0_OC.CGM0[0x27f]=0
CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_1_MAX_OC.CGM0[0x28c]=0
CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_1_OC.CGM0[0x280]=0
CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_0_FR.CGM0[0x289]=0x10000
CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_0_MAX_OC.CGM0[0x290]=0
CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_0_OC.CGM0[0x284]=0
CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_1_FR.CGM0[0x28a]=0x10000
CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_1_MAX_OC.CGM0[0x291]=0
CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_1_OC.CGM0[0x285]=0
CGM_PB_VSQ_SRAM_PDS_HDRM_FR.CGM0[0x288]=0x10000
CGM_PB_VSQ_SRAM_PDS_HDRM_MAX_OC.CGM0[0x28f]=0
CGM_PB_VSQ_SRAM_PDS_HDRM_OC.CGM0[0x283]=0
CGM_PB_VSQ_SRAM_PDS_OC_TH.CGM0[0x217]=0x10008004002001fff
CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_0_FR.CGM0[0x286]=0x1ffff
CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_0_MAX_OC.CGM0[0x28d]=0xd6
CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_0_OC.CGM0[0x281]=0
CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_1_FR.CGM0[0x287]=0x10000
CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_1_MAX_OC.CGM0[0x28e]=0
CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_1_OC.CGM0[0x282]=0
CGM_PB_VSQ_WORDS_GRNTD_POOL_0_MAX_OC.CGM0[0x267]=0
CGM_PB_VSQ_WORDS_GRNTD_POOL_0_OC.CGM0[0x25f]=0
CGM_PB_VSQ_WORDS_GRNTD_POOL_1_MAX_OC.CGM0[0x268]=0
CGM_PB_VSQ_WORDS_GRNTD_POOL_1_OC.CGM0[0x260]=0
CGM_PB_VSQ_WORDS_HDRM_FR.CGM0[0x266]=0x8000000
CGM_PB_VSQ_WORDS_HDRM_MAX_OC.CGM0[0x26b]=0
CGM_PB_VSQ_WORDS_HDRM_OC.CGM0[0x263]=0
CGM_PB_VSQ_WORDS_OC_TH.CGM0[0x215]=0x800000800000ffffff
CGM_PB_VSQ_WORDS_SHRD_POOL_0_FR.CGM0[0x264]=0xfffffff
CGM_PB_VSQ_WORDS_SHRD_POOL_0_MAX_OC.CGM0[0x269]=0xec0
CGM_PB_VSQ_WORDS_SHRD_POOL_0_OC.CGM0[0x261]=0
CGM_PB_VSQ_WORDS_SHRD_POOL_1_FR.CGM0[0x265]=0x8000000
CGM_PB_VSQ_WORDS_SHRD_POOL_1_MAX_OC.CGM0[0x26a]=0
CGM_PB_VSQ_WORDS_SHRD_POOL_1_OC.CGM0[0x262]=0
CGM_PCMI_0.CGM0[0xb0]=0x3b9aca00
CGM_PCMI_1.CGM0[0xb3]=0x3b9aca00
CGM_PCMI_2.CGM0[0xb6]=0x3b9aca00
CGM_PCMI_3.CGM0[0xb9]=0x3b9aca00
CGM_PCMI_4.CGM0[0xbc]=0x3b9aca00
CGM_PCMI_0_S.CGM0[0xb1]=0
CGM_PCMI_0_T.CGM0[0xb2]=0
CGM_PCMI_1_S.CGM0[0xb4]=0
CGM_PCMI_1_T.CGM0[0xb5]=0
CGM_PCMI_2_S.CGM0[0xb7]=0
CGM_PCMI_2_T.CGM0[0xb8]=0
CGM_PCMI_3_S.CGM0[0xba]=0
CGM_PCMI_3_T.CGM0[0xbb]=0
CGM_PCMI_4_S.CGM0[0xbd]=0
CGM_PCMI_4_T.CGM0[0xbe]=0
CGM_PKT_SIZE_ERR_PKT_CTR.CGM0[0x2c5]=0
CGM_PRG_CTR_SETTINGS.CGM0[0x2a1]=0x1ffffd80000001
CGM_PRG_RJCT_PKT_CTR_0.CGM0[0x2d1]=0
CGM_PRG_RJCT_PKT_CTR_1.CGM0[0x2d2]=0
CGM_PRG_RJCT_PKT_CTR_2.CGM0[0x2d3]=0
CGM_PRG_RJCT_PKT_CTR_3.CGM0[0x2d4]=0
CGM_PRG_RJCT_PKT_CTR_4.CGM0[0x2d5]=0
CGM_PRG_RJCT_PKT_CTR_5.CGM0[0x2d6]=0
CGM_PRG_RJCT_PKT_CTR_6.CGM0[0x2d7]=0
CGM_PRG_RJCT_PKT_CTR_7.CGM0[0x2d8]=0
CGM_PRG_RJCT_PKT_CTR_0_MASK.CGM0[0x2c9]=0
CGM_PRG_RJCT_PKT_CTR_1_MASK.CGM0[0x2ca]=0
CGM_PRG_RJCT_PKT_CTR_2_MASK.CGM0[0x2cb]=0
CGM_PRG_RJCT_PKT_CTR_3_MASK.CGM0[0x2cc]=0
CGM_PRG_RJCT_PKT_CTR_4_MASK.CGM0[0x2cd]=0
CGM_PRG_RJCT_PKT_CTR_5_MASK.CGM0[0x2ce]=0
CGM_PRG_RJCT_PKT_CTR_6_MASK.CGM0[0x2cf]=0
CGM_PRG_RJCT_PKT_CTR_7_MASK.CGM0[0x2d0]=0
CGM_QB_VSQ_FC_STATUS.CGM0[0x29c]=0
CGM_QNUM_NOT_VALID_PKT_CTR.CGM0[0x2c1]=0x2c2081
CGM_QNUM_RES_ERR_PKT_CTR.CGM0[0x2c0]=0
CGM_REAS_RPRT_CTR.CGM0[0x2e1]=0xe12c3fb5
CGM_RECOVERY_CACHE_SETTINGS.CGM0[0x318]=0
CGM_REG_0041.CGM0[0x41]=0
CGM_REG_0225.CGM0[0x225]=0x1000000000
CGM_REG_0228.CGM0[0x228]=0
CGM_REG_0238.CGM0[0x238]=0x3fff8000
CGM_REG_0315.CGM0[0x315]=0
CGM_REG_0316.CGM0[0x316]=0x1c
CGM_REG_0317.CGM0[0x317]=1
CGM_REG_0320.CGM0[0x320]=0
CGM_REG_0321.CGM0[0x321]=0
CGM_REG_0322.CGM0[0x322]=0
CGM_REG_0323.CGM0[0x323]=0
CGM_REG_0324.CGM0[0x324]=0
CGM_REG_0325.CGM0[0x325]=0
CGM_REG_0326.CGM0[0x326]=0
CGM_REG_0327.CGM0[0x327]=0
CGM_REG_00C2.CGM0[0xc2]=0x10
CGM_REG_00C5.CGM0[0xc5]=0x786df
CGM_REG_00C7.CGM0[0xc7]=3
CGM_REG_031B.CGM0[0x31b]=0
CGM_REG_031C.CGM0[0x31c]=3
CGM_REG_031D.CGM0[0x31d]=0
CGM_REG_031E.CGM0[0x31e]=0
CGM_REG_031F.CGM0[0x31f]=0
CGM_REJECT_STATUS_BITMAP.CGM0[0x24a]=0x20
CGM_REP_CMD_FIFO_RJCT_STATUS.CGM0[0x20b]=0
CGM_RESERVED_MTCD.CGM0[0xae]=0x30
CGM_RESERVED_MTCP.CGM0[0xad]=0x300000600000000
CGM_RESERVED_SPARE_0.CGM0[0x90]=0xfffffffe
CGM_RESERVED_SPARE_1.CGM0[0x91]=0xffffffff
CGM_RESERVED_SPARE_2.CGM0[0x92]=0
CGM_RESERVED_SPARE_3.CGM0[0x93]=0
CGM_SBUS_BROADCAST_ID.CGM0[0x86]=0x7ff
CGM_SBUS_LAST_IN_CHAIN.CGM0[0x87]=0
CGM_SPB_PKT_RLS_NRDY_CTR.CGM0[0x300]=0
CGM_SPECIAL_CLOCK_CONTROLS.CGM0[0xc1]=2
CGM_SQM_ENQ_CMD_NRDY_CTR.CGM0[0x301]=0
CGM_SRAM_BUFFERS_FREE_MIN_STATUS.CGM0[0x293]=0x7efe
CGM_SRAM_BUFFERS_FREE_STATUS.CGM0[0x292]=0x8000
CGM_SRAM_BUFFERS_RJCT_PKT_CTR.CGM0[0x2bd]=0
CGM_SRAM_BUFFER_RLS_RPRT_BYTE_CTR.CGM0[0x2bb]=0x6e800c68901
CGM_SRAM_BUFFER_RLS_RPRT_PKT_CTR.CGM0[0x2ba]=0xe1a55dec
CGM_SRAM_HDRM_RSRC_FLOW_CONTROL_THS.CGM0[0x224]=0
CGM_SRAM_PDBS_FREE_MIN_STATUS.CGM0[0x295]=0x3fa3
CGM_SRAM_PDBS_FREE_STATUS.CGM0[0x294]=0x3fd9
CGM_SRAM_PDBS_RJCT_PKT_CTR.CGM0[0x2be]=0
CGM_SRAM_RSRC_ERR_PKT_CTR.CGM0[0x2c6]=0
CGM_STAT_DEQ_BILL_BUBBLE_REQ_CTR.CGM0[0x2fb]=0
CGM_STAT_DEQ_QSIZE_BUBBLE_REQ_CTR.CGM0[0x2fd]=0
CGM_STAT_ENQ_BILL_BUBBLE_REQ_CTR.CGM0[0x2fa]=0
CGM_STAT_ENQ_QSIZE_BUBBLE_REQ_CTR.CGM0[0x2fc]=0
CGM_STAT_RJCT_REASON_RJCT_MASK.CGM0[0x22b]=0x2007f80000002000000ffffc0000000000003c003f00001400000000000c000000000000007
CGM_SYSTEM_RED_QSIZE_FR_RSRC_TH.CGM0[0x214]=0
CGM_SYSTEM_RED_QSIZE_MAX_STATUS.CGM0[0x299]=0
CGM_SYSTEM_RED_QSIZE_STATUS.CGM0[0x298]=0
CGM_SYSTEM_RED_RANGE_FR_RSRC_TH.CGM0[0x213]=0
CGM_SYS_RED_SETTINGS.CGM0[0x237]=0x1e84
CGM_TAR_FIFO_RJCT_PKT_CTR.CGM0[0x2c4]=0
CGM_TAR_MCH_REP_FIFO_MAX_STATUS.CGM0[0x2a5]=2
CGM_TAR_MCH_REP_FIFO_STATUS.CGM0[0x2a4]=0
CGM_TAR_MCL_REP_FIFO_MAX_STATUS.CGM0[0x2a7]=0
CGM_TAR_MCL_REP_FIFO_STATUS.CGM0[0x2a6]=0
CGM_TAR_STATIC_CONFIGURATION.CGM0[0x206]=9
CGM_TAR_UC_REP_FIFO_MAX_STATUS.CGM0[0x2a3]=4
CGM_TAR_UC_REP_FIFO_STATUS.CGM0[0x2a2]=0
CGM_TOTAL_DRAM_RSRC_FLOW_CONTROL_THS.CGM0[0x222]=0
CGM_TOTAL_PB_VSQ_OC_ERR_INTERRUPT_MASK_REGISTER.CGM0[0x121]=0
CGM_TOTAL_PB_VSQ_OC_ERR_INTERRUPT_REGISTER.CGM0[0x120]=0
CGM_TOTAL_PB_VSQ_OC_ERR_INTERRUPT_REGISTER_TEST.CGM0[0x122]=0
CGM_TOTAL_SRAM_RSRC_FLOW_CONTROL_THS.CGM0[0x223]=0
CGM_TOTAL_VOQ_OC_ERR_INTERRUPT_MASK_REGISTER.CGM0[0x111]=0
CGM_TOTAL_VOQ_OC_ERR_INTERRUPT_REGISTER.CGM0[0x110]=0
CGM_TOTAL_VOQ_OC_ERR_INTERRUPT_REGISTER_TEST.CGM0[0x112]=0
CGM_UC_FWD_RX_REP_CTR.CGM0[0x2e2]=0xe0a921f4
CGM_UC_SNIF_0_PKT_DROP_CTR.CGM0[0x2ef]=0
CGM_UC_SNIF_0_RX_REP_CTR.CGM0[0x2e3]=0
CGM_UC_SNIF_1_PKT_DROP_CTR.CGM0[0x2f0]=0
CGM_UC_SNIF_1_RX_REP_CTR.CGM0[0x2e4]=0
CGM_UC_SNIF_2_PKT_DROP_CTR.CGM0[0x2f1]=0
CGM_UC_SNIF_2_RX_REP_CTR.CGM0[0x2e5]=0
CGM_VISIBILITY_RJCT_PKT_CTR.CGM0[0x2c8]=0
CGM_VISIBILITY_SETTINGS.CGM0[0x30e]=7
CGM_VISIBILITY_SRAM_ENQ_DATA_0.CGM0[0x312]=0x401800036008000
CGM_VISIBILITY_SRAM_ENQ_DATA_1.CGM0[0x313]=0x4390fc86c000000000000000000000000001e0284000fde7
CGM_VISIBILITY_SRAM_ENQ_DATA_2.CGM0[0x314]=0x184ec017fc007ffffc3cc0020000
CGM_VISIBILITY_TAR_DATA_0.CGM0[0x30f]=0xbff3b0094008000001c2091800000003c0090000001000000638020000000000000000000000000000000000000000000000000000001000000000000000000000006c0003
CGM_VISIBILITY_TAR_DATA_1.CGM0[0x310]=0xac000300000
CGM_VISIBILITY_TAR_DATA_2.CGM0[0x311]=0x7ffffc0c0003400c20060278006c0003853300003
CGM_VOQ_CONGESTION_FIFO_DATA.CGM0[0x2a0]=0
CGM_VOQ_CTR_ERR_INTERRUPT_MASK_REGISTER.CGM0[0x131]=0
CGM_VOQ_CTR_ERR_INTERRUPT_REGISTER.CGM0[0x130]=0
CGM_VOQ_CTR_ERR_INTERRUPT_REGISTER_TEST.CGM0[0x132]=0
CGM_VOQ_DRAM_BLOCK_BMP_MASK.CGM0[0x211]=0xa2e000a2e000a2e000a2e
CGM_VOQ_DRAM_BLOCK_SETTINGS.CGM0[0x212]=0xffffff
CGM_VOQ_DRAM_DEL_BUNDLE_CTR.CGM0[0x2b4]=0
CGM_VOQ_DRAM_DEL_BYTE_CTR.CGM0[0x2b5]=0
CGM_VOQ_DRAM_DEQ_RPRT_BYTE_CTR.CGM0[0x2e0]=0
CGM_VOQ_DRAM_DEQ_RPRT_CTR.CGM0[0x2df]=0
CGM_VOQ_DRAM_DEQ_TO_FABRIC_BUNDLE_CTR.CGM0[0x2ae]=0
CGM_VOQ_DRAM_DEQ_TO_FABRIC_BYTE_CTR.CGM0[0x2af]=0
CGM_VOQ_DRAM_ENQ_RPRT_BYTE_CTR.CGM0[0x2de]=0
CGM_VOQ_DRAM_ENQ_RPRT_CTR.CGM0[0x2dd]=0
CGM_VOQ_LATENCY_RJCT_SETTINGS.CGM0[0x236]=0
CGM_VOQ_OCCUPANCY_ERR_STATUS.CGM0[0x307]=0
CGM_VOQ_RJCT_SETTINGS.CGM0[0x220]=0
CGM_VOQ_SHRD_OC_RJCT_STATUS.CGM0[0x305]=0
CGM_VOQ_SRAM_BUFFERS_GRNTD_MAX_OC.CGM0[0x253]=0
CGM_VOQ_SRAM_BUFFERS_GRNTD_OC.CGM0[0x250]=0
CGM_VOQ_SRAM_BUFFERS_SHRD_FR.CGM0[0x252]=0xffff
CGM_VOQ_SRAM_BUFFERS_SHRD_MAX_OC.CGM0[0x254]=0xff
CGM_VOQ_SRAM_BUFFERS_SHRD_OC.CGM0[0x251]=0
CGM_VOQ_SRAM_DEL_BYTE_CTR.CGM0[0x2b3]=0
CGM_VOQ_SRAM_DEL_PKT_CTR.CGM0[0x2b2]=0
CGM_VOQ_SRAM_DEQ_RPRT_BYTE_CTR.CGM0[0x2dc]=0
CGM_VOQ_SRAM_DEQ_RPRT_CTR.CGM0[0x2db]=0
CGM_VOQ_SRAM_DEQ_TO_DRAM_BYTE_CTR.CGM0[0x2b1]=0
CGM_VOQ_SRAM_DEQ_TO_DRAM_PKT_CTR.CGM0[0x2b0]=0
CGM_VOQ_SRAM_DEQ_TO_FABRIC_BYTE_CTR.CGM0[0x2ad]=0
CGM_VOQ_SRAM_DEQ_TO_FABRIC_PKT_CTR.CGM0[0x2ac]=0
CGM_VOQ_SRAM_ENQ_BYTE_CTR.CGM0[0x2a9]=0
CGM_VOQ_SRAM_ENQ_PKT_CTR.CGM0[0x2a8]=0
CGM_VOQ_SRAM_ENQ_RJCT_BYTE_CTR.CGM0[0x2ab]=0
CGM_VOQ_SRAM_ENQ_RJCT_PKT_CTR.CGM0[0x2aa]=0
CGM_VOQ_SRAM_ENQ_RPRT_BYTE_CTR.CGM0[0x2da]=0
CGM_VOQ_SRAM_ENQ_RPRT_CTR.CGM0[0x2d9]=0
CGM_VOQ_SRAM_PDS_GRNTD_MAX_OC.CGM0[0x25d]=0
CGM_VOQ_SRAM_PDS_GRNTD_OC.CGM0[0x25a]=0
CGM_VOQ_SRAM_PDS_SHRD_FR.CGM0[0x25c]=0xff64
CGM_VOQ_SRAM_PDS_SHRD_MAX_OC.CGM0[0x25e]=0xd6
CGM_VOQ_SRAM_PDS_SHRD_OC.CGM0[0x25b]=0
CGM_VOQ_SRAM_WORDS_GRNTD_MAX_OC.CGM0[0x258]=0
CGM_VOQ_SRAM_WORDS_GRNTD_OC.CGM0[0x255]=0
CGM_VOQ_SRAM_WORDS_SHRD_FR.CGM0[0x257]=0xfffff
CGM_VOQ_SRAM_WORDS_SHRD_MAX_OC.CGM0[0x259]=0xec0
CGM_VOQ_SRAM_WORDS_SHRD_OC.CGM0[0x256]=0
CGM_VOQ_WORDS_GRNTD_MAX_OC.CGM0[0x24e]=0
CGM_VOQ_WORDS_GRNTD_OC.CGM0[0x24b]=0
CGM_VOQ_WORDS_SHRD_FR.CGM0[0x24d]=0x7ff8800
CGM_VOQ_WORDS_SHRD_MAX_OC.CGM0[0x24f]=0xec0
CGM_VOQ_WORDS_SHRD_OC.CGM0[0x24c]=0
CGM_VSQA_FC_STATUS_MASK.CGM0[0x219]=0xf
CGM_VSQA_OCCUPANCY_ERR_STATUS.CGM0[0x308]=0
CGM_VSQB_FC_STATUS_MASK.CGM0[0x21a]=0xffffffff
CGM_VSQB_OCCUPANCY_ERR_STATUS.CGM0[0x309]=0
CGM_VSQC_FC_STATUS_MASK.CGM0[0x21b]=0xffffffffffffffffffffffffffffffff
CGM_VSQC_OCCUPANCY_ERR_STATUS.CGM0[0x30a]=0
CGM_VSQD_FC_STATUS_MASK.CGM0[0x21c]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
CGM_VSQD_OCCUPANCY_ERR_STATUS.CGM0[0x30b]=0
CGM_VSQE_FC_STATUS_MASK.CGM0[0x21d]=0xffffffffffffffff
CGM_VSQE_OCCUPANCY_ERR_STATUS.CGM0[0x30c]=0
CGM_VSQF_FC_STATUS_MASK.CGM0[0x21e]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
CGM_VSQF_OCCUPANCY_ERR_STATUS.CGM0[0x30d]=0
CGM_VSQ_CATEGORY_RANGES.CGM0[0x21f]=0x1fffc0000000
CGM_VSQ_CTR_ERR_INTERRUPT_MASK_REGISTER.CGM0[0x141]=0
CGM_VSQ_CTR_ERR_INTERRUPT_REGISTER.CGM0[0x140]=0
CGM_VSQ_CTR_ERR_INTERRUPT_REGISTER_TEST.CGM0[0x142]=0
CGM_VSQ_SETTINGS.CGM0[0x218]=3
CGM_VSQ_SRAM_ENQ_BYTE_CTR.CGM0[0x2b7]=0x6e800c8c8bf
CGM_VSQ_SRAM_ENQ_PKT_CTR.CGM0[0x2b6]=0xe1a55e81
CGM_VSQ_SRAM_ENQ_RJCT_BYTE_CTR.CGM0[0x2b9]=0x1142e684
CGM_VSQ_SRAM_ENQ_RJCT_PKT_CTR.CGM0[0x2b8]=0x2c2081
CGM_XOR_MEM_INIT_DONE.CGM0[0x201]=0xfffffff
CLMAC_CLEAR_ECC_STATUS.eth1[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth2[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth3[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth4[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth5[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth6[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth7[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth8[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth9[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth10[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth11[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth12[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth13[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth14[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth15[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth16[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth17[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth18[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth19[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth20[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth21[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth22[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth23[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth24[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth25[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth26[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth27[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth28[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth29[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth30[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth31[0x63500]=0
CLMAC_CLEAR_ECC_STATUS.eth32[0x63500]=0
CLMAC_CLEAR_FIFO_STATUS.eth1[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth2[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth3[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth4[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth5[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth6[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth7[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth8[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth9[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth10[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth11[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth12[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth13[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth14[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth15[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth16[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth17[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth18[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth19[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth20[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth21[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth22[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth23[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth24[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth25[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth26[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth27[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth28[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth29[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth30[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth31[0x61700]=0
CLMAC_CLEAR_FIFO_STATUS.eth32[0x61700]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth1[0x60b00]=3
CLMAC_CLEAR_RX_LSS_STATUS.eth2[0x60b00]=3
CLMAC_CLEAR_RX_LSS_STATUS.eth3[0x60b00]=3
CLMAC_CLEAR_RX_LSS_STATUS.eth4[0x60b00]=3
CLMAC_CLEAR_RX_LSS_STATUS.eth5[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth6[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth7[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth8[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth9[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth10[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth11[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth12[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth13[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth14[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth15[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth16[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth17[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth18[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth19[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth20[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth21[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth22[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth23[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth24[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth25[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth26[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth27[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth28[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth29[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth30[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth31[0x60b00]=0
CLMAC_CLEAR_RX_LSS_STATUS.eth32[0x60b00]=3
CLMAC_CTRL.eth1[0x60100]=0xd003
CLMAC_CTRL.eth2[0x60100]=0xd003
CLMAC_CTRL.eth3[0x60100]=0xd003
CLMAC_CTRL.eth4[0x60100]=0xd003
CLMAC_CTRL.eth5[0x60100]=0xd040
CLMAC_CTRL.eth6[0x60100]=0xd040
CLMAC_CTRL.eth7[0x60100]=0xd040
CLMAC_CTRL.eth8[0x60100]=0xd040
CLMAC_CTRL.eth9[0x60100]=0xd040
CLMAC_CTRL.eth10[0x60100]=0xd040
CLMAC_CTRL.eth11[0x60100]=0xd040
CLMAC_CTRL.eth12[0x60100]=0xd040
CLMAC_CTRL.eth13[0x60100]=0xd040
CLMAC_CTRL.eth14[0x60100]=0xd040
CLMAC_CTRL.eth15[0x60100]=0xd040
CLMAC_CTRL.eth16[0x60100]=0xd040
CLMAC_CTRL.eth17[0x60100]=0xd040
CLMAC_CTRL.eth18[0x60100]=0xd040
CLMAC_CTRL.eth19[0x60100]=0xd040
CLMAC_CTRL.eth20[0x60100]=0xd040
CLMAC_CTRL.eth21[0x60100]=0xd040
CLMAC_CTRL.eth22[0x60100]=0xd040
CLMAC_CTRL.eth23[0x60100]=0xd040
CLMAC_CTRL.eth24[0x60100]=0xd040
CLMAC_CTRL.eth25[0x60100]=0xd040
CLMAC_CTRL.eth26[0x60100]=0xd040
CLMAC_CTRL.eth27[0x60100]=0xd040
CLMAC_CTRL.eth28[0x60100]=0xd040
CLMAC_CTRL.eth29[0x60100]=0xd040
CLMAC_CTRL.eth30[0x60100]=0xd040
CLMAC_CTRL.eth31[0x60100]=0xd040
CLMAC_CTRL.eth32[0x60100]=0xd003
CLMAC_E2ECC_DATA_HDR_0.eth1[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth2[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth3[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth4[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth5[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth6[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth7[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth8[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth9[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth10[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth11[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth12[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth13[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth14[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth15[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth16[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth17[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth18[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth19[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth20[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth21[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth22[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth23[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth24[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth25[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth26[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth27[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth28[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth29[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth30[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth31[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_0.eth32[0x62500]=0xffffffffffff0000
CLMAC_E2ECC_DATA_HDR_1.eth1[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth2[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth3[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth4[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth5[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth6[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth7[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth8[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth9[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth10[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth11[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth12[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth13[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth14[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth15[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth16[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth17[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth18[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth19[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth20[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth21[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth22[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth23[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth24[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth25[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth26[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth27[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth28[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth29[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth30[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth31[0x62600]=0x170000000
CLMAC_E2ECC_DATA_HDR_1.eth32[0x62600]=0x170000000
CLMAC_E2ECC_MODULE_HDR_0.eth1[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth2[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth3[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth4[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth5[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth6[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth7[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth8[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth9[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth10[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth11[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth12[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth13[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth14[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth15[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth16[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth17[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth18[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth19[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth20[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth21[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth22[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth23[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth24[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth25[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth26[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth27[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth28[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth29[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth30[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth31[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_0.eth32[0x62300]=0xfb800ffe20000000
CLMAC_E2ECC_MODULE_HDR_1.eth1[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth2[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth3[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth4[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth5[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth6[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth7[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth8[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth9[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth10[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth11[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth12[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth13[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth14[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth15[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth16[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth17[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth18[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth19[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth20[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth21[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth22[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth23[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth24[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth25[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth26[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth27[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth28[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth29[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth30[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth31[0x62400]=0
CLMAC_E2ECC_MODULE_HDR_1.eth32[0x62400]=0
CLMAC_E2EFC_DATA_HDR_0.eth1[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth2[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth3[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth4[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth5[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth6[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth7[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth8[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth9[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth10[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth11[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth12[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth13[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth14[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth15[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth16[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth17[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth18[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth19[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth20[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth21[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth22[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth23[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth24[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth25[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth26[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth27[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth28[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth29[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth30[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth31[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_0.eth32[0x62900]=0xffffffffffff0000
CLMAC_E2EFC_DATA_HDR_1.eth1[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth2[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth3[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth4[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth5[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth6[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth7[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth8[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth9[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth10[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth11[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth12[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth13[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth14[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth15[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth16[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth17[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth18[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth19[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth20[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth21[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth22[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth23[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth24[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth25[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth26[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth27[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth28[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth29[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth30[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth31[0x62a00]=0x170000000
CLMAC_E2EFC_DATA_HDR_1.eth32[0x62a00]=0x170000000
CLMAC_E2EFC_MODULE_HDR_0.eth1[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth2[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth3[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth4[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth5[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth6[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth7[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth8[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth9[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth10[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth11[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth12[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth13[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth14[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth15[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth16[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth17[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth18[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth19[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth20[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth21[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth22[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth23[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth24[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth25[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth26[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth27[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth28[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth29[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth30[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth31[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_0.eth32[0x62700]=0xfb800ffe10000000
CLMAC_E2EFC_MODULE_HDR_1.eth1[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth2[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth3[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth4[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth5[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth6[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth7[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth8[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth9[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth10[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth11[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth12[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth13[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth14[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth15[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth16[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth17[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth18[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth19[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth20[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth21[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth22[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth23[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth24[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth25[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth26[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth27[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth28[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth29[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth30[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth31[0x62800]=0
CLMAC_E2EFC_MODULE_HDR_1.eth32[0x62800]=0
CLMAC_E2E_CTRL.eth1[0x62200]=0
CLMAC_E2E_CTRL.eth2[0x62200]=0
CLMAC_E2E_CTRL.eth3[0x62200]=0
CLMAC_E2E_CTRL.eth4[0x62200]=0
CLMAC_E2E_CTRL.eth5[0x62200]=0
CLMAC_E2E_CTRL.eth6[0x62200]=0
CLMAC_E2E_CTRL.eth7[0x62200]=0
CLMAC_E2E_CTRL.eth8[0x62200]=0
CLMAC_E2E_CTRL.eth9[0x62200]=0
CLMAC_E2E_CTRL.eth10[0x62200]=0
CLMAC_E2E_CTRL.eth11[0x62200]=0
CLMAC_E2E_CTRL.eth12[0x62200]=0
CLMAC_E2E_CTRL.eth13[0x62200]=0
CLMAC_E2E_CTRL.eth14[0x62200]=0
CLMAC_E2E_CTRL.eth15[0x62200]=0
CLMAC_E2E_CTRL.eth16[0x62200]=0
CLMAC_E2E_CTRL.eth17[0x62200]=0
CLMAC_E2E_CTRL.eth18[0x62200]=0
CLMAC_E2E_CTRL.eth19[0x62200]=0
CLMAC_E2E_CTRL.eth20[0x62200]=0
CLMAC_E2E_CTRL.eth21[0x62200]=0
CLMAC_E2E_CTRL.eth22[0x62200]=0
CLMAC_E2E_CTRL.eth23[0x62200]=0
CLMAC_E2E_CTRL.eth24[0x62200]=0
CLMAC_E2E_CTRL.eth25[0x62200]=0
CLMAC_E2E_CTRL.eth26[0x62200]=0
CLMAC_E2E_CTRL.eth27[0x62200]=0
CLMAC_E2E_CTRL.eth28[0x62200]=0
CLMAC_E2E_CTRL.eth29[0x62200]=0
CLMAC_E2E_CTRL.eth30[0x62200]=0
CLMAC_E2E_CTRL.eth31[0x62200]=0
CLMAC_E2E_CTRL.eth32[0x62200]=0
CLMAC_ECC_CTRL.eth1[0x62f00]=7
CLMAC_ECC_CTRL.eth2[0x62f00]=7
CLMAC_ECC_CTRL.eth3[0x62f00]=7
CLMAC_ECC_CTRL.eth4[0x62f00]=7
CLMAC_ECC_CTRL.eth5[0x62f00]=7
CLMAC_ECC_CTRL.eth6[0x62f00]=7
CLMAC_ECC_CTRL.eth7[0x62f00]=7
CLMAC_ECC_CTRL.eth8[0x62f00]=7
CLMAC_ECC_CTRL.eth9[0x62f00]=7
CLMAC_ECC_CTRL.eth10[0x62f00]=7
CLMAC_ECC_CTRL.eth11[0x62f00]=7
CLMAC_ECC_CTRL.eth12[0x62f00]=7
CLMAC_ECC_CTRL.eth13[0x62f00]=7
CLMAC_ECC_CTRL.eth14[0x62f00]=7
CLMAC_ECC_CTRL.eth15[0x62f00]=7
CLMAC_ECC_CTRL.eth16[0x62f00]=7
CLMAC_ECC_CTRL.eth17[0x62f00]=7
CLMAC_ECC_CTRL.eth18[0x62f00]=7
CLMAC_ECC_CTRL.eth19[0x62f00]=7
CLMAC_ECC_CTRL.eth20[0x62f00]=7
CLMAC_ECC_CTRL.eth21[0x62f00]=7
CLMAC_ECC_CTRL.eth22[0x62f00]=7
CLMAC_ECC_CTRL.eth23[0x62f00]=7
CLMAC_ECC_CTRL.eth24[0x62f00]=7
CLMAC_ECC_CTRL.eth25[0x62f00]=7
CLMAC_ECC_CTRL.eth26[0x62f00]=7
CLMAC_ECC_CTRL.eth27[0x62f00]=7
CLMAC_ECC_CTRL.eth28[0x62f00]=7
CLMAC_ECC_CTRL.eth29[0x62f00]=7
CLMAC_ECC_CTRL.eth30[0x62f00]=7
CLMAC_ECC_CTRL.eth31[0x62f00]=7
CLMAC_ECC_CTRL.eth32[0x62f00]=7
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth1[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth2[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth3[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth4[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth5[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth6[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth7[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth8[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth9[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth10[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth11[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth12[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth13[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth14[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth15[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth16[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth17[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth18[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth19[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth20[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth21[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth22[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth23[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth24[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth25[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth26[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth27[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth28[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth29[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth30[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth31[0x63000]=0
CLMAC_ECC_FORCE_DOUBLE_BIT_ERR.eth32[0x63000]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth1[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth2[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth3[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth4[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth5[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth6[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth7[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth8[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth9[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth10[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth11[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth12[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth13[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth14[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth15[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth16[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth17[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth18[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth19[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth20[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth21[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth22[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth23[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth24[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth25[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth26[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth27[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth28[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth29[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth30[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth31[0x63100]=0
CLMAC_ECC_FORCE_SINGLE_BIT_ERR.eth32[0x63100]=0
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth1[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth2[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth3[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth4[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth5[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth6[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth7[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth8[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth9[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth10[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth11[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth12[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth13[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth14[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth15[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth16[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth17[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth18[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth19[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth20[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth21[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth22[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth23[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth24[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth25[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth26[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth27[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth28[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth29[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth30[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth31[0x61b00]=0xf4240
CLMAC_EEE_1_SEC_LINK_STATUS_TIMER.eth32[0x61b00]=0xf4240
CLMAC_EEE_CTRL.eth1[0x61900]=0
CLMAC_EEE_CTRL.eth2[0x61900]=0
CLMAC_EEE_CTRL.eth3[0x61900]=0
CLMAC_EEE_CTRL.eth4[0x61900]=0
CLMAC_EEE_CTRL.eth5[0x61900]=0
CLMAC_EEE_CTRL.eth6[0x61900]=0
CLMAC_EEE_CTRL.eth7[0x61900]=0
CLMAC_EEE_CTRL.eth8[0x61900]=0
CLMAC_EEE_CTRL.eth9[0x61900]=0
CLMAC_EEE_CTRL.eth10[0x61900]=0
CLMAC_EEE_CTRL.eth11[0x61900]=0
CLMAC_EEE_CTRL.eth12[0x61900]=0
CLMAC_EEE_CTRL.eth13[0x61900]=0
CLMAC_EEE_CTRL.eth14[0x61900]=0
CLMAC_EEE_CTRL.eth15[0x61900]=0
CLMAC_EEE_CTRL.eth16[0x61900]=0
CLMAC_EEE_CTRL.eth17[0x61900]=0
CLMAC_EEE_CTRL.eth18[0x61900]=0
CLMAC_EEE_CTRL.eth19[0x61900]=0
CLMAC_EEE_CTRL.eth20[0x61900]=0
CLMAC_EEE_CTRL.eth21[0x61900]=0
CLMAC_EEE_CTRL.eth22[0x61900]=0
CLMAC_EEE_CTRL.eth23[0x61900]=0
CLMAC_EEE_CTRL.eth24[0x61900]=0
CLMAC_EEE_CTRL.eth25[0x61900]=0
CLMAC_EEE_CTRL.eth26[0x61900]=0
CLMAC_EEE_CTRL.eth27[0x61900]=0
CLMAC_EEE_CTRL.eth28[0x61900]=0
CLMAC_EEE_CTRL.eth29[0x61900]=0
CLMAC_EEE_CTRL.eth30[0x61900]=0
CLMAC_EEE_CTRL.eth31[0x61900]=0
CLMAC_EEE_CTRL.eth32[0x61900]=0
CLMAC_EEE_TIMERS.eth1[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth2[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth3[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth4[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth5[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth6[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth7[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth8[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth9[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth10[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth11[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth12[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth13[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth14[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth15[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth16[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth17[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth18[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth19[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth20[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth21[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth22[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth23[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth24[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth25[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth26[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth27[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth28[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth29[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth30[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth31[0x61a00]=0x138000000000000
CLMAC_EEE_TIMERS.eth32[0x61a00]=0x138000000000000
CLMAC_FIFO_STATUS.eth1[0x61600]=0x100
CLMAC_FIFO_STATUS.eth2[0x61600]=0x100
CLMAC_FIFO_STATUS.eth3[0x61600]=0x100
CLMAC_FIFO_STATUS.eth4[0x61600]=0x100
CLMAC_FIFO_STATUS.eth5[0x61600]=0x100
CLMAC_FIFO_STATUS.eth6[0x61600]=0x100
CLMAC_FIFO_STATUS.eth7[0x61600]=0x100
CLMAC_FIFO_STATUS.eth8[0x61600]=0x100
CLMAC_FIFO_STATUS.eth9[0x61600]=0x100
CLMAC_FIFO_STATUS.eth10[0x61600]=0x100
CLMAC_FIFO_STATUS.eth11[0x61600]=0x100
CLMAC_FIFO_STATUS.eth12[0x61600]=0x100
CLMAC_FIFO_STATUS.eth13[0x61600]=0x100
CLMAC_FIFO_STATUS.eth14[0x61600]=0x100
CLMAC_FIFO_STATUS.eth15[0x61600]=0x100
CLMAC_FIFO_STATUS.eth16[0x61600]=0x100
CLMAC_FIFO_STATUS.eth17[0x61600]=0x100
CLMAC_FIFO_STATUS.eth18[0x61600]=0x100
CLMAC_FIFO_STATUS.eth19[0x61600]=0x100
CLMAC_FIFO_STATUS.eth20[0x61600]=0x100
CLMAC_FIFO_STATUS.eth21[0x61600]=0x100
CLMAC_FIFO_STATUS.eth22[0x61600]=0x100
CLMAC_FIFO_STATUS.eth23[0x61600]=0x100
CLMAC_FIFO_STATUS.eth24[0x61600]=0x100
CLMAC_FIFO_STATUS.eth25[0x61600]=0x100
CLMAC_FIFO_STATUS.eth26[0x61600]=0x100
CLMAC_FIFO_STATUS.eth27[0x61600]=0x100
CLMAC_FIFO_STATUS.eth28[0x61600]=0x100
CLMAC_FIFO_STATUS.eth29[0x61600]=0x100
CLMAC_FIFO_STATUS.eth30[0x61600]=0x100
CLMAC_FIFO_STATUS.eth31[0x61600]=0x100
CLMAC_FIFO_STATUS.eth32[0x61600]=0x100
CLMAC_GMII_EEE_CTRL.eth1[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth2[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth3[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth4[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth5[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth6[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth7[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth8[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth9[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth10[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth11[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth12[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth13[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth14[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth15[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth16[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth17[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth18[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth19[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth20[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth21[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth22[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth23[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth24[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth25[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth26[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth27[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth28[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth29[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth30[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth31[0x61e00]=0
CLMAC_GMII_EEE_CTRL.eth32[0x61e00]=0
CLMAC_HIGIG_HDR_0.eth1[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth2[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth3[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth4[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth5[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth6[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth7[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth8[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth9[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth10[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth11[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth12[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth13[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth14[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth15[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth16[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth17[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth18[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth19[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth20[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth21[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth22[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth23[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth24[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth25[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth26[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth27[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth28[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth29[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth30[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth31[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_0.eth32[0x61c00]=0xfb80000000000000
CLMAC_HIGIG_HDR_1.eth1[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth2[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth3[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth4[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth5[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth6[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth7[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth8[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth9[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth10[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth11[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth12[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth13[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth14[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth15[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth16[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth17[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth18[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth19[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth20[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth21[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth22[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth23[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth24[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth25[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth26[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth27[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth28[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth29[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth30[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth31[0x61d00]=0
CLMAC_HIGIG_HDR_1.eth32[0x61d00]=0
CLMAC_INTR_ENABLE.eth1[0x63700]=0
CLMAC_INTR_ENABLE.eth2[0x63700]=0
CLMAC_INTR_ENABLE.eth3[0x63700]=0
CLMAC_INTR_ENABLE.eth4[0x63700]=0
CLMAC_INTR_ENABLE.eth5[0x63700]=0
CLMAC_INTR_ENABLE.eth6[0x63700]=0
CLMAC_INTR_ENABLE.eth7[0x63700]=0
CLMAC_INTR_ENABLE.eth8[0x63700]=0
CLMAC_INTR_ENABLE.eth9[0x63700]=0
CLMAC_INTR_ENABLE.eth10[0x63700]=0
CLMAC_INTR_ENABLE.eth11[0x63700]=0
CLMAC_INTR_ENABLE.eth12[0x63700]=0
CLMAC_INTR_ENABLE.eth13[0x63700]=0
CLMAC_INTR_ENABLE.eth14[0x63700]=0
CLMAC_INTR_ENABLE.eth15[0x63700]=0
CLMAC_INTR_ENABLE.eth16[0x63700]=0
CLMAC_INTR_ENABLE.eth17[0x63700]=0
CLMAC_INTR_ENABLE.eth18[0x63700]=0
CLMAC_INTR_ENABLE.eth19[0x63700]=0
CLMAC_INTR_ENABLE.eth20[0x63700]=0
CLMAC_INTR_ENABLE.eth21[0x63700]=0
CLMAC_INTR_ENABLE.eth22[0x63700]=0
CLMAC_INTR_ENABLE.eth23[0x63700]=0
CLMAC_INTR_ENABLE.eth24[0x63700]=0
CLMAC_INTR_ENABLE.eth25[0x63700]=0
CLMAC_INTR_ENABLE.eth26[0x63700]=0
CLMAC_INTR_ENABLE.eth27[0x63700]=0
CLMAC_INTR_ENABLE.eth28[0x63700]=0
CLMAC_INTR_ENABLE.eth29[0x63700]=0
CLMAC_INTR_ENABLE.eth30[0x63700]=0
CLMAC_INTR_ENABLE.eth31[0x63700]=0
CLMAC_INTR_ENABLE.eth32[0x63700]=0
CLMAC_INTR_STATUS.eth1[0x63600]=0
CLMAC_INTR_STATUS.eth2[0x63600]=0
CLMAC_INTR_STATUS.eth3[0x63600]=0
CLMAC_INTR_STATUS.eth4[0x63600]=0
CLMAC_INTR_STATUS.eth5[0x63600]=0x1000
CLMAC_INTR_STATUS.eth6[0x63600]=0x1000
CLMAC_INTR_STATUS.eth7[0x63600]=0x1000
CLMAC_INTR_STATUS.eth8[0x63600]=0x1000
CLMAC_INTR_STATUS.eth9[0x63600]=0x1000
CLMAC_INTR_STATUS.eth10[0x63600]=0x1000
CLMAC_INTR_STATUS.eth11[0x63600]=0x1000
CLMAC_INTR_STATUS.eth12[0x63600]=0x1000
CLMAC_INTR_STATUS.eth13[0x63600]=0x1000
CLMAC_INTR_STATUS.eth14[0x63600]=0x1000
CLMAC_INTR_STATUS.eth15[0x63600]=0x1000
CLMAC_INTR_STATUS.eth16[0x63600]=0x1000
CLMAC_INTR_STATUS.eth17[0x63600]=0x1000
CLMAC_INTR_STATUS.eth18[0x63600]=0x1000
CLMAC_INTR_STATUS.eth19[0x63600]=0x1000
CLMAC_INTR_STATUS.eth20[0x63600]=0x1000
CLMAC_INTR_STATUS.eth21[0x63600]=0x1000
CLMAC_INTR_STATUS.eth22[0x63600]=0x1000
CLMAC_INTR_STATUS.eth23[0x63600]=0x1000
CLMAC_INTR_STATUS.eth24[0x63600]=0x1000
CLMAC_INTR_STATUS.eth25[0x63600]=0x1000
CLMAC_INTR_STATUS.eth26[0x63600]=0x1000
CLMAC_INTR_STATUS.eth27[0x63600]=0x1000
CLMAC_INTR_STATUS.eth28[0x63600]=0x1000
CLMAC_INTR_STATUS.eth29[0x63600]=0x1000
CLMAC_INTR_STATUS.eth30[0x63600]=0x1000
CLMAC_INTR_STATUS.eth31[0x63600]=0x1000
CLMAC_INTR_STATUS.eth32[0x63600]=0
CLMAC_LAG_FAILOVER_STATUS.eth1[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth2[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth3[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth4[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth5[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth6[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth7[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth8[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth9[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth10[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth11[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth12[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth13[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth14[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth15[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth16[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth17[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth18[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth19[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth20[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth21[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth22[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth23[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth24[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth25[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth26[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth27[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth28[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth29[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth30[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth31[0x61800]=0
CLMAC_LAG_FAILOVER_STATUS.eth32[0x61800]=0
CLMAC_LLFC_CTRL.eth1[0x61100]=0x600
CLMAC_LLFC_CTRL.eth2[0x61100]=0x600
CLMAC_LLFC_CTRL.eth3[0x61100]=0x600
CLMAC_LLFC_CTRL.eth4[0x61100]=0x600
CLMAC_LLFC_CTRL.eth5[0x61100]=0x600
CLMAC_LLFC_CTRL.eth6[0x61100]=0x600
CLMAC_LLFC_CTRL.eth7[0x61100]=0x600
CLMAC_LLFC_CTRL.eth8[0x61100]=0x600
CLMAC_LLFC_CTRL.eth9[0x61100]=0x600
CLMAC_LLFC_CTRL.eth10[0x61100]=0x600
CLMAC_LLFC_CTRL.eth11[0x61100]=0x600
CLMAC_LLFC_CTRL.eth12[0x61100]=0x600
CLMAC_LLFC_CTRL.eth13[0x61100]=0x600
CLMAC_LLFC_CTRL.eth14[0x61100]=0x600
CLMAC_LLFC_CTRL.eth15[0x61100]=0x600
CLMAC_LLFC_CTRL.eth16[0x61100]=0x600
CLMAC_LLFC_CTRL.eth17[0x61100]=0x600
CLMAC_LLFC_CTRL.eth18[0x61100]=0x600
CLMAC_LLFC_CTRL.eth19[0x61100]=0x600
CLMAC_LLFC_CTRL.eth20[0x61100]=0x600
CLMAC_LLFC_CTRL.eth21[0x61100]=0x600
CLMAC_LLFC_CTRL.eth22[0x61100]=0x600
CLMAC_LLFC_CTRL.eth23[0x61100]=0x600
CLMAC_LLFC_CTRL.eth24[0x61100]=0x600
CLMAC_LLFC_CTRL.eth25[0x61100]=0x600
CLMAC_LLFC_CTRL.eth26[0x61100]=0x600
CLMAC_LLFC_CTRL.eth27[0x61100]=0x600
CLMAC_LLFC_CTRL.eth28[0x61100]=0x600
CLMAC_LLFC_CTRL.eth29[0x61100]=0x600
CLMAC_LLFC_CTRL.eth30[0x61100]=0x600
CLMAC_LLFC_CTRL.eth31[0x61100]=0x600
CLMAC_LLFC_CTRL.eth32[0x61100]=0x600
CLMAC_MEM_CTRL.eth1[0x62d00]=0
CLMAC_MEM_CTRL.eth2[0x62d00]=0
CLMAC_MEM_CTRL.eth3[0x62d00]=0
CLMAC_MEM_CTRL.eth4[0x62d00]=0
CLMAC_MEM_CTRL.eth5[0x62d00]=0
CLMAC_MEM_CTRL.eth6[0x62d00]=0
CLMAC_MEM_CTRL.eth7[0x62d00]=0
CLMAC_MEM_CTRL.eth8[0x62d00]=0
CLMAC_MEM_CTRL.eth9[0x62d00]=0
CLMAC_MEM_CTRL.eth10[0x62d00]=0
CLMAC_MEM_CTRL.eth11[0x62d00]=0
CLMAC_MEM_CTRL.eth12[0x62d00]=0
CLMAC_MEM_CTRL.eth13[0x62d00]=0
CLMAC_MEM_CTRL.eth14[0x62d00]=0
CLMAC_MEM_CTRL.eth15[0x62d00]=0
CLMAC_MEM_CTRL.eth16[0x62d00]=0
CLMAC_MEM_CTRL.eth17[0x62d00]=0
CLMAC_MEM_CTRL.eth18[0x62d00]=0
CLMAC_MEM_CTRL.eth19[0x62d00]=0
CLMAC_MEM_CTRL.eth20[0x62d00]=0
CLMAC_MEM_CTRL.eth21[0x62d00]=0
CLMAC_MEM_CTRL.eth22[0x62d00]=0
CLMAC_MEM_CTRL.eth23[0x62d00]=0
CLMAC_MEM_CTRL.eth24[0x62d00]=0
CLMAC_MEM_CTRL.eth25[0x62d00]=0
CLMAC_MEM_CTRL.eth26[0x62d00]=0
CLMAC_MEM_CTRL.eth27[0x62d00]=0
CLMAC_MEM_CTRL.eth28[0x62d00]=0
CLMAC_MEM_CTRL.eth29[0x62d00]=0
CLMAC_MEM_CTRL.eth30[0x62d00]=0
CLMAC_MEM_CTRL.eth31[0x62d00]=0
CLMAC_MEM_CTRL.eth32[0x62d00]=0
CLMAC_MERGE_CLEAR_STATUS.eth1[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth2[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth3[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth4[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth5[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth6[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth7[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth8[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth9[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth10[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth11[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth12[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth13[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth14[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth15[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth16[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth17[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth18[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth19[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth20[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth21[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth22[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth23[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth24[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth25[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth26[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth27[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth28[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth29[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth30[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth31[0x64000]=0
CLMAC_MERGE_CLEAR_STATUS.eth32[0x64000]=0
CLMAC_MERGE_CONFIG.eth1[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth2[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth3[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth4[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth5[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth6[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth7[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth8[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth9[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth10[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth11[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth12[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth13[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth14[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth15[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth16[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth17[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth18[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth19[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth20[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth21[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth22[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth23[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth24[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth25[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth26[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth27[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth28[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth29[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth30[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth31[0x63800]=0x6848
CLMAC_MERGE_CONFIG.eth32[0x63800]=0x6848
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth1[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth2[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth3[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth4[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth5[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth6[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth7[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth8[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth9[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth10[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth11[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth12[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth13[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth14[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth15[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth16[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth17[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth18[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth19[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth20[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth21[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth22[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth23[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth24[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth25[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth26[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth27[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth28[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth29[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth30[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth31[0x63c00]=1
CLMAC_MERGE_CTRL_SECRET_CONFIG.eth32[0x63c00]=1
CLMAC_MERGE_FRG_CNT_CONFIG.eth1[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth2[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth3[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth4[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth5[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth6[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth7[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth8[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth9[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth10[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth11[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth12[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth13[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth14[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth15[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth16[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth17[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth18[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth19[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth20[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth21[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth22[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth23[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth24[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth25[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth26[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth27[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth28[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth29[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth30[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth31[0x63b00]=0xb37f4ce6
CLMAC_MERGE_FRG_CNT_CONFIG.eth32[0x63b00]=0xb37f4ce6
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth1[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth2[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth3[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth4[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth5[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth6[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth7[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth8[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth9[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth10[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth11[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth12[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth13[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth14[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth15[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth16[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth17[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth18[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth19[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth20[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth21[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth22[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth23[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth24[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth25[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth26[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth27[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth28[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth29[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth30[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth31[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG.eth32[0x64100]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth1[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth2[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth3[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth4[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth5[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth6[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth7[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth8[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth9[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth10[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth11[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth12[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth13[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth14[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth15[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth16[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth17[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth18[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth19[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth20[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth21[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth22[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth23[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth24[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth25[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth26[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth27[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth28[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth29[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth30[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth31[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0.eth32[0x64200]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth1[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth2[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth3[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth4[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth5[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth6[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth7[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth8[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth9[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth10[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth11[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth12[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth13[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth14[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth15[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth16[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth17[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth18[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth19[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth20[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth21[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth22[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth23[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth24[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth25[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth26[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth27[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth28[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth29[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth30[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth31[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1.eth32[0x64300]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth1[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth2[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth3[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth4[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth5[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth6[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth7[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth8[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth9[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth10[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth11[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth12[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth13[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth14[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth15[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth16[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth17[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth18[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth19[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth20[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth21[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth22[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth23[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth24[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth25[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth26[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth27[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth28[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth29[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth30[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth31[0x64400]=0
CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2.eth32[0x64400]=0
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth1[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth2[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth3[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth4[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth5[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth6[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth7[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth8[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth9[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth10[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth11[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth12[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth13[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth14[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth15[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth16[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth17[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth18[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth19[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth20[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth21[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth22[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth23[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth24[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth25[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth26[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth27[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth28[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth29[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth30[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth31[0x63d00]=0xffffff
CLMAC_MERGE_RX_TIMEOUT_CONFIG.eth32[0x63d00]=0xffffff
CLMAC_MERGE_SMD_CONFIG_0.eth1[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth2[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth3[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth4[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth5[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth6[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth7[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth8[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth9[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth10[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth11[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth12[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth13[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth14[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth15[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth16[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth17[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth18[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth19[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth20[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth21[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth22[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth23[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth24[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth25[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth26[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth27[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth28[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth29[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth30[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth31[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_0.eth32[0x63900]=0x2a9e5261b37f4ce6
CLMAC_MERGE_SMD_CONFIG_1.eth1[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth2[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth3[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth4[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth5[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth6[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth7[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth8[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth9[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth10[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth11[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth12[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth13[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth14[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth15[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth16[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth17[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth18[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth19[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth20[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth21[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth22[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth23[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth24[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth25[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth26[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth27[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth28[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth29[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth30[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth31[0x63a00]=0x1907
CLMAC_MERGE_SMD_CONFIG_1.eth32[0x63a00]=0x1907
CLMAC_MERGE_STATUS.eth1[0x63f00]=0
CLMAC_MERGE_STATUS.eth2[0x63f00]=0
CLMAC_MERGE_STATUS.eth3[0x63f00]=0
CLMAC_MERGE_STATUS.eth4[0x63f00]=0
CLMAC_MERGE_STATUS.eth5[0x63f00]=0
CLMAC_MERGE_STATUS.eth6[0x63f00]=0
CLMAC_MERGE_STATUS.eth7[0x63f00]=0
CLMAC_MERGE_STATUS.eth8[0x63f00]=0
CLMAC_MERGE_STATUS.eth9[0x63f00]=0
CLMAC_MERGE_STATUS.eth10[0x63f00]=0
CLMAC_MERGE_STATUS.eth11[0x63f00]=0
CLMAC_MERGE_STATUS.eth12[0x63f00]=0
CLMAC_MERGE_STATUS.eth13[0x63f00]=0
CLMAC_MERGE_STATUS.eth14[0x63f00]=0
CLMAC_MERGE_STATUS.eth15[0x63f00]=0
CLMAC_MERGE_STATUS.eth16[0x63f00]=0
CLMAC_MERGE_STATUS.eth17[0x63f00]=0
CLMAC_MERGE_STATUS.eth18[0x63f00]=0
CLMAC_MERGE_STATUS.eth19[0x63f00]=0
CLMAC_MERGE_STATUS.eth20[0x63f00]=0
CLMAC_MERGE_STATUS.eth21[0x63f00]=0
CLMAC_MERGE_STATUS.eth22[0x63f00]=0
CLMAC_MERGE_STATUS.eth23[0x63f00]=0
CLMAC_MERGE_STATUS.eth24[0x63f00]=0
CLMAC_MERGE_STATUS.eth25[0x63f00]=0
CLMAC_MERGE_STATUS.eth26[0x63f00]=0
CLMAC_MERGE_STATUS.eth27[0x63f00]=0
CLMAC_MERGE_STATUS.eth28[0x63f00]=0
CLMAC_MERGE_STATUS.eth29[0x63f00]=0
CLMAC_MERGE_STATUS.eth30[0x63f00]=0
CLMAC_MERGE_STATUS.eth31[0x63f00]=0
CLMAC_MERGE_STATUS.eth32[0x63f00]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth1[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth2[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth3[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth4[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth5[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth6[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth7[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth8[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth9[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth10[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth11[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth12[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth13[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth14[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth15[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth16[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth17[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth18[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth19[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth20[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth21[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth22[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth23[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth24[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth25[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth26[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth27[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth28[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth29[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth30[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth31[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG.eth32[0x64500]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth1[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth2[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth3[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth4[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth5[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth6[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth7[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth8[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth9[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth10[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth11[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth12[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth13[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth14[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth15[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth16[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth17[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth18[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth19[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth20[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth21[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth22[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth23[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth24[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth25[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth26[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth27[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth28[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth29[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth30[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth31[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0.eth32[0x64600]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth1[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth2[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth3[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth4[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth5[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth6[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth7[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth8[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth9[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth10[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth11[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth12[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth13[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth14[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth15[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth16[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth17[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth18[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth19[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth20[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth21[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth22[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth23[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth24[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth25[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth26[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth27[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth28[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth29[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth30[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth31[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1.eth32[0x64700]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth1[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth2[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth3[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth4[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth5[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth6[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth7[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth8[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth9[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth10[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth11[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth12[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth13[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth14[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth15[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth16[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth17[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth18[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth19[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth20[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth21[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth22[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth23[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth24[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth25[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth26[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth27[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth28[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth29[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth30[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth31[0x64800]=0
CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2.eth32[0x64800]=0
CLMAC_MERGE_VERIFY_STATE.eth1[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth2[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth3[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth4[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth5[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth6[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth7[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth8[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth9[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth10[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth11[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth12[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth13[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth14[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth15[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth16[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth17[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth18[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth19[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth20[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth21[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth22[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth23[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth24[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth25[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth26[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth27[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth28[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth29[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth30[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth31[0x63e00]=0
CLMAC_MERGE_VERIFY_STATE.eth32[0x63e00]=0
CLMAC_MODE.eth1[0x60200]=0x40
CLMAC_MODE.eth2[0x60200]=0x40
CLMAC_MODE.eth3[0x60200]=0x40
CLMAC_MODE.eth4[0x60200]=0x40
CLMAC_MODE.eth5[0x60200]=0x40
CLMAC_MODE.eth6[0x60200]=0x40
CLMAC_MODE.eth7[0x60200]=0x40
CLMAC_MODE.eth8[0x60200]=0x40
CLMAC_MODE.eth9[0x60200]=0x40
CLMAC_MODE.eth10[0x60200]=0x40
CLMAC_MODE.eth11[0x60200]=0x40
CLMAC_MODE.eth12[0x60200]=0x40
CLMAC_MODE.eth13[0x60200]=0x40
CLMAC_MODE.eth14[0x60200]=0x40
CLMAC_MODE.eth15[0x60200]=0x40
CLMAC_MODE.eth16[0x60200]=0x40
CLMAC_MODE.eth17[0x60200]=0x40
CLMAC_MODE.eth18[0x60200]=0x40
CLMAC_MODE.eth19[0x60200]=0x40
CLMAC_MODE.eth20[0x60200]=0x40
CLMAC_MODE.eth21[0x60200]=0x40
CLMAC_MODE.eth22[0x60200]=0x40
CLMAC_MODE.eth23[0x60200]=0x40
CLMAC_MODE.eth24[0x60200]=0x40
CLMAC_MODE.eth25[0x60200]=0x40
CLMAC_MODE.eth26[0x60200]=0x40
CLMAC_MODE.eth27[0x60200]=0x40
CLMAC_MODE.eth28[0x60200]=0x40
CLMAC_MODE.eth29[0x60200]=0x40
CLMAC_MODE.eth30[0x60200]=0x40
CLMAC_MODE.eth31[0x60200]=0x40
CLMAC_MODE.eth32[0x60200]=0x40
CLMAC_PAUSE_CTRL.eth1[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth2[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth3[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth4[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth5[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth6[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth7[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth8[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth9[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth10[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth11[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth12[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth13[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth14[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth15[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth16[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth17[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth18[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth19[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth20[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth21[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth22[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth23[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth24[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth25[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth26[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth27[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth28[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth29[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth30[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth31[0x60c00]=0x1fffe1c000
CLMAC_PAUSE_CTRL.eth32[0x60c00]=0x1fffe1c000
CLMAC_PFC_CTRL.eth1[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth2[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth3[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth4[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth5[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth6[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth7[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth8[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth9[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth10[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth11[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth12[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth13[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth14[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth15[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth16[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth17[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth18[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth19[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth20[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth21[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth22[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth23[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth24[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth25[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth26[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth27[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth28[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth29[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth30[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth31[0x60d00]=0x9ffffc000
CLMAC_PFC_CTRL.eth32[0x60d00]=0x9ffffc000
CLMAC_PFC_DA.eth1[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth2[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth3[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth4[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth5[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth6[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth7[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth8[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth9[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth10[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth11[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth12[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth13[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth14[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth15[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth16[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth17[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth18[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth19[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth20[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth21[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth22[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth23[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth24[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth25[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth26[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth27[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth28[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth29[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth30[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth31[0x61000]=0x180c2000001
CLMAC_PFC_DA.eth32[0x61000]=0x180c2000001
CLMAC_PFC_OPCODE.eth1[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth2[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth3[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth4[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth5[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth6[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth7[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth8[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth9[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth10[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth11[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth12[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth13[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth14[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth15[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth16[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth17[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth18[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth19[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth20[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth21[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth22[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth23[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth24[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth25[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth26[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth27[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth28[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth29[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth30[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth31[0x60f00]=0x101
CLMAC_PFC_OPCODE.eth32[0x60f00]=0x101
CLMAC_PFC_TYPE.eth1[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth2[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth3[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth4[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth5[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth6[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth7[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth8[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth9[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth10[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth11[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth12[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth13[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth14[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth15[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth16[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth17[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth18[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth19[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth20[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth21[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth22[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth23[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth24[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth25[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth26[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth27[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth28[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth29[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth30[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth31[0x60e00]=0x8808
CLMAC_PFC_TYPE.eth32[0x60e00]=0x8808
CLMAC_RX_CDC_ECC_STATUS.eth1[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth2[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth3[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth4[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth5[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth6[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth7[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth8[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth9[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth10[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth11[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth12[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth13[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth14[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth15[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth16[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth17[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth18[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth19[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth20[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth21[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth22[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth23[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth24[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth25[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth26[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth27[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth28[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth29[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth30[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth31[0x63300]=0
CLMAC_RX_CDC_ECC_STATUS.eth32[0x63300]=0
CLMAC_RX_CTRL.eth1[0x60500]=0x40c
CLMAC_RX_CTRL.eth2[0x60500]=0x40c
CLMAC_RX_CTRL.eth3[0x60500]=0x40c
CLMAC_RX_CTRL.eth4[0x60500]=0x40c
CLMAC_RX_CTRL.eth5[0x60500]=0x40c
CLMAC_RX_CTRL.eth6[0x60500]=0x40c
CLMAC_RX_CTRL.eth7[0x60500]=0x40c
CLMAC_RX_CTRL.eth8[0x60500]=0x40c
CLMAC_RX_CTRL.eth9[0x60500]=0x40c
CLMAC_RX_CTRL.eth10[0x60500]=0x40c
CLMAC_RX_CTRL.eth11[0x60500]=0x40c
CLMAC_RX_CTRL.eth12[0x60500]=0x40c
CLMAC_RX_CTRL.eth13[0x60500]=0x40c
CLMAC_RX_CTRL.eth14[0x60500]=0x40c
CLMAC_RX_CTRL.eth15[0x60500]=0x40c
CLMAC_RX_CTRL.eth16[0x60500]=0x40c
CLMAC_RX_CTRL.eth17[0x60500]=0x40c
CLMAC_RX_CTRL.eth18[0x60500]=0x40c
CLMAC_RX_CTRL.eth19[0x60500]=0x40c
CLMAC_RX_CTRL.eth20[0x60500]=0x40c
CLMAC_RX_CTRL.eth21[0x60500]=0x40c
CLMAC_RX_CTRL.eth22[0x60500]=0x40c
CLMAC_RX_CTRL.eth23[0x60500]=0x40c
CLMAC_RX_CTRL.eth24[0x60500]=0x40c
CLMAC_RX_CTRL.eth25[0x60500]=0x40c
CLMAC_RX_CTRL.eth26[0x60500]=0x40c
CLMAC_RX_CTRL.eth27[0x60500]=0x40c
CLMAC_RX_CTRL.eth28[0x60500]=0x40c
CLMAC_RX_CTRL.eth29[0x60500]=0x40c
CLMAC_RX_CTRL.eth30[0x60500]=0x40c
CLMAC_RX_CTRL.eth31[0x60500]=0x40c
CLMAC_RX_CTRL.eth32[0x60500]=0x40c
CLMAC_RX_LLFC_MSG_FIELDS.eth1[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth2[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth3[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth4[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth5[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth6[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth7[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth8[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth9[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth10[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth11[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth12[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth13[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth14[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth15[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth16[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth17[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth18[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth19[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth20[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth21[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth22[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth23[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth24[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth25[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth26[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth27[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth28[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth29[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth30[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth31[0x61300]=0x200
CLMAC_RX_LLFC_MSG_FIELDS.eth32[0x61300]=0x200
CLMAC_RX_LSS_CTRL.eth1[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth2[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth3[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth4[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth5[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth6[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth7[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth8[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth9[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth10[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth11[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth12[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth13[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth14[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth15[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth16[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth17[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth18[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth19[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth20[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth21[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth22[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth23[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth24[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth25[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth26[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth27[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth28[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth29[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth30[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth31[0x60900]=0x30
CLMAC_RX_LSS_CTRL.eth32[0x60900]=0x30
CLMAC_RX_LSS_STATUS.eth1[0x60a00]=0
CLMAC_RX_LSS_STATUS.eth2[0x60a00]=0
CLMAC_RX_LSS_STATUS.eth3[0x60a00]=0
CLMAC_RX_LSS_STATUS.eth4[0x60a00]=0
CLMAC_RX_LSS_STATUS.eth5[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth6[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth7[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth8[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth9[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth10[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth11[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth12[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth13[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth14[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth15[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth16[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth17[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth18[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth19[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth20[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth21[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth22[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth23[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth24[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth25[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth26[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth27[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth28[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth29[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth30[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth31[0x60a00]=1
CLMAC_RX_LSS_STATUS.eth32[0x60a00]=0
CLMAC_RX_MAC_SA.eth1[0x60600]=0
CLMAC_RX_MAC_SA.eth2[0x60600]=0
CLMAC_RX_MAC_SA.eth3[0x60600]=0
CLMAC_RX_MAC_SA.eth4[0x60600]=0
CLMAC_RX_MAC_SA.eth5[0x60600]=0
CLMAC_RX_MAC_SA.eth6[0x60600]=0
CLMAC_RX_MAC_SA.eth7[0x60600]=0
CLMAC_RX_MAC_SA.eth8[0x60600]=0
CLMAC_RX_MAC_SA.eth9[0x60600]=0
CLMAC_RX_MAC_SA.eth10[0x60600]=0
CLMAC_RX_MAC_SA.eth11[0x60600]=0
CLMAC_RX_MAC_SA.eth12[0x60600]=0
CLMAC_RX_MAC_SA.eth13[0x60600]=0
CLMAC_RX_MAC_SA.eth14[0x60600]=0
CLMAC_RX_MAC_SA.eth15[0x60600]=0
CLMAC_RX_MAC_SA.eth16[0x60600]=0
CLMAC_RX_MAC_SA.eth17[0x60600]=0
CLMAC_RX_MAC_SA.eth18[0x60600]=0
CLMAC_RX_MAC_SA.eth19[0x60600]=0
CLMAC_RX_MAC_SA.eth20[0x60600]=0
CLMAC_RX_MAC_SA.eth21[0x60600]=0
CLMAC_RX_MAC_SA.eth22[0x60600]=0
CLMAC_RX_MAC_SA.eth23[0x60600]=0
CLMAC_RX_MAC_SA.eth24[0x60600]=0
CLMAC_RX_MAC_SA.eth25[0x60600]=0
CLMAC_RX_MAC_SA.eth26[0x60600]=0
CLMAC_RX_MAC_SA.eth27[0x60600]=0
CLMAC_RX_MAC_SA.eth28[0x60600]=0
CLMAC_RX_MAC_SA.eth29[0x60600]=0
CLMAC_RX_MAC_SA.eth30[0x60600]=0
CLMAC_RX_MAC_SA.eth31[0x60600]=0
CLMAC_RX_MAC_SA.eth32[0x60600]=0
CLMAC_RX_MAX_SIZE.eth1[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth2[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth3[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth4[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth5[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth6[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth7[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth8[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth9[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth10[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth11[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth12[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth13[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth14[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth15[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth16[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth17[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth18[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth19[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth20[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth21[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth22[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth23[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth24[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth25[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth26[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth27[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth28[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth29[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth30[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth31[0x60700]=0x5f2
CLMAC_RX_MAX_SIZE.eth32[0x60700]=0x5f2
CLMAC_RX_TS_MEM_ECC_STATUS.eth1[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth2[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth3[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth4[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth5[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth6[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth7[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth8[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth9[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth10[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth11[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth12[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth13[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth14[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth15[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth16[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth17[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth18[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth19[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth20[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth21[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth22[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth23[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth24[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth25[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth26[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth27[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth28[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth29[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth30[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth31[0x63200]=0
CLMAC_RX_TS_MEM_ECC_STATUS.eth32[0x63200]=0
CLMAC_RX_VLAN_TAG.eth1[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth2[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth3[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth4[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth5[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth6[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth7[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth8[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth9[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth10[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth11[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth12[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth13[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth14[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth15[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth16[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth17[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth18[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth19[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth20[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth21[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth22[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth23[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth24[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth25[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth26[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth27[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth28[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth29[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth30[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth31[0x60800]=0x381008100
CLMAC_RX_VLAN_TAG.eth32[0x60800]=0x381008100
CLMAC_SPARE0.eth1[0x64900]=0
CLMAC_SPARE0.eth2[0x64900]=0
CLMAC_SPARE0.eth3[0x64900]=0
CLMAC_SPARE0.eth4[0x64900]=0
CLMAC_SPARE0.eth5[0x64900]=0
CLMAC_SPARE0.eth6[0x64900]=0
CLMAC_SPARE0.eth7[0x64900]=0
CLMAC_SPARE0.eth8[0x64900]=0
CLMAC_SPARE0.eth9[0x64900]=0
CLMAC_SPARE0.eth10[0x64900]=0
CLMAC_SPARE0.eth11[0x64900]=0
CLMAC_SPARE0.eth12[0x64900]=0
CLMAC_SPARE0.eth13[0x64900]=0
CLMAC_SPARE0.eth14[0x64900]=0
CLMAC_SPARE0.eth15[0x64900]=0
CLMAC_SPARE0.eth16[0x64900]=0
CLMAC_SPARE0.eth17[0x64900]=0
CLMAC_SPARE0.eth18[0x64900]=0
CLMAC_SPARE0.eth19[0x64900]=0
CLMAC_SPARE0.eth20[0x64900]=0
CLMAC_SPARE0.eth21[0x64900]=0
CLMAC_SPARE0.eth22[0x64900]=0
CLMAC_SPARE0.eth23[0x64900]=0
CLMAC_SPARE0.eth24[0x64900]=0
CLMAC_SPARE0.eth25[0x64900]=0
CLMAC_SPARE0.eth26[0x64900]=0
CLMAC_SPARE0.eth27[0x64900]=0
CLMAC_SPARE0.eth28[0x64900]=0
CLMAC_SPARE0.eth29[0x64900]=0
CLMAC_SPARE0.eth30[0x64900]=0
CLMAC_SPARE0.eth31[0x64900]=0
CLMAC_SPARE0.eth32[0x64900]=0
CLMAC_SPARE1.eth1[0x64a00]=0
CLMAC_SPARE1.eth2[0x64a00]=0
CLMAC_SPARE1.eth3[0x64a00]=0
CLMAC_SPARE1.eth4[0x64a00]=0
CLMAC_SPARE1.eth5[0x64a00]=0
CLMAC_SPARE1.eth6[0x64a00]=0
CLMAC_SPARE1.eth7[0x64a00]=0
CLMAC_SPARE1.eth8[0x64a00]=0
CLMAC_SPARE1.eth9[0x64a00]=0
CLMAC_SPARE1.eth10[0x64a00]=0
CLMAC_SPARE1.eth11[0x64a00]=0
CLMAC_SPARE1.eth12[0x64a00]=0
CLMAC_SPARE1.eth13[0x64a00]=0
CLMAC_SPARE1.eth14[0x64a00]=0
CLMAC_SPARE1.eth15[0x64a00]=0
CLMAC_SPARE1.eth16[0x64a00]=0
CLMAC_SPARE1.eth17[0x64a00]=0
CLMAC_SPARE1.eth18[0x64a00]=0
CLMAC_SPARE1.eth19[0x64a00]=0
CLMAC_SPARE1.eth20[0x64a00]=0
CLMAC_SPARE1.eth21[0x64a00]=0
CLMAC_SPARE1.eth22[0x64a00]=0
CLMAC_SPARE1.eth23[0x64a00]=0
CLMAC_SPARE1.eth24[0x64a00]=0
CLMAC_SPARE1.eth25[0x64a00]=0
CLMAC_SPARE1.eth26[0x64a00]=0
CLMAC_SPARE1.eth27[0x64a00]=0
CLMAC_SPARE1.eth28[0x64a00]=0
CLMAC_SPARE1.eth29[0x64a00]=0
CLMAC_SPARE1.eth30[0x64a00]=0
CLMAC_SPARE1.eth31[0x64a00]=0
CLMAC_SPARE1.eth32[0x64a00]=0
CLMAC_TIMESTAMP_ADJUST.eth1[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth2[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth3[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth4[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth5[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth6[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth7[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth8[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth9[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth10[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth11[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth12[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth13[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth14[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth15[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth16[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth17[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth18[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth19[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth20[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth21[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth22[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth23[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth24[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth25[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth26[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth27[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth28[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth29[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth30[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth31[0x61f00]=0
CLMAC_TIMESTAMP_ADJUST.eth32[0x61f00]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth1[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth2[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth3[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth4[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth5[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth6[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth7[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth8[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth9[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth10[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth11[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth12[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth13[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth14[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth15[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth16[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth17[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth18[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth19[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth20[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth21[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth22[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth23[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth24[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth25[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth26[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth27[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth28[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth29[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth30[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth31[0x62000]=0
CLMAC_TIMESTAMP_BYTE_ADJUST.eth32[0x62000]=0
CLMAC_TXFIFO_CELL_CNT.eth1[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth2[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth3[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth4[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth5[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth6[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth7[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth8[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth9[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth10[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth11[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth12[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth13[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth14[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth15[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth16[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth17[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth18[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth19[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth20[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth21[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth22[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth23[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth24[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth25[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth26[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth27[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth28[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth29[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth30[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth31[0x62b00]=0
CLMAC_TXFIFO_CELL_CNT.eth32[0x62b00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth1[0x62c00]=8
CLMAC_TXFIFO_CELL_REQ_CNT.eth2[0x62c00]=8
CLMAC_TXFIFO_CELL_REQ_CNT.eth3[0x62c00]=8
CLMAC_TXFIFO_CELL_REQ_CNT.eth4[0x62c00]=8
CLMAC_TXFIFO_CELL_REQ_CNT.eth5[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth6[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth7[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth8[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth9[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth10[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth11[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth12[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth13[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth14[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth15[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth16[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth17[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth18[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth19[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth20[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth21[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth22[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth23[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth24[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth25[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth26[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth27[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth28[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth29[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth30[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth31[0x62c00]=0
CLMAC_TXFIFO_CELL_REQ_CNT.eth32[0x62c00]=8
CLMAC_TX_CDC_ECC_STATUS.eth1[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth2[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth3[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth4[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth5[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth6[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth7[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth8[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth9[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth10[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth11[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth12[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth13[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth14[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth15[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth16[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth17[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth18[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth19[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth20[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth21[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth22[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth23[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth24[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth25[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth26[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth27[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth28[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth29[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth30[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth31[0x63400]=0
CLMAC_TX_CDC_ECC_STATUS.eth32[0x63400]=0
CLMAC_TX_CRC_CORRUPT_CTRL.eth1[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth2[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth3[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth4[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth5[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth6[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth7[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth8[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth9[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth10[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth11[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth12[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth13[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth14[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth15[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth16[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth17[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth18[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth19[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth20[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth21[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth22[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth23[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth24[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth25[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth26[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth27[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth28[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth29[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth30[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth31[0x62100]=3
CLMAC_TX_CRC_CORRUPT_CTRL.eth32[0x62100]=3
CLMAC_TX_CTRL.eth1[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth2[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth3[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth4[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth5[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth6[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth7[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth8[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth9[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth10[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth11[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth12[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth13[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth14[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth15[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth16[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth17[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth18[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth19[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth20[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth21[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth22[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth23[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth24[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth25[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth26[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth27[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth28[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth29[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth30[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth31[0x60300]=0x500000c813
CLMAC_TX_CTRL.eth32[0x60300]=0x500000c813
CLMAC_TX_EP_CREDITS_CONFIG.eth1[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth2[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth3[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth4[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth5[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth6[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth7[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth8[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth9[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth10[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth11[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth12[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth13[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth14[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth15[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth16[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth17[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth18[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth19[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth20[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth21[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth22[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth23[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth24[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth25[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth26[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth27[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth28[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth29[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth30[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth31[0x62e00]=0
CLMAC_TX_EP_CREDITS_CONFIG.eth32[0x62e00]=0
CLMAC_TX_LLFC_MSG_FIELDS.eth1[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth2[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth3[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth4[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth5[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth6[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth7[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth8[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth9[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth10[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth11[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth12[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth13[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth14[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth15[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth16[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth17[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth18[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth19[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth20[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth21[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth22[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth23[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth24[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth25[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth26[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth27[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth28[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth29[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth30[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth31[0x61200]=0xffff200
CLMAC_TX_LLFC_MSG_FIELDS.eth32[0x61200]=0xffff200
CLMAC_TX_MAC_SA.eth1[0x60400]=0
CLMAC_TX_MAC_SA.eth2[0x60400]=0
CLMAC_TX_MAC_SA.eth3[0x60400]=0
CLMAC_TX_MAC_SA.eth4[0x60400]=0
CLMAC_TX_MAC_SA.eth5[0x60400]=0
CLMAC_TX_MAC_SA.eth6[0x60400]=0
CLMAC_TX_MAC_SA.eth7[0x60400]=0
CLMAC_TX_MAC_SA.eth8[0x60400]=0
CLMAC_TX_MAC_SA.eth9[0x60400]=0
CLMAC_TX_MAC_SA.eth10[0x60400]=0
CLMAC_TX_MAC_SA.eth11[0x60400]=0
CLMAC_TX_MAC_SA.eth12[0x60400]=0
CLMAC_TX_MAC_SA.eth13[0x60400]=0
CLMAC_TX_MAC_SA.eth14[0x60400]=0
CLMAC_TX_MAC_SA.eth15[0x60400]=0
CLMAC_TX_MAC_SA.eth16[0x60400]=0
CLMAC_TX_MAC_SA.eth17[0x60400]=0
CLMAC_TX_MAC_SA.eth18[0x60400]=0
CLMAC_TX_MAC_SA.eth19[0x60400]=0
CLMAC_TX_MAC_SA.eth20[0x60400]=0
CLMAC_TX_MAC_SA.eth21[0x60400]=0
CLMAC_TX_MAC_SA.eth22[0x60400]=0
CLMAC_TX_MAC_SA.eth23[0x60400]=0
CLMAC_TX_MAC_SA.eth24[0x60400]=0
CLMAC_TX_MAC_SA.eth25[0x60400]=0
CLMAC_TX_MAC_SA.eth26[0x60400]=0
CLMAC_TX_MAC_SA.eth27[0x60400]=0
CLMAC_TX_MAC_SA.eth28[0x60400]=0
CLMAC_TX_MAC_SA.eth29[0x60400]=0
CLMAC_TX_MAC_SA.eth30[0x60400]=0
CLMAC_TX_MAC_SA.eth31[0x60400]=0
CLMAC_TX_MAC_SA.eth32[0x60400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth1[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth2[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth3[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth4[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth5[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth6[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth7[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth8[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth9[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth10[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth11[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth12[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth13[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth14[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth15[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth16[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth17[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth18[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth19[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth20[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth21[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth22[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth23[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth24[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth25[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth26[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth27[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth28[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth29[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth30[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth31[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_DATA.eth32[0x61400]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth1[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth2[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth3[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth4[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth5[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth6[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth7[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth8[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth9[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth10[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth11[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth12[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth13[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth14[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth15[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth16[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth17[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth18[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth19[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth20[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth21[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth22[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth23[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth24[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth25[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth26[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth27[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth28[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth29[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth30[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth31[0x61500]=0
CLMAC_TX_TIMESTAMP_FIFO_STATUS.eth32[0x61500]=0
CLMAC_VERSION_ID.eth1[0x60000]=0xa033
CLMAC_VERSION_ID.eth2[0x60000]=0xa033
CLMAC_VERSION_ID.eth3[0x60000]=0xa033
CLMAC_VERSION_ID.eth4[0x60000]=0xa033
CLMAC_VERSION_ID.eth5[0x60000]=0xa033
CLMAC_VERSION_ID.eth6[0x60000]=0xa033
CLMAC_VERSION_ID.eth7[0x60000]=0xa033
CLMAC_VERSION_ID.eth8[0x60000]=0xa033
CLMAC_VERSION_ID.eth9[0x60000]=0xa033
CLMAC_VERSION_ID.eth10[0x60000]=0xa033
CLMAC_VERSION_ID.eth11[0x60000]=0xa033
CLMAC_VERSION_ID.eth12[0x60000]=0xa033
CLMAC_VERSION_ID.eth13[0x60000]=0xa033
CLMAC_VERSION_ID.eth14[0x60000]=0xa033
CLMAC_VERSION_ID.eth15[0x60000]=0xa033
CLMAC_VERSION_ID.eth16[0x60000]=0xa033
CLMAC_VERSION_ID.eth17[0x60000]=0xa033
CLMAC_VERSION_ID.eth18[0x60000]=0xa033
CLMAC_VERSION_ID.eth19[0x60000]=0xa033
CLMAC_VERSION_ID.eth20[0x60000]=0xa033
CLMAC_VERSION_ID.eth21[0x60000]=0xa033
CLMAC_VERSION_ID.eth22[0x60000]=0xa033
CLMAC_VERSION_ID.eth23[0x60000]=0xa033
CLMAC_VERSION_ID.eth24[0x60000]=0xa033
CLMAC_VERSION_ID.eth25[0x60000]=0xa033
CLMAC_VERSION_ID.eth26[0x60000]=0xa033
CLMAC_VERSION_ID.eth27[0x60000]=0xa033
CLMAC_VERSION_ID.eth28[0x60000]=0xa033
CLMAC_VERSION_ID.eth29[0x60000]=0xa033
CLMAC_VERSION_ID.eth30[0x60000]=0xa033
CLMAC_VERSION_ID.eth31[0x60000]=0xa033
CLMAC_VERSION_ID.eth32[0x60000]=0xa033
CLMIB_R64.eth1[0x0]=0x212d801
CLMIB_R64.eth2[0x0]=0x1ce3de1
CLMIB_R64.eth3[0x0]=0x3d578df
CLMIB_R64.eth4[0x0]=0x220912f
CLMIB_R64.eth5[0x0]=0
CLMIB_R64.eth6[0x0]=0
CLMIB_R64.eth7[0x0]=0
CLMIB_R64.eth8[0x0]=0
CLMIB_R64.eth9[0x0]=0
CLMIB_R64.eth10[0x0]=0
CLMIB_R64.eth11[0x0]=0
CLMIB_R64.eth12[0x0]=0
CLMIB_R64.eth13[0x0]=0
CLMIB_R64.eth14[0x0]=0
CLMIB_R64.eth15[0x0]=0
CLMIB_R64.eth16[0x0]=0
CLMIB_R64.eth17[0x0]=0
CLMIB_R64.eth18[0x0]=0
CLMIB_R64.eth19[0x0]=0
CLMIB_R64.eth20[0x0]=0
CLMIB_R64.eth21[0x0]=0
CLMIB_R64.eth22[0x0]=0
CLMIB_R64.eth23[0x0]=0
CLMIB_R64.eth24[0x0]=0
CLMIB_R64.eth25[0x0]=0
CLMIB_R64.eth26[0x0]=0
CLMIB_R64.eth27[0x0]=0
CLMIB_R64.eth28[0x0]=0
CLMIB_R64.eth29[0x0]=0
CLMIB_R64.eth30[0x0]=0
CLMIB_R64.eth31[0x0]=0
CLMIB_R64.eth32[0x0]=0x5f89c995
CLMIB_R127.eth1[0x100]=0x1e43d40cb
CLMIB_R127.eth2[0x100]=0xd6014be3
CLMIB_R127.eth3[0x100]=0x20a476a1d
CLMIB_R127.eth4[0x100]=0x1016042ce
CLMIB_R127.eth5[0x100]=0
CLMIB_R127.eth6[0x100]=0
CLMIB_R127.eth7[0x100]=0
CLMIB_R127.eth8[0x100]=0
CLMIB_R127.eth9[0x100]=0
CLMIB_R127.eth10[0x100]=0
CLMIB_R127.eth11[0x100]=0
CLMIB_R127.eth12[0x100]=0
CLMIB_R127.eth13[0x100]=0
CLMIB_R127.eth14[0x100]=0
CLMIB_R127.eth15[0x100]=0
CLMIB_R127.eth16[0x100]=0
CLMIB_R127.eth17[0x100]=0
CLMIB_R127.eth18[0x100]=0
CLMIB_R127.eth19[0x100]=0
CLMIB_R127.eth20[0x100]=0
CLMIB_R127.eth21[0x100]=0
CLMIB_R127.eth22[0x100]=0
CLMIB_R127.eth23[0x100]=0
CLMIB_R127.eth24[0x100]=0
CLMIB_R127.eth25[0x100]=0
CLMIB_R127.eth26[0x100]=0
CLMIB_R127.eth27[0x100]=0
CLMIB_R127.eth28[0x100]=0
CLMIB_R127.eth29[0x100]=0
CLMIB_R127.eth30[0x100]=0
CLMIB_R127.eth31[0x100]=0
CLMIB_R127.eth32[0x100]=0x25a6f611f
CLMIB_R255.eth1[0x200]=0x305ea972
CLMIB_R255.eth2[0x200]=0x157de79a
CLMIB_R255.eth3[0x200]=0x2ffd61d7
CLMIB_R255.eth4[0x200]=0x30761108
CLMIB_R255.eth5[0x200]=0
CLMIB_R255.eth6[0x200]=0
CLMIB_R255.eth7[0x200]=0
CLMIB_R255.eth8[0x200]=0
CLMIB_R255.eth9[0x200]=0
CLMIB_R255.eth10[0x200]=0
CLMIB_R255.eth11[0x200]=0
CLMIB_R255.eth12[0x200]=0
CLMIB_R255.eth13[0x200]=0
CLMIB_R255.eth14[0x200]=0
CLMIB_R255.eth15[0x200]=0
CLMIB_R255.eth16[0x200]=0
CLMIB_R255.eth17[0x200]=0
CLMIB_R255.eth18[0x200]=0
CLMIB_R255.eth19[0x200]=0
CLMIB_R255.eth20[0x200]=0
CLMIB_R255.eth21[0x200]=0
CLMIB_R255.eth22[0x200]=0
CLMIB_R255.eth23[0x200]=0
CLMIB_R255.eth24[0x200]=0
CLMIB_R255.eth25[0x200]=0
CLMIB_R255.eth26[0x200]=0
CLMIB_R255.eth27[0x200]=0
CLMIB_R255.eth28[0x200]=0
CLMIB_R255.eth29[0x200]=0
CLMIB_R255.eth30[0x200]=0
CLMIB_R255.eth31[0x200]=0
CLMIB_R255.eth32[0x200]=0x6cb8e144
CLMIB_R511.eth1[0x300]=0x2ea21a16
CLMIB_R511.eth2[0x300]=0x7987930
CLMIB_R511.eth3[0x300]=0x24baf6e6
CLMIB_R511.eth4[0x300]=0x8577d46
CLMIB_R511.eth5[0x300]=0
CLMIB_R511.eth6[0x300]=0
CLMIB_R511.eth7[0x300]=0
CLMIB_R511.eth8[0x300]=0
CLMIB_R511.eth9[0x300]=0
CLMIB_R511.eth10[0x300]=0
CLMIB_R511.eth11[0x300]=0
CLMIB_R511.eth12[0x300]=0
CLMIB_R511.eth13[0x300]=0
CLMIB_R511.eth14[0x300]=0
CLMIB_R511.eth15[0x300]=0
CLMIB_R511.eth16[0x300]=0
CLMIB_R511.eth17[0x300]=0
CLMIB_R511.eth18[0x300]=0
CLMIB_R511.eth19[0x300]=0
CLMIB_R511.eth20[0x300]=0
CLMIB_R511.eth21[0x300]=0
CLMIB_R511.eth22[0x300]=0
CLMIB_R511.eth23[0x300]=0
CLMIB_R511.eth24[0x300]=0
CLMIB_R511.eth25[0x300]=0
CLMIB_R511.eth26[0x300]=0
CLMIB_R511.eth27[0x300]=0
CLMIB_R511.eth28[0x300]=0
CLMIB_R511.eth29[0x300]=0
CLMIB_R511.eth30[0x300]=0
CLMIB_R511.eth31[0x300]=0
CLMIB_R511.eth32[0x300]=0x47bfd7b9
CLMIB_R1023.eth1[0x400]=0x145231b1
CLMIB_R1023.eth2[0x400]=0x8cf1445
CLMIB_R1023.eth3[0x400]=0x15c5fb98
CLMIB_R1023.eth4[0x400]=0xa5e4cdd
CLMIB_R1023.eth5[0x400]=0
CLMIB_R1023.eth6[0x400]=0
CLMIB_R1023.eth7[0x400]=0
CLMIB_R1023.eth8[0x400]=0
CLMIB_R1023.eth9[0x400]=0
CLMIB_R1023.eth10[0x400]=0
CLMIB_R1023.eth11[0x400]=0
CLMIB_R1023.eth12[0x400]=0
CLMIB_R1023.eth13[0x400]=0
CLMIB_R1023.eth14[0x400]=0
CLMIB_R1023.eth15[0x400]=0
CLMIB_R1023.eth16[0x400]=0
CLMIB_R1023.eth17[0x400]=0
CLMIB_R1023.eth18[0x400]=0
CLMIB_R1023.eth19[0x400]=0
CLMIB_R1023.eth20[0x400]=0
CLMIB_R1023.eth21[0x400]=0
CLMIB_R1023.eth22[0x400]=0
CLMIB_R1023.eth23[0x400]=0
CLMIB_R1023.eth24[0x400]=0
CLMIB_R1023.eth25[0x400]=0
CLMIB_R1023.eth26[0x400]=0
CLMIB_R1023.eth27[0x400]=0
CLMIB_R1023.eth28[0x400]=0
CLMIB_R1023.eth29[0x400]=0
CLMIB_R1023.eth30[0x400]=0
CLMIB_R1023.eth31[0x400]=0
CLMIB_R1023.eth32[0x400]=0x6376eb57
CLMIB_R1518.eth1[0x500]=0x69e45ee7
CLMIB_R1518.eth2[0x500]=0x204915c3
CLMIB_R1518.eth3[0x500]=0x8f228b63
CLMIB_R1518.eth4[0x500]=0x6bc72d0c
CLMIB_R1518.eth5[0x500]=0
CLMIB_R1518.eth6[0x500]=0
CLMIB_R1518.eth7[0x500]=0
CLMIB_R1518.eth8[0x500]=0
CLMIB_R1518.eth9[0x500]=0
CLMIB_R1518.eth10[0x500]=0
CLMIB_R1518.eth11[0x500]=0
CLMIB_R1518.eth12[0x500]=0
CLMIB_R1518.eth13[0x500]=0
CLMIB_R1518.eth14[0x500]=0
CLMIB_R1518.eth15[0x500]=0
CLMIB_R1518.eth16[0x500]=0
CLMIB_R1518.eth17[0x500]=0
CLMIB_R1518.eth18[0x500]=0
CLMIB_R1518.eth19[0x500]=0
CLMIB_R1518.eth20[0x500]=0
CLMIB_R1518.eth21[0x500]=0
CLMIB_R1518.eth22[0x500]=0
CLMIB_R1518.eth23[0x500]=0
CLMIB_R1518.eth24[0x500]=0
CLMIB_R1518.eth25[0x500]=0
CLMIB_R1518.eth26[0x500]=0
CLMIB_R1518.eth27[0x500]=0
CLMIB_R1518.eth28[0x500]=0
CLMIB_R1518.eth29[0x500]=0
CLMIB_R1518.eth30[0x500]=0
CLMIB_R1518.eth31[0x500]=0
CLMIB_R1518.eth32[0x500]=0x7e9dc61be
CLMIB_R2047.eth1[0x700]=0x1f9e423c
CLMIB_R2047.eth2[0x700]=0x172d1ddc
CLMIB_R2047.eth3[0x700]=0x3022fdf9
CLMIB_R2047.eth4[0x700]=0x114b8603
CLMIB_R2047.eth5[0x700]=0
CLMIB_R2047.eth6[0x700]=0
CLMIB_R2047.eth7[0x700]=0
CLMIB_R2047.eth8[0x700]=0
CLMIB_R2047.eth9[0x700]=0
CLMIB_R2047.eth10[0x700]=0
CLMIB_R2047.eth11[0x700]=0
CLMIB_R2047.eth12[0x700]=0
CLMIB_R2047.eth13[0x700]=0
CLMIB_R2047.eth14[0x700]=0
CLMIB_R2047.eth15[0x700]=0
CLMIB_R2047.eth16[0x700]=0
CLMIB_R2047.eth17[0x700]=0
CLMIB_R2047.eth18[0x700]=0
CLMIB_R2047.eth19[0x700]=0
CLMIB_R2047.eth20[0x700]=0
CLMIB_R2047.eth21[0x700]=0
CLMIB_R2047.eth22[0x700]=0
CLMIB_R2047.eth23[0x700]=0
CLMIB_R2047.eth24[0x700]=0
CLMIB_R2047.eth25[0x700]=0
CLMIB_R2047.eth26[0x700]=0
CLMIB_R2047.eth27[0x700]=0
CLMIB_R2047.eth28[0x700]=0
CLMIB_R2047.eth29[0x700]=0
CLMIB_R2047.eth30[0x700]=0
CLMIB_R2047.eth31[0x700]=0
CLMIB_R2047.eth32[0x700]=0x6f1dc59de
CLMIB_R4095.eth1[0x800]=0
CLMIB_R4095.eth2[0x800]=0
CLMIB_R4095.eth3[0x800]=0
CLMIB_R4095.eth4[0x800]=0
CLMIB_R4095.eth5[0x800]=0
CLMIB_R4095.eth6[0x800]=0
CLMIB_R4095.eth7[0x800]=0
CLMIB_R4095.eth8[0x800]=0
CLMIB_R4095.eth9[0x800]=0
CLMIB_R4095.eth10[0x800]=0
CLMIB_R4095.eth11[0x800]=0
CLMIB_R4095.eth12[0x800]=0
CLMIB_R4095.eth13[0x800]=0
CLMIB_R4095.eth14[0x800]=0
CLMIB_R4095.eth15[0x800]=0
CLMIB_R4095.eth16[0x800]=0
CLMIB_R4095.eth17[0x800]=0
CLMIB_R4095.eth18[0x800]=0
CLMIB_R4095.eth19[0x800]=0
CLMIB_R4095.eth20[0x800]=0
CLMIB_R4095.eth21[0x800]=0
CLMIB_R4095.eth22[0x800]=0
CLMIB_R4095.eth23[0x800]=0
CLMIB_R4095.eth24[0x800]=0
CLMIB_R4095.eth25[0x800]=0
CLMIB_R4095.eth26[0x800]=0
CLMIB_R4095.eth27[0x800]=0
CLMIB_R4095.eth28[0x800]=0
CLMIB_R4095.eth29[0x800]=0
CLMIB_R4095.eth30[0x800]=0
CLMIB_R4095.eth31[0x800]=0
CLMIB_R4095.eth32[0x800]=0
CLMIB_R9216.eth1[0x900]=0
CLMIB_R9216.eth2[0x900]=0
CLMIB_R9216.eth3[0x900]=0
CLMIB_R9216.eth4[0x900]=0
CLMIB_R9216.eth5[0x900]=0
CLMIB_R9216.eth6[0x900]=0
CLMIB_R9216.eth7[0x900]=0
CLMIB_R9216.eth8[0x900]=0
CLMIB_R9216.eth9[0x900]=0
CLMIB_R9216.eth10[0x900]=0
CLMIB_R9216.eth11[0x900]=0
CLMIB_R9216.eth12[0x900]=0
CLMIB_R9216.eth13[0x900]=0
CLMIB_R9216.eth14[0x900]=0
CLMIB_R9216.eth15[0x900]=0
CLMIB_R9216.eth16[0x900]=0
CLMIB_R9216.eth17[0x900]=0
CLMIB_R9216.eth18[0x900]=0
CLMIB_R9216.eth19[0x900]=0
CLMIB_R9216.eth20[0x900]=0
CLMIB_R9216.eth21[0x900]=0
CLMIB_R9216.eth22[0x900]=0
CLMIB_R9216.eth23[0x900]=0
CLMIB_R9216.eth24[0x900]=0
CLMIB_R9216.eth25[0x900]=0
CLMIB_R9216.eth26[0x900]=0
CLMIB_R9216.eth27[0x900]=0
CLMIB_R9216.eth28[0x900]=0
CLMIB_R9216.eth29[0x900]=0
CLMIB_R9216.eth30[0x900]=0
CLMIB_R9216.eth31[0x900]=0
CLMIB_R9216.eth32[0x900]=0
CLMIB_R16383.eth1[0xa00]=0
CLMIB_R16383.eth2[0xa00]=0
CLMIB_R16383.eth3[0xa00]=0
CLMIB_R16383.eth4[0xa00]=0
CLMIB_R16383.eth5[0xa00]=0
CLMIB_R16383.eth6[0xa00]=0
CLMIB_R16383.eth7[0xa00]=0
CLMIB_R16383.eth8[0xa00]=0
CLMIB_R16383.eth9[0xa00]=0
CLMIB_R16383.eth10[0xa00]=0
CLMIB_R16383.eth11[0xa00]=0
CLMIB_R16383.eth12[0xa00]=0
CLMIB_R16383.eth13[0xa00]=0
CLMIB_R16383.eth14[0xa00]=0
CLMIB_R16383.eth15[0xa00]=0
CLMIB_R16383.eth16[0xa00]=0
CLMIB_R16383.eth17[0xa00]=0
CLMIB_R16383.eth18[0xa00]=0
CLMIB_R16383.eth19[0xa00]=0
CLMIB_R16383.eth20[0xa00]=0
CLMIB_R16383.eth21[0xa00]=0
CLMIB_R16383.eth22[0xa00]=0
CLMIB_R16383.eth23[0xa00]=0
CLMIB_R16383.eth24[0xa00]=0
CLMIB_R16383.eth25[0xa00]=0
CLMIB_R16383.eth26[0xa00]=0
CLMIB_R16383.eth27[0xa00]=0
CLMIB_R16383.eth28[0xa00]=0
CLMIB_R16383.eth29[0xa00]=0
CLMIB_R16383.eth30[0xa00]=0
CLMIB_R16383.eth31[0xa00]=0
CLMIB_R16383.eth32[0xa00]=0
CLMIB_RBCA.eth1[0xe00]=0x5a73e5
CLMIB_RBCA.eth2[0xe00]=0x35a297
CLMIB_RBCA.eth3[0xe00]=0x6e0d81
CLMIB_RBCA.eth4[0xe00]=0x470fcd
CLMIB_RBCA.eth5[0xe00]=0
CLMIB_RBCA.eth6[0xe00]=0
CLMIB_RBCA.eth7[0xe00]=0
CLMIB_RBCA.eth8[0xe00]=0
CLMIB_RBCA.eth9[0xe00]=0
CLMIB_RBCA.eth10[0xe00]=0
CLMIB_RBCA.eth11[0xe00]=0
CLMIB_RBCA.eth12[0xe00]=0
CLMIB_RBCA.eth13[0xe00]=0
CLMIB_RBCA.eth14[0xe00]=0
CLMIB_RBCA.eth15[0xe00]=0
CLMIB_RBCA.eth16[0xe00]=0
CLMIB_RBCA.eth17[0xe00]=0
CLMIB_RBCA.eth18[0xe00]=0
CLMIB_RBCA.eth19[0xe00]=0
CLMIB_RBCA.eth20[0xe00]=0
CLMIB_RBCA.eth21[0xe00]=0
CLMIB_RBCA.eth22[0xe00]=0
CLMIB_RBCA.eth23[0xe00]=0
CLMIB_RBCA.eth24[0xe00]=0
CLMIB_RBCA.eth25[0xe00]=0
CLMIB_RBCA.eth26[0xe00]=0
CLMIB_RBCA.eth27[0xe00]=0
CLMIB_RBCA.eth28[0xe00]=0
CLMIB_RBCA.eth29[0xe00]=0
CLMIB_RBCA.eth30[0xe00]=0
CLMIB_RBCA.eth31[0xe00]=0
CLMIB_RBCA.eth32[0xe00]=0x18b7235
CLMIB_RBYT.eth1[0x3d00]=0x43dd8b142e5
CLMIB_RBYT.eth2[0x3d00]=0x1a89ed11945
CLMIB_RBYT.eth3[0x3d00]=0x569e0ebb80c
CLMIB_RBYT.eth4[0x3d00]=0x365477994d6
CLMIB_RBYT.eth5[0x3d00]=0
CLMIB_RBYT.eth6[0x3d00]=0
CLMIB_RBYT.eth7[0x3d00]=0
CLMIB_RBYT.eth8[0x3d00]=0
CLMIB_RBYT.eth9[0x3d00]=0
CLMIB_RBYT.eth10[0x3d00]=0
CLMIB_RBYT.eth11[0x3d00]=0
CLMIB_RBYT.eth12[0x3d00]=0
CLMIB_RBYT.eth13[0x3d00]=0
CLMIB_RBYT.eth14[0x3d00]=0
CLMIB_RBYT.eth15[0x3d00]=0
CLMIB_RBYT.eth16[0x3d00]=0
CLMIB_RBYT.eth17[0x3d00]=0
CLMIB_RBYT.eth18[0x3d00]=0
CLMIB_RBYT.eth19[0x3d00]=0
CLMIB_RBYT.eth20[0x3d00]=0
CLMIB_RBYT.eth21[0x3d00]=0
CLMIB_RBYT.eth22[0x3d00]=0
CLMIB_RBYT.eth23[0x3d00]=0
CLMIB_RBYT.eth24[0x3d00]=0
CLMIB_RBYT.eth25[0x3d00]=0
CLMIB_RBYT.eth26[0x3d00]=0
CLMIB_RBYT.eth27[0x3d00]=0
CLMIB_RBYT.eth28[0x3d00]=0
CLMIB_RBYT.eth29[0x3d00]=0
CLMIB_RBYT.eth30[0x3d00]=0
CLMIB_RBYT.eth31[0x3d00]=0
CLMIB_RBYT.eth32[0x3d00]=0x58775f7628f9
CLMIB_RDVLN.eth1[0x2000]=0
CLMIB_RDVLN.eth2[0x2000]=0
CLMIB_RDVLN.eth3[0x2000]=0
CLMIB_RDVLN.eth4[0x2000]=0
CLMIB_RDVLN.eth5[0x2000]=0
CLMIB_RDVLN.eth6[0x2000]=0
CLMIB_RDVLN.eth7[0x2000]=0
CLMIB_RDVLN.eth8[0x2000]=0
CLMIB_RDVLN.eth9[0x2000]=0
CLMIB_RDVLN.eth10[0x2000]=0
CLMIB_RDVLN.eth11[0x2000]=0
CLMIB_RDVLN.eth12[0x2000]=0
CLMIB_RDVLN.eth13[0x2000]=0
CLMIB_RDVLN.eth14[0x2000]=0
CLMIB_RDVLN.eth15[0x2000]=0
CLMIB_RDVLN.eth16[0x2000]=0
CLMIB_RDVLN.eth17[0x2000]=0
CLMIB_RDVLN.eth18[0x2000]=0
CLMIB_RDVLN.eth19[0x2000]=0
CLMIB_RDVLN.eth20[0x2000]=0
CLMIB_RDVLN.eth21[0x2000]=0
CLMIB_RDVLN.eth22[0x2000]=0
CLMIB_RDVLN.eth23[0x2000]=0
CLMIB_RDVLN.eth24[0x2000]=0
CLMIB_RDVLN.eth25[0x2000]=0
CLMIB_RDVLN.eth26[0x2000]=0
CLMIB_RDVLN.eth27[0x2000]=0
CLMIB_RDVLN.eth28[0x2000]=0
CLMIB_RDVLN.eth29[0x2000]=0
CLMIB_RDVLN.eth30[0x2000]=0
CLMIB_RDVLN.eth31[0x2000]=0
CLMIB_RDVLN.eth32[0x2000]=0
CLMIB_RERPKT.eth1[0x1800]=0
CLMIB_RERPKT.eth2[0x1800]=0
CLMIB_RERPKT.eth3[0x1800]=0
CLMIB_RERPKT.eth4[0x1800]=0
CLMIB_RERPKT.eth5[0x1800]=0
CLMIB_RERPKT.eth6[0x1800]=0
CLMIB_RERPKT.eth7[0x1800]=0
CLMIB_RERPKT.eth8[0x1800]=0
CLMIB_RERPKT.eth9[0x1800]=0
CLMIB_RERPKT.eth10[0x1800]=0
CLMIB_RERPKT.eth11[0x1800]=0
CLMIB_RERPKT.eth12[0x1800]=0
CLMIB_RERPKT.eth13[0x1800]=0
CLMIB_RERPKT.eth14[0x1800]=0
CLMIB_RERPKT.eth15[0x1800]=0
CLMIB_RERPKT.eth16[0x1800]=0
CLMIB_RERPKT.eth17[0x1800]=0
CLMIB_RERPKT.eth18[0x1800]=0
CLMIB_RERPKT.eth19[0x1800]=0
CLMIB_RERPKT.eth20[0x1800]=0
CLMIB_RERPKT.eth21[0x1800]=0
CLMIB_RERPKT.eth22[0x1800]=0
CLMIB_RERPKT.eth23[0x1800]=0
CLMIB_RERPKT.eth24[0x1800]=0
CLMIB_RERPKT.eth25[0x1800]=0
CLMIB_RERPKT.eth26[0x1800]=0
CLMIB_RERPKT.eth27[0x1800]=0
CLMIB_RERPKT.eth28[0x1800]=0
CLMIB_RERPKT.eth29[0x1800]=0
CLMIB_RERPKT.eth30[0x1800]=0
CLMIB_RERPKT.eth31[0x1800]=0
CLMIB_RERPKT.eth32[0x1800]=0xd2
CLMIB_RFCS.eth1[0xf00]=0
CLMIB_RFCS.eth2[0xf00]=0
CLMIB_RFCS.eth3[0xf00]=0
CLMIB_RFCS.eth4[0xf00]=0
CLMIB_RFCS.eth5[0xf00]=0
CLMIB_RFCS.eth6[0xf00]=0
CLMIB_RFCS.eth7[0xf00]=0
CLMIB_RFCS.eth8[0xf00]=0
CLMIB_RFCS.eth9[0xf00]=0
CLMIB_RFCS.eth10[0xf00]=0
CLMIB_RFCS.eth11[0xf00]=0
CLMIB_RFCS.eth12[0xf00]=0
CLMIB_RFCS.eth13[0xf00]=0
CLMIB_RFCS.eth14[0xf00]=0
CLMIB_RFCS.eth15[0xf00]=0
CLMIB_RFCS.eth16[0xf00]=0
CLMIB_RFCS.eth17[0xf00]=0
CLMIB_RFCS.eth18[0xf00]=0
CLMIB_RFCS.eth19[0xf00]=0
CLMIB_RFCS.eth20[0xf00]=0
CLMIB_RFCS.eth21[0xf00]=0
CLMIB_RFCS.eth22[0xf00]=0
CLMIB_RFCS.eth23[0xf00]=0
CLMIB_RFCS.eth24[0xf00]=0
CLMIB_RFCS.eth25[0xf00]=0
CLMIB_RFCS.eth26[0xf00]=0
CLMIB_RFCS.eth27[0xf00]=0
CLMIB_RFCS.eth28[0xf00]=0
CLMIB_RFCS.eth29[0xf00]=0
CLMIB_RFCS.eth30[0xf00]=0
CLMIB_RFCS.eth31[0xf00]=0
CLMIB_RFCS.eth32[0xf00]=0xb99
CLMIB_RFLR.eth1[0x1700]=0x2a67
CLMIB_RFLR.eth2[0x1700]=0x14d
CLMIB_RFLR.eth3[0x1700]=0xdee83
CLMIB_RFLR.eth4[0x1700]=0x2b659b
CLMIB_RFLR.eth5[0x1700]=0
CLMIB_RFLR.eth6[0x1700]=0
CLMIB_RFLR.eth7[0x1700]=0
CLMIB_RFLR.eth8[0x1700]=0
CLMIB_RFLR.eth9[0x1700]=0
CLMIB_RFLR.eth10[0x1700]=0
CLMIB_RFLR.eth11[0x1700]=0
CLMIB_RFLR.eth12[0x1700]=0
CLMIB_RFLR.eth13[0x1700]=0
CLMIB_RFLR.eth14[0x1700]=0
CLMIB_RFLR.eth15[0x1700]=0
CLMIB_RFLR.eth16[0x1700]=0
CLMIB_RFLR.eth17[0x1700]=0
CLMIB_RFLR.eth18[0x1700]=0
CLMIB_RFLR.eth19[0x1700]=0
CLMIB_RFLR.eth20[0x1700]=0
CLMIB_RFLR.eth21[0x1700]=0
CLMIB_RFLR.eth22[0x1700]=0
CLMIB_RFLR.eth23[0x1700]=0
CLMIB_RFLR.eth24[0x1700]=0
CLMIB_RFLR.eth25[0x1700]=0
CLMIB_RFLR.eth26[0x1700]=0
CLMIB_RFLR.eth27[0x1700]=0
CLMIB_RFLR.eth28[0x1700]=0
CLMIB_RFLR.eth29[0x1700]=0
CLMIB_RFLR.eth30[0x1700]=0
CLMIB_RFLR.eth31[0x1700]=0
CLMIB_RFLR.eth32[0x1700]=0
CLMIB_RFRG.eth1[0x3500]=0
CLMIB_RFRG.eth2[0x3500]=0
CLMIB_RFRG.eth3[0x3500]=0
CLMIB_RFRG.eth4[0x3500]=0
CLMIB_RFRG.eth5[0x3500]=0
CLMIB_RFRG.eth6[0x3500]=0
CLMIB_RFRG.eth7[0x3500]=0
CLMIB_RFRG.eth8[0x3500]=0
CLMIB_RFRG.eth9[0x3500]=0
CLMIB_RFRG.eth10[0x3500]=0
CLMIB_RFRG.eth11[0x3500]=0
CLMIB_RFRG.eth12[0x3500]=0
CLMIB_RFRG.eth13[0x3500]=0
CLMIB_RFRG.eth14[0x3500]=0
CLMIB_RFRG.eth15[0x3500]=0
CLMIB_RFRG.eth16[0x3500]=0
CLMIB_RFRG.eth17[0x3500]=0
CLMIB_RFRG.eth18[0x3500]=0
CLMIB_RFRG.eth19[0x3500]=0
CLMIB_RFRG.eth20[0x3500]=0
CLMIB_RFRG.eth21[0x3500]=0
CLMIB_RFRG.eth22[0x3500]=0
CLMIB_RFRG.eth23[0x3500]=0
CLMIB_RFRG.eth24[0x3500]=0
CLMIB_RFRG.eth25[0x3500]=0
CLMIB_RFRG.eth26[0x3500]=0
CLMIB_RFRG.eth27[0x3500]=0
CLMIB_RFRG.eth28[0x3500]=0
CLMIB_RFRG.eth29[0x3500]=0
CLMIB_RFRG.eth30[0x3500]=0
CLMIB_RFRG.eth31[0x3500]=0
CLMIB_RFRG.eth32[0x3500]=2
CLMIB_RJBR.eth1[0x1b00]=0
CLMIB_RJBR.eth2[0x1b00]=0
CLMIB_RJBR.eth3[0x1b00]=0
CLMIB_RJBR.eth4[0x1b00]=0
CLMIB_RJBR.eth5[0x1b00]=0
CLMIB_RJBR.eth6[0x1b00]=0
CLMIB_RJBR.eth7[0x1b00]=0
CLMIB_RJBR.eth8[0x1b00]=0
CLMIB_RJBR.eth9[0x1b00]=0
CLMIB_RJBR.eth10[0x1b00]=0
CLMIB_RJBR.eth11[0x1b00]=0
CLMIB_RJBR.eth12[0x1b00]=0
CLMIB_RJBR.eth13[0x1b00]=0
CLMIB_RJBR.eth14[0x1b00]=0
CLMIB_RJBR.eth15[0x1b00]=0
CLMIB_RJBR.eth16[0x1b00]=0
CLMIB_RJBR.eth17[0x1b00]=0
CLMIB_RJBR.eth18[0x1b00]=0
CLMIB_RJBR.eth19[0x1b00]=0
CLMIB_RJBR.eth20[0x1b00]=0
CLMIB_RJBR.eth21[0x1b00]=0
CLMIB_RJBR.eth22[0x1b00]=0
CLMIB_RJBR.eth23[0x1b00]=0
CLMIB_RJBR.eth24[0x1b00]=0
CLMIB_RJBR.eth25[0x1b00]=0
CLMIB_RJBR.eth26[0x1b00]=0
CLMIB_RJBR.eth27[0x1b00]=0
CLMIB_RJBR.eth28[0x1b00]=0
CLMIB_RJBR.eth29[0x1b00]=0
CLMIB_RJBR.eth30[0x1b00]=0
CLMIB_RJBR.eth31[0x1b00]=0
CLMIB_RJBR.eth32[0x1b00]=8
CLMIB_RMCA.eth1[0xd00]=0xae3301
CLMIB_RMCA.eth2[0xd00]=0x476a97
CLMIB_RMCA.eth3[0xd00]=0x90e6dd
CLMIB_RMCA.eth4[0xd00]=0x4ed474
CLMIB_RMCA.eth5[0xd00]=0
CLMIB_RMCA.eth6[0xd00]=0
CLMIB_RMCA.eth7[0xd00]=0
CLMIB_RMCA.eth8[0xd00]=0
CLMIB_RMCA.eth9[0xd00]=0
CLMIB_RMCA.eth10[0xd00]=0
CLMIB_RMCA.eth11[0xd00]=0
CLMIB_RMCA.eth12[0xd00]=0
CLMIB_RMCA.eth13[0xd00]=0
CLMIB_RMCA.eth14[0xd00]=0
CLMIB_RMCA.eth15[0xd00]=0
CLMIB_RMCA.eth16[0xd00]=0
CLMIB_RMCA.eth17[0xd00]=0
CLMIB_RMCA.eth18[0xd00]=0
CLMIB_RMCA.eth19[0xd00]=0
CLMIB_RMCA.eth20[0xd00]=0
CLMIB_RMCA.eth21[0xd00]=0
CLMIB_RMCA.eth22[0xd00]=0
CLMIB_RMCA.eth23[0xd00]=0
CLMIB_RMCA.eth24[0xd00]=0
CLMIB_RMCA.eth25[0xd00]=0
CLMIB_RMCA.eth26[0xd00]=0
CLMIB_RMCA.eth27[0xd00]=0
CLMIB_RMCA.eth28[0xd00]=0
CLMIB_RMCA.eth29[0xd00]=0
CLMIB_RMCA.eth30[0xd00]=0
CLMIB_RMCA.eth31[0xd00]=0
CLMIB_RMCA.eth32[0xd00]=0x553d1f
CLMIB_RMCRC.eth1[0x1d00]=2
CLMIB_RMCRC.eth2[0x1d00]=2
CLMIB_RMCRC.eth3[0x1d00]=0
CLMIB_RMCRC.eth4[0x1d00]=1
CLMIB_RMCRC.eth5[0x1d00]=0
CLMIB_RMCRC.eth6[0x1d00]=0
CLMIB_RMCRC.eth7[0x1d00]=0
CLMIB_RMCRC.eth8[0x1d00]=0
CLMIB_RMCRC.eth9[0x1d00]=0
CLMIB_RMCRC.eth10[0x1d00]=0
CLMIB_RMCRC.eth11[0x1d00]=0
CLMIB_RMCRC.eth12[0x1d00]=0
CLMIB_RMCRC.eth13[0x1d00]=0
CLMIB_RMCRC.eth14[0x1d00]=0
CLMIB_RMCRC.eth15[0x1d00]=0
CLMIB_RMCRC.eth16[0x1d00]=0
CLMIB_RMCRC.eth17[0x1d00]=0
CLMIB_RMCRC.eth18[0x1d00]=0
CLMIB_RMCRC.eth19[0x1d00]=0
CLMIB_RMCRC.eth20[0x1d00]=0
CLMIB_RMCRC.eth21[0x1d00]=0
CLMIB_RMCRC.eth22[0x1d00]=0
CLMIB_RMCRC.eth23[0x1d00]=0
CLMIB_RMCRC.eth24[0x1d00]=0
CLMIB_RMCRC.eth25[0x1d00]=0
CLMIB_RMCRC.eth26[0x1d00]=0
CLMIB_RMCRC.eth27[0x1d00]=0
CLMIB_RMCRC.eth28[0x1d00]=0
CLMIB_RMCRC.eth29[0x1d00]=0
CLMIB_RMCRC.eth30[0x1d00]=0
CLMIB_RMCRC.eth31[0x1d00]=0
CLMIB_RMCRC.eth32[0x1d00]=8
CLMIB_RMGV.eth1[0x600]=0x1f9e423c
CLMIB_RMGV.eth2[0x600]=0x172d1e71
CLMIB_RMGV.eth3[0x600]=0x3022fdf9
CLMIB_RMGV.eth4[0x600]=0x114b8603
CLMIB_RMGV.eth5[0x600]=0
CLMIB_RMGV.eth6[0x600]=0
CLMIB_RMGV.eth7[0x600]=0
CLMIB_RMGV.eth8[0x600]=0
CLMIB_RMGV.eth9[0x600]=0
CLMIB_RMGV.eth10[0x600]=0
CLMIB_RMGV.eth11[0x600]=0
CLMIB_RMGV.eth12[0x600]=0
CLMIB_RMGV.eth13[0x600]=0
CLMIB_RMGV.eth14[0x600]=0
CLMIB_RMGV.eth15[0x600]=0
CLMIB_RMGV.eth16[0x600]=0
CLMIB_RMGV.eth17[0x600]=0
CLMIB_RMGV.eth18[0x600]=0
CLMIB_RMGV.eth19[0x600]=0
CLMIB_RMGV.eth20[0x600]=0
CLMIB_RMGV.eth21[0x600]=0
CLMIB_RMGV.eth22[0x600]=0
CLMIB_RMGV.eth23[0x600]=0
CLMIB_RMGV.eth24[0x600]=0
CLMIB_RMGV.eth25[0x600]=0
CLMIB_RMGV.eth26[0x600]=0
CLMIB_RMGV.eth27[0x600]=0
CLMIB_RMGV.eth28[0x600]=0
CLMIB_RMGV.eth29[0x600]=0
CLMIB_RMGV.eth30[0x600]=0
CLMIB_RMGV.eth31[0x600]=0
CLMIB_RMGV.eth32[0x600]=0x6f1dc5547
CLMIB_RMTUE.eth1[0x1c00]=0
CLMIB_RMTUE.eth2[0x1c00]=0
CLMIB_RMTUE.eth3[0x1c00]=0
CLMIB_RMTUE.eth4[0x1c00]=0
CLMIB_RMTUE.eth5[0x1c00]=0
CLMIB_RMTUE.eth6[0x1c00]=0
CLMIB_RMTUE.eth7[0x1c00]=0
CLMIB_RMTUE.eth8[0x1c00]=0
CLMIB_RMTUE.eth9[0x1c00]=0
CLMIB_RMTUE.eth10[0x1c00]=0
CLMIB_RMTUE.eth11[0x1c00]=0
CLMIB_RMTUE.eth12[0x1c00]=0
CLMIB_RMTUE.eth13[0x1c00]=0
CLMIB_RMTUE.eth14[0x1c00]=0
CLMIB_RMTUE.eth15[0x1c00]=0
CLMIB_RMTUE.eth16[0x1c00]=0
CLMIB_RMTUE.eth17[0x1c00]=0
CLMIB_RMTUE.eth18[0x1c00]=0
CLMIB_RMTUE.eth19[0x1c00]=0
CLMIB_RMTUE.eth20[0x1c00]=0
CLMIB_RMTUE.eth21[0x1c00]=0
CLMIB_RMTUE.eth22[0x1c00]=0
CLMIB_RMTUE.eth23[0x1c00]=0
CLMIB_RMTUE.eth24[0x1c00]=0
CLMIB_RMTUE.eth25[0x1c00]=0
CLMIB_RMTUE.eth26[0x1c00]=0
CLMIB_RMTUE.eth27[0x1c00]=0
CLMIB_RMTUE.eth28[0x1c00]=0
CLMIB_RMTUE.eth29[0x1c00]=0
CLMIB_RMTUE.eth30[0x1c00]=0
CLMIB_RMTUE.eth31[0x1c00]=0
CLMIB_RMTUE.eth32[0x1c00]=0
CLMIB_ROVR.eth1[0x1a00]=0
CLMIB_ROVR.eth2[0x1a00]=0
CLMIB_ROVR.eth3[0x1a00]=0
CLMIB_ROVR.eth4[0x1a00]=0
CLMIB_ROVR.eth5[0x1a00]=0
CLMIB_ROVR.eth6[0x1a00]=0
CLMIB_ROVR.eth7[0x1a00]=0
CLMIB_ROVR.eth8[0x1a00]=0
CLMIB_ROVR.eth9[0x1a00]=0
CLMIB_ROVR.eth10[0x1a00]=0
CLMIB_ROVR.eth11[0x1a00]=0
CLMIB_ROVR.eth12[0x1a00]=0
CLMIB_ROVR.eth13[0x1a00]=0
CLMIB_ROVR.eth14[0x1a00]=0
CLMIB_ROVR.eth15[0x1a00]=0
CLMIB_ROVR.eth16[0x1a00]=0
CLMIB_ROVR.eth17[0x1a00]=0
CLMIB_ROVR.eth18[0x1a00]=0
CLMIB_ROVR.eth19[0x1a00]=0
CLMIB_ROVR.eth20[0x1a00]=0
CLMIB_ROVR.eth21[0x1a00]=0
CLMIB_ROVR.eth22[0x1a00]=0
CLMIB_ROVR.eth23[0x1a00]=0
CLMIB_ROVR.eth24[0x1a00]=0
CLMIB_ROVR.eth25[0x1a00]=0
CLMIB_ROVR.eth26[0x1a00]=0
CLMIB_ROVR.eth27[0x1a00]=0
CLMIB_ROVR.eth28[0x1a00]=0
CLMIB_ROVR.eth29[0x1a00]=0
CLMIB_ROVR.eth30[0x1a00]=0
CLMIB_ROVR.eth31[0x1a00]=0
CLMIB_ROVR.eth32[0x1a00]=0
CLMIB_RPFC0.eth1[0x2b00]=0
CLMIB_RPFC0.eth2[0x2b00]=0
CLMIB_RPFC0.eth3[0x2b00]=0
CLMIB_RPFC0.eth4[0x2b00]=0
CLMIB_RPFC0.eth5[0x2b00]=0
CLMIB_RPFC0.eth6[0x2b00]=0
CLMIB_RPFC0.eth7[0x2b00]=0
CLMIB_RPFC0.eth8[0x2b00]=0
CLMIB_RPFC0.eth9[0x2b00]=0
CLMIB_RPFC0.eth10[0x2b00]=0
CLMIB_RPFC0.eth11[0x2b00]=0
CLMIB_RPFC0.eth12[0x2b00]=0
CLMIB_RPFC0.eth13[0x2b00]=0
CLMIB_RPFC0.eth14[0x2b00]=0
CLMIB_RPFC0.eth15[0x2b00]=0
CLMIB_RPFC0.eth16[0x2b00]=0
CLMIB_RPFC0.eth17[0x2b00]=0
CLMIB_RPFC0.eth18[0x2b00]=0
CLMIB_RPFC0.eth19[0x2b00]=0
CLMIB_RPFC0.eth20[0x2b00]=0
CLMIB_RPFC0.eth21[0x2b00]=0
CLMIB_RPFC0.eth22[0x2b00]=0
CLMIB_RPFC0.eth23[0x2b00]=0
CLMIB_RPFC0.eth24[0x2b00]=0
CLMIB_RPFC0.eth25[0x2b00]=0
CLMIB_RPFC0.eth26[0x2b00]=0
CLMIB_RPFC0.eth27[0x2b00]=0
CLMIB_RPFC0.eth28[0x2b00]=0
CLMIB_RPFC0.eth29[0x2b00]=0
CLMIB_RPFC0.eth30[0x2b00]=0
CLMIB_RPFC0.eth31[0x2b00]=0
CLMIB_RPFC0.eth32[0x2b00]=0
CLMIB_RPFC1.eth1[0x2c00]=0
CLMIB_RPFC1.eth2[0x2c00]=0
CLMIB_RPFC1.eth3[0x2c00]=0
CLMIB_RPFC1.eth4[0x2c00]=0
CLMIB_RPFC1.eth5[0x2c00]=0
CLMIB_RPFC1.eth6[0x2c00]=0
CLMIB_RPFC1.eth7[0x2c00]=0
CLMIB_RPFC1.eth8[0x2c00]=0
CLMIB_RPFC1.eth9[0x2c00]=0
CLMIB_RPFC1.eth10[0x2c00]=0
CLMIB_RPFC1.eth11[0x2c00]=0
CLMIB_RPFC1.eth12[0x2c00]=0
CLMIB_RPFC1.eth13[0x2c00]=0
CLMIB_RPFC1.eth14[0x2c00]=0
CLMIB_RPFC1.eth15[0x2c00]=0
CLMIB_RPFC1.eth16[0x2c00]=0
CLMIB_RPFC1.eth17[0x2c00]=0
CLMIB_RPFC1.eth18[0x2c00]=0
CLMIB_RPFC1.eth19[0x2c00]=0
CLMIB_RPFC1.eth20[0x2c00]=0
CLMIB_RPFC1.eth21[0x2c00]=0
CLMIB_RPFC1.eth22[0x2c00]=0
CLMIB_RPFC1.eth23[0x2c00]=0
CLMIB_RPFC1.eth24[0x2c00]=0
CLMIB_RPFC1.eth25[0x2c00]=0
CLMIB_RPFC1.eth26[0x2c00]=0
CLMIB_RPFC1.eth27[0x2c00]=0
CLMIB_RPFC1.eth28[0x2c00]=0
CLMIB_RPFC1.eth29[0x2c00]=0
CLMIB_RPFC1.eth30[0x2c00]=0
CLMIB_RPFC1.eth31[0x2c00]=0
CLMIB_RPFC1.eth32[0x2c00]=0
CLMIB_RPFC2.eth1[0x2d00]=0
CLMIB_RPFC2.eth2[0x2d00]=0
CLMIB_RPFC2.eth3[0x2d00]=0
CLMIB_RPFC2.eth4[0x2d00]=0
CLMIB_RPFC2.eth5[0x2d00]=0
CLMIB_RPFC2.eth6[0x2d00]=0
CLMIB_RPFC2.eth7[0x2d00]=0
CLMIB_RPFC2.eth8[0x2d00]=0
CLMIB_RPFC2.eth9[0x2d00]=0
CLMIB_RPFC2.eth10[0x2d00]=0
CLMIB_RPFC2.eth11[0x2d00]=0
CLMIB_RPFC2.eth12[0x2d00]=0
CLMIB_RPFC2.eth13[0x2d00]=0
CLMIB_RPFC2.eth14[0x2d00]=0
CLMIB_RPFC2.eth15[0x2d00]=0
CLMIB_RPFC2.eth16[0x2d00]=0
CLMIB_RPFC2.eth17[0x2d00]=0
CLMIB_RPFC2.eth18[0x2d00]=0
CLMIB_RPFC2.eth19[0x2d00]=0
CLMIB_RPFC2.eth20[0x2d00]=0
CLMIB_RPFC2.eth21[0x2d00]=0
CLMIB_RPFC2.eth22[0x2d00]=0
CLMIB_RPFC2.eth23[0x2d00]=0
CLMIB_RPFC2.eth24[0x2d00]=0
CLMIB_RPFC2.eth25[0x2d00]=0
CLMIB_RPFC2.eth26[0x2d00]=0
CLMIB_RPFC2.eth27[0x2d00]=0
CLMIB_RPFC2.eth28[0x2d00]=0
CLMIB_RPFC2.eth29[0x2d00]=0
CLMIB_RPFC2.eth30[0x2d00]=0
CLMIB_RPFC2.eth31[0x2d00]=0
CLMIB_RPFC2.eth32[0x2d00]=0
CLMIB_RPFC3.eth1[0x2e00]=0
CLMIB_RPFC3.eth2[0x2e00]=0
CLMIB_RPFC3.eth3[0x2e00]=0
CLMIB_RPFC3.eth4[0x2e00]=0
CLMIB_RPFC3.eth5[0x2e00]=0
CLMIB_RPFC3.eth6[0x2e00]=0
CLMIB_RPFC3.eth7[0x2e00]=0
CLMIB_RPFC3.eth8[0x2e00]=0
CLMIB_RPFC3.eth9[0x2e00]=0
CLMIB_RPFC3.eth10[0x2e00]=0
CLMIB_RPFC3.eth11[0x2e00]=0
CLMIB_RPFC3.eth12[0x2e00]=0
CLMIB_RPFC3.eth13[0x2e00]=0
CLMIB_RPFC3.eth14[0x2e00]=0
CLMIB_RPFC3.eth15[0x2e00]=0
CLMIB_RPFC3.eth16[0x2e00]=0
CLMIB_RPFC3.eth17[0x2e00]=0
CLMIB_RPFC3.eth18[0x2e00]=0
CLMIB_RPFC3.eth19[0x2e00]=0
CLMIB_RPFC3.eth20[0x2e00]=0
CLMIB_RPFC3.eth21[0x2e00]=0
CLMIB_RPFC3.eth22[0x2e00]=0
CLMIB_RPFC3.eth23[0x2e00]=0
CLMIB_RPFC3.eth24[0x2e00]=0
CLMIB_RPFC3.eth25[0x2e00]=0
CLMIB_RPFC3.eth26[0x2e00]=0
CLMIB_RPFC3.eth27[0x2e00]=0
CLMIB_RPFC3.eth28[0x2e00]=0
CLMIB_RPFC3.eth29[0x2e00]=0
CLMIB_RPFC3.eth30[0x2e00]=0
CLMIB_RPFC3.eth31[0x2e00]=0
CLMIB_RPFC3.eth32[0x2e00]=0
CLMIB_RPFC4.eth1[0x2f00]=0
CLMIB_RPFC4.eth2[0x2f00]=0
CLMIB_RPFC4.eth3[0x2f00]=0
CLMIB_RPFC4.eth4[0x2f00]=0
CLMIB_RPFC4.eth5[0x2f00]=0
CLMIB_RPFC4.eth6[0x2f00]=0
CLMIB_RPFC4.eth7[0x2f00]=0
CLMIB_RPFC4.eth8[0x2f00]=0
CLMIB_RPFC4.eth9[0x2f00]=0
CLMIB_RPFC4.eth10[0x2f00]=0
CLMIB_RPFC4.eth11[0x2f00]=0
CLMIB_RPFC4.eth12[0x2f00]=0
CLMIB_RPFC4.eth13[0x2f00]=0
CLMIB_RPFC4.eth14[0x2f00]=0
CLMIB_RPFC4.eth15[0x2f00]=0
CLMIB_RPFC4.eth16[0x2f00]=0
CLMIB_RPFC4.eth17[0x2f00]=0
CLMIB_RPFC4.eth18[0x2f00]=0
CLMIB_RPFC4.eth19[0x2f00]=0
CLMIB_RPFC4.eth20[0x2f00]=0
CLMIB_RPFC4.eth21[0x2f00]=0
CLMIB_RPFC4.eth22[0x2f00]=0
CLMIB_RPFC4.eth23[0x2f00]=0
CLMIB_RPFC4.eth24[0x2f00]=0
CLMIB_RPFC4.eth25[0x2f00]=0
CLMIB_RPFC4.eth26[0x2f00]=0
CLMIB_RPFC4.eth27[0x2f00]=0
CLMIB_RPFC4.eth28[0x2f00]=0
CLMIB_RPFC4.eth29[0x2f00]=0
CLMIB_RPFC4.eth30[0x2f00]=0
CLMIB_RPFC4.eth31[0x2f00]=0
CLMIB_RPFC4.eth32[0x2f00]=0
CLMIB_RPFC5.eth1[0x3000]=0
CLMIB_RPFC5.eth2[0x3000]=0
CLMIB_RPFC5.eth3[0x3000]=0
CLMIB_RPFC5.eth4[0x3000]=0
CLMIB_RPFC5.eth5[0x3000]=0
CLMIB_RPFC5.eth6[0x3000]=0
CLMIB_RPFC5.eth7[0x3000]=0
CLMIB_RPFC5.eth8[0x3000]=0
CLMIB_RPFC5.eth9[0x3000]=0
CLMIB_RPFC5.eth10[0x3000]=0
CLMIB_RPFC5.eth11[0x3000]=0
CLMIB_RPFC5.eth12[0x3000]=0
CLMIB_RPFC5.eth13[0x3000]=0
CLMIB_RPFC5.eth14[0x3000]=0
CLMIB_RPFC5.eth15[0x3000]=0
CLMIB_RPFC5.eth16[0x3000]=0
CLMIB_RPFC5.eth17[0x3000]=0
CLMIB_RPFC5.eth18[0x3000]=0
CLMIB_RPFC5.eth19[0x3000]=0
CLMIB_RPFC5.eth20[0x3000]=0
CLMIB_RPFC5.eth21[0x3000]=0
CLMIB_RPFC5.eth22[0x3000]=0
CLMIB_RPFC5.eth23[0x3000]=0
CLMIB_RPFC5.eth24[0x3000]=0
CLMIB_RPFC5.eth25[0x3000]=0
CLMIB_RPFC5.eth26[0x3000]=0
CLMIB_RPFC5.eth27[0x3000]=0
CLMIB_RPFC5.eth28[0x3000]=0
CLMIB_RPFC5.eth29[0x3000]=0
CLMIB_RPFC5.eth30[0x3000]=0
CLMIB_RPFC5.eth31[0x3000]=0
CLMIB_RPFC5.eth32[0x3000]=0
CLMIB_RPFC6.eth1[0x3100]=0
CLMIB_RPFC6.eth2[0x3100]=0
CLMIB_RPFC6.eth3[0x3100]=0
CLMIB_RPFC6.eth4[0x3100]=0
CLMIB_RPFC6.eth5[0x3100]=0
CLMIB_RPFC6.eth6[0x3100]=0
CLMIB_RPFC6.eth7[0x3100]=0
CLMIB_RPFC6.eth8[0x3100]=0
CLMIB_RPFC6.eth9[0x3100]=0
CLMIB_RPFC6.eth10[0x3100]=0
CLMIB_RPFC6.eth11[0x3100]=0
CLMIB_RPFC6.eth12[0x3100]=0
CLMIB_RPFC6.eth13[0x3100]=0
CLMIB_RPFC6.eth14[0x3100]=0
CLMIB_RPFC6.eth15[0x3100]=0
CLMIB_RPFC6.eth16[0x3100]=0
CLMIB_RPFC6.eth17[0x3100]=0
CLMIB_RPFC6.eth18[0x3100]=0
CLMIB_RPFC6.eth19[0x3100]=0
CLMIB_RPFC6.eth20[0x3100]=0
CLMIB_RPFC6.eth21[0x3100]=0
CLMIB_RPFC6.eth22[0x3100]=0
CLMIB_RPFC6.eth23[0x3100]=0
CLMIB_RPFC6.eth24[0x3100]=0
CLMIB_RPFC6.eth25[0x3100]=0
CLMIB_RPFC6.eth26[0x3100]=0
CLMIB_RPFC6.eth27[0x3100]=0
CLMIB_RPFC6.eth28[0x3100]=0
CLMIB_RPFC6.eth29[0x3100]=0
CLMIB_RPFC6.eth30[0x3100]=0
CLMIB_RPFC6.eth31[0x3100]=0
CLMIB_RPFC6.eth32[0x3100]=0
CLMIB_RPFC7.eth1[0x3200]=0
CLMIB_RPFC7.eth2[0x3200]=0
CLMIB_RPFC7.eth3[0x3200]=0
CLMIB_RPFC7.eth4[0x3200]=0
CLMIB_RPFC7.eth5[0x3200]=0
CLMIB_RPFC7.eth6[0x3200]=0
CLMIB_RPFC7.eth7[0x3200]=0
CLMIB_RPFC7.eth8[0x3200]=0
CLMIB_RPFC7.eth9[0x3200]=0
CLMIB_RPFC7.eth10[0x3200]=0
CLMIB_RPFC7.eth11[0x3200]=0
CLMIB_RPFC7.eth12[0x3200]=0
CLMIB_RPFC7.eth13[0x3200]=0
CLMIB_RPFC7.eth14[0x3200]=0
CLMIB_RPFC7.eth15[0x3200]=0
CLMIB_RPFC7.eth16[0x3200]=0
CLMIB_RPFC7.eth17[0x3200]=0
CLMIB_RPFC7.eth18[0x3200]=0
CLMIB_RPFC7.eth19[0x3200]=0
CLMIB_RPFC7.eth20[0x3200]=0
CLMIB_RPFC7.eth21[0x3200]=0
CLMIB_RPFC7.eth22[0x3200]=0
CLMIB_RPFC7.eth23[0x3200]=0
CLMIB_RPFC7.eth24[0x3200]=0
CLMIB_RPFC7.eth25[0x3200]=0
CLMIB_RPFC7.eth26[0x3200]=0
CLMIB_RPFC7.eth27[0x3200]=0
CLMIB_RPFC7.eth28[0x3200]=0
CLMIB_RPFC7.eth29[0x3200]=0
CLMIB_RPFC7.eth30[0x3200]=0
CLMIB_RPFC7.eth31[0x3200]=0
CLMIB_RPFC7.eth32[0x3200]=0
CLMIB_RPFCOFF0.eth1[0x2300]=0
CLMIB_RPFCOFF0.eth2[0x2300]=0
CLMIB_RPFCOFF0.eth3[0x2300]=0
CLMIB_RPFCOFF0.eth4[0x2300]=0
CLMIB_RPFCOFF0.eth5[0x2300]=0
CLMIB_RPFCOFF0.eth6[0x2300]=0
CLMIB_RPFCOFF0.eth7[0x2300]=0
CLMIB_RPFCOFF0.eth8[0x2300]=0
CLMIB_RPFCOFF0.eth9[0x2300]=0
CLMIB_RPFCOFF0.eth10[0x2300]=0
CLMIB_RPFCOFF0.eth11[0x2300]=0
CLMIB_RPFCOFF0.eth12[0x2300]=0
CLMIB_RPFCOFF0.eth13[0x2300]=0
CLMIB_RPFCOFF0.eth14[0x2300]=0
CLMIB_RPFCOFF0.eth15[0x2300]=0
CLMIB_RPFCOFF0.eth16[0x2300]=0
CLMIB_RPFCOFF0.eth17[0x2300]=0
CLMIB_RPFCOFF0.eth18[0x2300]=0
CLMIB_RPFCOFF0.eth19[0x2300]=0
CLMIB_RPFCOFF0.eth20[0x2300]=0
CLMIB_RPFCOFF0.eth21[0x2300]=0
CLMIB_RPFCOFF0.eth22[0x2300]=0
CLMIB_RPFCOFF0.eth23[0x2300]=0
CLMIB_RPFCOFF0.eth24[0x2300]=0
CLMIB_RPFCOFF0.eth25[0x2300]=0
CLMIB_RPFCOFF0.eth26[0x2300]=0
CLMIB_RPFCOFF0.eth27[0x2300]=0
CLMIB_RPFCOFF0.eth28[0x2300]=0
CLMIB_RPFCOFF0.eth29[0x2300]=0
CLMIB_RPFCOFF0.eth30[0x2300]=0
CLMIB_RPFCOFF0.eth31[0x2300]=0
CLMIB_RPFCOFF0.eth32[0x2300]=0
CLMIB_RPFCOFF1.eth1[0x2400]=0
CLMIB_RPFCOFF1.eth2[0x2400]=0
CLMIB_RPFCOFF1.eth3[0x2400]=0
CLMIB_RPFCOFF1.eth4[0x2400]=0
CLMIB_RPFCOFF1.eth5[0x2400]=0
CLMIB_RPFCOFF1.eth6[0x2400]=0
CLMIB_RPFCOFF1.eth7[0x2400]=0
CLMIB_RPFCOFF1.eth8[0x2400]=0
CLMIB_RPFCOFF1.eth9[0x2400]=0
CLMIB_RPFCOFF1.eth10[0x2400]=0
CLMIB_RPFCOFF1.eth11[0x2400]=0
CLMIB_RPFCOFF1.eth12[0x2400]=0
CLMIB_RPFCOFF1.eth13[0x2400]=0
CLMIB_RPFCOFF1.eth14[0x2400]=0
CLMIB_RPFCOFF1.eth15[0x2400]=0
CLMIB_RPFCOFF1.eth16[0x2400]=0
CLMIB_RPFCOFF1.eth17[0x2400]=0
CLMIB_RPFCOFF1.eth18[0x2400]=0
CLMIB_RPFCOFF1.eth19[0x2400]=0
CLMIB_RPFCOFF1.eth20[0x2400]=0
CLMIB_RPFCOFF1.eth21[0x2400]=0
CLMIB_RPFCOFF1.eth22[0x2400]=0
CLMIB_RPFCOFF1.eth23[0x2400]=0
CLMIB_RPFCOFF1.eth24[0x2400]=0
CLMIB_RPFCOFF1.eth25[0x2400]=0
CLMIB_RPFCOFF1.eth26[0x2400]=0
CLMIB_RPFCOFF1.eth27[0x2400]=0
CLMIB_RPFCOFF1.eth28[0x2400]=0
CLMIB_RPFCOFF1.eth29[0x2400]=0
CLMIB_RPFCOFF1.eth30[0x2400]=0
CLMIB_RPFCOFF1.eth31[0x2400]=0
CLMIB_RPFCOFF1.eth32[0x2400]=0
CLMIB_RPFCOFF2.eth1[0x2500]=0
CLMIB_RPFCOFF2.eth2[0x2500]=0
CLMIB_RPFCOFF2.eth3[0x2500]=0
CLMIB_RPFCOFF2.eth4[0x2500]=0
CLMIB_RPFCOFF2.eth5[0x2500]=0
CLMIB_RPFCOFF2.eth6[0x2500]=0
CLMIB_RPFCOFF2.eth7[0x2500]=0
CLMIB_RPFCOFF2.eth8[0x2500]=0
CLMIB_RPFCOFF2.eth9[0x2500]=0
CLMIB_RPFCOFF2.eth10[0x2500]=0
CLMIB_RPFCOFF2.eth11[0x2500]=0
CLMIB_RPFCOFF2.eth12[0x2500]=0
CLMIB_RPFCOFF2.eth13[0x2500]=0
CLMIB_RPFCOFF2.eth14[0x2500]=0
CLMIB_RPFCOFF2.eth15[0x2500]=0
CLMIB_RPFCOFF2.eth16[0x2500]=0
CLMIB_RPFCOFF2.eth17[0x2500]=0
CLMIB_RPFCOFF2.eth18[0x2500]=0
CLMIB_RPFCOFF2.eth19[0x2500]=0
CLMIB_RPFCOFF2.eth20[0x2500]=0
CLMIB_RPFCOFF2.eth21[0x2500]=0
CLMIB_RPFCOFF2.eth22[0x2500]=0
CLMIB_RPFCOFF2.eth23[0x2500]=0
CLMIB_RPFCOFF2.eth24[0x2500]=0
CLMIB_RPFCOFF2.eth25[0x2500]=0
CLMIB_RPFCOFF2.eth26[0x2500]=0
CLMIB_RPFCOFF2.eth27[0x2500]=0
CLMIB_RPFCOFF2.eth28[0x2500]=0
CLMIB_RPFCOFF2.eth29[0x2500]=0
CLMIB_RPFCOFF2.eth30[0x2500]=0
CLMIB_RPFCOFF2.eth31[0x2500]=0
CLMIB_RPFCOFF2.eth32[0x2500]=0
CLMIB_RPFCOFF3.eth1[0x2600]=0
CLMIB_RPFCOFF3.eth2[0x2600]=0
CLMIB_RPFCOFF3.eth3[0x2600]=0
CLMIB_RPFCOFF3.eth4[0x2600]=0
CLMIB_RPFCOFF3.eth5[0x2600]=0
CLMIB_RPFCOFF3.eth6[0x2600]=0
CLMIB_RPFCOFF3.eth7[0x2600]=0
CLMIB_RPFCOFF3.eth8[0x2600]=0
CLMIB_RPFCOFF3.eth9[0x2600]=0
CLMIB_RPFCOFF3.eth10[0x2600]=0
CLMIB_RPFCOFF3.eth11[0x2600]=0
CLMIB_RPFCOFF3.eth12[0x2600]=0
CLMIB_RPFCOFF3.eth13[0x2600]=0
CLMIB_RPFCOFF3.eth14[0x2600]=0
CLMIB_RPFCOFF3.eth15[0x2600]=0
CLMIB_RPFCOFF3.eth16[0x2600]=0
CLMIB_RPFCOFF3.eth17[0x2600]=0
CLMIB_RPFCOFF3.eth18[0x2600]=0
CLMIB_RPFCOFF3.eth19[0x2600]=0
CLMIB_RPFCOFF3.eth20[0x2600]=0
CLMIB_RPFCOFF3.eth21[0x2600]=0
CLMIB_RPFCOFF3.eth22[0x2600]=0
CLMIB_RPFCOFF3.eth23[0x2600]=0
CLMIB_RPFCOFF3.eth24[0x2600]=0
CLMIB_RPFCOFF3.eth25[0x2600]=0
CLMIB_RPFCOFF3.eth26[0x2600]=0
CLMIB_RPFCOFF3.eth27[0x2600]=0
CLMIB_RPFCOFF3.eth28[0x2600]=0
CLMIB_RPFCOFF3.eth29[0x2600]=0
CLMIB_RPFCOFF3.eth30[0x2600]=0
CLMIB_RPFCOFF3.eth31[0x2600]=0
CLMIB_RPFCOFF3.eth32[0x2600]=0
CLMIB_RPFCOFF4.eth1[0x2700]=0
CLMIB_RPFCOFF4.eth2[0x2700]=0
CLMIB_RPFCOFF4.eth3[0x2700]=0
CLMIB_RPFCOFF4.eth4[0x2700]=0
CLMIB_RPFCOFF4.eth5[0x2700]=0
CLMIB_RPFCOFF4.eth6[0x2700]=0
CLMIB_RPFCOFF4.eth7[0x2700]=0
CLMIB_RPFCOFF4.eth8[0x2700]=0
CLMIB_RPFCOFF4.eth9[0x2700]=0
CLMIB_RPFCOFF4.eth10[0x2700]=0
CLMIB_RPFCOFF4.eth11[0x2700]=0
CLMIB_RPFCOFF4.eth12[0x2700]=0
CLMIB_RPFCOFF4.eth13[0x2700]=0
CLMIB_RPFCOFF4.eth14[0x2700]=0
CLMIB_RPFCOFF4.eth15[0x2700]=0
CLMIB_RPFCOFF4.eth16[0x2700]=0
CLMIB_RPFCOFF4.eth17[0x2700]=0
CLMIB_RPFCOFF4.eth18[0x2700]=0
CLMIB_RPFCOFF4.eth19[0x2700]=0
CLMIB_RPFCOFF4.eth20[0x2700]=0
CLMIB_RPFCOFF4.eth21[0x2700]=0
CLMIB_RPFCOFF4.eth22[0x2700]=0
CLMIB_RPFCOFF4.eth23[0x2700]=0
CLMIB_RPFCOFF4.eth24[0x2700]=0
CLMIB_RPFCOFF4.eth25[0x2700]=0
CLMIB_RPFCOFF4.eth26[0x2700]=0
CLMIB_RPFCOFF4.eth27[0x2700]=0
CLMIB_RPFCOFF4.eth28[0x2700]=0
CLMIB_RPFCOFF4.eth29[0x2700]=0
CLMIB_RPFCOFF4.eth30[0x2700]=0
CLMIB_RPFCOFF4.eth31[0x2700]=0
CLMIB_RPFCOFF4.eth32[0x2700]=0
CLMIB_RPFCOFF5.eth1[0x2800]=0
CLMIB_RPFCOFF5.eth2[0x2800]=0
CLMIB_RPFCOFF5.eth3[0x2800]=0
CLMIB_RPFCOFF5.eth4[0x2800]=0
CLMIB_RPFCOFF5.eth5[0x2800]=0
CLMIB_RPFCOFF5.eth6[0x2800]=0
CLMIB_RPFCOFF5.eth7[0x2800]=0
CLMIB_RPFCOFF5.eth8[0x2800]=0
CLMIB_RPFCOFF5.eth9[0x2800]=0
CLMIB_RPFCOFF5.eth10[0x2800]=0
CLMIB_RPFCOFF5.eth11[0x2800]=0
CLMIB_RPFCOFF5.eth12[0x2800]=0
CLMIB_RPFCOFF5.eth13[0x2800]=0
CLMIB_RPFCOFF5.eth14[0x2800]=0
CLMIB_RPFCOFF5.eth15[0x2800]=0
CLMIB_RPFCOFF5.eth16[0x2800]=0
CLMIB_RPFCOFF5.eth17[0x2800]=0
CLMIB_RPFCOFF5.eth18[0x2800]=0
CLMIB_RPFCOFF5.eth19[0x2800]=0
CLMIB_RPFCOFF5.eth20[0x2800]=0
CLMIB_RPFCOFF5.eth21[0x2800]=0
CLMIB_RPFCOFF5.eth22[0x2800]=0
CLMIB_RPFCOFF5.eth23[0x2800]=0
CLMIB_RPFCOFF5.eth24[0x2800]=0
CLMIB_RPFCOFF5.eth25[0x2800]=0
CLMIB_RPFCOFF5.eth26[0x2800]=0
CLMIB_RPFCOFF5.eth27[0x2800]=0
CLMIB_RPFCOFF5.eth28[0x2800]=0
CLMIB_RPFCOFF5.eth29[0x2800]=0
CLMIB_RPFCOFF5.eth30[0x2800]=0
CLMIB_RPFCOFF5.eth31[0x2800]=0
CLMIB_RPFCOFF5.eth32[0x2800]=0
CLMIB_RPFCOFF6.eth1[0x2900]=0
CLMIB_RPFCOFF6.eth2[0x2900]=0
CLMIB_RPFCOFF6.eth3[0x2900]=0
CLMIB_RPFCOFF6.eth4[0x2900]=0
CLMIB_RPFCOFF6.eth5[0x2900]=0
CLMIB_RPFCOFF6.eth6[0x2900]=0
CLMIB_RPFCOFF6.eth7[0x2900]=0
CLMIB_RPFCOFF6.eth8[0x2900]=0
CLMIB_RPFCOFF6.eth9[0x2900]=0
CLMIB_RPFCOFF6.eth10[0x2900]=0
CLMIB_RPFCOFF6.eth11[0x2900]=0
CLMIB_RPFCOFF6.eth12[0x2900]=0
CLMIB_RPFCOFF6.eth13[0x2900]=0
CLMIB_RPFCOFF6.eth14[0x2900]=0
CLMIB_RPFCOFF6.eth15[0x2900]=0
CLMIB_RPFCOFF6.eth16[0x2900]=0
CLMIB_RPFCOFF6.eth17[0x2900]=0
CLMIB_RPFCOFF6.eth18[0x2900]=0
CLMIB_RPFCOFF6.eth19[0x2900]=0
CLMIB_RPFCOFF6.eth20[0x2900]=0
CLMIB_RPFCOFF6.eth21[0x2900]=0
CLMIB_RPFCOFF6.eth22[0x2900]=0
CLMIB_RPFCOFF6.eth23[0x2900]=0
CLMIB_RPFCOFF6.eth24[0x2900]=0
CLMIB_RPFCOFF6.eth25[0x2900]=0
CLMIB_RPFCOFF6.eth26[0x2900]=0
CLMIB_RPFCOFF6.eth27[0x2900]=0
CLMIB_RPFCOFF6.eth28[0x2900]=0
CLMIB_RPFCOFF6.eth29[0x2900]=0
CLMIB_RPFCOFF6.eth30[0x2900]=0
CLMIB_RPFCOFF6.eth31[0x2900]=0
CLMIB_RPFCOFF6.eth32[0x2900]=0
CLMIB_RPFCOFF7.eth1[0x2a00]=0
CLMIB_RPFCOFF7.eth2[0x2a00]=0
CLMIB_RPFCOFF7.eth3[0x2a00]=0
CLMIB_RPFCOFF7.eth4[0x2a00]=0
CLMIB_RPFCOFF7.eth5[0x2a00]=0
CLMIB_RPFCOFF7.eth6[0x2a00]=0
CLMIB_RPFCOFF7.eth7[0x2a00]=0
CLMIB_RPFCOFF7.eth8[0x2a00]=0
CLMIB_RPFCOFF7.eth9[0x2a00]=0
CLMIB_RPFCOFF7.eth10[0x2a00]=0
CLMIB_RPFCOFF7.eth11[0x2a00]=0
CLMIB_RPFCOFF7.eth12[0x2a00]=0
CLMIB_RPFCOFF7.eth13[0x2a00]=0
CLMIB_RPFCOFF7.eth14[0x2a00]=0
CLMIB_RPFCOFF7.eth15[0x2a00]=0
CLMIB_RPFCOFF7.eth16[0x2a00]=0
CLMIB_RPFCOFF7.eth17[0x2a00]=0
CLMIB_RPFCOFF7.eth18[0x2a00]=0
CLMIB_RPFCOFF7.eth19[0x2a00]=0
CLMIB_RPFCOFF7.eth20[0x2a00]=0
CLMIB_RPFCOFF7.eth21[0x2a00]=0
CLMIB_RPFCOFF7.eth22[0x2a00]=0
CLMIB_RPFCOFF7.eth23[0x2a00]=0
CLMIB_RPFCOFF7.eth24[0x2a00]=0
CLMIB_RPFCOFF7.eth25[0x2a00]=0
CLMIB_RPFCOFF7.eth26[0x2a00]=0
CLMIB_RPFCOFF7.eth27[0x2a00]=0
CLMIB_RPFCOFF7.eth28[0x2a00]=0
CLMIB_RPFCOFF7.eth29[0x2a00]=0
CLMIB_RPFCOFF7.eth30[0x2a00]=0
CLMIB_RPFCOFF7.eth31[0x2a00]=0
CLMIB_RPFCOFF7.eth32[0x2a00]=0
CLMIB_RPKT.eth1[0xb00]=0x2e325b04e
CLMIB_RPKT.eth2[0xb00]=0x1352b3623
CLMIB_RPKT.eth3[0xb00]=0x337e0c19e
CLMIB_RPKT.eth4[0xb00]=0x1c3bf630b
CLMIB_RPKT.eth5[0xb00]=0
CLMIB_RPKT.eth6[0xb00]=0
CLMIB_RPKT.eth7[0xb00]=0
CLMIB_RPKT.eth8[0xb00]=0
CLMIB_RPKT.eth9[0xb00]=0
CLMIB_RPKT.eth10[0xb00]=0
CLMIB_RPKT.eth11[0xb00]=0
CLMIB_RPKT.eth12[0xb00]=0
CLMIB_RPKT.eth13[0xb00]=0
CLMIB_RPKT.eth14[0xb00]=0
CLMIB_RPKT.eth15[0xb00]=0
CLMIB_RPKT.eth16[0xb00]=0
CLMIB_RPKT.eth17[0xb00]=0
CLMIB_RPKT.eth18[0xb00]=0
CLMIB_RPKT.eth19[0xb00]=0
CLMIB_RPKT.eth20[0xb00]=0
CLMIB_RPKT.eth21[0xb00]=0
CLMIB_RPKT.eth22[0xb00]=0
CLMIB_RPKT.eth23[0xb00]=0
CLMIB_RPKT.eth24[0xb00]=0
CLMIB_RPKT.eth25[0xb00]=0
CLMIB_RPKT.eth26[0xb00]=0
CLMIB_RPKT.eth27[0xb00]=0
CLMIB_RPKT.eth28[0xb00]=0
CLMIB_RPKT.eth29[0xb00]=0
CLMIB_RPKT.eth30[0xb00]=0
CLMIB_RPKT.eth31[0xb00]=0
CLMIB_RPKT.eth32[0xb00]=0x12ada18fd0
CLMIB_RPOK.eth1[0x2200]=0x2e32585e8
CLMIB_RPOK.eth2[0x2200]=0x1352b34ec
CLMIB_RPOK.eth3[0x2200]=0x337d2d321
CLMIB_RPOK.eth4[0x2200]=0x1c393fd7b
CLMIB_RPOK.eth5[0x2200]=0
CLMIB_RPOK.eth6[0x2200]=0
CLMIB_RPOK.eth7[0x2200]=0
CLMIB_RPOK.eth8[0x2200]=0
CLMIB_RPOK.eth9[0x2200]=0
CLMIB_RPOK.eth10[0x2200]=0
CLMIB_RPOK.eth11[0x2200]=0
CLMIB_RPOK.eth12[0x2200]=0
CLMIB_RPOK.eth13[0x2200]=0
CLMIB_RPOK.eth14[0x2200]=0
CLMIB_RPOK.eth15[0x2200]=0
CLMIB_RPOK.eth16[0x2200]=0
CLMIB_RPOK.eth17[0x2200]=0
CLMIB_RPOK.eth18[0x2200]=0
CLMIB_RPOK.eth19[0x2200]=0
CLMIB_RPOK.eth20[0x2200]=0
CLMIB_RPOK.eth21[0x2200]=0
CLMIB_RPOK.eth22[0x2200]=0
CLMIB_RPOK.eth23[0x2200]=0
CLMIB_RPOK.eth24[0x2200]=0
CLMIB_RPOK.eth25[0x2200]=0
CLMIB_RPOK.eth26[0x2200]=0
CLMIB_RPOK.eth27[0x2200]=0
CLMIB_RPOK.eth28[0x2200]=0
CLMIB_RPOK.eth29[0x2200]=0
CLMIB_RPOK.eth30[0x2200]=0
CLMIB_RPOK.eth31[0x2200]=0
CLMIB_RPOK.eth32[0x2200]=0x12ada18464
CLMIB_RPRM.eth1[0x1e00]=0x2c27e9d05
CLMIB_RPRM.eth2[0x1e00]=0x11d810816
CLMIB_RPRM.eth3[0x1e00]=0x306b0e122
CLMIB_RPRM.eth4[0x1e00]=0x1b1b2933a
CLMIB_RPRM.eth5[0x1e00]=0
CLMIB_RPRM.eth6[0x1e00]=0
CLMIB_RPRM.eth7[0x1e00]=0
CLMIB_RPRM.eth8[0x1e00]=0
CLMIB_RPRM.eth9[0x1e00]=0
CLMIB_RPRM.eth10[0x1e00]=0
CLMIB_RPRM.eth11[0x1e00]=0
CLMIB_RPRM.eth12[0x1e00]=0
CLMIB_RPRM.eth13[0x1e00]=0
CLMIB_RPRM.eth14[0x1e00]=0
CLMIB_RPRM.eth15[0x1e00]=0
CLMIB_RPRM.eth16[0x1e00]=0
CLMIB_RPRM.eth17[0x1e00]=0
CLMIB_RPRM.eth18[0x1e00]=0
CLMIB_RPRM.eth19[0x1e00]=0
CLMIB_RPRM.eth20[0x1e00]=0
CLMIB_RPRM.eth21[0x1e00]=0
CLMIB_RPRM.eth22[0x1e00]=0
CLMIB_RPRM.eth23[0x1e00]=0
CLMIB_RPRM.eth24[0x1e00]=0
CLMIB_RPRM.eth25[0x1e00]=0
CLMIB_RPRM.eth26[0x1e00]=0
CLMIB_RPRM.eth27[0x1e00]=0
CLMIB_RPRM.eth28[0x1e00]=0
CLMIB_RPRM.eth29[0x1e00]=0
CLMIB_RPRM.eth30[0x1e00]=0
CLMIB_RPRM.eth31[0x1e00]=0
CLMIB_RPRM.eth32[0x1e00]=0xbb9e47e9a
CLMIB_RPROG0.eth1[0x7500]=0x17ce05b7b
CLMIB_RPROG0.eth2[0x7500]=0x99d505ca
CLMIB_RPROG0.eth3[0x7500]=0x177a27a0b
CLMIB_RPROG0.eth4[0x7500]=0xb17c00eb
CLMIB_RPROG0.eth5[0x7500]=0
CLMIB_RPROG0.eth6[0x7500]=0
CLMIB_RPROG0.eth7[0x7500]=0
CLMIB_RPROG0.eth8[0x7500]=0
CLMIB_RPROG0.eth9[0x7500]=0
CLMIB_RPROG0.eth10[0x7500]=0
CLMIB_RPROG0.eth11[0x7500]=0
CLMIB_RPROG0.eth12[0x7500]=0
CLMIB_RPROG0.eth13[0x7500]=0
CLMIB_RPROG0.eth14[0x7500]=0
CLMIB_RPROG0.eth15[0x7500]=0
CLMIB_RPROG0.eth16[0x7500]=0
CLMIB_RPROG0.eth17[0x7500]=0
CLMIB_RPROG0.eth18[0x7500]=0
CLMIB_RPROG0.eth19[0x7500]=0
CLMIB_RPROG0.eth20[0x7500]=0
CLMIB_RPROG0.eth21[0x7500]=0
CLMIB_RPROG0.eth22[0x7500]=0
CLMIB_RPROG0.eth23[0x7500]=0
CLMIB_RPROG0.eth24[0x7500]=0
CLMIB_RPROG0.eth25[0x7500]=0
CLMIB_RPROG0.eth26[0x7500]=0
CLMIB_RPROG0.eth27[0x7500]=0
CLMIB_RPROG0.eth28[0x7500]=0
CLMIB_RPROG0.eth29[0x7500]=0
CLMIB_RPROG0.eth30[0x7500]=0
CLMIB_RPROG0.eth31[0x7500]=0
CLMIB_RPROG0.eth32[0x7500]=0x1fe9f9e4b
CLMIB_RPROG1.eth1[0x7600]=0x3caed33d
CLMIB_RPROG1.eth2[0x7600]=0x24326545
CLMIB_RPROG1.eth3[0x7600]=0x5deffa58
CLMIB_RPROG1.eth4[0x7600]=0x26577682
CLMIB_RPROG1.eth5[0x7600]=0
CLMIB_RPROG1.eth6[0x7600]=0
CLMIB_RPROG1.eth7[0x7600]=0
CLMIB_RPROG1.eth8[0x7600]=0
CLMIB_RPROG1.eth9[0x7600]=0
CLMIB_RPROG1.eth10[0x7600]=0
CLMIB_RPROG1.eth11[0x7600]=0
CLMIB_RPROG1.eth12[0x7600]=0
CLMIB_RPROG1.eth13[0x7600]=0
CLMIB_RPROG1.eth14[0x7600]=0
CLMIB_RPROG1.eth15[0x7600]=0
CLMIB_RPROG1.eth16[0x7600]=0
CLMIB_RPROG1.eth17[0x7600]=0
CLMIB_RPROG1.eth18[0x7600]=0
CLMIB_RPROG1.eth19[0x7600]=0
CLMIB_RPROG1.eth20[0x7600]=0
CLMIB_RPROG1.eth21[0x7600]=0
CLMIB_RPROG1.eth22[0x7600]=0
CLMIB_RPROG1.eth23[0x7600]=0
CLMIB_RPROG1.eth24[0x7600]=0
CLMIB_RPROG1.eth25[0x7600]=0
CLMIB_RPROG1.eth26[0x7600]=0
CLMIB_RPROG1.eth27[0x7600]=0
CLMIB_RPROG1.eth28[0x7600]=0
CLMIB_RPROG1.eth29[0x7600]=0
CLMIB_RPROG1.eth30[0x7600]=0
CLMIB_RPROG1.eth31[0x7600]=0
CLMIB_RPROG1.eth32[0x7600]=0x342881f7
CLMIB_RPROG2.eth1[0x7700]=0x23b03218
CLMIB_RPROG2.eth2[0x7700]=0x13519155
CLMIB_RPROG2.eth3[0x7700]=0x2db99b83
CLMIB_RPROG2.eth4[0x7700]=0x14c308f7
CLMIB_RPROG2.eth5[0x7700]=0
CLMIB_RPROG2.eth6[0x7700]=0
CLMIB_RPROG2.eth7[0x7700]=0
CLMIB_RPROG2.eth8[0x7700]=0
CLMIB_RPROG2.eth9[0x7700]=0
CLMIB_RPROG2.eth10[0x7700]=0
CLMIB_RPROG2.eth11[0x7700]=0
CLMIB_RPROG2.eth12[0x7700]=0
CLMIB_RPROG2.eth13[0x7700]=0
CLMIB_RPROG2.eth14[0x7700]=0
CLMIB_RPROG2.eth15[0x7700]=0
CLMIB_RPROG2.eth16[0x7700]=0
CLMIB_RPROG2.eth17[0x7700]=0
CLMIB_RPROG2.eth18[0x7700]=0
CLMIB_RPROG2.eth19[0x7700]=0
CLMIB_RPROG2.eth20[0x7700]=0
CLMIB_RPROG2.eth21[0x7700]=0
CLMIB_RPROG2.eth22[0x7700]=0
CLMIB_RPROG2.eth23[0x7700]=0
CLMIB_RPROG2.eth24[0x7700]=0
CLMIB_RPROG2.eth25[0x7700]=0
CLMIB_RPROG2.eth26[0x7700]=0
CLMIB_RPROG2.eth27[0x7700]=0
CLMIB_RPROG2.eth28[0x7700]=0
CLMIB_RPROG2.eth29[0x7700]=0
CLMIB_RPROG2.eth30[0x7700]=0
CLMIB_RPROG2.eth31[0x7700]=0
CLMIB_RPROG2.eth32[0x7700]=0x2d7079b3
CLMIB_RPROG3.eth1[0x7800]=0x910b903
CLMIB_RPROG3.eth2[0x7800]=0x6768db0
CLMIB_RPROG3.eth3[0x7800]=0xad0d387
CLMIB_RPROG3.eth4[0x7800]=0x16ea540a
CLMIB_RPROG3.eth5[0x7800]=0
CLMIB_RPROG3.eth6[0x7800]=0
CLMIB_RPROG3.eth7[0x7800]=0
CLMIB_RPROG3.eth8[0x7800]=0
CLMIB_RPROG3.eth9[0x7800]=0
CLMIB_RPROG3.eth10[0x7800]=0
CLMIB_RPROG3.eth11[0x7800]=0
CLMIB_RPROG3.eth12[0x7800]=0
CLMIB_RPROG3.eth13[0x7800]=0
CLMIB_RPROG3.eth14[0x7800]=0
CLMIB_RPROG3.eth15[0x7800]=0
CLMIB_RPROG3.eth16[0x7800]=0
CLMIB_RPROG3.eth17[0x7800]=0
CLMIB_RPROG3.eth18[0x7800]=0
CLMIB_RPROG3.eth19[0x7800]=0
CLMIB_RPROG3.eth20[0x7800]=0
CLMIB_RPROG3.eth21[0x7800]=0
CLMIB_RPROG3.eth22[0x7800]=0
CLMIB_RPROG3.eth23[0x7800]=0
CLMIB_RPROG3.eth24[0x7800]=0
CLMIB_RPROG3.eth25[0x7800]=0
CLMIB_RPROG3.eth26[0x7800]=0
CLMIB_RPROG3.eth27[0x7800]=0
CLMIB_RPROG3.eth28[0x7800]=0
CLMIB_RPROG3.eth29[0x7800]=0
CLMIB_RPROG3.eth30[0x7800]=0
CLMIB_RPROG3.eth31[0x7800]=0
CLMIB_RPROG3.eth32[0x7800]=0x59c09326
CLMIB_RRBYT.eth1[0x3e00]=0
CLMIB_RRBYT.eth2[0x3e00]=0
CLMIB_RRBYT.eth3[0x3e00]=0
CLMIB_RRBYT.eth4[0x3e00]=0
CLMIB_RRBYT.eth5[0x3e00]=0
CLMIB_RRBYT.eth6[0x3e00]=0
CLMIB_RRBYT.eth7[0x3e00]=0
CLMIB_RRBYT.eth8[0x3e00]=0
CLMIB_RRBYT.eth9[0x3e00]=0
CLMIB_RRBYT.eth10[0x3e00]=0
CLMIB_RRBYT.eth11[0x3e00]=0
CLMIB_RRBYT.eth12[0x3e00]=0
CLMIB_RRBYT.eth13[0x3e00]=0
CLMIB_RRBYT.eth14[0x3e00]=0
CLMIB_RRBYT.eth15[0x3e00]=0
CLMIB_RRBYT.eth16[0x3e00]=0
CLMIB_RRBYT.eth17[0x3e00]=0
CLMIB_RRBYT.eth18[0x3e00]=0
CLMIB_RRBYT.eth19[0x3e00]=0
CLMIB_RRBYT.eth20[0x3e00]=0
CLMIB_RRBYT.eth21[0x3e00]=0
CLMIB_RRBYT.eth22[0x3e00]=0
CLMIB_RRBYT.eth23[0x3e00]=0
CLMIB_RRBYT.eth24[0x3e00]=0
CLMIB_RRBYT.eth25[0x3e00]=0
CLMIB_RRBYT.eth26[0x3e00]=0
CLMIB_RRBYT.eth27[0x3e00]=0
CLMIB_RRBYT.eth28[0x3e00]=0
CLMIB_RRBYT.eth29[0x3e00]=0
CLMIB_RRBYT.eth30[0x3e00]=0
CLMIB_RRBYT.eth31[0x3e00]=0
CLMIB_RRBYT.eth32[0x3e00]=0xd0
CLMIB_RREPLY.eth1[0x1900]=0
CLMIB_RREPLY.eth2[0x1900]=0
CLMIB_RREPLY.eth3[0x1900]=0
CLMIB_RREPLY.eth4[0x1900]=0
CLMIB_RREPLY.eth5[0x1900]=0
CLMIB_RREPLY.eth6[0x1900]=0
CLMIB_RREPLY.eth7[0x1900]=0
CLMIB_RREPLY.eth8[0x1900]=0
CLMIB_RREPLY.eth9[0x1900]=0
CLMIB_RREPLY.eth10[0x1900]=0
CLMIB_RREPLY.eth11[0x1900]=0
CLMIB_RREPLY.eth12[0x1900]=0
CLMIB_RREPLY.eth13[0x1900]=0
CLMIB_RREPLY.eth14[0x1900]=0
CLMIB_RREPLY.eth15[0x1900]=0
CLMIB_RREPLY.eth16[0x1900]=0
CLMIB_RREPLY.eth17[0x1900]=0
CLMIB_RREPLY.eth18[0x1900]=0
CLMIB_RREPLY.eth19[0x1900]=0
CLMIB_RREPLY.eth20[0x1900]=0
CLMIB_RREPLY.eth21[0x1900]=0
CLMIB_RREPLY.eth22[0x1900]=0
CLMIB_RREPLY.eth23[0x1900]=0
CLMIB_RREPLY.eth24[0x1900]=0
CLMIB_RREPLY.eth25[0x1900]=0
CLMIB_RREPLY.eth26[0x1900]=0
CLMIB_RREPLY.eth27[0x1900]=0
CLMIB_RREPLY.eth28[0x1900]=0
CLMIB_RREPLY.eth29[0x1900]=0
CLMIB_RREPLY.eth30[0x1900]=0
CLMIB_RREPLY.eth31[0x1900]=0
CLMIB_RREPLY.eth32[0x1900]=0
CLMIB_RRPKT.eth1[0x3f00]=0
CLMIB_RRPKT.eth2[0x3f00]=0
CLMIB_RRPKT.eth3[0x3f00]=0
CLMIB_RRPKT.eth4[0x3f00]=0
CLMIB_RRPKT.eth5[0x3f00]=0
CLMIB_RRPKT.eth6[0x3f00]=0
CLMIB_RRPKT.eth7[0x3f00]=0
CLMIB_RRPKT.eth8[0x3f00]=0
CLMIB_RRPKT.eth9[0x3f00]=0
CLMIB_RRPKT.eth10[0x3f00]=0
CLMIB_RRPKT.eth11[0x3f00]=0
CLMIB_RRPKT.eth12[0x3f00]=0
CLMIB_RRPKT.eth13[0x3f00]=0
CLMIB_RRPKT.eth14[0x3f00]=0
CLMIB_RRPKT.eth15[0x3f00]=0
CLMIB_RRPKT.eth16[0x3f00]=0
CLMIB_RRPKT.eth17[0x3f00]=0
CLMIB_RRPKT.eth18[0x3f00]=0
CLMIB_RRPKT.eth19[0x3f00]=0
CLMIB_RRPKT.eth20[0x3f00]=0
CLMIB_RRPKT.eth21[0x3f00]=0
CLMIB_RRPKT.eth22[0x3f00]=0
CLMIB_RRPKT.eth23[0x3f00]=0
CLMIB_RRPKT.eth24[0x3f00]=0
CLMIB_RRPKT.eth25[0x3f00]=0
CLMIB_RRPKT.eth26[0x3f00]=0
CLMIB_RRPKT.eth27[0x3f00]=0
CLMIB_RRPKT.eth28[0x3f00]=0
CLMIB_RRPKT.eth29[0x3f00]=0
CLMIB_RRPKT.eth30[0x3f00]=0
CLMIB_RRPKT.eth31[0x3f00]=0
CLMIB_RRPKT.eth32[0x3f00]=6
CLMIB_RSCHCRC.eth1[0x3300]=0
CLMIB_RSCHCRC.eth2[0x3300]=0
CLMIB_RSCHCRC.eth3[0x3300]=0
CLMIB_RSCHCRC.eth4[0x3300]=0
CLMIB_RSCHCRC.eth5[0x3300]=0
CLMIB_RSCHCRC.eth6[0x3300]=0
CLMIB_RSCHCRC.eth7[0x3300]=0
CLMIB_RSCHCRC.eth8[0x3300]=0
CLMIB_RSCHCRC.eth9[0x3300]=0
CLMIB_RSCHCRC.eth10[0x3300]=0
CLMIB_RSCHCRC.eth11[0x3300]=0
CLMIB_RSCHCRC.eth12[0x3300]=0
CLMIB_RSCHCRC.eth13[0x3300]=0
CLMIB_RSCHCRC.eth14[0x3300]=0
CLMIB_RSCHCRC.eth15[0x3300]=0
CLMIB_RSCHCRC.eth16[0x3300]=0
CLMIB_RSCHCRC.eth17[0x3300]=0
CLMIB_RSCHCRC.eth18[0x3300]=0
CLMIB_RSCHCRC.eth19[0x3300]=0
CLMIB_RSCHCRC.eth20[0x3300]=0
CLMIB_RSCHCRC.eth21[0x3300]=0
CLMIB_RSCHCRC.eth22[0x3300]=0
CLMIB_RSCHCRC.eth23[0x3300]=0
CLMIB_RSCHCRC.eth24[0x3300]=0
CLMIB_RSCHCRC.eth25[0x3300]=0
CLMIB_RSCHCRC.eth26[0x3300]=0
CLMIB_RSCHCRC.eth27[0x3300]=0
CLMIB_RSCHCRC.eth28[0x3300]=0
CLMIB_RSCHCRC.eth29[0x3300]=0
CLMIB_RSCHCRC.eth30[0x3300]=0
CLMIB_RSCHCRC.eth31[0x3300]=0
CLMIB_RSCHCRC.eth32[0x3300]=0
CLMIB_RTRFU.eth1[0x2100]=0
CLMIB_RTRFU.eth2[0x2100]=0
CLMIB_RTRFU.eth3[0x2100]=0
CLMIB_RTRFU.eth4[0x2100]=0
CLMIB_RTRFU.eth5[0x2100]=0
CLMIB_RTRFU.eth6[0x2100]=0
CLMIB_RTRFU.eth7[0x2100]=0
CLMIB_RTRFU.eth8[0x2100]=0
CLMIB_RTRFU.eth9[0x2100]=0
CLMIB_RTRFU.eth10[0x2100]=0
CLMIB_RTRFU.eth11[0x2100]=0
CLMIB_RTRFU.eth12[0x2100]=0
CLMIB_RTRFU.eth13[0x2100]=0
CLMIB_RTRFU.eth14[0x2100]=0
CLMIB_RTRFU.eth15[0x2100]=0
CLMIB_RTRFU.eth16[0x2100]=0
CLMIB_RTRFU.eth17[0x2100]=0
CLMIB_RTRFU.eth18[0x2100]=0
CLMIB_RTRFU.eth19[0x2100]=0
CLMIB_RTRFU.eth20[0x2100]=0
CLMIB_RTRFU.eth21[0x2100]=0
CLMIB_RTRFU.eth22[0x2100]=0
CLMIB_RTRFU.eth23[0x2100]=0
CLMIB_RTRFU.eth24[0x2100]=0
CLMIB_RTRFU.eth25[0x2100]=0
CLMIB_RTRFU.eth26[0x2100]=0
CLMIB_RTRFU.eth27[0x2100]=0
CLMIB_RTRFU.eth28[0x2100]=0
CLMIB_RTRFU.eth29[0x2100]=0
CLMIB_RTRFU.eth30[0x2100]=0
CLMIB_RTRFU.eth31[0x2100]=0
CLMIB_RTRFU.eth32[0x2100]=0
CLMIB_RUCA.eth1[0xc00]=0x2e21cdfe4
CLMIB_RUCA.eth2[0xc00]=0x134ae299a
CLMIB_RUCA.eth3[0xc00]=0x336d3df10
CLMIB_RUCA.eth4[0xc00]=0x1c2fe19a3
CLMIB_RUCA.eth5[0xc00]=0
CLMIB_RUCA.eth6[0xc00]=0
CLMIB_RUCA.eth7[0xc00]=0
CLMIB_RUCA.eth8[0xc00]=0
CLMIB_RUCA.eth9[0xc00]=0
CLMIB_RUCA.eth10[0xc00]=0
CLMIB_RUCA.eth11[0xc00]=0
CLMIB_RUCA.eth12[0xc00]=0
CLMIB_RUCA.eth13[0xc00]=0
CLMIB_RUCA.eth14[0xc00]=0
CLMIB_RUCA.eth15[0xc00]=0
CLMIB_RUCA.eth16[0xc00]=0
CLMIB_RUCA.eth17[0xc00]=0
CLMIB_RUCA.eth18[0xc00]=0
CLMIB_RUCA.eth19[0xc00]=0
CLMIB_RUCA.eth20[0xc00]=0
CLMIB_RUCA.eth21[0xc00]=0
CLMIB_RUCA.eth22[0xc00]=0
CLMIB_RUCA.eth23[0xc00]=0
CLMIB_RUCA.eth24[0xc00]=0
CLMIB_RUCA.eth25[0xc00]=0
CLMIB_RUCA.eth26[0xc00]=0
CLMIB_RUCA.eth27[0xc00]=0
CLMIB_RUCA.eth28[0xc00]=0
CLMIB_RUCA.eth29[0xc00]=0
CLMIB_RUCA.eth30[0xc00]=0
CLMIB_RUCA.eth31[0xc00]=0
CLMIB_RUCA.eth32[0xc00]=0x12abc0d99c
CLMIB_RUND.eth1[0x3400]=0
CLMIB_RUND.eth2[0x3400]=0
CLMIB_RUND.eth3[0x3400]=0
CLMIB_RUND.eth4[0x3400]=0
CLMIB_RUND.eth5[0x3400]=0
CLMIB_RUND.eth6[0x3400]=0
CLMIB_RUND.eth7[0x3400]=0
CLMIB_RUND.eth8[0x3400]=0
CLMIB_RUND.eth9[0x3400]=0
CLMIB_RUND.eth10[0x3400]=0
CLMIB_RUND.eth11[0x3400]=0
CLMIB_RUND.eth12[0x3400]=0
CLMIB_RUND.eth13[0x3400]=0
CLMIB_RUND.eth14[0x3400]=0
CLMIB_RUND.eth15[0x3400]=0
CLMIB_RUND.eth16[0x3400]=0
CLMIB_RUND.eth17[0x3400]=0
CLMIB_RUND.eth18[0x3400]=0
CLMIB_RUND.eth19[0x3400]=0
CLMIB_RUND.eth20[0x3400]=0
CLMIB_RUND.eth21[0x3400]=0
CLMIB_RUND.eth22[0x3400]=0
CLMIB_RUND.eth23[0x3400]=0
CLMIB_RUND.eth24[0x3400]=0
CLMIB_RUND.eth25[0x3400]=0
CLMIB_RUND.eth26[0x3400]=0
CLMIB_RUND.eth27[0x3400]=0
CLMIB_RUND.eth28[0x3400]=0
CLMIB_RUND.eth29[0x3400]=0
CLMIB_RUND.eth30[0x3400]=0
CLMIB_RUND.eth31[0x3400]=0
CLMIB_RUND.eth32[0x3400]=0
CLMIB_RVERIFY.eth1[0x1600]=0
CLMIB_RVERIFY.eth2[0x1600]=0
CLMIB_RVERIFY.eth3[0x1600]=0
CLMIB_RVERIFY.eth4[0x1600]=0
CLMIB_RVERIFY.eth5[0x1600]=0
CLMIB_RVERIFY.eth6[0x1600]=0
CLMIB_RVERIFY.eth7[0x1600]=0
CLMIB_RVERIFY.eth8[0x1600]=0
CLMIB_RVERIFY.eth9[0x1600]=0
CLMIB_RVERIFY.eth10[0x1600]=0
CLMIB_RVERIFY.eth11[0x1600]=0
CLMIB_RVERIFY.eth12[0x1600]=0
CLMIB_RVERIFY.eth13[0x1600]=0
CLMIB_RVERIFY.eth14[0x1600]=0
CLMIB_RVERIFY.eth15[0x1600]=0
CLMIB_RVERIFY.eth16[0x1600]=0
CLMIB_RVERIFY.eth17[0x1600]=0
CLMIB_RVERIFY.eth18[0x1600]=0
CLMIB_RVERIFY.eth19[0x1600]=0
CLMIB_RVERIFY.eth20[0x1600]=0
CLMIB_RVERIFY.eth21[0x1600]=0
CLMIB_RVERIFY.eth22[0x1600]=0
CLMIB_RVERIFY.eth23[0x1600]=0
CLMIB_RVERIFY.eth24[0x1600]=0
CLMIB_RVERIFY.eth25[0x1600]=0
CLMIB_RVERIFY.eth26[0x1600]=0
CLMIB_RVERIFY.eth27[0x1600]=0
CLMIB_RVERIFY.eth28[0x1600]=0
CLMIB_RVERIFY.eth29[0x1600]=0
CLMIB_RVERIFY.eth30[0x1600]=0
CLMIB_RVERIFY.eth31[0x1600]=0
CLMIB_RVERIFY.eth32[0x1600]=0
CLMIB_RVLN.eth1[0x1f00]=0x2e325b14b
CLMIB_RVLN.eth2[0x1f00]=0x1352b383d
CLMIB_RVLN.eth3[0x1f00]=0x337e0c202
CLMIB_RVLN.eth4[0x1f00]=0x1c3bf6394
CLMIB_RVLN.eth5[0x1f00]=0
CLMIB_RVLN.eth6[0x1f00]=0
CLMIB_RVLN.eth7[0x1f00]=0
CLMIB_RVLN.eth8[0x1f00]=0
CLMIB_RVLN.eth9[0x1f00]=0
CLMIB_RVLN.eth10[0x1f00]=0
CLMIB_RVLN.eth11[0x1f00]=0
CLMIB_RVLN.eth12[0x1f00]=0
CLMIB_RVLN.eth13[0x1f00]=0
CLMIB_RVLN.eth14[0x1f00]=0
CLMIB_RVLN.eth15[0x1f00]=0
CLMIB_RVLN.eth16[0x1f00]=0
CLMIB_RVLN.eth17[0x1f00]=0
CLMIB_RVLN.eth18[0x1f00]=0
CLMIB_RVLN.eth19[0x1f00]=0
CLMIB_RVLN.eth20[0x1f00]=0
CLMIB_RVLN.eth21[0x1f00]=0
CLMIB_RVLN.eth22[0x1f00]=0
CLMIB_RVLN.eth23[0x1f00]=0
CLMIB_RVLN.eth24[0x1f00]=0
CLMIB_RVLN.eth25[0x1f00]=0
CLMIB_RVLN.eth26[0x1f00]=0
CLMIB_RVLN.eth27[0x1f00]=0
CLMIB_RVLN.eth28[0x1f00]=0
CLMIB_RVLN.eth29[0x1f00]=0
CLMIB_RVLN.eth30[0x1f00]=0
CLMIB_RVLN.eth31[0x1f00]=0
CLMIB_RVLN.eth32[0x1f00]=0x12ac349c9b
CLMIB_RXCF.eth1[0x1000]=0
CLMIB_RXCF.eth2[0x1000]=0
CLMIB_RXCF.eth3[0x1000]=0
CLMIB_RXCF.eth4[0x1000]=0
CLMIB_RXCF.eth5[0x1000]=0
CLMIB_RXCF.eth6[0x1000]=0
CLMIB_RXCF.eth7[0x1000]=0
CLMIB_RXCF.eth8[0x1000]=0
CLMIB_RXCF.eth9[0x1000]=0
CLMIB_RXCF.eth10[0x1000]=0
CLMIB_RXCF.eth11[0x1000]=0
CLMIB_RXCF.eth12[0x1000]=0
CLMIB_RXCF.eth13[0x1000]=0
CLMIB_RXCF.eth14[0x1000]=0
CLMIB_RXCF.eth15[0x1000]=0
CLMIB_RXCF.eth16[0x1000]=0
CLMIB_RXCF.eth17[0x1000]=0
CLMIB_RXCF.eth18[0x1000]=0
CLMIB_RXCF.eth19[0x1000]=0
CLMIB_RXCF.eth20[0x1000]=0
CLMIB_RXCF.eth21[0x1000]=0
CLMIB_RXCF.eth22[0x1000]=0
CLMIB_RXCF.eth23[0x1000]=0
CLMIB_RXCF.eth24[0x1000]=0
CLMIB_RXCF.eth25[0x1000]=0
CLMIB_RXCF.eth26[0x1000]=0
CLMIB_RXCF.eth27[0x1000]=0
CLMIB_RXCF.eth28[0x1000]=0
CLMIB_RXCF.eth29[0x1000]=0
CLMIB_RXCF.eth30[0x1000]=0
CLMIB_RXCF.eth31[0x1000]=0
CLMIB_RXCF.eth32[0x1000]=0
CLMIB_RXPF.eth1[0x1100]=0
CLMIB_RXPF.eth2[0x1100]=0
CLMIB_RXPF.eth3[0x1100]=0
CLMIB_RXPF.eth4[0x1100]=0
CLMIB_RXPF.eth5[0x1100]=0
CLMIB_RXPF.eth6[0x1100]=0
CLMIB_RXPF.eth7[0x1100]=0
CLMIB_RXPF.eth8[0x1100]=0
CLMIB_RXPF.eth9[0x1100]=0
CLMIB_RXPF.eth10[0x1100]=0
CLMIB_RXPF.eth11[0x1100]=0
CLMIB_RXPF.eth12[0x1100]=0
CLMIB_RXPF.eth13[0x1100]=0
CLMIB_RXPF.eth14[0x1100]=0
CLMIB_RXPF.eth15[0x1100]=0
CLMIB_RXPF.eth16[0x1100]=0
CLMIB_RXPF.eth17[0x1100]=0
CLMIB_RXPF.eth18[0x1100]=0
CLMIB_RXPF.eth19[0x1100]=0
CLMIB_RXPF.eth20[0x1100]=0
CLMIB_RXPF.eth21[0x1100]=0
CLMIB_RXPF.eth22[0x1100]=0
CLMIB_RXPF.eth23[0x1100]=0
CLMIB_RXPF.eth24[0x1100]=0
CLMIB_RXPF.eth25[0x1100]=0
CLMIB_RXPF.eth26[0x1100]=0
CLMIB_RXPF.eth27[0x1100]=0
CLMIB_RXPF.eth28[0x1100]=0
CLMIB_RXPF.eth29[0x1100]=0
CLMIB_RXPF.eth30[0x1100]=0
CLMIB_RXPF.eth31[0x1100]=0
CLMIB_RXPF.eth32[0x1100]=0
CLMIB_RXPP.eth1[0x1200]=0
CLMIB_RXPP.eth2[0x1200]=0
CLMIB_RXPP.eth3[0x1200]=0
CLMIB_RXPP.eth4[0x1200]=0
CLMIB_RXPP.eth5[0x1200]=0
CLMIB_RXPP.eth6[0x1200]=0
CLMIB_RXPP.eth7[0x1200]=0
CLMIB_RXPP.eth8[0x1200]=0
CLMIB_RXPP.eth9[0x1200]=0
CLMIB_RXPP.eth10[0x1200]=0
CLMIB_RXPP.eth11[0x1200]=0
CLMIB_RXPP.eth12[0x1200]=0
CLMIB_RXPP.eth13[0x1200]=0
CLMIB_RXPP.eth14[0x1200]=0
CLMIB_RXPP.eth15[0x1200]=0
CLMIB_RXPP.eth16[0x1200]=0
CLMIB_RXPP.eth17[0x1200]=0
CLMIB_RXPP.eth18[0x1200]=0
CLMIB_RXPP.eth19[0x1200]=0
CLMIB_RXPP.eth20[0x1200]=0
CLMIB_RXPP.eth21[0x1200]=0
CLMIB_RXPP.eth22[0x1200]=0
CLMIB_RXPP.eth23[0x1200]=0
CLMIB_RXPP.eth24[0x1200]=0
CLMIB_RXPP.eth25[0x1200]=0
CLMIB_RXPP.eth26[0x1200]=0
CLMIB_RXPP.eth27[0x1200]=0
CLMIB_RXPP.eth28[0x1200]=0
CLMIB_RXPP.eth29[0x1200]=0
CLMIB_RXPP.eth30[0x1200]=0
CLMIB_RXPP.eth31[0x1200]=0
CLMIB_RXPP.eth32[0x1200]=0
CLMIB_RXUDA.eth1[0x1400]=0
CLMIB_RXUDA.eth2[0x1400]=0
CLMIB_RXUDA.eth3[0x1400]=0
CLMIB_RXUDA.eth4[0x1400]=0
CLMIB_RXUDA.eth5[0x1400]=0
CLMIB_RXUDA.eth6[0x1400]=0
CLMIB_RXUDA.eth7[0x1400]=0
CLMIB_RXUDA.eth8[0x1400]=0
CLMIB_RXUDA.eth9[0x1400]=0
CLMIB_RXUDA.eth10[0x1400]=0
CLMIB_RXUDA.eth11[0x1400]=0
CLMIB_RXUDA.eth12[0x1400]=0
CLMIB_RXUDA.eth13[0x1400]=0
CLMIB_RXUDA.eth14[0x1400]=0
CLMIB_RXUDA.eth15[0x1400]=0
CLMIB_RXUDA.eth16[0x1400]=0
CLMIB_RXUDA.eth17[0x1400]=0
CLMIB_RXUDA.eth18[0x1400]=0
CLMIB_RXUDA.eth19[0x1400]=0
CLMIB_RXUDA.eth20[0x1400]=0
CLMIB_RXUDA.eth21[0x1400]=0
CLMIB_RXUDA.eth22[0x1400]=0
CLMIB_RXUDA.eth23[0x1400]=0
CLMIB_RXUDA.eth24[0x1400]=0
CLMIB_RXUDA.eth25[0x1400]=0
CLMIB_RXUDA.eth26[0x1400]=0
CLMIB_RXUDA.eth27[0x1400]=0
CLMIB_RXUDA.eth28[0x1400]=0
CLMIB_RXUDA.eth29[0x1400]=0
CLMIB_RXUDA.eth30[0x1400]=0
CLMIB_RXUDA.eth31[0x1400]=0
CLMIB_RXUDA.eth32[0x1400]=0
CLMIB_RXUO.eth1[0x1300]=0
CLMIB_RXUO.eth2[0x1300]=0
CLMIB_RXUO.eth3[0x1300]=0
CLMIB_RXUO.eth4[0x1300]=0
CLMIB_RXUO.eth5[0x1300]=0
CLMIB_RXUO.eth6[0x1300]=0
CLMIB_RXUO.eth7[0x1300]=0
CLMIB_RXUO.eth8[0x1300]=0
CLMIB_RXUO.eth9[0x1300]=0
CLMIB_RXUO.eth10[0x1300]=0
CLMIB_RXUO.eth11[0x1300]=0
CLMIB_RXUO.eth12[0x1300]=0
CLMIB_RXUO.eth13[0x1300]=0
CLMIB_RXUO.eth14[0x1300]=0
CLMIB_RXUO.eth15[0x1300]=0
CLMIB_RXUO.eth16[0x1300]=0
CLMIB_RXUO.eth17[0x1300]=0
CLMIB_RXUO.eth18[0x1300]=0
CLMIB_RXUO.eth19[0x1300]=0
CLMIB_RXUO.eth20[0x1300]=0
CLMIB_RXUO.eth21[0x1300]=0
CLMIB_RXUO.eth22[0x1300]=0
CLMIB_RXUO.eth23[0x1300]=0
CLMIB_RXUO.eth24[0x1300]=0
CLMIB_RXUO.eth25[0x1300]=0
CLMIB_RXUO.eth26[0x1300]=0
CLMIB_RXUO.eth27[0x1300]=0
CLMIB_RXUO.eth28[0x1300]=0
CLMIB_RXUO.eth29[0x1300]=0
CLMIB_RXUO.eth30[0x1300]=0
CLMIB_RXUO.eth31[0x1300]=0
CLMIB_RXUO.eth32[0x1300]=0
CLMIB_RXWSA.eth1[0x1500]=0
CLMIB_RXWSA.eth2[0x1500]=0
CLMIB_RXWSA.eth3[0x1500]=0
CLMIB_RXWSA.eth4[0x1500]=0
CLMIB_RXWSA.eth5[0x1500]=0
CLMIB_RXWSA.eth6[0x1500]=0
CLMIB_RXWSA.eth7[0x1500]=0
CLMIB_RXWSA.eth8[0x1500]=0
CLMIB_RXWSA.eth9[0x1500]=0
CLMIB_RXWSA.eth10[0x1500]=0
CLMIB_RXWSA.eth11[0x1500]=0
CLMIB_RXWSA.eth12[0x1500]=0
CLMIB_RXWSA.eth13[0x1500]=0
CLMIB_RXWSA.eth14[0x1500]=0
CLMIB_RXWSA.eth15[0x1500]=0
CLMIB_RXWSA.eth16[0x1500]=0
CLMIB_RXWSA.eth17[0x1500]=0
CLMIB_RXWSA.eth18[0x1500]=0
CLMIB_RXWSA.eth19[0x1500]=0
CLMIB_RXWSA.eth20[0x1500]=0
CLMIB_RXWSA.eth21[0x1500]=0
CLMIB_RXWSA.eth22[0x1500]=0
CLMIB_RXWSA.eth23[0x1500]=0
CLMIB_RXWSA.eth24[0x1500]=0
CLMIB_RXWSA.eth25[0x1500]=0
CLMIB_RXWSA.eth26[0x1500]=0
CLMIB_RXWSA.eth27[0x1500]=0
CLMIB_RXWSA.eth28[0x1500]=0
CLMIB_RXWSA.eth29[0x1500]=0
CLMIB_RXWSA.eth30[0x1500]=0
CLMIB_RXWSA.eth31[0x1500]=0
CLMIB_RXWSA.eth32[0x1500]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth1[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth2[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth3[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth4[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth5[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth6[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth7[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth8[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth9[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth10[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth11[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth12[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth13[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth14[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth15[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth16[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth17[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth18[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth19[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth20[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth21[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth22[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth23[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth24[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth25[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth26[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth27[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth28[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth29[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth30[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth31[0x3700]=0
CLMIB_RX_EEE_LPI_DURATION_COUNTER.eth32[0x3700]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth1[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth2[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth3[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth4[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth5[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth6[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth7[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth8[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth9[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth10[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth11[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth12[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth13[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth14[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth15[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth16[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth17[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth18[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth19[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth20[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth21[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth22[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth23[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth24[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth25[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth26[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth27[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth28[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth29[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth30[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth31[0x3600]=0
CLMIB_RX_EEE_LPI_EVENT_COUNTER.eth32[0x3600]=0
CLMIB_RX_HCFC_COUNTER.eth1[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth2[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth3[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth4[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth5[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth6[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth7[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth8[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth9[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth10[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth11[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth12[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth13[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth14[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth15[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth16[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth17[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth18[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth19[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth20[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth21[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth22[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth23[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth24[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth25[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth26[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth27[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth28[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth29[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth30[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth31[0x3b00]=0
CLMIB_RX_HCFC_COUNTER.eth32[0x3b00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth1[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth2[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth3[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth4[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth5[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth6[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth7[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth8[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth9[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth10[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth11[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth12[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth13[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth14[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth15[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth16[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth17[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth18[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth19[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth20[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth21[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth22[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth23[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth24[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth25[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth26[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth27[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth28[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth29[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth30[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth31[0x3c00]=0
CLMIB_RX_HCFC_CRC_COUNTER.eth32[0x3c00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth1[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth2[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth3[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth4[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth5[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth6[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth7[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth8[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth9[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth10[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth11[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth12[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth13[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth14[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth15[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth16[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth17[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth18[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth19[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth20[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth21[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth22[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth23[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth24[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth25[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth26[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth27[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth28[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth29[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth30[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth31[0x3a00]=0
CLMIB_RX_LLFC_CRC_COUNTER.eth32[0x3a00]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth1[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth2[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth3[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth4[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth5[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth6[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth7[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth8[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth9[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth10[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth11[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth12[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth13[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth14[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth15[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth16[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth17[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth18[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth19[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth20[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth21[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth22[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth23[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth24[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth25[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth26[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth27[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth28[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth29[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth30[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth31[0x3900]=0
CLMIB_RX_LLFC_LOG_COUNTER.eth32[0x3900]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth1[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth2[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth3[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth4[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth5[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth6[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth7[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth8[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth9[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth10[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth11[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth12[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth13[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth14[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth15[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth16[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth17[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth18[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth19[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth20[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth21[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth22[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth23[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth24[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth25[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth26[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth27[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth28[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth29[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth30[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth31[0x3800]=0
CLMIB_RX_LLFC_PHY_COUNTER.eth32[0x3800]=0
CLMIB_T64.eth1[0x4000]=0x154c8861
CLMIB_T64.eth2[0x4000]=0x1076a867
CLMIB_T64.eth3[0x4000]=0x25af2718
CLMIB_T64.eth4[0x4000]=0x12c21a71
CLMIB_T64.eth5[0x4000]=0
CLMIB_T64.eth6[0x4000]=0
CLMIB_T64.eth7[0x4000]=0
CLMIB_T64.eth8[0x4000]=0
CLMIB_T64.eth9[0x4000]=0
CLMIB_T64.eth10[0x4000]=0
CLMIB_T64.eth11[0x4000]=0
CLMIB_T64.eth12[0x4000]=0
CLMIB_T64.eth13[0x4000]=0
CLMIB_T64.eth14[0x4000]=0
CLMIB_T64.eth15[0x4000]=0
CLMIB_T64.eth16[0x4000]=0
CLMIB_T64.eth17[0x4000]=0
CLMIB_T64.eth18[0x4000]=0
CLMIB_T64.eth19[0x4000]=0
CLMIB_T64.eth20[0x4000]=0
CLMIB_T64.eth21[0x4000]=0
CLMIB_T64.eth22[0x4000]=0
CLMIB_T64.eth23[0x4000]=0
CLMIB_T64.eth24[0x4000]=0
CLMIB_T64.eth25[0x4000]=0
CLMIB_T64.eth26[0x4000]=0
CLMIB_T64.eth27[0x4000]=0
CLMIB_T64.eth28[0x4000]=0
CLMIB_T64.eth29[0x4000]=0
CLMIB_T64.eth30[0x4000]=0
CLMIB_T64.eth31[0x4000]=0
CLMIB_T64.eth32[0x4000]=0
CLMIB_T127.eth1[0x4100]=0xce88325b
CLMIB_T127.eth2[0x4100]=0x4df9f5ac
CLMIB_T127.eth3[0x4100]=0xdf64eb5a
CLMIB_T127.eth4[0x4100]=0x7822865a
CLMIB_T127.eth5[0x4100]=0
CLMIB_T127.eth6[0x4100]=0
CLMIB_T127.eth7[0x4100]=0
CLMIB_T127.eth8[0x4100]=0
CLMIB_T127.eth9[0x4100]=0
CLMIB_T127.eth10[0x4100]=0
CLMIB_T127.eth11[0x4100]=0
CLMIB_T127.eth12[0x4100]=0
CLMIB_T127.eth13[0x4100]=0
CLMIB_T127.eth14[0x4100]=0
CLMIB_T127.eth15[0x4100]=0
CLMIB_T127.eth16[0x4100]=0
CLMIB_T127.eth17[0x4100]=0
CLMIB_T127.eth18[0x4100]=0
CLMIB_T127.eth19[0x4100]=0
CLMIB_T127.eth20[0x4100]=0
CLMIB_T127.eth21[0x4100]=0
CLMIB_T127.eth22[0x4100]=0
CLMIB_T127.eth23[0x4100]=0
CLMIB_T127.eth24[0x4100]=0
CLMIB_T127.eth25[0x4100]=0
CLMIB_T127.eth26[0x4100]=0
CLMIB_T127.eth27[0x4100]=0
CLMIB_T127.eth28[0x4100]=0
CLMIB_T127.eth29[0x4100]=0
CLMIB_T127.eth30[0x4100]=0
CLMIB_T127.eth31[0x4100]=0
CLMIB_T127.eth32[0x4100]=0x5bef0c884
CLMIB_T255.eth1[0x4200]=0x15bd11e3
CLMIB_T255.eth2[0x4200]=0xfe0d3c6
CLMIB_T255.eth3[0x4200]=0x26e67458
CLMIB_T255.eth4[0x4200]=0x203cd8b0
CLMIB_T255.eth5[0x4200]=0
CLMIB_T255.eth6[0x4200]=0
CLMIB_T255.eth7[0x4200]=0
CLMIB_T255.eth8[0x4200]=0
CLMIB_T255.eth9[0x4200]=0
CLMIB_T255.eth10[0x4200]=0
CLMIB_T255.eth11[0x4200]=0
CLMIB_T255.eth12[0x4200]=0
CLMIB_T255.eth13[0x4200]=0
CLMIB_T255.eth14[0x4200]=0
CLMIB_T255.eth15[0x4200]=0
CLMIB_T255.eth16[0x4200]=0
CLMIB_T255.eth17[0x4200]=0
CLMIB_T255.eth18[0x4200]=0
CLMIB_T255.eth19[0x4200]=0
CLMIB_T255.eth20[0x4200]=0
CLMIB_T255.eth21[0x4200]=0
CLMIB_T255.eth22[0x4200]=0
CLMIB_T255.eth23[0x4200]=0
CLMIB_T255.eth24[0x4200]=0
CLMIB_T255.eth25[0x4200]=0
CLMIB_T255.eth26[0x4200]=0
CLMIB_T255.eth27[0x4200]=0
CLMIB_T255.eth28[0x4200]=0
CLMIB_T255.eth29[0x4200]=0
CLMIB_T255.eth30[0x4200]=0
CLMIB_T255.eth31[0x4200]=0
CLMIB_T255.eth32[0x4200]=0x9a88eed2
CLMIB_T511.eth1[0x4300]=0x10a4d66f
CLMIB_T511.eth2[0x4300]=0x9d20833
CLMIB_T511.eth3[0x4300]=0x1a8c83cb
CLMIB_T511.eth4[0x4300]=0x12cbc58f
CLMIB_T511.eth5[0x4300]=0
CLMIB_T511.eth6[0x4300]=0
CLMIB_T511.eth7[0x4300]=0
CLMIB_T511.eth8[0x4300]=0
CLMIB_T511.eth9[0x4300]=0
CLMIB_T511.eth10[0x4300]=0
CLMIB_T511.eth11[0x4300]=0
CLMIB_T511.eth12[0x4300]=0
CLMIB_T511.eth13[0x4300]=0
CLMIB_T511.eth14[0x4300]=0
CLMIB_T511.eth15[0x4300]=0
CLMIB_T511.eth16[0x4300]=0
CLMIB_T511.eth17[0x4300]=0
CLMIB_T511.eth18[0x4300]=0
CLMIB_T511.eth19[0x4300]=0
CLMIB_T511.eth20[0x4300]=0
CLMIB_T511.eth21[0x4300]=0
CLMIB_T511.eth22[0x4300]=0
CLMIB_T511.eth23[0x4300]=0
CLMIB_T511.eth24[0x4300]=0
CLMIB_T511.eth25[0x4300]=0
CLMIB_T511.eth26[0x4300]=0
CLMIB_T511.eth27[0x4300]=0
CLMIB_T511.eth28[0x4300]=0
CLMIB_T511.eth29[0x4300]=0
CLMIB_T511.eth30[0x4300]=0
CLMIB_T511.eth31[0x4300]=0
CLMIB_T511.eth32[0x4300]=0x63107731
CLMIB_T1023.eth1[0x4400]=0x17ad8045
CLMIB_T1023.eth2[0x4400]=0xc3c04d8
CLMIB_T1023.eth3[0x4400]=0x21a3cdeb
CLMIB_T1023.eth4[0x4400]=0x1de99933
CLMIB_T1023.eth5[0x4400]=0
CLMIB_T1023.eth6[0x4400]=0
CLMIB_T1023.eth7[0x4400]=0
CLMIB_T1023.eth8[0x4400]=0
CLMIB_T1023.eth9[0x4400]=0
CLMIB_T1023.eth10[0x4400]=0
CLMIB_T1023.eth11[0x4400]=0
CLMIB_T1023.eth12[0x4400]=0
CLMIB_T1023.eth13[0x4400]=0
CLMIB_T1023.eth14[0x4400]=0
CLMIB_T1023.eth15[0x4400]=0
CLMIB_T1023.eth16[0x4400]=0
CLMIB_T1023.eth17[0x4400]=0
CLMIB_T1023.eth18[0x4400]=0
CLMIB_T1023.eth19[0x4400]=0
CLMIB_T1023.eth20[0x4400]=0
CLMIB_T1023.eth21[0x4400]=0
CLMIB_T1023.eth22[0x4400]=0
CLMIB_T1023.eth23[0x4400]=0
CLMIB_T1023.eth24[0x4400]=0
CLMIB_T1023.eth25[0x4400]=0
CLMIB_T1023.eth26[0x4400]=0
CLMIB_T1023.eth27[0x4400]=0
CLMIB_T1023.eth28[0x4400]=0
CLMIB_T1023.eth29[0x4400]=0
CLMIB_T1023.eth30[0x4400]=0
CLMIB_T1023.eth31[0x4400]=0
CLMIB_T1023.eth32[0x4400]=0x3d36072b
CLMIB_T1518.eth1[0x4500]=0x2bcf36ee2
CLMIB_T1518.eth2[0x4500]=0x154d48cf5
CLMIB_T1518.eth3[0x4500]=0x2b0fe263b
CLMIB_T1518.eth4[0x4500]=0x127164d39
CLMIB_T1518.eth5[0x4500]=0
CLMIB_T1518.eth6[0x4500]=0
CLMIB_T1518.eth7[0x4500]=0
CLMIB_T1518.eth8[0x4500]=0
CLMIB_T1518.eth9[0x4500]=0
CLMIB_T1518.eth10[0x4500]=0
CLMIB_T1518.eth11[0x4500]=0
CLMIB_T1518.eth12[0x4500]=0
CLMIB_T1518.eth13[0x4500]=0
CLMIB_T1518.eth14[0x4500]=0
CLMIB_T1518.eth15[0x4500]=0
CLMIB_T1518.eth16[0x4500]=0
CLMIB_T1518.eth17[0x4500]=0
CLMIB_T1518.eth18[0x4500]=0
CLMIB_T1518.eth19[0x4500]=0
CLMIB_T1518.eth20[0x4500]=0
CLMIB_T1518.eth21[0x4500]=0
CLMIB_T1518.eth22[0x4500]=0
CLMIB_T1518.eth23[0x4500]=0
CLMIB_T1518.eth24[0x4500]=0
CLMIB_T1518.eth25[0x4500]=0
CLMIB_T1518.eth26[0x4500]=0
CLMIB_T1518.eth27[0x4500]=0
CLMIB_T1518.eth28[0x4500]=0
CLMIB_T1518.eth29[0x4500]=0
CLMIB_T1518.eth30[0x4500]=0
CLMIB_T1518.eth31[0x4500]=0
CLMIB_T1518.eth32[0x4500]=0x18517329f
CLMIB_T2047.eth1[0x4700]=0x1fcafee47
CLMIB_T2047.eth2[0x4700]=0xe16a9cef
CLMIB_T2047.eth3[0x4700]=0x2d93f7093
CLMIB_T2047.eth4[0x4700]=0x13a826453
CLMIB_T2047.eth5[0x4700]=0
CLMIB_T2047.eth6[0x4700]=0
CLMIB_T2047.eth7[0x4700]=0
CLMIB_T2047.eth8[0x4700]=0
CLMIB_T2047.eth9[0x4700]=0
CLMIB_T2047.eth10[0x4700]=0
CLMIB_T2047.eth11[0x4700]=0
CLMIB_T2047.eth12[0x4700]=0
CLMIB_T2047.eth13[0x4700]=0
CLMIB_T2047.eth14[0x4700]=0
CLMIB_T2047.eth15[0x4700]=0
CLMIB_T2047.eth16[0x4700]=0
CLMIB_T2047.eth17[0x4700]=0
CLMIB_T2047.eth18[0x4700]=0
CLMIB_T2047.eth19[0x4700]=0
CLMIB_T2047.eth20[0x4700]=0
CLMIB_T2047.eth21[0x4700]=0
CLMIB_T2047.eth22[0x4700]=0
CLMIB_T2047.eth23[0x4700]=0
CLMIB_T2047.eth24[0x4700]=0
CLMIB_T2047.eth25[0x4700]=0
CLMIB_T2047.eth26[0x4700]=0
CLMIB_T2047.eth27[0x4700]=0
CLMIB_T2047.eth28[0x4700]=0
CLMIB_T2047.eth29[0x4700]=0
CLMIB_T2047.eth30[0x4700]=0
CLMIB_T2047.eth31[0x4700]=0
CLMIB_T2047.eth32[0x4700]=0x7839e7d1
CLMIB_T4095.eth1[0x4800]=0
CLMIB_T4095.eth2[0x4800]=0
CLMIB_T4095.eth3[0x4800]=0
CLMIB_T4095.eth4[0x4800]=0
CLMIB_T4095.eth5[0x4800]=0
CLMIB_T4095.eth6[0x4800]=0
CLMIB_T4095.eth7[0x4800]=0
CLMIB_T4095.eth8[0x4800]=0
CLMIB_T4095.eth9[0x4800]=0
CLMIB_T4095.eth10[0x4800]=0
CLMIB_T4095.eth11[0x4800]=0
CLMIB_T4095.eth12[0x4800]=0
CLMIB_T4095.eth13[0x4800]=0
CLMIB_T4095.eth14[0x4800]=0
CLMIB_T4095.eth15[0x4800]=0
CLMIB_T4095.eth16[0x4800]=0
CLMIB_T4095.eth17[0x4800]=0
CLMIB_T4095.eth18[0x4800]=0
CLMIB_T4095.eth19[0x4800]=0
CLMIB_T4095.eth20[0x4800]=0
CLMIB_T4095.eth21[0x4800]=0
CLMIB_T4095.eth22[0x4800]=0
CLMIB_T4095.eth23[0x4800]=0
CLMIB_T4095.eth24[0x4800]=0
CLMIB_T4095.eth25[0x4800]=0
CLMIB_T4095.eth26[0x4800]=0
CLMIB_T4095.eth27[0x4800]=0
CLMIB_T4095.eth28[0x4800]=0
CLMIB_T4095.eth29[0x4800]=0
CLMIB_T4095.eth30[0x4800]=0
CLMIB_T4095.eth31[0x4800]=0
CLMIB_T4095.eth32[0x4800]=0
CLMIB_T9216.eth1[0x4900]=0
CLMIB_T9216.eth2[0x4900]=0
CLMIB_T9216.eth3[0x4900]=0
CLMIB_T9216.eth4[0x4900]=0
CLMIB_T9216.eth5[0x4900]=0
CLMIB_T9216.eth6[0x4900]=0
CLMIB_T9216.eth7[0x4900]=0
CLMIB_T9216.eth8[0x4900]=0
CLMIB_T9216.eth9[0x4900]=0
CLMIB_T9216.eth10[0x4900]=0
CLMIB_T9216.eth11[0x4900]=0
CLMIB_T9216.eth12[0x4900]=0
CLMIB_T9216.eth13[0x4900]=0
CLMIB_T9216.eth14[0x4900]=0
CLMIB_T9216.eth15[0x4900]=0
CLMIB_T9216.eth16[0x4900]=0
CLMIB_T9216.eth17[0x4900]=0
CLMIB_T9216.eth18[0x4900]=0
CLMIB_T9216.eth19[0x4900]=0
CLMIB_T9216.eth20[0x4900]=0
CLMIB_T9216.eth21[0x4900]=0
CLMIB_T9216.eth22[0x4900]=0
CLMIB_T9216.eth23[0x4900]=0
CLMIB_T9216.eth24[0x4900]=0
CLMIB_T9216.eth25[0x4900]=0
CLMIB_T9216.eth26[0x4900]=0
CLMIB_T9216.eth27[0x4900]=0
CLMIB_T9216.eth28[0x4900]=0
CLMIB_T9216.eth29[0x4900]=0
CLMIB_T9216.eth30[0x4900]=0
CLMIB_T9216.eth31[0x4900]=0
CLMIB_T9216.eth32[0x4900]=0
CLMIB_T16383.eth1[0x4a00]=0
CLMIB_T16383.eth2[0x4a00]=0
CLMIB_T16383.eth3[0x4a00]=0
CLMIB_T16383.eth4[0x4a00]=0
CLMIB_T16383.eth5[0x4a00]=0
CLMIB_T16383.eth6[0x4a00]=0
CLMIB_T16383.eth7[0x4a00]=0
CLMIB_T16383.eth8[0x4a00]=0
CLMIB_T16383.eth9[0x4a00]=0
CLMIB_T16383.eth10[0x4a00]=0
CLMIB_T16383.eth11[0x4a00]=0
CLMIB_T16383.eth12[0x4a00]=0
CLMIB_T16383.eth13[0x4a00]=0
CLMIB_T16383.eth14[0x4a00]=0
CLMIB_T16383.eth15[0x4a00]=0
CLMIB_T16383.eth16[0x4a00]=0
CLMIB_T16383.eth17[0x4a00]=0
CLMIB_T16383.eth18[0x4a00]=0
CLMIB_T16383.eth19[0x4a00]=0
CLMIB_T16383.eth20[0x4a00]=0
CLMIB_T16383.eth21[0x4a00]=0
CLMIB_T16383.eth22[0x4a00]=0
CLMIB_T16383.eth23[0x4a00]=0
CLMIB_T16383.eth24[0x4a00]=0
CLMIB_T16383.eth25[0x4a00]=0
CLMIB_T16383.eth26[0x4a00]=0
CLMIB_T16383.eth27[0x4a00]=0
CLMIB_T16383.eth28[0x4a00]=0
CLMIB_T16383.eth29[0x4a00]=0
CLMIB_T16383.eth30[0x4a00]=0
CLMIB_T16383.eth31[0x4a00]=0
CLMIB_T16383.eth32[0x4a00]=0
CLMIB_TBCA.eth1[0x4f00]=0x28e663
CLMIB_TBCA.eth2[0x4f00]=0x20fc81
CLMIB_TBCA.eth3[0x4f00]=0x2785d8
CLMIB_TBCA.eth4[0x4f00]=0x3401bb
CLMIB_TBCA.eth5[0x4f00]=0
CLMIB_TBCA.eth6[0x4f00]=0
CLMIB_TBCA.eth7[0x4f00]=0
CLMIB_TBCA.eth8[0x4f00]=0
CLMIB_TBCA.eth9[0x4f00]=0
CLMIB_TBCA.eth10[0x4f00]=0
CLMIB_TBCA.eth11[0x4f00]=0
CLMIB_TBCA.eth12[0x4f00]=0
CLMIB_TBCA.eth13[0x4f00]=0
CLMIB_TBCA.eth14[0x4f00]=0
CLMIB_TBCA.eth15[0x4f00]=0
CLMIB_TBCA.eth16[0x4f00]=0
CLMIB_TBCA.eth17[0x4f00]=0
CLMIB_TBCA.eth18[0x4f00]=0
CLMIB_TBCA.eth19[0x4f00]=0
CLMIB_TBCA.eth20[0x4f00]=0
CLMIB_TBCA.eth21[0x4f00]=0
CLMIB_TBCA.eth22[0x4f00]=0
CLMIB_TBCA.eth23[0x4f00]=0
CLMIB_TBCA.eth24[0x4f00]=0
CLMIB_TBCA.eth25[0x4f00]=0
CLMIB_TBCA.eth26[0x4f00]=0
CLMIB_TBCA.eth27[0x4f00]=0
CLMIB_TBCA.eth28[0x4f00]=0
CLMIB_TBCA.eth29[0x4f00]=0
CLMIB_TBCA.eth30[0x4f00]=0
CLMIB_TBCA.eth31[0x4f00]=0
CLMIB_TBCA.eth32[0x4f00]=0x1490576
CLMIB_TBYT.eth1[0x6f00]=0x1c1a77293165
CLMIB_TBYT.eth2[0x6f00]=0xcfa266d8d93
CLMIB_TBYT.eth3[0x6f00]=0x20ea3dbedfd2
CLMIB_TBYT.eth4[0x6f00]=0xe8016d8ad31
CLMIB_TBYT.eth5[0x6f00]=0
CLMIB_TBYT.eth6[0x6f00]=0
CLMIB_TBYT.eth7[0x6f00]=0
CLMIB_TBYT.eth8[0x6f00]=0
CLMIB_TBYT.eth9[0x6f00]=0
CLMIB_TBYT.eth10[0x6f00]=0
CLMIB_TBYT.eth11[0x6f00]=0
CLMIB_TBYT.eth12[0x6f00]=0
CLMIB_TBYT.eth13[0x6f00]=0
CLMIB_TBYT.eth14[0x6f00]=0
CLMIB_TBYT.eth15[0x6f00]=0
CLMIB_TBYT.eth16[0x6f00]=0
CLMIB_TBYT.eth17[0x6f00]=0
CLMIB_TBYT.eth18[0x6f00]=0
CLMIB_TBYT.eth19[0x6f00]=0
CLMIB_TBYT.eth20[0x6f00]=0
CLMIB_TBYT.eth21[0x6f00]=0
CLMIB_TBYT.eth22[0x6f00]=0
CLMIB_TBYT.eth23[0x6f00]=0
CLMIB_TBYT.eth24[0x6f00]=0
CLMIB_TBYT.eth25[0x6f00]=0
CLMIB_TBYT.eth26[0x6f00]=0
CLMIB_TBYT.eth27[0x6f00]=0
CLMIB_TBYT.eth28[0x6f00]=0
CLMIB_TBYT.eth29[0x6f00]=0
CLMIB_TBYT.eth30[0x6f00]=0
CLMIB_TBYT.eth31[0x6f00]=0
CLMIB_TBYT.eth32[0x6f00]=0xeaa419da9ac
CLMIB_TDVLN.eth1[0x5f00]=0
CLMIB_TDVLN.eth2[0x5f00]=0
CLMIB_TDVLN.eth3[0x5f00]=0
CLMIB_TDVLN.eth4[0x5f00]=0
CLMIB_TDVLN.eth5[0x5f00]=0
CLMIB_TDVLN.eth6[0x5f00]=0
CLMIB_TDVLN.eth7[0x5f00]=0
CLMIB_TDVLN.eth8[0x5f00]=0
CLMIB_TDVLN.eth9[0x5f00]=0
CLMIB_TDVLN.eth10[0x5f00]=0
CLMIB_TDVLN.eth11[0x5f00]=0
CLMIB_TDVLN.eth12[0x5f00]=0
CLMIB_TDVLN.eth13[0x5f00]=0
CLMIB_TDVLN.eth14[0x5f00]=0
CLMIB_TDVLN.eth15[0x5f00]=0
CLMIB_TDVLN.eth16[0x5f00]=0
CLMIB_TDVLN.eth17[0x5f00]=0
CLMIB_TDVLN.eth18[0x5f00]=0
CLMIB_TDVLN.eth19[0x5f00]=0
CLMIB_TDVLN.eth20[0x5f00]=0
CLMIB_TDVLN.eth21[0x5f00]=0
CLMIB_TDVLN.eth22[0x5f00]=0
CLMIB_TDVLN.eth23[0x5f00]=0
CLMIB_TDVLN.eth24[0x5f00]=0
CLMIB_TDVLN.eth25[0x5f00]=0
CLMIB_TDVLN.eth26[0x5f00]=0
CLMIB_TDVLN.eth27[0x5f00]=0
CLMIB_TDVLN.eth28[0x5f00]=0
CLMIB_TDVLN.eth29[0x5f00]=0
CLMIB_TDVLN.eth30[0x5f00]=0
CLMIB_TDVLN.eth31[0x5f00]=0
CLMIB_TDVLN.eth32[0x5f00]=0
CLMIB_TERR.eth1[0x5d00]=0
CLMIB_TERR.eth2[0x5d00]=0
CLMIB_TERR.eth3[0x5d00]=0
CLMIB_TERR.eth4[0x5d00]=0
CLMIB_TERR.eth5[0x5d00]=0
CLMIB_TERR.eth6[0x5d00]=0
CLMIB_TERR.eth7[0x5d00]=0
CLMIB_TERR.eth8[0x5d00]=0
CLMIB_TERR.eth9[0x5d00]=0
CLMIB_TERR.eth10[0x5d00]=0
CLMIB_TERR.eth11[0x5d00]=0
CLMIB_TERR.eth12[0x5d00]=0
CLMIB_TERR.eth13[0x5d00]=0
CLMIB_TERR.eth14[0x5d00]=0
CLMIB_TERR.eth15[0x5d00]=0
CLMIB_TERR.eth16[0x5d00]=0
CLMIB_TERR.eth17[0x5d00]=0
CLMIB_TERR.eth18[0x5d00]=0
CLMIB_TERR.eth19[0x5d00]=0
CLMIB_TERR.eth20[0x5d00]=0
CLMIB_TERR.eth21[0x5d00]=0
CLMIB_TERR.eth22[0x5d00]=0
CLMIB_TERR.eth23[0x5d00]=0
CLMIB_TERR.eth24[0x5d00]=0
CLMIB_TERR.eth25[0x5d00]=0
CLMIB_TERR.eth26[0x5d00]=0
CLMIB_TERR.eth27[0x5d00]=0
CLMIB_TERR.eth28[0x5d00]=0
CLMIB_TERR.eth29[0x5d00]=0
CLMIB_TERR.eth30[0x5d00]=0
CLMIB_TERR.eth31[0x5d00]=0
CLMIB_TERR.eth32[0x5d00]=0
CLMIB_TFCS.eth1[0x5300]=0
CLMIB_TFCS.eth2[0x5300]=0
CLMIB_TFCS.eth3[0x5300]=0
CLMIB_TFCS.eth4[0x5300]=0
CLMIB_TFCS.eth5[0x5300]=0
CLMIB_TFCS.eth6[0x5300]=0
CLMIB_TFCS.eth7[0x5300]=0
CLMIB_TFCS.eth8[0x5300]=0
CLMIB_TFCS.eth9[0x5300]=0
CLMIB_TFCS.eth10[0x5300]=0
CLMIB_TFCS.eth11[0x5300]=0
CLMIB_TFCS.eth12[0x5300]=0
CLMIB_TFCS.eth13[0x5300]=0
CLMIB_TFCS.eth14[0x5300]=0
CLMIB_TFCS.eth15[0x5300]=0
CLMIB_TFCS.eth16[0x5300]=0
CLMIB_TFCS.eth17[0x5300]=0
CLMIB_TFCS.eth18[0x5300]=0
CLMIB_TFCS.eth19[0x5300]=0
CLMIB_TFCS.eth20[0x5300]=0
CLMIB_TFCS.eth21[0x5300]=0
CLMIB_TFCS.eth22[0x5300]=0
CLMIB_TFCS.eth23[0x5300]=0
CLMIB_TFCS.eth24[0x5300]=0
CLMIB_TFCS.eth25[0x5300]=0
CLMIB_TFCS.eth26[0x5300]=0
CLMIB_TFCS.eth27[0x5300]=0
CLMIB_TFCS.eth28[0x5300]=0
CLMIB_TFCS.eth29[0x5300]=0
CLMIB_TFCS.eth30[0x5300]=0
CLMIB_TFCS.eth31[0x5300]=0
CLMIB_TFCS.eth32[0x5300]=0
CLMIB_TFRG.eth1[0x5c00]=0
CLMIB_TFRG.eth2[0x5c00]=0
CLMIB_TFRG.eth3[0x5c00]=0
CLMIB_TFRG.eth4[0x5c00]=0
CLMIB_TFRG.eth5[0x5c00]=0
CLMIB_TFRG.eth6[0x5c00]=0
CLMIB_TFRG.eth7[0x5c00]=0
CLMIB_TFRG.eth8[0x5c00]=0
CLMIB_TFRG.eth9[0x5c00]=0
CLMIB_TFRG.eth10[0x5c00]=0
CLMIB_TFRG.eth11[0x5c00]=0
CLMIB_TFRG.eth12[0x5c00]=0
CLMIB_TFRG.eth13[0x5c00]=0
CLMIB_TFRG.eth14[0x5c00]=0
CLMIB_TFRG.eth15[0x5c00]=0
CLMIB_TFRG.eth16[0x5c00]=0
CLMIB_TFRG.eth17[0x5c00]=0
CLMIB_TFRG.eth18[0x5c00]=0
CLMIB_TFRG.eth19[0x5c00]=0
CLMIB_TFRG.eth20[0x5c00]=0
CLMIB_TFRG.eth21[0x5c00]=0
CLMIB_TFRG.eth22[0x5c00]=0
CLMIB_TFRG.eth23[0x5c00]=0
CLMIB_TFRG.eth24[0x5c00]=0
CLMIB_TFRG.eth25[0x5c00]=0
CLMIB_TFRG.eth26[0x5c00]=0
CLMIB_TFRG.eth27[0x5c00]=0
CLMIB_TFRG.eth28[0x5c00]=0
CLMIB_TFRG.eth29[0x5c00]=0
CLMIB_TFRG.eth30[0x5c00]=0
CLMIB_TFRG.eth31[0x5c00]=0
CLMIB_TFRG.eth32[0x5c00]=0
CLMIB_TJBR.eth1[0x5200]=0
CLMIB_TJBR.eth2[0x5200]=0
CLMIB_TJBR.eth3[0x5200]=0
CLMIB_TJBR.eth4[0x5200]=0
CLMIB_TJBR.eth5[0x5200]=0
CLMIB_TJBR.eth6[0x5200]=0
CLMIB_TJBR.eth7[0x5200]=0
CLMIB_TJBR.eth8[0x5200]=0
CLMIB_TJBR.eth9[0x5200]=0
CLMIB_TJBR.eth10[0x5200]=0
CLMIB_TJBR.eth11[0x5200]=0
CLMIB_TJBR.eth12[0x5200]=0
CLMIB_TJBR.eth13[0x5200]=0
CLMIB_TJBR.eth14[0x5200]=0
CLMIB_TJBR.eth15[0x5200]=0
CLMIB_TJBR.eth16[0x5200]=0
CLMIB_TJBR.eth17[0x5200]=0
CLMIB_TJBR.eth18[0x5200]=0
CLMIB_TJBR.eth19[0x5200]=0
CLMIB_TJBR.eth20[0x5200]=0
CLMIB_TJBR.eth21[0x5200]=0
CLMIB_TJBR.eth22[0x5200]=0
CLMIB_TJBR.eth23[0x5200]=0
CLMIB_TJBR.eth24[0x5200]=0
CLMIB_TJBR.eth25[0x5200]=0
CLMIB_TJBR.eth26[0x5200]=0
CLMIB_TJBR.eth27[0x5200]=0
CLMIB_TJBR.eth28[0x5200]=0
CLMIB_TJBR.eth29[0x5200]=0
CLMIB_TJBR.eth30[0x5200]=0
CLMIB_TJBR.eth31[0x5200]=0
CLMIB_TJBR.eth32[0x5200]=0
CLMIB_TLCL.eth1[0x5a00]=0
CLMIB_TLCL.eth2[0x5a00]=0
CLMIB_TLCL.eth3[0x5a00]=0
CLMIB_TLCL.eth4[0x5a00]=0
CLMIB_TLCL.eth5[0x5a00]=0
CLMIB_TLCL.eth6[0x5a00]=0
CLMIB_TLCL.eth7[0x5a00]=0
CLMIB_TLCL.eth8[0x5a00]=0
CLMIB_TLCL.eth9[0x5a00]=0
CLMIB_TLCL.eth10[0x5a00]=0
CLMIB_TLCL.eth11[0x5a00]=0
CLMIB_TLCL.eth12[0x5a00]=0
CLMIB_TLCL.eth13[0x5a00]=0
CLMIB_TLCL.eth14[0x5a00]=0
CLMIB_TLCL.eth15[0x5a00]=0
CLMIB_TLCL.eth16[0x5a00]=0
CLMIB_TLCL.eth17[0x5a00]=0
CLMIB_TLCL.eth18[0x5a00]=0
CLMIB_TLCL.eth19[0x5a00]=0
CLMIB_TLCL.eth20[0x5a00]=0
CLMIB_TLCL.eth21[0x5a00]=0
CLMIB_TLCL.eth22[0x5a00]=0
CLMIB_TLCL.eth23[0x5a00]=0
CLMIB_TLCL.eth24[0x5a00]=0
CLMIB_TLCL.eth25[0x5a00]=0
CLMIB_TLCL.eth26[0x5a00]=0
CLMIB_TLCL.eth27[0x5a00]=0
CLMIB_TLCL.eth28[0x5a00]=0
CLMIB_TLCL.eth29[0x5a00]=0
CLMIB_TLCL.eth30[0x5a00]=0
CLMIB_TLCL.eth31[0x5a00]=0
CLMIB_TLCL.eth32[0x5a00]=0
CLMIB_TMCA.eth1[0x4e00]=0x17cb1a
CLMIB_TMCA.eth2[0x4e00]=0x17ca73
CLMIB_TMCA.eth3[0x4e00]=0x17cae6
CLMIB_TMCA.eth4[0x4e00]=0x17cab2
CLMIB_TMCA.eth5[0x4e00]=0
CLMIB_TMCA.eth6[0x4e00]=0
CLMIB_TMCA.eth7[0x4e00]=0
CLMIB_TMCA.eth8[0x4e00]=0
CLMIB_TMCA.eth9[0x4e00]=0
CLMIB_TMCA.eth10[0x4e00]=0
CLMIB_TMCA.eth11[0x4e00]=0
CLMIB_TMCA.eth12[0x4e00]=0
CLMIB_TMCA.eth13[0x4e00]=0
CLMIB_TMCA.eth14[0x4e00]=0
CLMIB_TMCA.eth15[0x4e00]=0
CLMIB_TMCA.eth16[0x4e00]=0
CLMIB_TMCA.eth17[0x4e00]=0
CLMIB_TMCA.eth18[0x4e00]=0
CLMIB_TMCA.eth19[0x4e00]=0
CLMIB_TMCA.eth20[0x4e00]=0
CLMIB_TMCA.eth21[0x4e00]=0
CLMIB_TMCA.eth22[0x4e00]=0
CLMIB_TMCA.eth23[0x4e00]=0
CLMIB_TMCA.eth24[0x4e00]=0
CLMIB_TMCA.eth25[0x4e00]=0
CLMIB_TMCA.eth26[0x4e00]=0
CLMIB_TMCA.eth27[0x4e00]=0
CLMIB_TMCA.eth28[0x4e00]=0
CLMIB_TMCA.eth29[0x4e00]=0
CLMIB_TMCA.eth30[0x4e00]=0
CLMIB_TMCA.eth31[0x4e00]=0
CLMIB_TMCA.eth32[0x4e00]=0x218855c
CLMIB_TMCL.eth1[0x5900]=0
CLMIB_TMCL.eth2[0x5900]=0
CLMIB_TMCL.eth3[0x5900]=0
CLMIB_TMCL.eth4[0x5900]=0
CLMIB_TMCL.eth5[0x5900]=0
CLMIB_TMCL.eth6[0x5900]=0
CLMIB_TMCL.eth7[0x5900]=0
CLMIB_TMCL.eth8[0x5900]=0
CLMIB_TMCL.eth9[0x5900]=0
CLMIB_TMCL.eth10[0x5900]=0
CLMIB_TMCL.eth11[0x5900]=0
CLMIB_TMCL.eth12[0x5900]=0
CLMIB_TMCL.eth13[0x5900]=0
CLMIB_TMCL.eth14[0x5900]=0
CLMIB_TMCL.eth15[0x5900]=0
CLMIB_TMCL.eth16[0x5900]=0
CLMIB_TMCL.eth17[0x5900]=0
CLMIB_TMCL.eth18[0x5900]=0
CLMIB_TMCL.eth19[0x5900]=0
CLMIB_TMCL.eth20[0x5900]=0
CLMIB_TMCL.eth21[0x5900]=0
CLMIB_TMCL.eth22[0x5900]=0
CLMIB_TMCL.eth23[0x5900]=0
CLMIB_TMCL.eth24[0x5900]=0
CLMIB_TMCL.eth25[0x5900]=0
CLMIB_TMCL.eth26[0x5900]=0
CLMIB_TMCL.eth27[0x5900]=0
CLMIB_TMCL.eth28[0x5900]=0
CLMIB_TMCL.eth29[0x5900]=0
CLMIB_TMCL.eth30[0x5900]=0
CLMIB_TMCL.eth31[0x5900]=0
CLMIB_TMCL.eth32[0x5900]=0
CLMIB_TMGV.eth1[0x4600]=0x1fcafee48
CLMIB_TMGV.eth2[0x4600]=0xe16a9e68
CLMIB_TMGV.eth3[0x4600]=0x2d93f711a
CLMIB_TMGV.eth4[0x4600]=0x13a8265a4
CLMIB_TMGV.eth5[0x4600]=0
CLMIB_TMGV.eth6[0x4600]=0
CLMIB_TMGV.eth7[0x4600]=0
CLMIB_TMGV.eth8[0x4600]=0
CLMIB_TMGV.eth9[0x4600]=0
CLMIB_TMGV.eth10[0x4600]=0
CLMIB_TMGV.eth11[0x4600]=0
CLMIB_TMGV.eth12[0x4600]=0
CLMIB_TMGV.eth13[0x4600]=0
CLMIB_TMGV.eth14[0x4600]=0
CLMIB_TMGV.eth15[0x4600]=0
CLMIB_TMGV.eth16[0x4600]=0
CLMIB_TMGV.eth17[0x4600]=0
CLMIB_TMGV.eth18[0x4600]=0
CLMIB_TMGV.eth19[0x4600]=0
CLMIB_TMGV.eth20[0x4600]=0
CLMIB_TMGV.eth21[0x4600]=0
CLMIB_TMGV.eth22[0x4600]=0
CLMIB_TMGV.eth23[0x4600]=0
CLMIB_TMGV.eth24[0x4600]=0
CLMIB_TMGV.eth25[0x4600]=0
CLMIB_TMGV.eth26[0x4600]=0
CLMIB_TMGV.eth27[0x4600]=0
CLMIB_TMGV.eth28[0x4600]=0
CLMIB_TMGV.eth29[0x4600]=0
CLMIB_TMGV.eth30[0x4600]=0
CLMIB_TMGV.eth31[0x4600]=0
CLMIB_TMGV.eth32[0x4600]=0x7839e876
CLMIB_TNCL.eth1[0x6e00]=0
CLMIB_TNCL.eth2[0x6e00]=0
CLMIB_TNCL.eth3[0x6e00]=0
CLMIB_TNCL.eth4[0x6e00]=0
CLMIB_TNCL.eth5[0x6e00]=0
CLMIB_TNCL.eth6[0x6e00]=0
CLMIB_TNCL.eth7[0x6e00]=0
CLMIB_TNCL.eth8[0x6e00]=0
CLMIB_TNCL.eth9[0x6e00]=0
CLMIB_TNCL.eth10[0x6e00]=0
CLMIB_TNCL.eth11[0x6e00]=0
CLMIB_TNCL.eth12[0x6e00]=0
CLMIB_TNCL.eth13[0x6e00]=0
CLMIB_TNCL.eth14[0x6e00]=0
CLMIB_TNCL.eth15[0x6e00]=0
CLMIB_TNCL.eth16[0x6e00]=0
CLMIB_TNCL.eth17[0x6e00]=0
CLMIB_TNCL.eth18[0x6e00]=0
CLMIB_TNCL.eth19[0x6e00]=0
CLMIB_TNCL.eth20[0x6e00]=0
CLMIB_TNCL.eth21[0x6e00]=0
CLMIB_TNCL.eth22[0x6e00]=0
CLMIB_TNCL.eth23[0x6e00]=0
CLMIB_TNCL.eth24[0x6e00]=0
CLMIB_TNCL.eth25[0x6e00]=0
CLMIB_TNCL.eth26[0x6e00]=0
CLMIB_TNCL.eth27[0x6e00]=0
CLMIB_TNCL.eth28[0x6e00]=0
CLMIB_TNCL.eth29[0x6e00]=0
CLMIB_TNCL.eth30[0x6e00]=0
CLMIB_TNCL.eth31[0x6e00]=0
CLMIB_TNCL.eth32[0x6e00]=0
CLMIB_TOVR.eth1[0x5500]=0
CLMIB_TOVR.eth2[0x5500]=0
CLMIB_TOVR.eth3[0x5500]=0
CLMIB_TOVR.eth4[0x5500]=0
CLMIB_TOVR.eth5[0x5500]=0
CLMIB_TOVR.eth6[0x5500]=0
CLMIB_TOVR.eth7[0x5500]=0
CLMIB_TOVR.eth8[0x5500]=0
CLMIB_TOVR.eth9[0x5500]=0
CLMIB_TOVR.eth10[0x5500]=0
CLMIB_TOVR.eth11[0x5500]=0
CLMIB_TOVR.eth12[0x5500]=0
CLMIB_TOVR.eth13[0x5500]=0
CLMIB_TOVR.eth14[0x5500]=0
CLMIB_TOVR.eth15[0x5500]=0
CLMIB_TOVR.eth16[0x5500]=0
CLMIB_TOVR.eth17[0x5500]=0
CLMIB_TOVR.eth18[0x5500]=0
CLMIB_TOVR.eth19[0x5500]=0
CLMIB_TOVR.eth20[0x5500]=0
CLMIB_TOVR.eth21[0x5500]=0
CLMIB_TOVR.eth22[0x5500]=0
CLMIB_TOVR.eth23[0x5500]=0
CLMIB_TOVR.eth24[0x5500]=0
CLMIB_TOVR.eth25[0x5500]=0
CLMIB_TOVR.eth26[0x5500]=0
CLMIB_TOVR.eth27[0x5500]=0
CLMIB_TOVR.eth28[0x5500]=0
CLMIB_TOVR.eth29[0x5500]=0
CLMIB_TOVR.eth30[0x5500]=0
CLMIB_TOVR.eth31[0x5500]=0
CLMIB_TOVR.eth32[0x5500]=0
CLMIB_TPFC0.eth1[0x6200]=0
CLMIB_TPFC0.eth2[0x6200]=0
CLMIB_TPFC0.eth3[0x6200]=0
CLMIB_TPFC0.eth4[0x6200]=0
CLMIB_TPFC0.eth5[0x6200]=0
CLMIB_TPFC0.eth6[0x6200]=0
CLMIB_TPFC0.eth7[0x6200]=0
CLMIB_TPFC0.eth8[0x6200]=0
CLMIB_TPFC0.eth9[0x6200]=0
CLMIB_TPFC0.eth10[0x6200]=0
CLMIB_TPFC0.eth11[0x6200]=0
CLMIB_TPFC0.eth12[0x6200]=0
CLMIB_TPFC0.eth13[0x6200]=0
CLMIB_TPFC0.eth14[0x6200]=0
CLMIB_TPFC0.eth15[0x6200]=0
CLMIB_TPFC0.eth16[0x6200]=0
CLMIB_TPFC0.eth17[0x6200]=0
CLMIB_TPFC0.eth18[0x6200]=0
CLMIB_TPFC0.eth19[0x6200]=0
CLMIB_TPFC0.eth20[0x6200]=0
CLMIB_TPFC0.eth21[0x6200]=0
CLMIB_TPFC0.eth22[0x6200]=0
CLMIB_TPFC0.eth23[0x6200]=0
CLMIB_TPFC0.eth24[0x6200]=0
CLMIB_TPFC0.eth25[0x6200]=0
CLMIB_TPFC0.eth26[0x6200]=0
CLMIB_TPFC0.eth27[0x6200]=0
CLMIB_TPFC0.eth28[0x6200]=0
CLMIB_TPFC0.eth29[0x6200]=0
CLMIB_TPFC0.eth30[0x6200]=0
CLMIB_TPFC0.eth31[0x6200]=0
CLMIB_TPFC0.eth32[0x6200]=0
CLMIB_TPFC1.eth1[0x6300]=0
CLMIB_TPFC1.eth2[0x6300]=0
CLMIB_TPFC1.eth3[0x6300]=0
CLMIB_TPFC1.eth4[0x6300]=0
CLMIB_TPFC1.eth5[0x6300]=0
CLMIB_TPFC1.eth6[0x6300]=0
CLMIB_TPFC1.eth7[0x6300]=0
CLMIB_TPFC1.eth8[0x6300]=0
CLMIB_TPFC1.eth9[0x6300]=0
CLMIB_TPFC1.eth10[0x6300]=0
CLMIB_TPFC1.eth11[0x6300]=0
CLMIB_TPFC1.eth12[0x6300]=0
CLMIB_TPFC1.eth13[0x6300]=0
CLMIB_TPFC1.eth14[0x6300]=0
CLMIB_TPFC1.eth15[0x6300]=0
CLMIB_TPFC1.eth16[0x6300]=0
CLMIB_TPFC1.eth17[0x6300]=0
CLMIB_TPFC1.eth18[0x6300]=0
CLMIB_TPFC1.eth19[0x6300]=0
CLMIB_TPFC1.eth20[0x6300]=0
CLMIB_TPFC1.eth21[0x6300]=0
CLMIB_TPFC1.eth22[0x6300]=0
CLMIB_TPFC1.eth23[0x6300]=0
CLMIB_TPFC1.eth24[0x6300]=0
CLMIB_TPFC1.eth25[0x6300]=0
CLMIB_TPFC1.eth26[0x6300]=0
CLMIB_TPFC1.eth27[0x6300]=0
CLMIB_TPFC1.eth28[0x6300]=0
CLMIB_TPFC1.eth29[0x6300]=0
CLMIB_TPFC1.eth30[0x6300]=0
CLMIB_TPFC1.eth31[0x6300]=0
CLMIB_TPFC1.eth32[0x6300]=0
CLMIB_TPFC2.eth1[0x6400]=0
CLMIB_TPFC2.eth2[0x6400]=0
CLMIB_TPFC2.eth3[0x6400]=0
CLMIB_TPFC2.eth4[0x6400]=0
CLMIB_TPFC2.eth5[0x6400]=0
CLMIB_TPFC2.eth6[0x6400]=0
CLMIB_TPFC2.eth7[0x6400]=0
CLMIB_TPFC2.eth8[0x6400]=0
CLMIB_TPFC2.eth9[0x6400]=0
CLMIB_TPFC2.eth10[0x6400]=0
CLMIB_TPFC2.eth11[0x6400]=0
CLMIB_TPFC2.eth12[0x6400]=0
CLMIB_TPFC2.eth13[0x6400]=0
CLMIB_TPFC2.eth14[0x6400]=0
CLMIB_TPFC2.eth15[0x6400]=0
CLMIB_TPFC2.eth16[0x6400]=0
CLMIB_TPFC2.eth17[0x6400]=0
CLMIB_TPFC2.eth18[0x6400]=0
CLMIB_TPFC2.eth19[0x6400]=0
CLMIB_TPFC2.eth20[0x6400]=0
CLMIB_TPFC2.eth21[0x6400]=0
CLMIB_TPFC2.eth22[0x6400]=0
CLMIB_TPFC2.eth23[0x6400]=0
CLMIB_TPFC2.eth24[0x6400]=0
CLMIB_TPFC2.eth25[0x6400]=0
CLMIB_TPFC2.eth26[0x6400]=0
CLMIB_TPFC2.eth27[0x6400]=0
CLMIB_TPFC2.eth28[0x6400]=0
CLMIB_TPFC2.eth29[0x6400]=0
CLMIB_TPFC2.eth30[0x6400]=0
CLMIB_TPFC2.eth31[0x6400]=0
CLMIB_TPFC2.eth32[0x6400]=0
CLMIB_TPFC3.eth1[0x6500]=0
CLMIB_TPFC3.eth2[0x6500]=0
CLMIB_TPFC3.eth3[0x6500]=0
CLMIB_TPFC3.eth4[0x6500]=0
CLMIB_TPFC3.eth5[0x6500]=0
CLMIB_TPFC3.eth6[0x6500]=0
CLMIB_TPFC3.eth7[0x6500]=0
CLMIB_TPFC3.eth8[0x6500]=0
CLMIB_TPFC3.eth9[0x6500]=0
CLMIB_TPFC3.eth10[0x6500]=0
CLMIB_TPFC3.eth11[0x6500]=0
CLMIB_TPFC3.eth12[0x6500]=0
CLMIB_TPFC3.eth13[0x6500]=0
CLMIB_TPFC3.eth14[0x6500]=0
CLMIB_TPFC3.eth15[0x6500]=0
CLMIB_TPFC3.eth16[0x6500]=0
CLMIB_TPFC3.eth17[0x6500]=0
CLMIB_TPFC3.eth18[0x6500]=0
CLMIB_TPFC3.eth19[0x6500]=0
CLMIB_TPFC3.eth20[0x6500]=0
CLMIB_TPFC3.eth21[0x6500]=0
CLMIB_TPFC3.eth22[0x6500]=0
CLMIB_TPFC3.eth23[0x6500]=0
CLMIB_TPFC3.eth24[0x6500]=0
CLMIB_TPFC3.eth25[0x6500]=0
CLMIB_TPFC3.eth26[0x6500]=0
CLMIB_TPFC3.eth27[0x6500]=0
CLMIB_TPFC3.eth28[0x6500]=0
CLMIB_TPFC3.eth29[0x6500]=0
CLMIB_TPFC3.eth30[0x6500]=0
CLMIB_TPFC3.eth31[0x6500]=0
CLMIB_TPFC3.eth32[0x6500]=0
CLMIB_TPFC4.eth1[0x6600]=0
CLMIB_TPFC4.eth2[0x6600]=0
CLMIB_TPFC4.eth3[0x6600]=0
CLMIB_TPFC4.eth4[0x6600]=0
CLMIB_TPFC4.eth5[0x6600]=0
CLMIB_TPFC4.eth6[0x6600]=0
CLMIB_TPFC4.eth7[0x6600]=0
CLMIB_TPFC4.eth8[0x6600]=0
CLMIB_TPFC4.eth9[0x6600]=0
CLMIB_TPFC4.eth10[0x6600]=0
CLMIB_TPFC4.eth11[0x6600]=0
CLMIB_TPFC4.eth12[0x6600]=0
CLMIB_TPFC4.eth13[0x6600]=0
CLMIB_TPFC4.eth14[0x6600]=0
CLMIB_TPFC4.eth15[0x6600]=0
CLMIB_TPFC4.eth16[0x6600]=0
CLMIB_TPFC4.eth17[0x6600]=0
CLMIB_TPFC4.eth18[0x6600]=0
CLMIB_TPFC4.eth19[0x6600]=0
CLMIB_TPFC4.eth20[0x6600]=0
CLMIB_TPFC4.eth21[0x6600]=0
CLMIB_TPFC4.eth22[0x6600]=0
CLMIB_TPFC4.eth23[0x6600]=0
CLMIB_TPFC4.eth24[0x6600]=0
CLMIB_TPFC4.eth25[0x6600]=0
CLMIB_TPFC4.eth26[0x6600]=0
CLMIB_TPFC4.eth27[0x6600]=0
CLMIB_TPFC4.eth28[0x6600]=0
CLMIB_TPFC4.eth29[0x6600]=0
CLMIB_TPFC4.eth30[0x6600]=0
CLMIB_TPFC4.eth31[0x6600]=0
CLMIB_TPFC4.eth32[0x6600]=0
CLMIB_TPFC5.eth1[0x6700]=0
CLMIB_TPFC5.eth2[0x6700]=0
CLMIB_TPFC5.eth3[0x6700]=0
CLMIB_TPFC5.eth4[0x6700]=0
CLMIB_TPFC5.eth5[0x6700]=0
CLMIB_TPFC5.eth6[0x6700]=0
CLMIB_TPFC5.eth7[0x6700]=0
CLMIB_TPFC5.eth8[0x6700]=0
CLMIB_TPFC5.eth9[0x6700]=0
CLMIB_TPFC5.eth10[0x6700]=0
CLMIB_TPFC5.eth11[0x6700]=0
CLMIB_TPFC5.eth12[0x6700]=0
CLMIB_TPFC5.eth13[0x6700]=0
CLMIB_TPFC5.eth14[0x6700]=0
CLMIB_TPFC5.eth15[0x6700]=0
CLMIB_TPFC5.eth16[0x6700]=0
CLMIB_TPFC5.eth17[0x6700]=0
CLMIB_TPFC5.eth18[0x6700]=0
CLMIB_TPFC5.eth19[0x6700]=0
CLMIB_TPFC5.eth20[0x6700]=0
CLMIB_TPFC5.eth21[0x6700]=0
CLMIB_TPFC5.eth22[0x6700]=0
CLMIB_TPFC5.eth23[0x6700]=0
CLMIB_TPFC5.eth24[0x6700]=0
CLMIB_TPFC5.eth25[0x6700]=0
CLMIB_TPFC5.eth26[0x6700]=0
CLMIB_TPFC5.eth27[0x6700]=0
CLMIB_TPFC5.eth28[0x6700]=0
CLMIB_TPFC5.eth29[0x6700]=0
CLMIB_TPFC5.eth30[0x6700]=0
CLMIB_TPFC5.eth31[0x6700]=0
CLMIB_TPFC5.eth32[0x6700]=0
CLMIB_TPFC6.eth1[0x6800]=0
CLMIB_TPFC6.eth2[0x6800]=0
CLMIB_TPFC6.eth3[0x6800]=0
CLMIB_TPFC6.eth4[0x6800]=0
CLMIB_TPFC6.eth5[0x6800]=0
CLMIB_TPFC6.eth6[0x6800]=0
CLMIB_TPFC6.eth7[0x6800]=0
CLMIB_TPFC6.eth8[0x6800]=0
CLMIB_TPFC6.eth9[0x6800]=0
CLMIB_TPFC6.eth10[0x6800]=0
CLMIB_TPFC6.eth11[0x6800]=0
CLMIB_TPFC6.eth12[0x6800]=0
CLMIB_TPFC6.eth13[0x6800]=0
CLMIB_TPFC6.eth14[0x6800]=0
CLMIB_TPFC6.eth15[0x6800]=0
CLMIB_TPFC6.eth16[0x6800]=0
CLMIB_TPFC6.eth17[0x6800]=0
CLMIB_TPFC6.eth18[0x6800]=0
CLMIB_TPFC6.eth19[0x6800]=0
CLMIB_TPFC6.eth20[0x6800]=0
CLMIB_TPFC6.eth21[0x6800]=0
CLMIB_TPFC6.eth22[0x6800]=0
CLMIB_TPFC6.eth23[0x6800]=0
CLMIB_TPFC6.eth24[0x6800]=0
CLMIB_TPFC6.eth25[0x6800]=0
CLMIB_TPFC6.eth26[0x6800]=0
CLMIB_TPFC6.eth27[0x6800]=0
CLMIB_TPFC6.eth28[0x6800]=0
CLMIB_TPFC6.eth29[0x6800]=0
CLMIB_TPFC6.eth30[0x6800]=0
CLMIB_TPFC6.eth31[0x6800]=0
CLMIB_TPFC6.eth32[0x6800]=0
CLMIB_TPFC7.eth1[0x6900]=0
CLMIB_TPFC7.eth2[0x6900]=0
CLMIB_TPFC7.eth3[0x6900]=0
CLMIB_TPFC7.eth4[0x6900]=0
CLMIB_TPFC7.eth5[0x6900]=0
CLMIB_TPFC7.eth6[0x6900]=0
CLMIB_TPFC7.eth7[0x6900]=0
CLMIB_TPFC7.eth8[0x6900]=0
CLMIB_TPFC7.eth9[0x6900]=0
CLMIB_TPFC7.eth10[0x6900]=0
CLMIB_TPFC7.eth11[0x6900]=0
CLMIB_TPFC7.eth12[0x6900]=0
CLMIB_TPFC7.eth13[0x6900]=0
CLMIB_TPFC7.eth14[0x6900]=0
CLMIB_TPFC7.eth15[0x6900]=0
CLMIB_TPFC7.eth16[0x6900]=0
CLMIB_TPFC7.eth17[0x6900]=0
CLMIB_TPFC7.eth18[0x6900]=0
CLMIB_TPFC7.eth19[0x6900]=0
CLMIB_TPFC7.eth20[0x6900]=0
CLMIB_TPFC7.eth21[0x6900]=0
CLMIB_TPFC7.eth22[0x6900]=0
CLMIB_TPFC7.eth23[0x6900]=0
CLMIB_TPFC7.eth24[0x6900]=0
CLMIB_TPFC7.eth25[0x6900]=0
CLMIB_TPFC7.eth26[0x6900]=0
CLMIB_TPFC7.eth27[0x6900]=0
CLMIB_TPFC7.eth28[0x6900]=0
CLMIB_TPFC7.eth29[0x6900]=0
CLMIB_TPFC7.eth30[0x6900]=0
CLMIB_TPFC7.eth31[0x6900]=0
CLMIB_TPFC7.eth32[0x6900]=0
CLMIB_TPFCOFF0.eth1[0x7900]=0
CLMIB_TPFCOFF0.eth2[0x7900]=0
CLMIB_TPFCOFF0.eth3[0x7900]=0
CLMIB_TPFCOFF0.eth4[0x7900]=0
CLMIB_TPFCOFF0.eth5[0x7900]=0
CLMIB_TPFCOFF0.eth6[0x7900]=0
CLMIB_TPFCOFF0.eth7[0x7900]=0
CLMIB_TPFCOFF0.eth8[0x7900]=0
CLMIB_TPFCOFF0.eth9[0x7900]=0
CLMIB_TPFCOFF0.eth10[0x7900]=0
CLMIB_TPFCOFF0.eth11[0x7900]=0
CLMIB_TPFCOFF0.eth12[0x7900]=0
CLMIB_TPFCOFF0.eth13[0x7900]=0
CLMIB_TPFCOFF0.eth14[0x7900]=0
CLMIB_TPFCOFF0.eth15[0x7900]=0
CLMIB_TPFCOFF0.eth16[0x7900]=0
CLMIB_TPFCOFF0.eth17[0x7900]=0
CLMIB_TPFCOFF0.eth18[0x7900]=0
CLMIB_TPFCOFF0.eth19[0x7900]=0
CLMIB_TPFCOFF0.eth20[0x7900]=0
CLMIB_TPFCOFF0.eth21[0x7900]=0
CLMIB_TPFCOFF0.eth22[0x7900]=0
CLMIB_TPFCOFF0.eth23[0x7900]=0
CLMIB_TPFCOFF0.eth24[0x7900]=0
CLMIB_TPFCOFF0.eth25[0x7900]=0
CLMIB_TPFCOFF0.eth26[0x7900]=0
CLMIB_TPFCOFF0.eth27[0x7900]=0
CLMIB_TPFCOFF0.eth28[0x7900]=0
CLMIB_TPFCOFF0.eth29[0x7900]=0
CLMIB_TPFCOFF0.eth30[0x7900]=0
CLMIB_TPFCOFF0.eth31[0x7900]=0
CLMIB_TPFCOFF0.eth32[0x7900]=0
CLMIB_TPFCOFF1.eth1[0x7a00]=0
CLMIB_TPFCOFF1.eth2[0x7a00]=0
CLMIB_TPFCOFF1.eth3[0x7a00]=0
CLMIB_TPFCOFF1.eth4[0x7a00]=0
CLMIB_TPFCOFF1.eth5[0x7a00]=0
CLMIB_TPFCOFF1.eth6[0x7a00]=0
CLMIB_TPFCOFF1.eth7[0x7a00]=0
CLMIB_TPFCOFF1.eth8[0x7a00]=0
CLMIB_TPFCOFF1.eth9[0x7a00]=0
CLMIB_TPFCOFF1.eth10[0x7a00]=0
CLMIB_TPFCOFF1.eth11[0x7a00]=0
CLMIB_TPFCOFF1.eth12[0x7a00]=0
CLMIB_TPFCOFF1.eth13[0x7a00]=0
CLMIB_TPFCOFF1.eth14[0x7a00]=0
CLMIB_TPFCOFF1.eth15[0x7a00]=0
CLMIB_TPFCOFF1.eth16[0x7a00]=0
CLMIB_TPFCOFF1.eth17[0x7a00]=0
CLMIB_TPFCOFF1.eth18[0x7a00]=0
CLMIB_TPFCOFF1.eth19[0x7a00]=0
CLMIB_TPFCOFF1.eth20[0x7a00]=0
CLMIB_TPFCOFF1.eth21[0x7a00]=0
CLMIB_TPFCOFF1.eth22[0x7a00]=0
CLMIB_TPFCOFF1.eth23[0x7a00]=0
CLMIB_TPFCOFF1.eth24[0x7a00]=0
CLMIB_TPFCOFF1.eth25[0x7a00]=0
CLMIB_TPFCOFF1.eth26[0x7a00]=0
CLMIB_TPFCOFF1.eth27[0x7a00]=0
CLMIB_TPFCOFF1.eth28[0x7a00]=0
CLMIB_TPFCOFF1.eth29[0x7a00]=0
CLMIB_TPFCOFF1.eth30[0x7a00]=0
CLMIB_TPFCOFF1.eth31[0x7a00]=0
CLMIB_TPFCOFF1.eth32[0x7a00]=0
CLMIB_TPFCOFF2.eth1[0x7b00]=0
CLMIB_TPFCOFF2.eth2[0x7b00]=0
CLMIB_TPFCOFF2.eth3[0x7b00]=0
CLMIB_TPFCOFF2.eth4[0x7b00]=0
CLMIB_TPFCOFF2.eth5[0x7b00]=0
CLMIB_TPFCOFF2.eth6[0x7b00]=0
CLMIB_TPFCOFF2.eth7[0x7b00]=0
CLMIB_TPFCOFF2.eth8[0x7b00]=0
CLMIB_TPFCOFF2.eth9[0x7b00]=0
CLMIB_TPFCOFF2.eth10[0x7b00]=0
CLMIB_TPFCOFF2.eth11[0x7b00]=0
CLMIB_TPFCOFF2.eth12[0x7b00]=0
CLMIB_TPFCOFF2.eth13[0x7b00]=0
CLMIB_TPFCOFF2.eth14[0x7b00]=0
CLMIB_TPFCOFF2.eth15[0x7b00]=0
CLMIB_TPFCOFF2.eth16[0x7b00]=0
CLMIB_TPFCOFF2.eth17[0x7b00]=0
CLMIB_TPFCOFF2.eth18[0x7b00]=0
CLMIB_TPFCOFF2.eth19[0x7b00]=0
CLMIB_TPFCOFF2.eth20[0x7b00]=0
CLMIB_TPFCOFF2.eth21[0x7b00]=0
CLMIB_TPFCOFF2.eth22[0x7b00]=0
CLMIB_TPFCOFF2.eth23[0x7b00]=0
CLMIB_TPFCOFF2.eth24[0x7b00]=0
CLMIB_TPFCOFF2.eth25[0x7b00]=0
CLMIB_TPFCOFF2.eth26[0x7b00]=0
CLMIB_TPFCOFF2.eth27[0x7b00]=0
CLMIB_TPFCOFF2.eth28[0x7b00]=0
CLMIB_TPFCOFF2.eth29[0x7b00]=0
CLMIB_TPFCOFF2.eth30[0x7b00]=0
CLMIB_TPFCOFF2.eth31[0x7b00]=0
CLMIB_TPFCOFF2.eth32[0x7b00]=0
CLMIB_TPFCOFF3.eth1[0x7c00]=0
CLMIB_TPFCOFF3.eth2[0x7c00]=0
CLMIB_TPFCOFF3.eth3[0x7c00]=0
CLMIB_TPFCOFF3.eth4[0x7c00]=0
CLMIB_TPFCOFF3.eth5[0x7c00]=0
CLMIB_TPFCOFF3.eth6[0x7c00]=0
CLMIB_TPFCOFF3.eth7[0x7c00]=0
CLMIB_TPFCOFF3.eth8[0x7c00]=0
CLMIB_TPFCOFF3.eth9[0x7c00]=0
CLMIB_TPFCOFF3.eth10[0x7c00]=0
CLMIB_TPFCOFF3.eth11[0x7c00]=0
CLMIB_TPFCOFF3.eth12[0x7c00]=0
CLMIB_TPFCOFF3.eth13[0x7c00]=0
CLMIB_TPFCOFF3.eth14[0x7c00]=0
CLMIB_TPFCOFF3.eth15[0x7c00]=0
CLMIB_TPFCOFF3.eth16[0x7c00]=0
CLMIB_TPFCOFF3.eth17[0x7c00]=0
CLMIB_TPFCOFF3.eth18[0x7c00]=0
CLMIB_TPFCOFF3.eth19[0x7c00]=0
CLMIB_TPFCOFF3.eth20[0x7c00]=0
CLMIB_TPFCOFF3.eth21[0x7c00]=0
CLMIB_TPFCOFF3.eth22[0x7c00]=0
CLMIB_TPFCOFF3.eth23[0x7c00]=0
CLMIB_TPFCOFF3.eth24[0x7c00]=0
CLMIB_TPFCOFF3.eth25[0x7c00]=0
CLMIB_TPFCOFF3.eth26[0x7c00]=0
CLMIB_TPFCOFF3.eth27[0x7c00]=0
CLMIB_TPFCOFF3.eth28[0x7c00]=0
CLMIB_TPFCOFF3.eth29[0x7c00]=0
CLMIB_TPFCOFF3.eth30[0x7c00]=0
CLMIB_TPFCOFF3.eth31[0x7c00]=0
CLMIB_TPFCOFF3.eth32[0x7c00]=0
CLMIB_TPFCOFF4.eth1[0x7d00]=0
CLMIB_TPFCOFF4.eth2[0x7d00]=0
CLMIB_TPFCOFF4.eth3[0x7d00]=0
CLMIB_TPFCOFF4.eth4[0x7d00]=0
CLMIB_TPFCOFF4.eth5[0x7d00]=0
CLMIB_TPFCOFF4.eth6[0x7d00]=0
CLMIB_TPFCOFF4.eth7[0x7d00]=0
CLMIB_TPFCOFF4.eth8[0x7d00]=0
CLMIB_TPFCOFF4.eth9[0x7d00]=0
CLMIB_TPFCOFF4.eth10[0x7d00]=0
CLMIB_TPFCOFF4.eth11[0x7d00]=0
CLMIB_TPFCOFF4.eth12[0x7d00]=0
CLMIB_TPFCOFF4.eth13[0x7d00]=0
CLMIB_TPFCOFF4.eth14[0x7d00]=0
CLMIB_TPFCOFF4.eth15[0x7d00]=0
CLMIB_TPFCOFF4.eth16[0x7d00]=0
CLMIB_TPFCOFF4.eth17[0x7d00]=0
CLMIB_TPFCOFF4.eth18[0x7d00]=0
CLMIB_TPFCOFF4.eth19[0x7d00]=0
CLMIB_TPFCOFF4.eth20[0x7d00]=0
CLMIB_TPFCOFF4.eth21[0x7d00]=0
CLMIB_TPFCOFF4.eth22[0x7d00]=0
CLMIB_TPFCOFF4.eth23[0x7d00]=0
CLMIB_TPFCOFF4.eth24[0x7d00]=0
CLMIB_TPFCOFF4.eth25[0x7d00]=0
CLMIB_TPFCOFF4.eth26[0x7d00]=0
CLMIB_TPFCOFF4.eth27[0x7d00]=0
CLMIB_TPFCOFF4.eth28[0x7d00]=0
CLMIB_TPFCOFF4.eth29[0x7d00]=0
CLMIB_TPFCOFF4.eth30[0x7d00]=0
CLMIB_TPFCOFF4.eth31[0x7d00]=0
CLMIB_TPFCOFF4.eth32[0x7d00]=0
CLMIB_TPFCOFF5.eth1[0x7e00]=0
CLMIB_TPFCOFF5.eth2[0x7e00]=0
CLMIB_TPFCOFF5.eth3[0x7e00]=0
CLMIB_TPFCOFF5.eth4[0x7e00]=0
CLMIB_TPFCOFF5.eth5[0x7e00]=0
CLMIB_TPFCOFF5.eth6[0x7e00]=0
CLMIB_TPFCOFF5.eth7[0x7e00]=0
CLMIB_TPFCOFF5.eth8[0x7e00]=0
CLMIB_TPFCOFF5.eth9[0x7e00]=0
CLMIB_TPFCOFF5.eth10[0x7e00]=0
CLMIB_TPFCOFF5.eth11[0x7e00]=0
CLMIB_TPFCOFF5.eth12[0x7e00]=0
CLMIB_TPFCOFF5.eth13[0x7e00]=0
CLMIB_TPFCOFF5.eth14[0x7e00]=0
CLMIB_TPFCOFF5.eth15[0x7e00]=0
CLMIB_TPFCOFF5.eth16[0x7e00]=0
CLMIB_TPFCOFF5.eth17[0x7e00]=0
CLMIB_TPFCOFF5.eth18[0x7e00]=0
CLMIB_TPFCOFF5.eth19[0x7e00]=0
CLMIB_TPFCOFF5.eth20[0x7e00]=0
CLMIB_TPFCOFF5.eth21[0x7e00]=0
CLMIB_TPFCOFF5.eth22[0x7e00]=0
CLMIB_TPFCOFF5.eth23[0x7e00]=0
CLMIB_TPFCOFF5.eth24[0x7e00]=0
CLMIB_TPFCOFF5.eth25[0x7e00]=0
CLMIB_TPFCOFF5.eth26[0x7e00]=0
CLMIB_TPFCOFF5.eth27[0x7e00]=0
CLMIB_TPFCOFF5.eth28[0x7e00]=0
CLMIB_TPFCOFF5.eth29[0x7e00]=0
CLMIB_TPFCOFF5.eth30[0x7e00]=0
CLMIB_TPFCOFF5.eth31[0x7e00]=0
CLMIB_TPFCOFF5.eth32[0x7e00]=0
CLMIB_TPFCOFF6.eth1[0x7f00]=0
CLMIB_TPFCOFF6.eth2[0x7f00]=0
CLMIB_TPFCOFF6.eth3[0x7f00]=0
CLMIB_TPFCOFF6.eth4[0x7f00]=0
CLMIB_TPFCOFF6.eth5[0x7f00]=0
CLMIB_TPFCOFF6.eth6[0x7f00]=0
CLMIB_TPFCOFF6.eth7[0x7f00]=0
CLMIB_TPFCOFF6.eth8[0x7f00]=0
CLMIB_TPFCOFF6.eth9[0x7f00]=0
CLMIB_TPFCOFF6.eth10[0x7f00]=0
CLMIB_TPFCOFF6.eth11[0x7f00]=0
CLMIB_TPFCOFF6.eth12[0x7f00]=0
CLMIB_TPFCOFF6.eth13[0x7f00]=0
CLMIB_TPFCOFF6.eth14[0x7f00]=0
CLMIB_TPFCOFF6.eth15[0x7f00]=0
CLMIB_TPFCOFF6.eth16[0x7f00]=0
CLMIB_TPFCOFF6.eth17[0x7f00]=0
CLMIB_TPFCOFF6.eth18[0x7f00]=0
CLMIB_TPFCOFF6.eth19[0x7f00]=0
CLMIB_TPFCOFF6.eth20[0x7f00]=0
CLMIB_TPFCOFF6.eth21[0x7f00]=0
CLMIB_TPFCOFF6.eth22[0x7f00]=0
CLMIB_TPFCOFF6.eth23[0x7f00]=0
CLMIB_TPFCOFF6.eth24[0x7f00]=0
CLMIB_TPFCOFF6.eth25[0x7f00]=0
CLMIB_TPFCOFF6.eth26[0x7f00]=0
CLMIB_TPFCOFF6.eth27[0x7f00]=0
CLMIB_TPFCOFF6.eth28[0x7f00]=0
CLMIB_TPFCOFF6.eth29[0x7f00]=0
CLMIB_TPFCOFF6.eth30[0x7f00]=0
CLMIB_TPFCOFF6.eth31[0x7f00]=0
CLMIB_TPFCOFF6.eth32[0x7f00]=0
CLMIB_TPFCOFF7.eth1[0x8000]=0
CLMIB_TPFCOFF7.eth2[0x8000]=0
CLMIB_TPFCOFF7.eth3[0x8000]=0
CLMIB_TPFCOFF7.eth4[0x8000]=0
CLMIB_TPFCOFF7.eth5[0x8000]=0
CLMIB_TPFCOFF7.eth6[0x8000]=0
CLMIB_TPFCOFF7.eth7[0x8000]=0
CLMIB_TPFCOFF7.eth8[0x8000]=0
CLMIB_TPFCOFF7.eth9[0x8000]=0
CLMIB_TPFCOFF7.eth10[0x8000]=0
CLMIB_TPFCOFF7.eth11[0x8000]=0
CLMIB_TPFCOFF7.eth12[0x8000]=0
CLMIB_TPFCOFF7.eth13[0x8000]=0
CLMIB_TPFCOFF7.eth14[0x8000]=0
CLMIB_TPFCOFF7.eth15[0x8000]=0
CLMIB_TPFCOFF7.eth16[0x8000]=0
CLMIB_TPFCOFF7.eth17[0x8000]=0
CLMIB_TPFCOFF7.eth18[0x8000]=0
CLMIB_TPFCOFF7.eth19[0x8000]=0
CLMIB_TPFCOFF7.eth20[0x8000]=0
CLMIB_TPFCOFF7.eth21[0x8000]=0
CLMIB_TPFCOFF7.eth22[0x8000]=0
CLMIB_TPFCOFF7.eth23[0x8000]=0
CLMIB_TPFCOFF7.eth24[0x8000]=0
CLMIB_TPFCOFF7.eth25[0x8000]=0
CLMIB_TPFCOFF7.eth26[0x8000]=0
CLMIB_TPFCOFF7.eth27[0x8000]=0
CLMIB_TPFCOFF7.eth28[0x8000]=0
CLMIB_TPFCOFF7.eth29[0x8000]=0
CLMIB_TPFCOFF7.eth30[0x8000]=0
CLMIB_TPFCOFF7.eth31[0x8000]=0
CLMIB_TPFCOFF7.eth32[0x8000]=0
CLMIB_TPKT.eth1[0x4c00]=0x5db87827f
CLMIB_TPKT.eth2[0x4c00]=0x2ba9eace5
CLMIB_TPKT.eth3[0x4c00]=0x6f26870ab
CLMIB_TPKT.eth4[0x4c00]=0x33d6f8bc6
CLMIB_TPKT.eth5[0x4c00]=0
CLMIB_TPKT.eth6[0x4c00]=0
CLMIB_TPKT.eth7[0x4c00]=0
CLMIB_TPKT.eth8[0x4c00]=0
CLMIB_TPKT.eth9[0x4c00]=0
CLMIB_TPKT.eth10[0x4c00]=0
CLMIB_TPKT.eth11[0x4c00]=0
CLMIB_TPKT.eth12[0x4c00]=0
CLMIB_TPKT.eth13[0x4c00]=0
CLMIB_TPKT.eth14[0x4c00]=0
CLMIB_TPKT.eth15[0x4c00]=0
CLMIB_TPKT.eth16[0x4c00]=0
CLMIB_TPKT.eth17[0x4c00]=0
CLMIB_TPKT.eth18[0x4c00]=0
CLMIB_TPKT.eth19[0x4c00]=0
CLMIB_TPKT.eth20[0x4c00]=0
CLMIB_TPKT.eth21[0x4c00]=0
CLMIB_TPKT.eth22[0x4c00]=0
CLMIB_TPKT.eth23[0x4c00]=0
CLMIB_TPKT.eth24[0x4c00]=0
CLMIB_TPKT.eth25[0x4c00]=0
CLMIB_TPKT.eth26[0x4c00]=0
CLMIB_TPKT.eth27[0x4c00]=0
CLMIB_TPKT.eth28[0x4c00]=0
CLMIB_TPKT.eth29[0x4c00]=0
CLMIB_TPKT.eth30[0x4c00]=0
CLMIB_TPKT.eth31[0x4c00]=0
CLMIB_TPKT.eth32[0x4c00]=0x8f71157b0
CLMIB_TPOK.eth1[0x4b00]=0x5db878280
CLMIB_TPOK.eth2[0x4b00]=0x2ba9eacef
CLMIB_TPOK.eth3[0x4b00]=0x6f26870ad
CLMIB_TPOK.eth4[0x4b00]=0x33d6f8bca
CLMIB_TPOK.eth5[0x4b00]=0
CLMIB_TPOK.eth6[0x4b00]=0
CLMIB_TPOK.eth7[0x4b00]=0
CLMIB_TPOK.eth8[0x4b00]=0
CLMIB_TPOK.eth9[0x4b00]=0
CLMIB_TPOK.eth10[0x4b00]=0
CLMIB_TPOK.eth11[0x4b00]=0
CLMIB_TPOK.eth12[0x4b00]=0
CLMIB_TPOK.eth13[0x4b00]=0
CLMIB_TPOK.eth14[0x4b00]=0
CLMIB_TPOK.eth15[0x4b00]=0
CLMIB_TPOK.eth16[0x4b00]=0
CLMIB_TPOK.eth17[0x4b00]=0
CLMIB_TPOK.eth18[0x4b00]=0
CLMIB_TPOK.eth19[0x4b00]=0
CLMIB_TPOK.eth20[0x4b00]=0
CLMIB_TPOK.eth21[0x4b00]=0
CLMIB_TPOK.eth22[0x4b00]=0
CLMIB_TPOK.eth23[0x4b00]=0
CLMIB_TPOK.eth24[0x4b00]=0
CLMIB_TPOK.eth25[0x4b00]=0
CLMIB_TPOK.eth26[0x4b00]=0
CLMIB_TPOK.eth27[0x4b00]=0
CLMIB_TPOK.eth28[0x4b00]=0
CLMIB_TPOK.eth29[0x4b00]=0
CLMIB_TPOK.eth30[0x4b00]=0
CLMIB_TPOK.eth31[0x4b00]=0
CLMIB_TPOK.eth32[0x4b00]=0x8f71157d5
CLMIB_TREPLY.eth1[0x5700]=0
CLMIB_TREPLY.eth2[0x5700]=0
CLMIB_TREPLY.eth3[0x5700]=0
CLMIB_TREPLY.eth4[0x5700]=0
CLMIB_TREPLY.eth5[0x5700]=0
CLMIB_TREPLY.eth6[0x5700]=0
CLMIB_TREPLY.eth7[0x5700]=0
CLMIB_TREPLY.eth8[0x5700]=0
CLMIB_TREPLY.eth9[0x5700]=0
CLMIB_TREPLY.eth10[0x5700]=0
CLMIB_TREPLY.eth11[0x5700]=0
CLMIB_TREPLY.eth12[0x5700]=0
CLMIB_TREPLY.eth13[0x5700]=0
CLMIB_TREPLY.eth14[0x5700]=0
CLMIB_TREPLY.eth15[0x5700]=0
CLMIB_TREPLY.eth16[0x5700]=0
CLMIB_TREPLY.eth17[0x5700]=0
CLMIB_TREPLY.eth18[0x5700]=0
CLMIB_TREPLY.eth19[0x5700]=0
CLMIB_TREPLY.eth20[0x5700]=0
CLMIB_TREPLY.eth21[0x5700]=0
CLMIB_TREPLY.eth22[0x5700]=0
CLMIB_TREPLY.eth23[0x5700]=0
CLMIB_TREPLY.eth24[0x5700]=0
CLMIB_TREPLY.eth25[0x5700]=0
CLMIB_TREPLY.eth26[0x5700]=0
CLMIB_TREPLY.eth27[0x5700]=0
CLMIB_TREPLY.eth28[0x5700]=0
CLMIB_TREPLY.eth29[0x5700]=0
CLMIB_TREPLY.eth30[0x5700]=0
CLMIB_TREPLY.eth31[0x5700]=0
CLMIB_TREPLY.eth32[0x5700]=0
CLMIB_TRPKT.eth1[0x6000]=0
CLMIB_TRPKT.eth2[0x6000]=0
CLMIB_TRPKT.eth3[0x6000]=0
CLMIB_TRPKT.eth4[0x6000]=0
CLMIB_TRPKT.eth5[0x6000]=0
CLMIB_TRPKT.eth6[0x6000]=0
CLMIB_TRPKT.eth7[0x6000]=0
CLMIB_TRPKT.eth8[0x6000]=0
CLMIB_TRPKT.eth9[0x6000]=0
CLMIB_TRPKT.eth10[0x6000]=0
CLMIB_TRPKT.eth11[0x6000]=0
CLMIB_TRPKT.eth12[0x6000]=0
CLMIB_TRPKT.eth13[0x6000]=0
CLMIB_TRPKT.eth14[0x6000]=0
CLMIB_TRPKT.eth15[0x6000]=0
CLMIB_TRPKT.eth16[0x6000]=0
CLMIB_TRPKT.eth17[0x6000]=0
CLMIB_TRPKT.eth18[0x6000]=0
CLMIB_TRPKT.eth19[0x6000]=0
CLMIB_TRPKT.eth20[0x6000]=0
CLMIB_TRPKT.eth21[0x6000]=0
CLMIB_TRPKT.eth22[0x6000]=0
CLMIB_TRPKT.eth23[0x6000]=0
CLMIB_TRPKT.eth24[0x6000]=0
CLMIB_TRPKT.eth25[0x6000]=0
CLMIB_TRPKT.eth26[0x6000]=0
CLMIB_TRPKT.eth27[0x6000]=0
CLMIB_TRPKT.eth28[0x6000]=0
CLMIB_TRPKT.eth29[0x6000]=0
CLMIB_TRPKT.eth30[0x6000]=0
CLMIB_TRPKT.eth31[0x6000]=0
CLMIB_TRPKT.eth32[0x6000]=0
CLMIB_TSCL.eth1[0x5800]=0
CLMIB_TSCL.eth2[0x5800]=0
CLMIB_TSCL.eth3[0x5800]=0
CLMIB_TSCL.eth4[0x5800]=0
CLMIB_TSCL.eth5[0x5800]=0
CLMIB_TSCL.eth6[0x5800]=0
CLMIB_TSCL.eth7[0x5800]=0
CLMIB_TSCL.eth8[0x5800]=0
CLMIB_TSCL.eth9[0x5800]=0
CLMIB_TSCL.eth10[0x5800]=0
CLMIB_TSCL.eth11[0x5800]=0
CLMIB_TSCL.eth12[0x5800]=0
CLMIB_TSCL.eth13[0x5800]=0
CLMIB_TSCL.eth14[0x5800]=0
CLMIB_TSCL.eth15[0x5800]=0
CLMIB_TSCL.eth16[0x5800]=0
CLMIB_TSCL.eth17[0x5800]=0
CLMIB_TSCL.eth18[0x5800]=0
CLMIB_TSCL.eth19[0x5800]=0
CLMIB_TSCL.eth20[0x5800]=0
CLMIB_TSCL.eth21[0x5800]=0
CLMIB_TSCL.eth22[0x5800]=0
CLMIB_TSCL.eth23[0x5800]=0
CLMIB_TSCL.eth24[0x5800]=0
CLMIB_TSCL.eth25[0x5800]=0
CLMIB_TSCL.eth26[0x5800]=0
CLMIB_TSCL.eth27[0x5800]=0
CLMIB_TSCL.eth28[0x5800]=0
CLMIB_TSCL.eth29[0x5800]=0
CLMIB_TSCL.eth30[0x5800]=0
CLMIB_TSCL.eth31[0x5800]=0
CLMIB_TSCL.eth32[0x5800]=0
CLMIB_TSPARE0.eth1[0x7100]=0
CLMIB_TSPARE0.eth2[0x7100]=0
CLMIB_TSPARE0.eth3[0x7100]=0
CLMIB_TSPARE0.eth4[0x7100]=0
CLMIB_TSPARE0.eth5[0x7100]=0
CLMIB_TSPARE0.eth6[0x7100]=0
CLMIB_TSPARE0.eth7[0x7100]=0
CLMIB_TSPARE0.eth8[0x7100]=0
CLMIB_TSPARE0.eth9[0x7100]=0
CLMIB_TSPARE0.eth10[0x7100]=0
CLMIB_TSPARE0.eth11[0x7100]=0
CLMIB_TSPARE0.eth12[0x7100]=0
CLMIB_TSPARE0.eth13[0x7100]=0
CLMIB_TSPARE0.eth14[0x7100]=0
CLMIB_TSPARE0.eth15[0x7100]=0
CLMIB_TSPARE0.eth16[0x7100]=0
CLMIB_TSPARE0.eth17[0x7100]=0
CLMIB_TSPARE0.eth18[0x7100]=0
CLMIB_TSPARE0.eth19[0x7100]=0
CLMIB_TSPARE0.eth20[0x7100]=0
CLMIB_TSPARE0.eth21[0x7100]=0
CLMIB_TSPARE0.eth22[0x7100]=0
CLMIB_TSPARE0.eth23[0x7100]=0
CLMIB_TSPARE0.eth24[0x7100]=0
CLMIB_TSPARE0.eth25[0x7100]=0
CLMIB_TSPARE0.eth26[0x7100]=0
CLMIB_TSPARE0.eth27[0x7100]=0
CLMIB_TSPARE0.eth28[0x7100]=0
CLMIB_TSPARE0.eth29[0x7100]=0
CLMIB_TSPARE0.eth30[0x7100]=0
CLMIB_TSPARE0.eth31[0x7100]=0
CLMIB_TSPARE0.eth32[0x7100]=0
CLMIB_TSPARE1.eth1[0x7200]=0
CLMIB_TSPARE1.eth2[0x7200]=0
CLMIB_TSPARE1.eth3[0x7200]=0
CLMIB_TSPARE1.eth4[0x7200]=0
CLMIB_TSPARE1.eth5[0x7200]=0
CLMIB_TSPARE1.eth6[0x7200]=0
CLMIB_TSPARE1.eth7[0x7200]=0
CLMIB_TSPARE1.eth8[0x7200]=0
CLMIB_TSPARE1.eth9[0x7200]=0
CLMIB_TSPARE1.eth10[0x7200]=0
CLMIB_TSPARE1.eth11[0x7200]=0
CLMIB_TSPARE1.eth12[0x7200]=0
CLMIB_TSPARE1.eth13[0x7200]=0
CLMIB_TSPARE1.eth14[0x7200]=0
CLMIB_TSPARE1.eth15[0x7200]=0
CLMIB_TSPARE1.eth16[0x7200]=0
CLMIB_TSPARE1.eth17[0x7200]=0
CLMIB_TSPARE1.eth18[0x7200]=0
CLMIB_TSPARE1.eth19[0x7200]=0
CLMIB_TSPARE1.eth20[0x7200]=0
CLMIB_TSPARE1.eth21[0x7200]=0
CLMIB_TSPARE1.eth22[0x7200]=0
CLMIB_TSPARE1.eth23[0x7200]=0
CLMIB_TSPARE1.eth24[0x7200]=0
CLMIB_TSPARE1.eth25[0x7200]=0
CLMIB_TSPARE1.eth26[0x7200]=0
CLMIB_TSPARE1.eth27[0x7200]=0
CLMIB_TSPARE1.eth28[0x7200]=0
CLMIB_TSPARE1.eth29[0x7200]=0
CLMIB_TSPARE1.eth30[0x7200]=0
CLMIB_TSPARE1.eth31[0x7200]=0
CLMIB_TSPARE1.eth32[0x7200]=0
CLMIB_TSPARE2.eth1[0x7300]=0
CLMIB_TSPARE2.eth2[0x7300]=0
CLMIB_TSPARE2.eth3[0x7300]=0
CLMIB_TSPARE2.eth4[0x7300]=0
CLMIB_TSPARE2.eth5[0x7300]=0
CLMIB_TSPARE2.eth6[0x7300]=0
CLMIB_TSPARE2.eth7[0x7300]=0
CLMIB_TSPARE2.eth8[0x7300]=0
CLMIB_TSPARE2.eth9[0x7300]=0
CLMIB_TSPARE2.eth10[0x7300]=0
CLMIB_TSPARE2.eth11[0x7300]=0
CLMIB_TSPARE2.eth12[0x7300]=0
CLMIB_TSPARE2.eth13[0x7300]=0
CLMIB_TSPARE2.eth14[0x7300]=0
CLMIB_TSPARE2.eth15[0x7300]=0
CLMIB_TSPARE2.eth16[0x7300]=0
CLMIB_TSPARE2.eth17[0x7300]=0
CLMIB_TSPARE2.eth18[0x7300]=0
CLMIB_TSPARE2.eth19[0x7300]=0
CLMIB_TSPARE2.eth20[0x7300]=0
CLMIB_TSPARE2.eth21[0x7300]=0
CLMIB_TSPARE2.eth22[0x7300]=0
CLMIB_TSPARE2.eth23[0x7300]=0
CLMIB_TSPARE2.eth24[0x7300]=0
CLMIB_TSPARE2.eth25[0x7300]=0
CLMIB_TSPARE2.eth26[0x7300]=0
CLMIB_TSPARE2.eth27[0x7300]=0
CLMIB_TSPARE2.eth28[0x7300]=0
CLMIB_TSPARE2.eth29[0x7300]=0
CLMIB_TSPARE2.eth30[0x7300]=0
CLMIB_TSPARE2.eth31[0x7300]=0
CLMIB_TSPARE2.eth32[0x7300]=0
CLMIB_TSPARE3.eth1[0x7400]=0
CLMIB_TSPARE3.eth2[0x7400]=0
CLMIB_TSPARE3.eth3[0x7400]=0
CLMIB_TSPARE3.eth4[0x7400]=0
CLMIB_TSPARE3.eth5[0x7400]=0
CLMIB_TSPARE3.eth6[0x7400]=0
CLMIB_TSPARE3.eth7[0x7400]=0
CLMIB_TSPARE3.eth8[0x7400]=0
CLMIB_TSPARE3.eth9[0x7400]=0
CLMIB_TSPARE3.eth10[0x7400]=0
CLMIB_TSPARE3.eth11[0x7400]=0
CLMIB_TSPARE3.eth12[0x7400]=0
CLMIB_TSPARE3.eth13[0x7400]=0
CLMIB_TSPARE3.eth14[0x7400]=0
CLMIB_TSPARE3.eth15[0x7400]=0
CLMIB_TSPARE3.eth16[0x7400]=0
CLMIB_TSPARE3.eth17[0x7400]=0
CLMIB_TSPARE3.eth18[0x7400]=0
CLMIB_TSPARE3.eth19[0x7400]=0
CLMIB_TSPARE3.eth20[0x7400]=0
CLMIB_TSPARE3.eth21[0x7400]=0
CLMIB_TSPARE3.eth22[0x7400]=0
CLMIB_TSPARE3.eth23[0x7400]=0
CLMIB_TSPARE3.eth24[0x7400]=0
CLMIB_TSPARE3.eth25[0x7400]=0
CLMIB_TSPARE3.eth26[0x7400]=0
CLMIB_TSPARE3.eth27[0x7400]=0
CLMIB_TSPARE3.eth28[0x7400]=0
CLMIB_TSPARE3.eth29[0x7400]=0
CLMIB_TSPARE3.eth30[0x7400]=0
CLMIB_TSPARE3.eth31[0x7400]=0
CLMIB_TSPARE3.eth32[0x7400]=0
CLMIB_TUCA.eth1[0x4d00]=0x5db46d120
CLMIB_TUCA.eth2[0x4d00]=0x2ba65e681
CLMIB_TUCA.eth3[0x4d00]=0x6f2292011
CLMIB_TUCA.eth4[0x4d00]=0x33d23bf61
CLMIB_TUCA.eth5[0x4d00]=0
CLMIB_TUCA.eth6[0x4d00]=0
CLMIB_TUCA.eth7[0x4d00]=0
CLMIB_TUCA.eth8[0x4d00]=0
CLMIB_TUCA.eth9[0x4d00]=0
CLMIB_TUCA.eth10[0x4d00]=0
CLMIB_TUCA.eth11[0x4d00]=0
CLMIB_TUCA.eth12[0x4d00]=0
CLMIB_TUCA.eth13[0x4d00]=0
CLMIB_TUCA.eth14[0x4d00]=0
CLMIB_TUCA.eth15[0x4d00]=0
CLMIB_TUCA.eth16[0x4d00]=0
CLMIB_TUCA.eth17[0x4d00]=0
CLMIB_TUCA.eth18[0x4d00]=0
CLMIB_TUCA.eth19[0x4d00]=0
CLMIB_TUCA.eth20[0x4d00]=0
CLMIB_TUCA.eth21[0x4d00]=0
CLMIB_TUCA.eth22[0x4d00]=0
CLMIB_TUCA.eth23[0x4d00]=0
CLMIB_TUCA.eth24[0x4d00]=0
CLMIB_TUCA.eth25[0x4d00]=0
CLMIB_TUCA.eth26[0x4d00]=0
CLMIB_TUCA.eth27[0x4d00]=0
CLMIB_TUCA.eth28[0x4d00]=0
CLMIB_TUCA.eth29[0x4d00]=0
CLMIB_TUCA.eth30[0x4d00]=0
CLMIB_TUCA.eth31[0x4d00]=0
CLMIB_TUCA.eth32[0x4d00]=0x8f3afcdc6
CLMIB_TUFL.eth1[0x6100]=0
CLMIB_TUFL.eth2[0x6100]=0
CLMIB_TUFL.eth3[0x6100]=0
CLMIB_TUFL.eth4[0x6100]=0
CLMIB_TUFL.eth5[0x6100]=0
CLMIB_TUFL.eth6[0x6100]=0
CLMIB_TUFL.eth7[0x6100]=0
CLMIB_TUFL.eth8[0x6100]=0
CLMIB_TUFL.eth9[0x6100]=0
CLMIB_TUFL.eth10[0x6100]=0
CLMIB_TUFL.eth11[0x6100]=0
CLMIB_TUFL.eth12[0x6100]=0
CLMIB_TUFL.eth13[0x6100]=0
CLMIB_TUFL.eth14[0x6100]=0
CLMIB_TUFL.eth15[0x6100]=0
CLMIB_TUFL.eth16[0x6100]=0
CLMIB_TUFL.eth17[0x6100]=0
CLMIB_TUFL.eth18[0x6100]=0
CLMIB_TUFL.eth19[0x6100]=0
CLMIB_TUFL.eth20[0x6100]=0
CLMIB_TUFL.eth21[0x6100]=0
CLMIB_TUFL.eth22[0x6100]=0
CLMIB_TUFL.eth23[0x6100]=0
CLMIB_TUFL.eth24[0x6100]=0
CLMIB_TUFL.eth25[0x6100]=0
CLMIB_TUFL.eth26[0x6100]=0
CLMIB_TUFL.eth27[0x6100]=0
CLMIB_TUFL.eth28[0x6100]=0
CLMIB_TUFL.eth29[0x6100]=0
CLMIB_TUFL.eth30[0x6100]=0
CLMIB_TUFL.eth31[0x6100]=0
CLMIB_TUFL.eth32[0x6100]=0
CLMIB_TVERIFY.eth1[0x5600]=0
CLMIB_TVERIFY.eth2[0x5600]=0
CLMIB_TVERIFY.eth3[0x5600]=0
CLMIB_TVERIFY.eth4[0x5600]=0
CLMIB_TVERIFY.eth5[0x5600]=0
CLMIB_TVERIFY.eth6[0x5600]=0
CLMIB_TVERIFY.eth7[0x5600]=0
CLMIB_TVERIFY.eth8[0x5600]=0
CLMIB_TVERIFY.eth9[0x5600]=0
CLMIB_TVERIFY.eth10[0x5600]=0
CLMIB_TVERIFY.eth11[0x5600]=0
CLMIB_TVERIFY.eth12[0x5600]=0
CLMIB_TVERIFY.eth13[0x5600]=0
CLMIB_TVERIFY.eth14[0x5600]=0
CLMIB_TVERIFY.eth15[0x5600]=0
CLMIB_TVERIFY.eth16[0x5600]=0
CLMIB_TVERIFY.eth17[0x5600]=0
CLMIB_TVERIFY.eth18[0x5600]=0
CLMIB_TVERIFY.eth19[0x5600]=0
CLMIB_TVERIFY.eth20[0x5600]=0
CLMIB_TVERIFY.eth21[0x5600]=0
CLMIB_TVERIFY.eth22[0x5600]=0
CLMIB_TVERIFY.eth23[0x5600]=0
CLMIB_TVERIFY.eth24[0x5600]=0
CLMIB_TVERIFY.eth25[0x5600]=0
CLMIB_TVERIFY.eth26[0x5600]=0
CLMIB_TVERIFY.eth27[0x5600]=0
CLMIB_TVERIFY.eth28[0x5600]=0
CLMIB_TVERIFY.eth29[0x5600]=0
CLMIB_TVERIFY.eth30[0x5600]=0
CLMIB_TVERIFY.eth31[0x5600]=0
CLMIB_TVERIFY.eth32[0x5600]=0
CLMIB_TVLN.eth1[0x5e00]=0x5db7ee8f3
CLMIB_TVLN.eth2[0x5e00]=0x2ba9613e9
CLMIB_TVLN.eth3[0x5e00]=0x6f25fd717
CLMIB_TVLN.eth4[0x5e00]=0x33d66f218
CLMIB_TVLN.eth5[0x5e00]=0
CLMIB_TVLN.eth6[0x5e00]=0
CLMIB_TVLN.eth7[0x5e00]=0
CLMIB_TVLN.eth8[0x5e00]=0
CLMIB_TVLN.eth9[0x5e00]=0
CLMIB_TVLN.eth10[0x5e00]=0
CLMIB_TVLN.eth11[0x5e00]=0
CLMIB_TVLN.eth12[0x5e00]=0
CLMIB_TVLN.eth13[0x5e00]=0
CLMIB_TVLN.eth14[0x5e00]=0
CLMIB_TVLN.eth15[0x5e00]=0
CLMIB_TVLN.eth16[0x5e00]=0
CLMIB_TVLN.eth17[0x5e00]=0
CLMIB_TVLN.eth18[0x5e00]=0
CLMIB_TVLN.eth19[0x5e00]=0
CLMIB_TVLN.eth20[0x5e00]=0
CLMIB_TVLN.eth21[0x5e00]=0
CLMIB_TVLN.eth22[0x5e00]=0
CLMIB_TVLN.eth23[0x5e00]=0
CLMIB_TVLN.eth24[0x5e00]=0
CLMIB_TVLN.eth25[0x5e00]=0
CLMIB_TVLN.eth26[0x5e00]=0
CLMIB_TVLN.eth27[0x5e00]=0
CLMIB_TVLN.eth28[0x5e00]=0
CLMIB_TVLN.eth29[0x5e00]=0
CLMIB_TVLN.eth30[0x5e00]=0
CLMIB_TVLN.eth31[0x5e00]=0
CLMIB_TVLN.eth32[0x5e00]=0x8f708beca
CLMIB_TXCF.eth1[0x5400]=0
CLMIB_TXCF.eth2[0x5400]=0
CLMIB_TXCF.eth3[0x5400]=0
CLMIB_TXCF.eth4[0x5400]=0
CLMIB_TXCF.eth5[0x5400]=0
CLMIB_TXCF.eth6[0x5400]=0
CLMIB_TXCF.eth7[0x5400]=0
CLMIB_TXCF.eth8[0x5400]=0
CLMIB_TXCF.eth9[0x5400]=0
CLMIB_TXCF.eth10[0x5400]=0
CLMIB_TXCF.eth11[0x5400]=0
CLMIB_TXCF.eth12[0x5400]=0
CLMIB_TXCF.eth13[0x5400]=0
CLMIB_TXCF.eth14[0x5400]=0
CLMIB_TXCF.eth15[0x5400]=0
CLMIB_TXCF.eth16[0x5400]=0
CLMIB_TXCF.eth17[0x5400]=0
CLMIB_TXCF.eth18[0x5400]=0
CLMIB_TXCF.eth19[0x5400]=0
CLMIB_TXCF.eth20[0x5400]=0
CLMIB_TXCF.eth21[0x5400]=0
CLMIB_TXCF.eth22[0x5400]=0
CLMIB_TXCF.eth23[0x5400]=0
CLMIB_TXCF.eth24[0x5400]=0
CLMIB_TXCF.eth25[0x5400]=0
CLMIB_TXCF.eth26[0x5400]=0
CLMIB_TXCF.eth27[0x5400]=0
CLMIB_TXCF.eth28[0x5400]=0
CLMIB_TXCF.eth29[0x5400]=0
CLMIB_TXCF.eth30[0x5400]=0
CLMIB_TXCF.eth31[0x5400]=0
CLMIB_TXCF.eth32[0x5400]=0
CLMIB_TXCL.eth1[0x5b00]=0
CLMIB_TXCL.eth2[0x5b00]=0
CLMIB_TXCL.eth3[0x5b00]=0
CLMIB_TXCL.eth4[0x5b00]=0
CLMIB_TXCL.eth5[0x5b00]=0
CLMIB_TXCL.eth6[0x5b00]=0
CLMIB_TXCL.eth7[0x5b00]=0
CLMIB_TXCL.eth8[0x5b00]=0
CLMIB_TXCL.eth9[0x5b00]=0
CLMIB_TXCL.eth10[0x5b00]=0
CLMIB_TXCL.eth11[0x5b00]=0
CLMIB_TXCL.eth12[0x5b00]=0
CLMIB_TXCL.eth13[0x5b00]=0
CLMIB_TXCL.eth14[0x5b00]=0
CLMIB_TXCL.eth15[0x5b00]=0
CLMIB_TXCL.eth16[0x5b00]=0
CLMIB_TXCL.eth17[0x5b00]=0
CLMIB_TXCL.eth18[0x5b00]=0
CLMIB_TXCL.eth19[0x5b00]=0
CLMIB_TXCL.eth20[0x5b00]=0
CLMIB_TXCL.eth21[0x5b00]=0
CLMIB_TXCL.eth22[0x5b00]=0
CLMIB_TXCL.eth23[0x5b00]=0
CLMIB_TXCL.eth24[0x5b00]=0
CLMIB_TXCL.eth25[0x5b00]=0
CLMIB_TXCL.eth26[0x5b00]=0
CLMIB_TXCL.eth27[0x5b00]=0
CLMIB_TXCL.eth28[0x5b00]=0
CLMIB_TXCL.eth29[0x5b00]=0
CLMIB_TXCL.eth30[0x5b00]=0
CLMIB_TXCL.eth31[0x5b00]=0
CLMIB_TXCL.eth32[0x5b00]=0
CLMIB_TXPF.eth1[0x5000]=0
CLMIB_TXPF.eth2[0x5000]=0
CLMIB_TXPF.eth3[0x5000]=0
CLMIB_TXPF.eth4[0x5000]=0
CLMIB_TXPF.eth5[0x5000]=0
CLMIB_TXPF.eth6[0x5000]=0
CLMIB_TXPF.eth7[0x5000]=0
CLMIB_TXPF.eth8[0x5000]=0
CLMIB_TXPF.eth9[0x5000]=0
CLMIB_TXPF.eth10[0x5000]=0
CLMIB_TXPF.eth11[0x5000]=0
CLMIB_TXPF.eth12[0x5000]=0
CLMIB_TXPF.eth13[0x5000]=0
CLMIB_TXPF.eth14[0x5000]=0
CLMIB_TXPF.eth15[0x5000]=0
CLMIB_TXPF.eth16[0x5000]=0
CLMIB_TXPF.eth17[0x5000]=0
CLMIB_TXPF.eth18[0x5000]=0
CLMIB_TXPF.eth19[0x5000]=0
CLMIB_TXPF.eth20[0x5000]=0
CLMIB_TXPF.eth21[0x5000]=0
CLMIB_TXPF.eth22[0x5000]=0
CLMIB_TXPF.eth23[0x5000]=0
CLMIB_TXPF.eth24[0x5000]=0
CLMIB_TXPF.eth25[0x5000]=0
CLMIB_TXPF.eth26[0x5000]=0
CLMIB_TXPF.eth27[0x5000]=0
CLMIB_TXPF.eth28[0x5000]=0
CLMIB_TXPF.eth29[0x5000]=0
CLMIB_TXPF.eth30[0x5000]=0
CLMIB_TXPF.eth31[0x5000]=0
CLMIB_TXPF.eth32[0x5000]=0
CLMIB_TXPP.eth1[0x5100]=0
CLMIB_TXPP.eth2[0x5100]=0
CLMIB_TXPP.eth3[0x5100]=0
CLMIB_TXPP.eth4[0x5100]=0
CLMIB_TXPP.eth5[0x5100]=0
CLMIB_TXPP.eth6[0x5100]=0
CLMIB_TXPP.eth7[0x5100]=0
CLMIB_TXPP.eth8[0x5100]=0
CLMIB_TXPP.eth9[0x5100]=0
CLMIB_TXPP.eth10[0x5100]=0
CLMIB_TXPP.eth11[0x5100]=0
CLMIB_TXPP.eth12[0x5100]=0
CLMIB_TXPP.eth13[0x5100]=0
CLMIB_TXPP.eth14[0x5100]=0
CLMIB_TXPP.eth15[0x5100]=0
CLMIB_TXPP.eth16[0x5100]=0
CLMIB_TXPP.eth17[0x5100]=0
CLMIB_TXPP.eth18[0x5100]=0
CLMIB_TXPP.eth19[0x5100]=0
CLMIB_TXPP.eth20[0x5100]=0
CLMIB_TXPP.eth21[0x5100]=0
CLMIB_TXPP.eth22[0x5100]=0
CLMIB_TXPP.eth23[0x5100]=0
CLMIB_TXPP.eth24[0x5100]=0
CLMIB_TXPP.eth25[0x5100]=0
CLMIB_TXPP.eth26[0x5100]=0
CLMIB_TXPP.eth27[0x5100]=0
CLMIB_TXPP.eth28[0x5100]=0
CLMIB_TXPP.eth29[0x5100]=0
CLMIB_TXPP.eth30[0x5100]=0
CLMIB_TXPP.eth31[0x5100]=0
CLMIB_TXPP.eth32[0x5100]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth1[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth2[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth3[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth4[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth5[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth6[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth7[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth8[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth9[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth10[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth11[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth12[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth13[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth14[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth15[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth16[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth17[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth18[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth19[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth20[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth21[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth22[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth23[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth24[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth25[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth26[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth27[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth28[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth29[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth30[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth31[0x6b00]=0
CLMIB_TX_EEE_LPI_DURATION_COUNTER.eth32[0x6b00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth1[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth2[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth3[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth4[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth5[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth6[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth7[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth8[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth9[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth10[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth11[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth12[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth13[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth14[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth15[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth16[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth17[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth18[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth19[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth20[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth21[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth22[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth23[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth24[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth25[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth26[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth27[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth28[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth29[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth30[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth31[0x6a00]=0
CLMIB_TX_EEE_LPI_EVENT_COUNTER.eth32[0x6a00]=0
CLMIB_TX_HCFC_COUNTER.eth1[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth2[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth3[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth4[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth5[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth6[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth7[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth8[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth9[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth10[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth11[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth12[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth13[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth14[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth15[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth16[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth17[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth18[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth19[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth20[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth21[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth22[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth23[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth24[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth25[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth26[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth27[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth28[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth29[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth30[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth31[0x6d00]=0
CLMIB_TX_HCFC_COUNTER.eth32[0x6d00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth1[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth2[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth3[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth4[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth5[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth6[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth7[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth8[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth9[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth10[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth11[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth12[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth13[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth14[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth15[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth16[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth17[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth18[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth19[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth20[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth21[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth22[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth23[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth24[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth25[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth26[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth27[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth28[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth29[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth30[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth31[0x6c00]=0
CLMIB_TX_LLFC_LOG_COUNTER.eth32[0x6c00]=0
CLMIB_XTHOL.eth1[0x7000]=0
CLMIB_XTHOL.eth2[0x7000]=0
CLMIB_XTHOL.eth3[0x7000]=0
CLMIB_XTHOL.eth4[0x7000]=0
CLMIB_XTHOL.eth5[0x7000]=0
CLMIB_XTHOL.eth6[0x7000]=0
CLMIB_XTHOL.eth7[0x7000]=0
CLMIB_XTHOL.eth8[0x7000]=0
CLMIB_XTHOL.eth9[0x7000]=0
CLMIB_XTHOL.eth10[0x7000]=0
CLMIB_XTHOL.eth11[0x7000]=0
CLMIB_XTHOL.eth12[0x7000]=0
CLMIB_XTHOL.eth13[0x7000]=0
CLMIB_XTHOL.eth14[0x7000]=0
CLMIB_XTHOL.eth15[0x7000]=0
CLMIB_XTHOL.eth16[0x7000]=0
CLMIB_XTHOL.eth17[0x7000]=0
CLMIB_XTHOL.eth18[0x7000]=0
CLMIB_XTHOL.eth19[0x7000]=0
CLMIB_XTHOL.eth20[0x7000]=0
CLMIB_XTHOL.eth21[0x7000]=0
CLMIB_XTHOL.eth22[0x7000]=0
CLMIB_XTHOL.eth23[0x7000]=0
CLMIB_XTHOL.eth24[0x7000]=0
CLMIB_XTHOL.eth25[0x7000]=0
CLMIB_XTHOL.eth26[0x7000]=0
CLMIB_XTHOL.eth27[0x7000]=0
CLMIB_XTHOL.eth28[0x7000]=0
CLMIB_XTHOL.eth29[0x7000]=0
CLMIB_XTHOL.eth30[0x7000]=0
CLMIB_XTHOL.eth31[0x7000]=0
CLMIB_XTHOL.eth32[0x7000]=0
CLPORT_CNTMAXSIZE.eth1[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth2[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth3[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth4[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth5[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth6[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth7[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth8[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth9[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth10[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth11[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth12[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth13[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth14[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth15[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth16[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth17[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth18[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth19[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth20[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth21[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth22[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth23[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth24[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth25[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth26[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth27[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth28[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth29[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth30[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth31[0x20100]=0x5ee
CLPORT_CNTMAXSIZE.eth32[0x20100]=0x5ee
CLPORT_CONFIG.eth1[0x20000]=0
CLPORT_CONFIG.eth2[0x20000]=0
CLPORT_CONFIG.eth3[0x20000]=0
CLPORT_CONFIG.eth4[0x20000]=0
CLPORT_CONFIG.eth5[0x20000]=0
CLPORT_CONFIG.eth6[0x20000]=0
CLPORT_CONFIG.eth7[0x20000]=0
CLPORT_CONFIG.eth8[0x20000]=0
CLPORT_CONFIG.eth9[0x20000]=0
CLPORT_CONFIG.eth10[0x20000]=0
CLPORT_CONFIG.eth11[0x20000]=0
CLPORT_CONFIG.eth12[0x20000]=0
CLPORT_CONFIG.eth13[0x20000]=0
CLPORT_CONFIG.eth14[0x20000]=0
CLPORT_CONFIG.eth15[0x20000]=0
CLPORT_CONFIG.eth16[0x20000]=0
CLPORT_CONFIG.eth17[0x20000]=0
CLPORT_CONFIG.eth18[0x20000]=0
CLPORT_CONFIG.eth19[0x20000]=0
CLPORT_CONFIG.eth20[0x20000]=0
CLPORT_CONFIG.eth21[0x20000]=0
CLPORT_CONFIG.eth22[0x20000]=0
CLPORT_CONFIG.eth23[0x20000]=0
CLPORT_CONFIG.eth24[0x20000]=0
CLPORT_CONFIG.eth25[0x20000]=0
CLPORT_CONFIG.eth26[0x20000]=0
CLPORT_CONFIG.eth27[0x20000]=0
CLPORT_CONFIG.eth28[0x20000]=0
CLPORT_CONFIG.eth29[0x20000]=0
CLPORT_CONFIG.eth30[0x20000]=0
CLPORT_CONFIG.eth31[0x20000]=0
CLPORT_CONFIG.eth32[0x20000]=0
CLPORT_ECC_CONTROL.CLPORT0[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT1[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT2[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT3[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT4[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT5[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT6[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT7[0x2021a00]=0
CLPORT_ECC_CONTROL.CLPORT8[0x2021a00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT0[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT1[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT2[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT3[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT4[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT5[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT6[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT7[0x2020e00]=0
CLPORT_EEE_CLOCK_GATE.CLPORT8[0x2020e00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT0[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT1[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT2[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT3[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT4[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT5[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT6[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT7[0x2020f00]=0
CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER.CLPORT8[0x2020f00]=0
CLPORT_EEE_COUNTER_MODE.eth1[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth2[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth3[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth4[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth5[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth6[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth7[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth8[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth9[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth10[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth11[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth12[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth13[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth14[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth15[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth16[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth17[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth18[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth19[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth20[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth21[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth22[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth23[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth24[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth25[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth26[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth27[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth28[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth29[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth30[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth31[0x20300]=0
CLPORT_EEE_COUNTER_MODE.eth32[0x20300]=0
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT0[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT1[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT2[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT3[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT4[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT5[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT6[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT7[0x2021200]=0xec
CLPORT_EEE_DURATION_TIMER_PULSE.CLPORT8[0x2021200]=0xec
CLPORT_ENABLE_REG.CLPORT0[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT1[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT2[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT3[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT4[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT5[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT6[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT7[0x2020b00]=0xf
CLPORT_ENABLE_REG.CLPORT8[0x2020b00]=0
CLPORT_FAULT_LINK_STATUS.eth1[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth2[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth3[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth4[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth5[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth6[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth7[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth8[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth9[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth10[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth11[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth12[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth13[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth14[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth15[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth16[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth17[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth18[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth19[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth20[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth21[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth22[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth23[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth24[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth25[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth26[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth27[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth28[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth29[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth30[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth31[0x20500]=3
CLPORT_FAULT_LINK_STATUS.eth32[0x20500]=3
CLPORT_FLOW_CONTROL_CONFIG.eth1[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth2[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth3[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth4[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth5[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth6[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth7[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth8[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth9[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth10[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth11[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth12[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth13[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth14[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth15[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth16[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth17[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth18[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth19[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth20[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth21[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth22[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth23[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth24[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth25[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth26[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth27[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth28[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth29[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth30[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth31[0x20700]=0
CLPORT_FLOW_CONTROL_CONFIG.eth32[0x20700]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT0[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT1[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT2[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT3[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT4[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT5[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT6[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT7[0x2021b00]=0
CLPORT_FORCE_DOUBLE_BIT_ERROR.CLPORT8[0x2021b00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT0[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT1[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT2[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT3[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT4[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT5[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT6[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT7[0x2021c00]=0
CLPORT_FORCE_SINGLE_BIT_ERROR.CLPORT8[0x2021c00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT0[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT1[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT2[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT3[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT4[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT5[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT6[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT7[0x2022e00]=0
CLPORT_GENERAL_SPARE1_REG.CLPORT8[0x2022e00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT0[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT1[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT2[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT3[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT4[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT5[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT6[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT7[0x2022f00]=0
CLPORT_GENERAL_SPARE2_REG.CLPORT8[0x2022f00]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT0[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT1[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT2[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT3[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT4[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT5[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT6[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT7[0x2023000]=0
CLPORT_GENERAL_SPARE3_REG.CLPORT8[0x2023000]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT0[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT1[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT2[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT3[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT4[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT5[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT6[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT7[0x2024f00]=0
CLPORT_GENERAL_SPARE6_REG.CLPORT8[0x2024f00]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT0[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT1[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT2[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT3[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT4[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT5[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT6[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT7[0x2025000]=0
CLPORT_GENERAL_SPARE7_REG.CLPORT8[0x2025000]=0
CLPORT_INTR_ENABLE.CLPORT0[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT1[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT2[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT3[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT4[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT5[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT6[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT7[0x2022a00]=0
CLPORT_INTR_ENABLE.CLPORT8[0x2022a00]=0
CLPORT_INTR_STATUS.CLPORT0[0x2022900]=0x18000
CLPORT_INTR_STATUS.CLPORT1[0x2022900]=0x18000
CLPORT_INTR_STATUS.CLPORT2[0x2022900]=0
CLPORT_INTR_STATUS.CLPORT3[0x2022900]=0
CLPORT_INTR_STATUS.CLPORT4[0x2022900]=0
CLPORT_INTR_STATUS.CLPORT5[0x2022900]=0
CLPORT_INTR_STATUS.CLPORT6[0x2022900]=0
CLPORT_INTR_STATUS.CLPORT7[0x2022900]=0x40000
CLPORT_INTR_STATUS.CLPORT8[0x2022900]=0
CLPORT_LAG_FAILOVER_CONFIG.eth1[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth2[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth3[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth4[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth5[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth6[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth7[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth8[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth9[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth10[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth11[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth12[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth13[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth14[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth15[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth16[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth17[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth18[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth19[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth20[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth21[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth22[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth23[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth24[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth25[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth26[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth27[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth28[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth29[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth30[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth31[0x20200]=0
CLPORT_LAG_FAILOVER_CONFIG.eth32[0x20200]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT0[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT1[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT2[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT3[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT4[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT5[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT6[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT7[0x2022300]=0
CLPORT_LED_CHAIN_CONFIG.CLPORT8[0x2022300]=0
CLPORT_LINKSTATUS_DOWN.CLPORT0[0x2022700]=3
CLPORT_LINKSTATUS_DOWN.CLPORT1[0x2022700]=3
CLPORT_LINKSTATUS_DOWN.CLPORT2[0x2022700]=0
CLPORT_LINKSTATUS_DOWN.CLPORT3[0x2022700]=0
CLPORT_LINKSTATUS_DOWN.CLPORT4[0x2022700]=0
CLPORT_LINKSTATUS_DOWN.CLPORT5[0x2022700]=0
CLPORT_LINKSTATUS_DOWN.CLPORT6[0x2022700]=0
CLPORT_LINKSTATUS_DOWN.CLPORT7[0x2022700]=8
CLPORT_LINKSTATUS_DOWN.CLPORT8[0x2022700]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT0[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT1[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT2[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT3[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT4[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT5[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT6[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT7[0x2022800]=0
CLPORT_LINKSTATUS_DOWN_CLEAR.CLPORT8[0x2022800]=0
CLPORT_MAC_CONTROL.CLPORT0[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT1[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT2[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT3[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT4[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT5[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT6[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT7[0x2021000]=0x40
CLPORT_MAC_CONTROL.CLPORT8[0x2021000]=1
CLPORT_MAC_RSV_MASK.eth1[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth2[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth3[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth4[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth5[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth6[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth7[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth8[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth9[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth10[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth11[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth12[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth13[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth14[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth15[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth16[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth17[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth18[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth19[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth20[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth21[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth22[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth23[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth24[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth25[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth26[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth27[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth28[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth29[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth30[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth31[0x20800]=0x20858
CLPORT_MAC_RSV_MASK.eth32[0x20800]=0x20858
CLPORT_MIB_MIN_FRAG_SIZE.eth1[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth2[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth3[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth4[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth5[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth6[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth7[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth8[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth9[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth10[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth11[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth12[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth13[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth14[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth15[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth16[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth17[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth18[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth19[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth20[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth21[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth22[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth23[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth24[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth25[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth26[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth27[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth28[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth29[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth30[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth31[0x23500]=0x808
CLPORT_MIB_MIN_FRAG_SIZE.eth32[0x23500]=0x808
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth1[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth2[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth3[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth4[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth5[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth6[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth7[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth8[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth9[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth10[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth11[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth12[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth13[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth14[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth15[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth16[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth17[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth18[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth19[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth20[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth21[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth22[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth23[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth24[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth25[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth26[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth27[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth28[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth29[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth30[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth31[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG.eth32[0x23100]=0x4f0040
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth1[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth2[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth3[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth4[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth5[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth6[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth7[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth8[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth9[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth10[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth11[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth12[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth13[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth14[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth15[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth16[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth17[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth18[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth19[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth20[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth21[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth22[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth23[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth24[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth25[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth26[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth27[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth28[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth29[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth30[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth31[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG.eth32[0x23200]=0x5f0050
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth1[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth2[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth3[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth4[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth5[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth6[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth7[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth8[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth9[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth10[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth11[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth12[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth13[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth14[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth15[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth16[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth17[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth18[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth19[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth20[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth21[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth22[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth23[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth24[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth25[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth26[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth27[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth28[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth29[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth30[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth31[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG.eth32[0x23300]=0x6f0060
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth1[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth2[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth3[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth4[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth5[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth6[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth7[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth8[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth9[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth10[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth11[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth12[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth13[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth14[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth15[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth16[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth17[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth18[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth19[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth20[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth21[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth22[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth23[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth24[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth25[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth26[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth27[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth28[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth29[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth30[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth31[0x23400]=0x7f0070
CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG.eth32[0x23400]=0x7f0070
CLPORT_MIB_RESET.CLPORT0[0x2022400]=0
CLPORT_MIB_RESET.CLPORT1[0x2022400]=0
CLPORT_MIB_RESET.CLPORT2[0x2022400]=0
CLPORT_MIB_RESET.CLPORT3[0x2022400]=0
CLPORT_MIB_RESET.CLPORT4[0x2022400]=0
CLPORT_MIB_RESET.CLPORT5[0x2022400]=0
CLPORT_MIB_RESET.CLPORT6[0x2022400]=0
CLPORT_MIB_RESET.CLPORT7[0x2022400]=0
CLPORT_MIB_RESET.CLPORT8[0x2022400]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT0[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT1[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT2[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT3[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT4[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT5[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT6[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT7[0x2021d00]=0
CLPORT_MIB_RSC0_ECC_STATUS.CLPORT8[0x2021d00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT0[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT1[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT2[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT3[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT4[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT5[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT6[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT7[0x2021e00]=0
CLPORT_MIB_RSC1_ECC_STATUS.CLPORT8[0x2021e00]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT0[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT1[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT2[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT3[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT4[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT5[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT6[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT7[0x2022200]=0
CLPORT_MIB_RSC_RAM_CONTROL.CLPORT8[0x2022200]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT0[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT1[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT2[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT3[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT4[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT5[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT6[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT7[0x2021f00]=0
CLPORT_MIB_TSC0_ECC_STATUS.CLPORT8[0x2021f00]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT0[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT1[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT2[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT3[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT4[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT5[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT6[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT7[0x2022000]=0
CLPORT_MIB_TSC1_ECC_STATUS.CLPORT8[0x2022000]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT0[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT1[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT2[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT3[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT4[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT5[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT6[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT7[0x2022100]=0
CLPORT_MIB_TSC_RAM_CONTROL.CLPORT8[0x2022100]=0
CLPORT_MODE_REG.CLPORT0[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT1[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT2[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT3[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT4[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT5[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT6[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT7[0x2020a00]=0x200
CLPORT_MODE_REG.CLPORT8[0x2020a00]=0x200
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT0[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT1[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT2[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT3[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT4[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT5[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT6[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT7[0x2024d00]=0
CLPORT_PMD_PLL0_CTRL_CONFIG.CLPORT8[0x2024d00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT0[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT1[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT2[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT3[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT4[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT5[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT6[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT7[0x2024e00]=0
CLPORT_PMD_PLL1_CTRL_CONFIG.CLPORT8[0x2024e00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT0[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT1[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT2[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT3[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT4[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT5[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT6[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT7[0x2022c00]=0
CLPORT_PMD_PLL_CTRL_CONFIG.CLPORT8[0x2022c00]=0
CLPORT_PM_VERSION_ID.CLPORT0[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT1[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT2[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT3[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT4[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT5[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT6[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT7[0x2022d00]=0x16
CLPORT_PM_VERSION_ID.CLPORT8[0x2022d00]=0x16
CLPORT_PORT_SPARE0.eth1[0x23600]=0
CLPORT_PORT_SPARE0.eth2[0x23600]=0
CLPORT_PORT_SPARE0.eth3[0x23600]=0
CLPORT_PORT_SPARE0.eth4[0x23600]=0
CLPORT_PORT_SPARE0.eth5[0x23600]=0
CLPORT_PORT_SPARE0.eth6[0x23600]=0
CLPORT_PORT_SPARE0.eth7[0x23600]=0
CLPORT_PORT_SPARE0.eth8[0x23600]=0
CLPORT_PORT_SPARE0.eth9[0x23600]=0
CLPORT_PORT_SPARE0.eth10[0x23600]=0
CLPORT_PORT_SPARE0.eth11[0x23600]=0
CLPORT_PORT_SPARE0.eth12[0x23600]=0
CLPORT_PORT_SPARE0.eth13[0x23600]=0
CLPORT_PORT_SPARE0.eth14[0x23600]=0
CLPORT_PORT_SPARE0.eth15[0x23600]=0
CLPORT_PORT_SPARE0.eth16[0x23600]=0
CLPORT_PORT_SPARE0.eth17[0x23600]=0
CLPORT_PORT_SPARE0.eth18[0x23600]=0
CLPORT_PORT_SPARE0.eth19[0x23600]=0
CLPORT_PORT_SPARE0.eth20[0x23600]=0
CLPORT_PORT_SPARE0.eth21[0x23600]=0
CLPORT_PORT_SPARE0.eth22[0x23600]=0
CLPORT_PORT_SPARE0.eth23[0x23600]=0
CLPORT_PORT_SPARE0.eth24[0x23600]=0
CLPORT_PORT_SPARE0.eth25[0x23600]=0
CLPORT_PORT_SPARE0.eth26[0x23600]=0
CLPORT_PORT_SPARE0.eth27[0x23600]=0
CLPORT_PORT_SPARE0.eth28[0x23600]=0
CLPORT_PORT_SPARE0.eth29[0x23600]=0
CLPORT_PORT_SPARE0.eth30[0x23600]=0
CLPORT_PORT_SPARE0.eth31[0x23600]=0
CLPORT_PORT_SPARE0.eth32[0x23600]=0
CLPORT_PORT_SPARE1.eth1[0x23700]=0
CLPORT_PORT_SPARE1.eth2[0x23700]=0
CLPORT_PORT_SPARE1.eth3[0x23700]=0
CLPORT_PORT_SPARE1.eth4[0x23700]=0
CLPORT_PORT_SPARE1.eth5[0x23700]=0
CLPORT_PORT_SPARE1.eth6[0x23700]=0
CLPORT_PORT_SPARE1.eth7[0x23700]=0
CLPORT_PORT_SPARE1.eth8[0x23700]=0
CLPORT_PORT_SPARE1.eth9[0x23700]=0
CLPORT_PORT_SPARE1.eth10[0x23700]=0
CLPORT_PORT_SPARE1.eth11[0x23700]=0
CLPORT_PORT_SPARE1.eth12[0x23700]=0
CLPORT_PORT_SPARE1.eth13[0x23700]=0
CLPORT_PORT_SPARE1.eth14[0x23700]=0
CLPORT_PORT_SPARE1.eth15[0x23700]=0
CLPORT_PORT_SPARE1.eth16[0x23700]=0
CLPORT_PORT_SPARE1.eth17[0x23700]=0
CLPORT_PORT_SPARE1.eth18[0x23700]=0
CLPORT_PORT_SPARE1.eth19[0x23700]=0
CLPORT_PORT_SPARE1.eth20[0x23700]=0
CLPORT_PORT_SPARE1.eth21[0x23700]=0
CLPORT_PORT_SPARE1.eth22[0x23700]=0
CLPORT_PORT_SPARE1.eth23[0x23700]=0
CLPORT_PORT_SPARE1.eth24[0x23700]=0
CLPORT_PORT_SPARE1.eth25[0x23700]=0
CLPORT_PORT_SPARE1.eth26[0x23700]=0
CLPORT_PORT_SPARE1.eth27[0x23700]=0
CLPORT_PORT_SPARE1.eth28[0x23700]=0
CLPORT_PORT_SPARE1.eth29[0x23700]=0
CLPORT_PORT_SPARE1.eth30[0x23700]=0
CLPORT_PORT_SPARE1.eth31[0x23700]=0
CLPORT_PORT_SPARE1.eth32[0x23700]=0
CLPORT_PORT_SPARE2.eth1[0x23800]=0
CLPORT_PORT_SPARE2.eth2[0x23800]=0
CLPORT_PORT_SPARE2.eth3[0x23800]=0
CLPORT_PORT_SPARE2.eth4[0x23800]=0
CLPORT_PORT_SPARE2.eth5[0x23800]=0
CLPORT_PORT_SPARE2.eth6[0x23800]=0
CLPORT_PORT_SPARE2.eth7[0x23800]=0
CLPORT_PORT_SPARE2.eth8[0x23800]=0
CLPORT_PORT_SPARE2.eth9[0x23800]=0
CLPORT_PORT_SPARE2.eth10[0x23800]=0
CLPORT_PORT_SPARE2.eth11[0x23800]=0
CLPORT_PORT_SPARE2.eth12[0x23800]=0
CLPORT_PORT_SPARE2.eth13[0x23800]=0
CLPORT_PORT_SPARE2.eth14[0x23800]=0
CLPORT_PORT_SPARE2.eth15[0x23800]=0
CLPORT_PORT_SPARE2.eth16[0x23800]=0
CLPORT_PORT_SPARE2.eth17[0x23800]=0
CLPORT_PORT_SPARE2.eth18[0x23800]=0
CLPORT_PORT_SPARE2.eth19[0x23800]=0
CLPORT_PORT_SPARE2.eth20[0x23800]=0
CLPORT_PORT_SPARE2.eth21[0x23800]=0
CLPORT_PORT_SPARE2.eth22[0x23800]=0
CLPORT_PORT_SPARE2.eth23[0x23800]=0
CLPORT_PORT_SPARE2.eth24[0x23800]=0
CLPORT_PORT_SPARE2.eth25[0x23800]=0
CLPORT_PORT_SPARE2.eth26[0x23800]=0
CLPORT_PORT_SPARE2.eth27[0x23800]=0
CLPORT_PORT_SPARE2.eth28[0x23800]=0
CLPORT_PORT_SPARE2.eth29[0x23800]=0
CLPORT_PORT_SPARE2.eth30[0x23800]=0
CLPORT_PORT_SPARE2.eth31[0x23800]=0
CLPORT_PORT_SPARE2.eth32[0x23800]=0
CLPORT_PORT_SPARE3.eth1[0x23900]=0
CLPORT_PORT_SPARE3.eth2[0x23900]=0
CLPORT_PORT_SPARE3.eth3[0x23900]=0
CLPORT_PORT_SPARE3.eth4[0x23900]=0
CLPORT_PORT_SPARE3.eth5[0x23900]=0
CLPORT_PORT_SPARE3.eth6[0x23900]=0
CLPORT_PORT_SPARE3.eth7[0x23900]=0
CLPORT_PORT_SPARE3.eth8[0x23900]=0
CLPORT_PORT_SPARE3.eth9[0x23900]=0
CLPORT_PORT_SPARE3.eth10[0x23900]=0
CLPORT_PORT_SPARE3.eth11[0x23900]=0
CLPORT_PORT_SPARE3.eth12[0x23900]=0
CLPORT_PORT_SPARE3.eth13[0x23900]=0
CLPORT_PORT_SPARE3.eth14[0x23900]=0
CLPORT_PORT_SPARE3.eth15[0x23900]=0
CLPORT_PORT_SPARE3.eth16[0x23900]=0
CLPORT_PORT_SPARE3.eth17[0x23900]=0
CLPORT_PORT_SPARE3.eth18[0x23900]=0
CLPORT_PORT_SPARE3.eth19[0x23900]=0
CLPORT_PORT_SPARE3.eth20[0x23900]=0
CLPORT_PORT_SPARE3.eth21[0x23900]=0
CLPORT_PORT_SPARE3.eth22[0x23900]=0
CLPORT_PORT_SPARE3.eth23[0x23900]=0
CLPORT_PORT_SPARE3.eth24[0x23900]=0
CLPORT_PORT_SPARE3.eth25[0x23900]=0
CLPORT_PORT_SPARE3.eth26[0x23900]=0
CLPORT_PORT_SPARE3.eth27[0x23900]=0
CLPORT_PORT_SPARE3.eth28[0x23900]=0
CLPORT_PORT_SPARE3.eth29[0x23900]=0
CLPORT_PORT_SPARE3.eth30[0x23900]=0
CLPORT_PORT_SPARE3.eth31[0x23900]=0
CLPORT_PORT_SPARE3.eth32[0x23900]=0
CLPORT_POWER_SAVE.CLPORT0[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT1[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT2[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT3[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT4[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT5[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT6[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT7[0x2020d00]=0
CLPORT_POWER_SAVE.CLPORT8[0x2020d00]=0
CLPORT_SBUS_CONTROL.CLPORT0[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT1[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT2[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT3[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT4[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT5[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT6[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT7[0x2022b00]=0x7f
CLPORT_SBUS_CONTROL.CLPORT8[0x2022b00]=0x7f
CLPORT_SGNDET_EARLYCRS.eth1[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth2[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth3[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth4[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth5[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth6[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth7[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth8[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth9[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth10[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth11[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth12[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth13[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth14[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth15[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth16[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth17[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth18[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth19[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth20[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth21[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth22[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth23[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth24[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth25[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth26[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth27[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth28[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth29[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth30[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth31[0x20400]=0
CLPORT_SGNDET_EARLYCRS.eth32[0x20400]=0
CLPORT_SOFT_RESET.CLPORT0[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT1[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT2[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT3[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT4[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT5[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT6[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT7[0x2020c00]=0
CLPORT_SOFT_RESET.CLPORT8[0x2020c00]=0
CLPORT_SPARE0_REG.eth1[0x20900]=0
CLPORT_SPARE0_REG.eth2[0x20900]=0
CLPORT_SPARE0_REG.eth3[0x20900]=0
CLPORT_SPARE0_REG.eth4[0x20900]=0
CLPORT_SPARE0_REG.eth5[0x20900]=0
CLPORT_SPARE0_REG.eth6[0x20900]=0
CLPORT_SPARE0_REG.eth7[0x20900]=0
CLPORT_SPARE0_REG.eth8[0x20900]=0
CLPORT_SPARE0_REG.eth9[0x20900]=0
CLPORT_SPARE0_REG.eth10[0x20900]=0
CLPORT_SPARE0_REG.eth11[0x20900]=0
CLPORT_SPARE0_REG.eth12[0x20900]=0
CLPORT_SPARE0_REG.eth13[0x20900]=0
CLPORT_SPARE0_REG.eth14[0x20900]=0
CLPORT_SPARE0_REG.eth15[0x20900]=0
CLPORT_SPARE0_REG.eth16[0x20900]=0
CLPORT_SPARE0_REG.eth17[0x20900]=0
CLPORT_SPARE0_REG.eth18[0x20900]=0
CLPORT_SPARE0_REG.eth19[0x20900]=0
CLPORT_SPARE0_REG.eth20[0x20900]=0
CLPORT_SPARE0_REG.eth21[0x20900]=0
CLPORT_SPARE0_REG.eth22[0x20900]=0
CLPORT_SPARE0_REG.eth23[0x20900]=0
CLPORT_SPARE0_REG.eth24[0x20900]=0
CLPORT_SPARE0_REG.eth25[0x20900]=0
CLPORT_SPARE0_REG.eth26[0x20900]=0
CLPORT_SPARE0_REG.eth27[0x20900]=0
CLPORT_SPARE0_REG.eth28[0x20900]=0
CLPORT_SPARE0_REG.eth29[0x20900]=0
CLPORT_SPARE0_REG.eth30[0x20900]=0
CLPORT_SPARE0_REG.eth31[0x20900]=0
CLPORT_SPARE0_REG.eth32[0x20900]=0
CLPORT_SW_FLOW_CONTROL.eth1[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth2[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth3[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth4[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth5[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth6[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth7[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth8[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth9[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth10[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth11[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth12[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth13[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth14[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth15[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth16[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth17[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth18[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth19[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth20[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth21[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth22[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth23[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth24[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth25[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth26[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth27[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth28[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth29[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth30[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth31[0x20600]=0
CLPORT_SW_FLOW_CONTROL.eth32[0x20600]=0
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT0[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT1[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT2[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT3[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT4[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT5[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT6[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT7[0x2021300]=1
CLPORT_TSC_PLL_LOCK_STATUS.CLPORT8[0x2021300]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT0[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT1[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT2[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT3[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT4[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT5[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT6[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT7[0x2022600]=0
CLPORT_TS_TIMER_31_0_REG.CLPORT8[0x2022600]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT0[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT1[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT2[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT3[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT4[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT5[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT6[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT7[0x2022500]=0
CLPORT_TS_TIMER_47_32_REG.CLPORT8[0x2022500]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT0[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT1[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT2[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT3[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT4[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT5[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT6[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT7[0x2024c00]=0
CLPORT_TXPI_CSR_CTRL1.CLPORT8[0x2024c00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT0[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT1[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT2[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT3[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT4[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT5[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT6[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT7[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_EN.CLPORT8[0x2023a00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT0[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT1[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT2[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT3[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT4[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT5[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT6[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT7[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_HIGH.CLPORT8[0x2023c00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT0[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT1[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT2[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT3[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT4[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT5[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT6[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT7[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_0_LOW.CLPORT8[0x2023b00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT0[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT1[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT2[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT3[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT4[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT5[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT6[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT7[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_HIGH.CLPORT8[0x2023e00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT0[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT1[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT2[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT3[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT4[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT5[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT6[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT7[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_1_LOW.CLPORT8[0x2023d00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT0[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT1[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT2[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT3[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT4[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT5[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT6[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT7[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_HIGH.CLPORT8[0x2024000]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT0[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT1[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT2[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT3[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT4[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT5[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT6[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT7[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_2_LOW.CLPORT8[0x2023f00]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT0[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT1[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT2[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT3[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT4[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT5[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT6[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT7[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_HIGH.CLPORT8[0x2024200]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT0[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT1[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT2[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT3[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT4[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT5[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT6[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT7[0x2024100]=0
CLPORT_TXPI_CSR_OVER_VAL_3_LOW.CLPORT8[0x2024100]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT0[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT1[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT2[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT3[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT4[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT5[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT6[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT7[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_HIGH.CLPORT8[0x2024400]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT0[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT1[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT2[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT3[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT4[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT5[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT6[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT7[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_0_LOW.CLPORT8[0x2024300]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT0[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT1[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT2[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT3[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT4[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT5[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT6[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT7[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_HIGH.CLPORT8[0x2024600]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT0[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT1[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT2[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT3[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT4[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT5[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT6[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT7[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_1_LOW.CLPORT8[0x2024500]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT0[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT1[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT2[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT3[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT4[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT5[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT6[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT7[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_HIGH.CLPORT8[0x2024800]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT0[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT1[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT2[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT3[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT4[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT5[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT6[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT7[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_2_LOW.CLPORT8[0x2024700]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT0[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT1[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT2[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT3[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT4[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT5[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT6[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT7[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_HIGH.CLPORT8[0x2024a00]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT0[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT1[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT2[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT3[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT4[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT5[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT6[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT7[0x2024900]=0
CLPORT_TXPI_DATA_OUT_STS_3_LOW.CLPORT8[0x2024900]=0
CLPORT_TXPI_LANE_SELECTION.CLPORT0[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT1[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT2[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT3[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT4[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT5[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT6[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT7[0x2024b00]=0xe4
CLPORT_TXPI_LANE_SELECTION.CLPORT8[0x2024b00]=0xe4
CLPORT_WC_UCMEM_CTRL.CLPORT0[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT1[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT2[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT3[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT4[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT5[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT6[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT7[0x2021900]=0
CLPORT_WC_UCMEM_CTRL.CLPORT8[0x2021900]=0
CLPORT_XGXS0_CTRL_REG.CLPORT0[0x2021400]=0x245
CLPORT_XGXS0_CTRL_REG.CLPORT1[0x2021400]=0x243
CLPORT_XGXS0_CTRL_REG.CLPORT2[0x2021400]=0x245
CLPORT_XGXS0_CTRL_REG.CLPORT3[0x2021400]=0x245
CLPORT_XGXS0_CTRL_REG.CLPORT4[0x2021400]=0x243
CLPORT_XGXS0_CTRL_REG.CLPORT5[0x2021400]=0x245
CLPORT_XGXS0_CTRL_REG.CLPORT6[0x2021400]=0x245
CLPORT_XGXS0_CTRL_REG.CLPORT7[0x2021400]=0x243
CLPORT_XGXS0_CTRL_REG.CLPORT8[0x2021400]=0x25c
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT0[0x2021500]=7
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT1[0x2021500]=7
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT2[0x2021500]=0
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT3[0x2021500]=0
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT4[0x2021500]=0
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT5[0x2021500]=0
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT6[0x2021500]=0
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT7[0x2021500]=0
CLPORT_XGXS0_LN0_STATUS0_REG.CLPORT8[0x2021500]=0
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT0[0x2021600]=7
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT1[0x2021600]=7
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT2[0x2021600]=0
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT3[0x2021600]=0
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT4[0x2021600]=0
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT5[0x2021600]=0
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT6[0x2021600]=0
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT7[0x2021600]=0
CLPORT_XGXS0_LN1_STATUS0_REG.CLPORT8[0x2021600]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT0[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT1[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT2[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT3[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT4[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT5[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT6[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT7[0x2021700]=0
CLPORT_XGXS0_LN2_STATUS0_REG.CLPORT8[0x2021700]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT0[0x2021800]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT1[0x2021800]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT2[0x2021800]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT3[0x2021800]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT4[0x2021800]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT5[0x2021800]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT6[0x2021800]=0
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT7[0x2021800]=7
CLPORT_XGXS0_LN3_STATUS0_REG.CLPORT8[0x2021800]=0
CLPORT_XGXS_COUNTER_MODE.CLPORT0[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT1[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT2[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT3[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT4[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT5[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT6[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT7[0x2021100]=1
CLPORT_XGXS_COUNTER_MODE.CLPORT8[0x2021100]=1
CLUP_ECC_2B_ERR_CNT.CLUP0[0x96]=0
CLUP_ECC_2B_ERR_CNT.CLUP1[0x96]=0
CLUP_ECC_2B_ERR_CNT.CLUP2[0x96]=0
CLUP_ECC_INTERRUPT_REGISTER.CLUP0[0x7]=0
CLUP_ECC_INTERRUPT_REGISTER.CLUP1[0x7]=0
CLUP_ECC_INTERRUPT_REGISTER.CLUP2[0x7]=0
CLUP_ECC_INTERRUPT_REGISTER_MASK.CLUP0[0x17]=0
CLUP_ECC_INTERRUPT_REGISTER_MASK.CLUP1[0x17]=0
CLUP_ECC_INTERRUPT_REGISTER_MASK.CLUP2[0x17]=0
CLUP_ECC_INTERRUPT_REGISTER_TEST.CLUP0[0x1f]=0
CLUP_ECC_INTERRUPT_REGISTER_TEST.CLUP1[0x1f]=0
CLUP_ECC_INTERRUPT_REGISTER_TEST.CLUP2[0x1f]=0
CLUP_GTIMER_CONFIGURATION.CLUP0[0x89]=0
CLUP_GTIMER_CONFIGURATION.CLUP1[0x89]=0
CLUP_GTIMER_CONFIGURATION.CLUP2[0x89]=0
CLUP_GTIMER_CYCLE.CLUP0[0x88]=0x3b9aca00
CLUP_GTIMER_CYCLE.CLUP1[0x88]=0x3b9aca00
CLUP_GTIMER_CYCLE.CLUP2[0x88]=0x3b9aca00
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(0).CLUP0[0x180]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(1).CLUP0[0x181]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(2).CLUP0[0x182]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(0).CLUP1[0x180]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(1).CLUP1[0x181]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(2).CLUP1[0x182]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(0).CLUP2[0x180]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(1).CLUP2[0x181]=0
CLUP_ILE_MUX_TX_ILKN_DATA_SEL(2).CLUP2[0x182]=0
CLUP_ILKN_ALIGNER_RX(0).CLUP0[0x18a]=0x20
CLUP_ILKN_ALIGNER_RX(1).CLUP0[0x18b]=0x20
CLUP_ILKN_ALIGNER_RX(2).CLUP0[0x18c]=0x20
CLUP_ILKN_ALIGNER_RX(3).CLUP0[0x18d]=0x20
CLUP_ILKN_ALIGNER_RX(4).CLUP0[0x18e]=0x20
CLUP_ILKN_ALIGNER_RX(5).CLUP0[0x18f]=0x20
CLUP_ILKN_ALIGNER_RX(6).CLUP0[0x190]=0x20
CLUP_ILKN_ALIGNER_RX(7).CLUP0[0x191]=0x20
CLUP_ILKN_ALIGNER_RX(8).CLUP0[0x192]=0x20
CLUP_ILKN_ALIGNER_RX(9).CLUP0[0x193]=0x20
CLUP_ILKN_ALIGNER_RX(10).CLUP0[0x194]=0x20
CLUP_ILKN_ALIGNER_RX(11).CLUP0[0x195]=0x20
CLUP_ILKN_ALIGNER_RX(0).CLUP1[0x18a]=0x20
CLUP_ILKN_ALIGNER_RX(1).CLUP1[0x18b]=0x20
CLUP_ILKN_ALIGNER_RX(2).CLUP1[0x18c]=0x20
CLUP_ILKN_ALIGNER_RX(3).CLUP1[0x18d]=0x20
CLUP_ILKN_ALIGNER_RX(4).CLUP1[0x18e]=0x20
CLUP_ILKN_ALIGNER_RX(5).CLUP1[0x18f]=0x20
CLUP_ILKN_ALIGNER_RX(6).CLUP1[0x190]=0x20
CLUP_ILKN_ALIGNER_RX(7).CLUP1[0x191]=0x20
CLUP_ILKN_ALIGNER_RX(8).CLUP1[0x192]=0x20
CLUP_ILKN_ALIGNER_RX(9).CLUP1[0x193]=0x20
CLUP_ILKN_ALIGNER_RX(10).CLUP1[0x194]=0x20
CLUP_ILKN_ALIGNER_RX(11).CLUP1[0x195]=0x20
CLUP_ILKN_ALIGNER_RX(0).CLUP2[0x18a]=0x20
CLUP_ILKN_ALIGNER_RX(1).CLUP2[0x18b]=0x20
CLUP_ILKN_ALIGNER_RX(2).CLUP2[0x18c]=0x20
CLUP_ILKN_ALIGNER_RX(3).CLUP2[0x18d]=0x20
CLUP_ILKN_ALIGNER_RX(4).CLUP2[0x18e]=0x20
CLUP_ILKN_ALIGNER_RX(5).CLUP2[0x18f]=0x20
CLUP_ILKN_ALIGNER_RX(6).CLUP2[0x190]=0x20
CLUP_ILKN_ALIGNER_RX(7).CLUP2[0x191]=0x20
CLUP_ILKN_ALIGNER_RX(8).CLUP2[0x192]=0x20
CLUP_ILKN_ALIGNER_RX(9).CLUP2[0x193]=0x20
CLUP_ILKN_ALIGNER_RX(10).CLUP2[0x194]=0x20
CLUP_ILKN_ALIGNER_RX(11).CLUP2[0x195]=0x20
CLUP_ILKN_ALIGNER_TX(0).CLUP0[0x196]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(1).CLUP0[0x197]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(2).CLUP0[0x198]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(3).CLUP0[0x199]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(4).CLUP0[0x19a]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(5).CLUP0[0x19b]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(6).CLUP0[0x19c]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(7).CLUP0[0x19d]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(8).CLUP0[0x19e]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(9).CLUP0[0x19f]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(10).CLUP0[0x1a0]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(11).CLUP0[0x1a1]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(0).CLUP1[0x196]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(1).CLUP1[0x197]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(2).CLUP1[0x198]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(3).CLUP1[0x199]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(4).CLUP1[0x19a]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(5).CLUP1[0x19b]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(6).CLUP1[0x19c]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(7).CLUP1[0x19d]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(8).CLUP1[0x19e]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(9).CLUP1[0x19f]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(10).CLUP1[0x1a0]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(11).CLUP1[0x1a1]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(0).CLUP2[0x196]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(1).CLUP2[0x197]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(2).CLUP2[0x198]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(3).CLUP2[0x199]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(4).CLUP2[0x19a]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(5).CLUP2[0x19b]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(6).CLUP2[0x19c]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(7).CLUP2[0x19d]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(8).CLUP2[0x19e]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(9).CLUP2[0x19f]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(10).CLUP2[0x1a0]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX(11).CLUP2[0x1a1]=0x7c004000c0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(0).CLUP0[0x1a3]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(1).CLUP0[0x1a4]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(2).CLUP0[0x1a5]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(3).CLUP0[0x1a6]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(4).CLUP0[0x1a7]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(5).CLUP0[0x1a8]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(6).CLUP0[0x1a9]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(7).CLUP0[0x1aa]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(8).CLUP0[0x1ab]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(9).CLUP0[0x1ac]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(10).CLUP0[0x1ad]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(11).CLUP0[0x1ae]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(0).CLUP1[0x1a3]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(1).CLUP1[0x1a4]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(2).CLUP1[0x1a5]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(3).CLUP1[0x1a6]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(4).CLUP1[0x1a7]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(5).CLUP1[0x1a8]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(6).CLUP1[0x1a9]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(7).CLUP1[0x1aa]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(8).CLUP1[0x1ab]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(9).CLUP1[0x1ac]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(10).CLUP1[0x1ad]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(11).CLUP1[0x1ae]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(0).CLUP2[0x1a3]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(1).CLUP2[0x1a4]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(2).CLUP2[0x1a5]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(3).CLUP2[0x1a6]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(4).CLUP2[0x1a7]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(5).CLUP2[0x1a8]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(6).CLUP2[0x1a9]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(7).CLUP2[0x1aa]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(8).CLUP2[0x1ab]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(9).CLUP2[0x1ac]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(10).CLUP2[0x1ad]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO(11).CLUP2[0x1ae]=0
CLUP_ILKN_ALIGNER_TX_FT_FIFO_INPUT_READY_TH.CLUP0[0x1af]=4
CLUP_ILKN_ALIGNER_TX_FT_FIFO_INPUT_READY_TH.CLUP1[0x1af]=4
CLUP_ILKN_ALIGNER_TX_FT_FIFO_INPUT_READY_TH.CLUP2[0x1af]=4
CLUP_INTERRUPT_MASK_REGISTER.CLUP0[0x10]=0
CLUP_INTERRUPT_MASK_REGISTER.CLUP1[0x10]=0
CLUP_INTERRUPT_MASK_REGISTER.CLUP2[0x10]=0
CLUP_INTERRUPT_REGISTER.CLUP0[0x0]=0
CLUP_INTERRUPT_REGISTER.CLUP1[0x0]=0
CLUP_INTERRUPT_REGISTER.CLUP2[0x0]=0
CLUP_INTERRUPT_REGISTER_TEST.CLUP0[0x18]=0
CLUP_INTERRUPT_REGISTER_TEST.CLUP1[0x18]=0
CLUP_INTERRUPT_REGISTER_TEST.CLUP2[0x18]=0
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(0).CLUP0[0x127]=0xa7ac027a8585
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(1).CLUP0[0x128]=0xa79981bc8585
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(2).CLUP0[0x129]=0x24c96b91c3f24
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(0).CLUP1[0x127]=0x959e5efbde2e
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(1).CLUP1[0x128]=0xfff5eadfd1aa
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(2).CLUP1[0x129]=0x2bcecea478f6c
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(0).CLUP2[0x127]=0x1f3eee65b6e0e
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(1).CLUP2[0x128]=0xa7c24f2f08f5
CLUP_LAST_RECEIVED_FROM_PM_CONTROLS(2).CLUP2[0x129]=0x3b7d3b265b9e0
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(0).CLUP0[0x12d]=0xde26794a6d19cc2de0238f4281000002080045000034000040003f06e1c90a0b761897654272d16c01bb30369aeebe83
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(1).CLUP0[0x12e]=0xde26794a6d1964d15405d9d58100000508004500008ec61040003e0600be0a0b7afd227ace198af301bb336b8d2bfe21
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(2).CLUP0[0x12f]=0x65ee0f8f17651841f7ee0d4f6299b4c027a178b9fe05f9dd8cb536a6f9be53e1ff3e64efcaebdbc32da4f4a0240aeefd
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(0).CLUP1[0x12d]=0x79208dbbed44670297bdf7b9f4feff4ee69a703e416914f4a73451aab067cc1c9385f2f0e8fe11a3ff7228bb52df7ea5
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(1).CLUP1[0x12e]=0xf56b43ddd53ab64dbe5de78bdf26f6dda9337795bcd2863cbcb6ff8daf775beb6d7fbfff57751ffc9f279755e9ff467b
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(2).CLUP1[0x12f]=0xd0defecaefc89d7e4f73765677d914ff227ee7541aaf2f7d3739dfefeab2fb676e79b77067ccbe96fc0ed45fb5efdc39
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(0).CLUP2[0x12d]=0x9d6b7f6be4d6d9a678d73ce3b3bff9f06fa749b37663f224df52dc4ec6cf17ae6beedfbe64a021e4573dbe34353f7ae7
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(1).CLUP2[0x12e]=0x85531f9b38ede26794a6d19810000030800450005dc8139400031066f9d11f8be500a0b78f201bbd594145f7d546f6e
CLUP_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(2).CLUP2[0x12f]=0xb1fffaae7ee5974f7ececf59dcdf556b7ecd7ded7dcbf9790c95f77fd76fbd87f7fcbea5ffa713e9eedfb397fb2fb576
CLUP_LAST_SENT_TO_PM_CONTROLS(0).CLUP0[0x100]=0x1001795
CLUP_LAST_SENT_TO_PM_CONTROLS(1).CLUP0[0x101]=0x1001785
CLUP_LAST_SENT_TO_PM_CONTROLS(2).CLUP0[0x102]=0x1f819b4
CLUP_LAST_SENT_TO_PM_CONTROLS(0).CLUP1[0x100]=0x1f81ab4
CLUP_LAST_SENT_TO_PM_CONTROLS(1).CLUP1[0x101]=0x1f81ab4
CLUP_LAST_SENT_TO_PM_CONTROLS(2).CLUP1[0x102]=0x1f81ab4
CLUP_LAST_SENT_TO_PM_CONTROLS(0).CLUP2[0x100]=0x1f81c32
CLUP_LAST_SENT_TO_PM_CONTROLS(1).CLUP2[0x101]=0x10015b5
CLUP_LAST_SENT_TO_PM_CONTROLS(2).CLUP2[0x102]=0x3fbffde
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(0).CLUP0[0x103]=0x85531f9b38ede26794a6d19810000030800450005dc813a400031066f9c11f8be500a0b78f201bbd594145f82fc6f6e
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(1).CLUP0[0x104]=0x6c3b6bdb5d52de26794a6d19810000040800450005dcd39c40003506146fd1c503080a0b79380050db4c60bfbf303e81
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(2).CLUP0[0x105]=0x33330000001694434dbc3a858100007f86dd60000000004c0001fe8000000000000096434dfffebc3a85ff0200000000
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(0).CLUP1[0x103]=0x33330000000194434dbc3a858100007f86dd6000000000203afffe8000000000000096434dfffebc3a85ff0200000000
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(1).CLUP1[0x104]=0x33330000000194434dbc3a858100007f86dd6000000000203afffe8000000000000096434dfffebc3a85ff0200000000
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(2).CLUP1[0x105]=0x33330000000194434dbc3a858100007f86dd6000000000203afffe8000000000000096434dfffebc3a85ff0200000000
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(0).CLUP2[0x103]=0x33330000001694434dbc3a858100007f86dd60000000004c0001fe8000000000000096434dfffebc3a85ff0200000000
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(1).CLUP2[0x104]=0xde26794a6d19085531f9b64c810000050800450005cb66ff40003f11b4b80a0b7ae9b84bdd2a853d01bb05b770db4900
CLUP_LAST_SENT_TO_PM_DATA_ON_SOP(2).CLUP2[0x105]=0xfdbedf3fbeebfdffefad3d6afbfbf772fffeffc2dcbfe76efd3fffedad9fefb5aeb95ffd6fa1e7f5afff3bbcfe2e7fb7
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(0).CLUP0[0x166]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(1).CLUP0[0x167]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(2).CLUP0[0x168]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(0).CLUP1[0x166]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(1).CLUP1[0x167]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(2).CLUP1[0x168]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(0).CLUP2[0x166]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(1).CLUP2[0x167]=0
CLUP_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION(2).CLUP2[0x168]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(0).CLUP0[0x160]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(1).CLUP0[0x161]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(2).CLUP0[0x162]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(0).CLUP1[0x160]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(1).CLUP1[0x161]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(2).CLUP1[0x162]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(0).CLUP2[0x160]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(1).CLUP2[0x161]=0
CLUP_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION(2).CLUP2[0x162]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(0).CLUP0[0x169]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(1).CLUP0[0x16a]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(2).CLUP0[0x16b]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(0).CLUP1[0x169]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(1).CLUP1[0x16a]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(2).CLUP1[0x16b]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(0).CLUP2[0x169]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(1).CLUP2[0x16a]=0
CLUP_NIF_PM_EXTERNAL_LPI_INDICATION(2).CLUP2[0x16b]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(0).CLUP0[0x163]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(1).CLUP0[0x164]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(2).CLUP0[0x165]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(0).CLUP1[0x163]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(1).CLUP1[0x164]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(2).CLUP1[0x165]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(0).CLUP2[0x163]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(1).CLUP2[0x164]=0
CLUP_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION(2).CLUP2[0x165]=0
CLUP_NIF_PM_ILKN_RX_RSTN(0).CLUP0[0x16c]=0
CLUP_NIF_PM_ILKN_RX_RSTN(1).CLUP0[0x16d]=0
CLUP_NIF_PM_ILKN_RX_RSTN(2).CLUP0[0x16e]=0
CLUP_NIF_PM_ILKN_RX_RSTN(0).CLUP1[0x16c]=0
CLUP_NIF_PM_ILKN_RX_RSTN(1).CLUP1[0x16d]=0
CLUP_NIF_PM_ILKN_RX_RSTN(2).CLUP1[0x16e]=0
CLUP_NIF_PM_ILKN_RX_RSTN(0).CLUP2[0x16c]=0
CLUP_NIF_PM_ILKN_RX_RSTN(1).CLUP2[0x16d]=0
CLUP_NIF_PM_ILKN_RX_RSTN(2).CLUP2[0x16e]=0
CLUP_NIF_PM_ILKN_TX_RSTN(0).CLUP0[0x16f]=0
CLUP_NIF_PM_ILKN_TX_RSTN(1).CLUP0[0x170]=0
CLUP_NIF_PM_ILKN_TX_RSTN(2).CLUP0[0x171]=0
CLUP_NIF_PM_ILKN_TX_RSTN(0).CLUP1[0x16f]=0
CLUP_NIF_PM_ILKN_TX_RSTN(1).CLUP1[0x170]=0
CLUP_NIF_PM_ILKN_TX_RSTN(2).CLUP1[0x171]=0
CLUP_NIF_PM_ILKN_TX_RSTN(0).CLUP2[0x16f]=0
CLUP_NIF_PM_ILKN_TX_RSTN(1).CLUP2[0x170]=0
CLUP_NIF_PM_ILKN_TX_RSTN(2).CLUP2[0x171]=0
CLUP_NIF_PM_RESOLVED_SPEED(0).CLUP0[0x157]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(1).CLUP0[0x158]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(2).CLUP0[0x159]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(0).CLUP1[0x157]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(1).CLUP1[0x158]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(2).CLUP1[0x159]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(0).CLUP2[0x157]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(1).CLUP2[0x158]=0x2020202
CLUP_NIF_PM_RESOLVED_SPEED(2).CLUP2[0x159]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(0).CLUP0[0x15a]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(1).CLUP0[0x15b]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(2).CLUP0[0x15c]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(0).CLUP1[0x15a]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(1).CLUP1[0x15b]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(2).CLUP1[0x15c]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(0).CLUP2[0x15a]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(1).CLUP2[0x15b]=0
CLUP_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS(2).CLUP2[0x15c]=0
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(0).CLUP0[0x15d]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(1).CLUP0[0x15e]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(2).CLUP0[0x15f]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(0).CLUP1[0x15d]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(1).CLUP1[0x15e]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(2).CLUP1[0x15f]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(0).CLUP2[0x15d]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(1).CLUP2[0x15e]=1
CLUP_NIF_PM_TX_PLL_LOCK_STATUS(2).CLUP2[0x15f]=0
CLUP_NIF_TSC_LANE_STATUS(0).CLUP0[0x151]=0x3f
CLUP_NIF_TSC_LANE_STATUS(1).CLUP0[0x152]=0x3f
CLUP_NIF_TSC_LANE_STATUS(2).CLUP0[0x153]=0
CLUP_NIF_TSC_LANE_STATUS(0).CLUP1[0x151]=0
CLUP_NIF_TSC_LANE_STATUS(1).CLUP1[0x152]=0
CLUP_NIF_TSC_LANE_STATUS(2).CLUP1[0x153]=0
CLUP_NIF_TSC_LANE_STATUS(0).CLUP2[0x151]=0
CLUP_NIF_TSC_LANE_STATUS(1).CLUP2[0x152]=0xe00
CLUP_NIF_TSC_LANE_STATUS(2).CLUP2[0x153]=0
CLUP_PHY_LED_SAMP_CFG.CLUP0[0x1a2]=2
CLUP_PHY_LED_SAMP_CFG.CLUP1[0x1a2]=2
CLUP_PHY_LED_SAMP_CFG.CLUP2[0x1a2]=2
CLUP_PM_MUX_TX_ILKN_DATA_SEL(0).CLUP0[0x183]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(1).CLUP0[0x184]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(2).CLUP0[0x185]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(0).CLUP1[0x183]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(1).CLUP1[0x184]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(2).CLUP1[0x185]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(0).CLUP2[0x183]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(1).CLUP2[0x184]=0xf
CLUP_PM_MUX_TX_ILKN_DATA_SEL(2).CLUP2[0x185]=0xf
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(0).CLUP0[0x186]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(1).CLUP0[0x187]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(2).CLUP0[0x188]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(0).CLUP1[0x186]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(1).CLUP1[0x187]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(2).CLUP1[0x188]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(0).CLUP2[0x186]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(1).CLUP2[0x187]=0
CLUP_PM_UP_MUX_RX_ILKN_DATA_SEL(2).CLUP2[0x188]=0
CLUP_REG_0094.CLUP0[0x94]=0
CLUP_REG_0094.CLUP1[0x94]=0
CLUP_REG_0094.CLUP2[0x94]=0
CLUP_REG_0098.CLUP0[0x98]=0
CLUP_REG_0098.CLUP1[0x98]=0
CLUP_REG_0098.CLUP2[0x98]=0
CLUP_REG_0154(0).CLUP0[0x154]=0x6900
CLUP_REG_0154(1).CLUP0[0x155]=0x6900
CLUP_REG_0154(2).CLUP0[0x156]=0x6900
CLUP_REG_0154(0).CLUP1[0x154]=0x6900
CLUP_REG_0154(1).CLUP1[0x155]=0x6900
CLUP_REG_0154(2).CLUP1[0x156]=0x6900
CLUP_REG_0154(0).CLUP2[0x154]=0x6900
CLUP_REG_0154(1).CLUP2[0x155]=0x6900
CLUP_REG_0154(2).CLUP2[0x156]=0x6900
CLUP_REG_009A.CLUP0[0x9a]=0
CLUP_REG_009A.CLUP1[0x9a]=0
CLUP_REG_009A.CLUP2[0x9a]=0
CLUP_REG_009C.CLUP0[0x9c]=0
CLUP_REG_009C.CLUP1[0x9c]=0
CLUP_REG_009C.CLUP2[0x9c]=0
CLUP_REG_00A0.CLUP0[0xa0]=0
CLUP_REG_00A0.CLUP1[0xa0]=0
CLUP_REG_00A0.CLUP2[0xa0]=0
CLUP_REG_00C2.CLUP0[0xc2]=0x10
CLUP_REG_00C2.CLUP1[0xc2]=0x10
CLUP_REG_00C2.CLUP2[0xc2]=0x10
CLUP_REG_00C4.CLUP0[0xc4]=0
CLUP_REG_00C4.CLUP1[0xc4]=0
CLUP_REG_00C4.CLUP2[0xc4]=0
CLUP_RESERVED_MTCD.CLUP0[0xae]=0x30
CLUP_RESERVED_MTCD.CLUP1[0xae]=0x30
CLUP_RESERVED_MTCD.CLUP2[0xae]=0x30
CLUP_RESERVED_MTCP.CLUP0[0xad]=0x300000600000000
CLUP_RESERVED_MTCP.CLUP1[0xad]=0x300000600000000
CLUP_RESERVED_MTCP.CLUP2[0xad]=0x300000600000000
CLUP_RESERVED_SPARE_0.CLUP0[0x90]=0xffffffff
CLUP_RESERVED_SPARE_0.CLUP1[0x90]=0xffffffff
CLUP_RESERVED_SPARE_0.CLUP2[0x90]=0xffffffff
CLUP_RESERVED_SPARE_1.CLUP0[0x91]=0xffffffff
CLUP_RESERVED_SPARE_1.CLUP1[0x91]=0xffffffff
CLUP_RESERVED_SPARE_1.CLUP2[0x91]=0xffffffff
CLUP_RESERVED_SPARE_2.CLUP0[0x92]=0
CLUP_RESERVED_SPARE_2.CLUP1[0x92]=0
CLUP_RESERVED_SPARE_2.CLUP2[0x92]=0
CLUP_RESERVED_SPARE_3.CLUP0[0x93]=0
CLUP_RESERVED_SPARE_3.CLUP1[0x93]=0
CLUP_RESERVED_SPARE_3.CLUP2[0x93]=0
CLUP_SBUS_BROADCAST_ID.CLUP0[0x86]=0x7ff
CLUP_SBUS_BROADCAST_ID.CLUP1[0x86]=0x7ff
CLUP_SBUS_BROADCAST_ID.CLUP2[0x86]=0x7ff
CLUP_SBUS_LAST_IN_CHAIN.CLUP0[0x87]=0
CLUP_SBUS_LAST_IN_CHAIN.CLUP1[0x87]=0
CLUP_SBUS_LAST_IN_CHAIN.CLUP2[0x87]=0
CLUP_SPECIAL_CLOCK_CONTROLS.CLUP0[0xc1]=2
CLUP_SPECIAL_CLOCK_CONTROLS.CLUP1[0xc1]=2
CLUP_SPECIAL_CLOCK_CONTROLS.CLUP2[0xc1]=2
CLUP_SYNC_ETH_CFG(0).CLUP0[0x172]=0
CLUP_SYNC_ETH_CFG(1).CLUP0[0x173]=0
CLUP_SYNC_ETH_CFG(0).CLUP1[0x172]=0
CLUP_SYNC_ETH_CFG(1).CLUP1[0x173]=0
CLUP_SYNC_ETH_CFG(0).CLUP2[0x172]=0
CLUP_SYNC_ETH_CFG(1).CLUP2[0x173]=0
CLUP_SYNC_ETH_DEBUG(0).CLUP0[0x174]=8
CLUP_SYNC_ETH_DEBUG(1).CLUP0[0x175]=8
CLUP_SYNC_ETH_DEBUG(2).CLUP0[0x176]=1
CLUP_SYNC_ETH_DEBUG(3).CLUP0[0x177]=1
CLUP_SYNC_ETH_DEBUG(4).CLUP0[0x178]=8
CLUP_SYNC_ETH_DEBUG(5).CLUP0[0x179]=9
CLUP_SYNC_ETH_DEBUG(6).CLUP0[0x17a]=0
CLUP_SYNC_ETH_DEBUG(7).CLUP0[0x17b]=1
CLUP_SYNC_ETH_DEBUG(8).CLUP0[0x17c]=0
CLUP_SYNC_ETH_DEBUG(9).CLUP0[0x17d]=0
CLUP_SYNC_ETH_DEBUG(10).CLUP0[0x17e]=0
CLUP_SYNC_ETH_DEBUG(11).CLUP0[0x17f]=0
CLUP_SYNC_ETH_DEBUG(0).CLUP1[0x174]=0
CLUP_SYNC_ETH_DEBUG(1).CLUP1[0x175]=0
CLUP_SYNC_ETH_DEBUG(2).CLUP1[0x176]=0
CLUP_SYNC_ETH_DEBUG(3).CLUP1[0x177]=0
CLUP_SYNC_ETH_DEBUG(4).CLUP1[0x178]=0
CLUP_SYNC_ETH_DEBUG(5).CLUP1[0x179]=0
CLUP_SYNC_ETH_DEBUG(6).CLUP1[0x17a]=0
CLUP_SYNC_ETH_DEBUG(7).CLUP1[0x17b]=0
CLUP_SYNC_ETH_DEBUG(8).CLUP1[0x17c]=0
CLUP_SYNC_ETH_DEBUG(9).CLUP1[0x17d]=0
CLUP_SYNC_ETH_DEBUG(10).CLUP1[0x17e]=0
CLUP_SYNC_ETH_DEBUG(11).CLUP1[0x17f]=0
CLUP_SYNC_ETH_DEBUG(0).CLUP2[0x174]=0
CLUP_SYNC_ETH_DEBUG(1).CLUP2[0x175]=0
CLUP_SYNC_ETH_DEBUG(2).CLUP2[0x176]=0
CLUP_SYNC_ETH_DEBUG(3).CLUP2[0x177]=0
CLUP_SYNC_ETH_DEBUG(4).CLUP2[0x178]=0
CLUP_SYNC_ETH_DEBUG(5).CLUP2[0x179]=0
CLUP_SYNC_ETH_DEBUG(6).CLUP2[0x17a]=0
CLUP_SYNC_ETH_DEBUG(7).CLUP2[0x17b]=0x3f
CLUP_SYNC_ETH_DEBUG(8).CLUP2[0x17c]=0
CLUP_SYNC_ETH_DEBUG(9).CLUP2[0x17d]=0
CLUP_SYNC_ETH_DEBUG(10).CLUP2[0x17e]=0
CLUP_SYNC_ETH_DEBUG(11).CLUP2[0x17f]=0
CLUP_TS_CFG_NUM_OF_SAMP.CLUP0[0x189]=2
CLUP_TS_CFG_NUM_OF_SAMP.CLUP1[0x189]=2
CLUP_TS_CFG_NUM_OF_SAMP.CLUP2[0x189]=2
CLU_ALIGNER_DEBUG_REG.CLU0[0x611]=0
CLU_ALIGNER_DEBUG_REG.CLU1[0x611]=0
CLU_ALIGNER_DEBUG_REG.CLU2[0x611]=0
CLU_ALIGNER_MEMS_RESET.CLU0[0x54a]=7
CLU_ALIGNER_MEMS_RESET.CLU1[0x54a]=7
CLU_ALIGNER_MEMS_RESET.CLU2[0x54a]=3
CLU_BIST_EVENTS_GENERATOR.CLU0[0x5b8]=0x1000000000000000000000000
CLU_BIST_EVENTS_GENERATOR.CLU1[0x5b8]=0x1000000000000000000000000
CLU_BIST_EVENTS_GENERATOR.CLU2[0x5b8]=0x1000000000000000000000000
CLU_BIST_EVENTS_STATUS.CLU0[0x5bc]=0x100000000
CLU_BIST_EVENTS_STATUS.CLU1[0x5bc]=0x100000000
CLU_BIST_EVENTS_STATUS.CLU2[0x5bc]=0x100000000
CLU_CONTROL_FRAME_CONFIG.CLU0[0x1cb]=0
CLU_CONTROL_FRAME_CONFIG.CLU1[0x1cb]=0
CLU_CONTROL_FRAME_CONFIG.CLU2[0x1cb]=0
CLU_ECC_1B_ERR_CNT.CLU0[0x94]=0
CLU_ECC_1B_ERR_CNT.CLU1[0x94]=0
CLU_ECC_1B_ERR_CNT.CLU2[0x94]=0
CLU_ECC_2B_ERR_CNT.CLU0[0x96]=0
CLU_ECC_2B_ERR_CNT.CLU1[0x96]=0
CLU_ECC_2B_ERR_CNT.CLU2[0x96]=0
CLU_ECC_ERR_1B_MONITOR_MEM_MASK.CLU0[0x9a]=0xfffff
CLU_ECC_ERR_1B_MONITOR_MEM_MASK.CLU1[0x9a]=0xfffff
CLU_ECC_ERR_1B_MONITOR_MEM_MASK.CLU2[0x9a]=0xfffff
CLU_ECC_ERR_2B_MONITOR_MEM_MASK.CLU0[0x9c]=0xfffff
CLU_ECC_ERR_2B_MONITOR_MEM_MASK.CLU1[0x9c]=0xfffff
CLU_ECC_ERR_2B_MONITOR_MEM_MASK.CLU2[0x9c]=0xfffff
CLU_ECC_INTERRUPT_REGISTER.CLU0[0x7]=0
CLU_ECC_INTERRUPT_REGISTER.CLU1[0x7]=0
CLU_ECC_INTERRUPT_REGISTER.CLU2[0x7]=0
CLU_ECC_INTERRUPT_REGISTER_MASK.CLU0[0x17]=0
CLU_ECC_INTERRUPT_REGISTER_MASK.CLU1[0x17]=0
CLU_ECC_INTERRUPT_REGISTER_MASK.CLU2[0x17]=0
CLU_ECC_INTERRUPT_REGISTER_TEST.CLU0[0x1f]=0
CLU_ECC_INTERRUPT_REGISTER_TEST.CLU1[0x1f]=0
CLU_ECC_INTERRUPT_REGISTER_TEST.CLU2[0x1f]=0
CLU_EGQ_CRDT_CONFIG.CLU0[0x280]=0x320320320320320320320320320320320320
CLU_EGQ_CRDT_CONFIG.CLU1[0x280]=0x320320320320320320320320320320320320
CLU_EGQ_CRDT_CONFIG.CLU2[0x280]=0x320320320320320320320320320320320320
CLU_ENABLE_DYNAMIC_MEMORY_ACCESS.CLU0[0x84]=0x3ff
CLU_ENABLE_DYNAMIC_MEMORY_ACCESS.CLU1[0x84]=0x3ff
CLU_ENABLE_DYNAMIC_MEMORY_ACCESS.CLU2[0x84]=0x3ff
CLU_ETH_TX_GEN_LLFC_CNT.CLU0[0x58b]=0
CLU_ETH_TX_GEN_LLFC_CNT.CLU1[0x58b]=0
CLU_ETH_TX_GEN_LLFC_CNT.CLU2[0x58b]=0
CLU_ETH_TX_LLFC_STOP_TX_CNT.CLU0[0x58a]=0
CLU_ETH_TX_LLFC_STOP_TX_CNT.CLU1[0x58a]=0
CLU_ETH_TX_LLFC_STOP_TX_CNT.CLU2[0x58a]=0
CLU_FC_CHAIN_RX_LLFC_SYNC_DBG.CLU0[0x62e]=0
CLU_FC_CHAIN_RX_LLFC_SYNC_DBG.CLU1[0x62e]=0
CLU_FC_CHAIN_RX_LLFC_SYNC_DBG.CLU2[0x62e]=0
CLU_FC_CHAIN_RX_PFC_SYNC_DBG.CLU0[0x62f]=1
CLU_FC_CHAIN_RX_PFC_SYNC_DBG.CLU1[0x62f]=1
CLU_FC_CHAIN_RX_PFC_SYNC_DBG.CLU2[0x62f]=1
CLU_FC_CHOOSE_PORT_FOR_ETH_TX.CLU0[0x589]=0
CLU_FC_CHOOSE_PORT_FOR_ETH_TX.CLU1[0x589]=0
CLU_FC_CHOOSE_PORT_FOR_ETH_TX.CLU2[0x589]=0
CLU_FC_CHOOSE_PORT_FOR_PFC.CLU0[0x587]=0
CLU_FC_CHOOSE_PORT_FOR_PFC.CLU1[0x587]=0
CLU_FC_CHOOSE_PORT_FOR_PFC.CLU2[0x587]=0
CLU_FC_GEN_SAFC_REFRESH_TIMER(0).CLU0[0x56a]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(1).CLU0[0x56b]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(2).CLU0[0x56c]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(3).CLU0[0x56d]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(4).CLU0[0x56e]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(5).CLU0[0x56f]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(6).CLU0[0x570]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(7).CLU0[0x571]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(8).CLU0[0x572]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(9).CLU0[0x573]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(10).CLU0[0x574]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(11).CLU0[0x575]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(0).CLU1[0x56a]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(1).CLU1[0x56b]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(2).CLU1[0x56c]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(3).CLU1[0x56d]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(4).CLU1[0x56e]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(5).CLU1[0x56f]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(6).CLU1[0x570]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(7).CLU1[0x571]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(8).CLU1[0x572]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(9).CLU1[0x573]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(10).CLU1[0x574]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(11).CLU1[0x575]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(0).CLU2[0x56a]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(1).CLU2[0x56b]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(2).CLU2[0x56c]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(3).CLU2[0x56d]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(4).CLU2[0x56e]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(5).CLU2[0x56f]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(6).CLU2[0x570]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(7).CLU2[0x571]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(8).CLU2[0x572]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(9).CLU2[0x573]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(10).CLU2[0x574]=0x1000000
CLU_FC_GEN_SAFC_REFRESH_TIMER(11).CLU2[0x575]=0x1000000
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(0).CLU0[0x58c]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(1).CLU0[0x58d]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(2).CLU0[0x58e]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(3).CLU0[0x58f]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(4).CLU0[0x590]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(5).CLU0[0x591]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(6).CLU0[0x592]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(7).CLU0[0x593]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(8).CLU0[0x594]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(9).CLU0[0x595]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(10).CLU0[0x596]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(11).CLU0[0x597]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(0).CLU1[0x58c]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(1).CLU1[0x58d]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(2).CLU1[0x58e]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(3).CLU1[0x58f]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(4).CLU1[0x590]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(5).CLU1[0x591]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(6).CLU1[0x592]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(7).CLU1[0x593]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(8).CLU1[0x594]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(9).CLU1[0x595]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(10).CLU1[0x596]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(11).CLU1[0x597]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(0).CLU2[0x58c]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(1).CLU2[0x58d]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(2).CLU2[0x58e]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(3).CLU2[0x58f]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(4).CLU2[0x590]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(5).CLU2[0x591]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(6).CLU2[0x592]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(7).CLU2[0x593]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(8).CLU2[0x594]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(9).CLU2[0x595]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(10).CLU2[0x596]=0
CLU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(11).CLU2[0x597]=0
CLU_FC_LLFC_STOP_TX_FORCE.CLU0[0x54e]=0
CLU_FC_LLFC_STOP_TX_FORCE.CLU1[0x54e]=0
CLU_FC_LLFC_STOP_TX_FORCE.CLU2[0x54e]=0
CLU_FC_LLFC_STOP_TX_FROM_CFC_MASK.CLU0[0x551]=0
CLU_FC_LLFC_STOP_TX_FROM_CFC_MASK.CLU1[0x551]=0
CLU_FC_LLFC_STOP_TX_FROM_CFC_MASK.CLU2[0x551]=0
CLU_FC_MASK_FC_WHEN_LINK_FAIL.CLU0[0x568]=0xfff
CLU_FC_MASK_FC_WHEN_LINK_FAIL.CLU1[0x568]=0xfff
CLU_FC_MASK_FC_WHEN_LINK_FAIL.CLU2[0x568]=0xfff
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(0).CLU0[0x5a8]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(1).CLU0[0x5a9]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(2).CLU0[0x5aa]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(3).CLU0[0x5ab]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(4).CLU0[0x5ac]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(5).CLU0[0x5ad]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(6).CLU0[0x5ae]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(7).CLU0[0x5af]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(8).CLU0[0x5b0]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(9).CLU0[0x5b1]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(10).CLU0[0x5b2]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(11).CLU0[0x5b3]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(12).CLU0[0x5b4]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(13).CLU0[0x5b5]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(14).CLU0[0x5b6]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(15).CLU0[0x5b7]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(0).CLU1[0x5a8]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(1).CLU1[0x5a9]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(2).CLU1[0x5aa]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(3).CLU1[0x5ab]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(4).CLU1[0x5ac]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(5).CLU1[0x5ad]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(6).CLU1[0x5ae]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(7).CLU1[0x5af]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(8).CLU1[0x5b0]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(9).CLU1[0x5b1]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(10).CLU1[0x5b2]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(11).CLU1[0x5b3]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(12).CLU1[0x5b4]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(13).CLU1[0x5b5]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(14).CLU1[0x5b6]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(15).CLU1[0x5b7]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(0).CLU2[0x5a8]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(1).CLU2[0x5a9]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(2).CLU2[0x5aa]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(3).CLU2[0x5ab]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(4).CLU2[0x5ac]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(5).CLU2[0x5ad]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(6).CLU2[0x5ae]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(7).CLU2[0x5af]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(8).CLU2[0x5b0]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(9).CLU2[0x5b1]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(10).CLU2[0x5b2]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(11).CLU2[0x5b3]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(12).CLU2[0x5b4]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(13).CLU2[0x5b5]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(14).CLU2[0x5b6]=0
CLU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(15).CLU2[0x5b7]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(0).CLU0[0x598]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(1).CLU0[0x599]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(2).CLU0[0x59a]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(3).CLU0[0x59b]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(4).CLU0[0x59c]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(5).CLU0[0x59d]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(6).CLU0[0x59e]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(7).CLU0[0x59f]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(8).CLU0[0x5a0]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(9).CLU0[0x5a1]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(10).CLU0[0x5a2]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(11).CLU0[0x5a3]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(12).CLU0[0x5a4]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(13).CLU0[0x5a5]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(14).CLU0[0x5a6]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(15).CLU0[0x5a7]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(0).CLU1[0x598]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(1).CLU1[0x599]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(2).CLU1[0x59a]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(3).CLU1[0x59b]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(4).CLU1[0x59c]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(5).CLU1[0x59d]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(6).CLU1[0x59e]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(7).CLU1[0x59f]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(8).CLU1[0x5a0]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(9).CLU1[0x5a1]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(10).CLU1[0x5a2]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(11).CLU1[0x5a3]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(12).CLU1[0x5a4]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(13).CLU1[0x5a5]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(14).CLU1[0x5a6]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(15).CLU1[0x5a7]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(0).CLU2[0x598]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(1).CLU2[0x599]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(2).CLU2[0x59a]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(3).CLU2[0x59b]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(4).CLU2[0x59c]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(5).CLU2[0x59d]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(6).CLU2[0x59e]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(7).CLU2[0x59f]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(8).CLU2[0x5a0]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(9).CLU2[0x5a1]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(10).CLU2[0x5a2]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(11).CLU2[0x5a3]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(12).CLU2[0x5a4]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(13).CLU2[0x5a5]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(14).CLU2[0x5a6]=0
CLU_FC_MASK_PFC_PRIO_OF_RMC(15).CLU2[0x5a7]=0
CLU_FC_PFC_CFG.CLU0[0x54c]=5
CLU_FC_PFC_CFG.CLU1[0x54c]=5
CLU_FC_PFC_CFG.CLU2[0x54c]=5
CLU_FC_PFC_DEBUG_INDICATIONS.CLU0[0x588]=0
CLU_FC_PFC_DEBUG_INDICATIONS.CLU1[0x588]=0
CLU_FC_PFC_DEBUG_INDICATIONS.CLU2[0x588]=0
CLU_FC_PFC_RX_BITMAP_MAP_FORCE_EN.CLU0[0x559]=0xfff
CLU_FC_PFC_RX_BITMAP_MAP_FORCE_EN.CLU1[0x559]=0xfff
CLU_FC_PFC_RX_BITMAP_MAP_FORCE_EN.CLU2[0x559]=0xfff
CLU_FC_PFC_RX_BITMAP_TYPE_A.CLU0[0x553]=0xff008040201008040201
CLU_FC_PFC_RX_BITMAP_TYPE_A.CLU1[0x553]=0xff008040201008040201
CLU_FC_PFC_RX_BITMAP_TYPE_A.CLU2[0x553]=0xff008040201008040201
CLU_FC_PFC_RX_BITMAP_TYPE_B.CLU0[0x556]=0xff008040201008040201
CLU_FC_PFC_RX_BITMAP_TYPE_B.CLU1[0x556]=0xff008040201008040201
CLU_FC_PFC_RX_BITMAP_TYPE_B.CLU2[0x556]=0xff008040201008040201
CLU_FC_PFC_RX_BITMAP_TYPE_PER_PORT.CLU0[0x55a]=0
CLU_FC_PFC_RX_BITMAP_TYPE_PER_PORT.CLU1[0x55a]=0
CLU_FC_PFC_RX_BITMAP_TYPE_PER_PORT.CLU2[0x55a]=0
CLU_FC_PFC_TX_BITMAP_TYPE_A.CLU0[0x55b]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_A.CLU1[0x55b]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_A.CLU2[0x55b]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_B.CLU0[0x55e]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_B.CLU1[0x55e]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_B.CLU2[0x55e]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_C.CLU0[0x561]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_C.CLU1[0x561]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_C.CLU2[0x561]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_D.CLU0[0x564]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_D.CLU1[0x564]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_D.CLU2[0x564]=0xfff8040201008040201
CLU_FC_PFC_TX_BITMAP_TYPE_PER_PORT.CLU0[0x567]=0
CLU_FC_PFC_TX_BITMAP_TYPE_PER_PORT.CLU1[0x567]=0
CLU_FC_PFC_TX_BITMAP_TYPE_PER_PORT.CLU2[0x567]=0
CLU_FC_RESET.CLU0[0x54b]=0
CLU_FC_RESET.CLU1[0x54b]=0
CLU_FC_RESET.CLU2[0x54b]=0
CLU_FC_RX_GEN_LLFC_FROM_QMLF.CLU0[0x576]=0
CLU_FC_RX_GEN_LLFC_FROM_QMLF.CLU1[0x576]=0
CLU_FC_RX_GEN_LLFC_FROM_QMLF.CLU2[0x576]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(0).CLU0[0x577]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(1).CLU0[0x578]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(2).CLU0[0x579]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(3).CLU0[0x57a]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(4).CLU0[0x57b]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(5).CLU0[0x57c]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(6).CLU0[0x57d]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(7).CLU0[0x57e]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(8).CLU0[0x57f]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(9).CLU0[0x580]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(10).CLU0[0x581]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(11).CLU0[0x582]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(0).CLU1[0x577]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(1).CLU1[0x578]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(2).CLU1[0x579]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(3).CLU1[0x57a]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(4).CLU1[0x57b]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(5).CLU1[0x57c]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(6).CLU1[0x57d]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(7).CLU1[0x57e]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(8).CLU1[0x57f]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(9).CLU1[0x580]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(10).CLU1[0x581]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(11).CLU1[0x582]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(0).CLU2[0x577]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(1).CLU2[0x578]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(2).CLU2[0x579]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(3).CLU2[0x57a]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(4).CLU2[0x57b]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(5).CLU2[0x57c]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(6).CLU2[0x57d]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(7).CLU2[0x57e]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(8).CLU2[0x57f]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(9).CLU2[0x580]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(10).CLU2[0x581]=0
CLU_FC_RX_GEN_PFC_FROM_QMLF_PORT(11).CLU2[0x582]=0
CLU_FC_TX_GEN_LLFC_FORCE.CLU0[0x54d]=0
CLU_FC_TX_GEN_LLFC_FORCE.CLU1[0x54d]=0
CLU_FC_TX_GEN_LLFC_FORCE.CLU2[0x54d]=0
CLU_FC_TX_GEN_LLFC_FROM_CFC.CLU0[0x583]=0
CLU_FC_TX_GEN_LLFC_FROM_CFC.CLU1[0x583]=0
CLU_FC_TX_GEN_LLFC_FROM_CFC.CLU2[0x583]=0
CLU_FC_TX_GEN_LLFC_FROM_CFC_MASK.CLU0[0x550]=0xfff
CLU_FC_TX_GEN_LLFC_FROM_CFC_MASK.CLU1[0x550]=0xfff
CLU_FC_TX_GEN_LLFC_FROM_CFC_MASK.CLU2[0x550]=0xfff
CLU_FC_TX_GEN_LLFC_TO_PM.CLU0[0x584]=0
CLU_FC_TX_GEN_LLFC_TO_PM.CLU1[0x584]=0
CLU_FC_TX_GEN_LLFC_TO_PM.CLU2[0x584]=0
CLU_FC_TX_GEN_PFC_FORCE.CLU0[0x54f]=0
CLU_FC_TX_GEN_PFC_FORCE.CLU1[0x54f]=0
CLU_FC_TX_GEN_PFC_FORCE.CLU2[0x54f]=0
CLU_FC_TX_GEN_PFC_FORCE_MASK.CLU0[0x552]=0
CLU_FC_TX_GEN_PFC_FORCE_MASK.CLU1[0x552]=0
CLU_FC_TX_GEN_PFC_FORCE_MASK.CLU2[0x552]=0
CLU_FC_TX_LLFC_STOP_TX_FROM_CFC.CLU0[0x585]=0
CLU_FC_TX_LLFC_STOP_TX_FROM_CFC.CLU1[0x585]=0
CLU_FC_TX_LLFC_STOP_TX_FROM_CFC.CLU2[0x585]=0
CLU_FC_TX_LLFC_STOP_TX_TO_PM.CLU0[0x586]=0
CLU_FC_TX_LLFC_STOP_TX_TO_PM.CLU1[0x586]=0
CLU_FC_TX_LLFC_STOP_TX_TO_PM.CLU2[0x586]=0
CLU_FC_TX_LOW_PASS_FILTER.CLU0[0x569]=0x10100
CLU_FC_TX_LOW_PASS_FILTER.CLU1[0x569]=0x10100
CLU_FC_TX_LOW_PASS_FILTER.CLU2[0x569]=0x10100
CLU_FIFO_WRITE_POINTER_QMLF_SELECT.CLU0[0x493]=0
CLU_FIFO_WRITE_POINTER_QMLF_SELECT.CLU1[0x493]=0
CLU_FIFO_WRITE_POINTER_QMLF_SELECT.CLU2[0x493]=0
CLU_FIFO_WRITE_POINTER_RESULT.CLU0[0x494]=0xf80af
CLU_FIFO_WRITE_POINTER_RESULT.CLU1[0x494]=0x20000
CLU_FIFO_WRITE_POINTER_RESULT.CLU2[0x494]=0x20000
CLU_FLUSH_OR_STOP_RX_FIFO.CLU0[0x626]=0x1fffe
CLU_FLUSH_OR_STOP_RX_FIFO.CLU1[0x626]=0x1fffe
CLU_FLUSH_OR_STOP_RX_FIFO.CLU2[0x626]=0x1fffe
CLU_FLUSH_SOP_WITH_ERR_CONFIG.CLU0[0x27d]=0xffffff
CLU_FLUSH_SOP_WITH_ERR_CONFIG.CLU1[0x27d]=0xffffff
CLU_FLUSH_SOP_WITH_ERR_CONFIG.CLU2[0x27d]=0xffffff
CLU_GTIMER_CONFIGURATION.CLU0[0x89]=0
CLU_GTIMER_CONFIGURATION.CLU1[0x89]=0
CLU_GTIMER_CONFIGURATION.CLU2[0x89]=0
CLU_GTIMER_CYCLE.CLU0[0x88]=0x3b9aca00
CLU_GTIMER_CYCLE.CLU1[0x88]=0x3b9aca00
CLU_GTIMER_CYCLE.CLU2[0x88]=0x3b9aca00
CLU_INDIRECT_COMMAND.CLU0[0x80]=0xe000002
CLU_INDIRECT_COMMAND.CLU1[0x80]=0xe000002
CLU_INDIRECT_COMMAND.CLU2[0x80]=0xe000002
CLU_INDIRECT_COMMAND_ADDRESS.CLU0[0x81]=0x119600
CLU_INDIRECT_COMMAND_ADDRESS.CLU1[0x81]=0x119600
CLU_INDIRECT_COMMAND_ADDRESS.CLU2[0x81]=0x119600
CLU_INDIRECT_COMMAND_RD_DATA.CLU0[0x60]=0xffff9fffff7ffffdfffafffbefffffbfefdbffffffbfdffffffbfffb6fff7efbfe77fffbf5fffffdff7fffffbffffefffff
CLU_INDIRECT_COMMAND_RD_DATA.CLU1[0x60]=0xfbfff7eeefebfffffffffff7ffffdfffb7ffff7fbffefffffffdfffffffbffffbffffffbffffffffffffb5fffaf7fbffeff
CLU_INDIRECT_COMMAND_RD_DATA.CLU2[0x60]=0xfffffcefeffff7f7fffdffffdfffffffffffffffdfffffffffffffffffffffff7fffffffffffdffffffbfffefef7fbfffff
CLU_INDIRECT_COMMAND_WR_DATA.CLU0[0x20]=0
CLU_INDIRECT_COMMAND_WR_DATA.CLU1[0x20]=0
CLU_INDIRECT_COMMAND_WR_DATA.CLU2[0x20]=0
CLU_INDIRECT_FORCE_BUBBLE.CLU0[0x83]=0x20019
CLU_INDIRECT_FORCE_BUBBLE.CLU1[0x83]=0x20019
CLU_INDIRECT_FORCE_BUBBLE.CLU2[0x83]=0x20019
CLU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION.CLU0[0x60f]=0
CLU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION.CLU1[0x60f]=0
CLU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION.CLU2[0x60f]=0
CLU_INSTRUMENTATION_DEBUG_WRAP_AROUND.CLU0[0x609]=0
CLU_INSTRUMENTATION_DEBUG_WRAP_AROUND.CLU1[0x609]=0
CLU_INSTRUMENTATION_DEBUG_WRAP_AROUND.CLU2[0x609]=0
CLU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.CLU0[0x492]=0
CLU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.CLU1[0x492]=0
CLU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.CLU2[0x492]=0
CLU_INSTRUMENTATION_INTERVALS_COUNTER.CLU0[0x60b]=0
CLU_INSTRUMENTATION_INTERVALS_COUNTER.CLU1[0x60b]=0
CLU_INSTRUMENTATION_INTERVALS_COUNTER.CLU2[0x60b]=0
CLU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN.CLU0[0x60a]=0
CLU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN.CLU1[0x60a]=0
CLU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN.CLU2[0x60a]=0
CLU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED.CLU0[0x607]=0xf
CLU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED.CLU1[0x607]=0xf
CLU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED.CLU2[0x607]=0xf
CLU_INSTRUMENTATION_OVERRIDE_MODE.CLU0[0x608]=1
CLU_INSTRUMENTATION_OVERRIDE_MODE.CLU1[0x608]=1
CLU_INSTRUMENTATION_OVERRIDE_MODE.CLU2[0x608]=1
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(0).CLU0[0x5d6]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(1).CLU0[0x5d7]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(2).CLU0[0x5d8]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(3).CLU0[0x5d9]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(4).CLU0[0x5da]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(5).CLU0[0x5db]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(6).CLU0[0x5dc]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(7).CLU0[0x5dd]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(8).CLU0[0x5de]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(9).CLU0[0x5df]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(10).CLU0[0x5e0]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(11).CLU0[0x5e1]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(0).CLU1[0x5d6]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(1).CLU1[0x5d7]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(2).CLU1[0x5d8]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(3).CLU1[0x5d9]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(4).CLU1[0x5da]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(5).CLU1[0x5db]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(6).CLU1[0x5dc]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(7).CLU1[0x5dd]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(8).CLU1[0x5de]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(9).CLU1[0x5df]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(10).CLU1[0x5e0]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(11).CLU1[0x5e1]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(0).CLU2[0x5d6]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(1).CLU2[0x5d7]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(2).CLU2[0x5d8]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(3).CLU2[0x5d9]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(4).CLU2[0x5da]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(5).CLU2[0x5db]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(6).CLU2[0x5dc]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(7).CLU2[0x5dd]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(8).CLU2[0x5de]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(9).CLU2[0x5df]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(10).CLU2[0x5e0]=0
CLU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT(11).CLU2[0x5e1]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(0).CLU0[0x5e2]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(1).CLU0[0x5e3]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(2).CLU0[0x5e4]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(3).CLU0[0x5e5]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(4).CLU0[0x5e6]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(5).CLU0[0x5e7]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(6).CLU0[0x5e8]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(7).CLU0[0x5e9]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(8).CLU0[0x5ea]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(9).CLU0[0x5eb]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(10).CLU0[0x5ec]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(11).CLU0[0x5ed]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(0).CLU1[0x5e2]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(1).CLU1[0x5e3]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(2).CLU1[0x5e4]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(3).CLU1[0x5e5]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(4).CLU1[0x5e6]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(5).CLU1[0x5e7]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(6).CLU1[0x5e8]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(7).CLU1[0x5e9]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(8).CLU1[0x5ea]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(9).CLU1[0x5eb]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(10).CLU1[0x5ec]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(11).CLU1[0x5ed]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(0).CLU2[0x5e2]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(1).CLU2[0x5e3]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(2).CLU2[0x5e4]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(3).CLU2[0x5e5]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(4).CLU2[0x5e6]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(5).CLU2[0x5e7]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(6).CLU2[0x5e8]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(7).CLU2[0x5e9]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(8).CLU2[0x5ea]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(9).CLU2[0x5eb]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(10).CLU2[0x5ec]=0
CLU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT(11).CLU2[0x5ed]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(0).CLU0[0x5ee]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(1).CLU0[0x5ef]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(2).CLU0[0x5f0]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(3).CLU0[0x5f1]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(4).CLU0[0x5f2]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(5).CLU0[0x5f3]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(6).CLU0[0x5f4]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(7).CLU0[0x5f5]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(8).CLU0[0x5f6]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(9).CLU0[0x5f7]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(10).CLU0[0x5f8]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(11).CLU0[0x5f9]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(0).CLU1[0x5ee]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(1).CLU1[0x5ef]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(2).CLU1[0x5f0]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(3).CLU1[0x5f1]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(4).CLU1[0x5f2]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(5).CLU1[0x5f3]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(6).CLU1[0x5f4]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(7).CLU1[0x5f5]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(8).CLU1[0x5f6]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(9).CLU1[0x5f7]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(10).CLU1[0x5f8]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(11).CLU1[0x5f9]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(0).CLU2[0x5ee]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(1).CLU2[0x5ef]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(2).CLU2[0x5f0]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(3).CLU2[0x5f1]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(4).CLU2[0x5f2]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(5).CLU2[0x5f3]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(6).CLU2[0x5f4]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(7).CLU2[0x5f5]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(8).CLU2[0x5f6]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(9).CLU2[0x5f7]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(10).CLU2[0x5f8]=0
CLU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT(11).CLU2[0x5f9]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(0).CLU0[0x5fa]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(1).CLU0[0x5fb]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(2).CLU0[0x5fc]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(3).CLU0[0x5fd]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(4).CLU0[0x5fe]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(5).CLU0[0x5ff]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(6).CLU0[0x600]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(7).CLU0[0x601]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(8).CLU0[0x602]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(9).CLU0[0x603]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(10).CLU0[0x604]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(11).CLU0[0x605]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(0).CLU1[0x5fa]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(1).CLU1[0x5fb]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(2).CLU1[0x5fc]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(3).CLU1[0x5fd]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(4).CLU1[0x5fe]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(5).CLU1[0x5ff]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(6).CLU1[0x600]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(7).CLU1[0x601]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(8).CLU1[0x602]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(9).CLU1[0x603]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(10).CLU1[0x604]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(11).CLU1[0x605]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(0).CLU2[0x5fa]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(1).CLU2[0x5fb]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(2).CLU2[0x5fc]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(3).CLU2[0x5fd]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(4).CLU2[0x5fe]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(5).CLU2[0x5ff]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(6).CLU2[0x600]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(7).CLU2[0x601]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(8).CLU2[0x602]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(9).CLU2[0x603]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(10).CLU2[0x604]=0
CLU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT(11).CLU2[0x605]=0
CLU_INSTRUMENTATION_PFC_DEBUG_AND_BREAKING_MECHANISM.CLU0[0x610]=0
CLU_INSTRUMENTATION_PFC_DEBUG_AND_BREAKING_MECHANISM.CLU1[0x610]=0
CLU_INSTRUMENTATION_PFC_DEBUG_AND_BREAKING_MECHANISM.CLU2[0x610]=0
CLU_INSTRUMENTATION_RESET_LOW.CLU0[0x60c]=1
CLU_INSTRUMENTATION_RESET_LOW.CLU1[0x60c]=1
CLU_INSTRUMENTATION_RESET_LOW.CLU2[0x60c]=1
CLU_INSTRUMENTATION_RSTN_PFC_CNTS.CLU0[0x60e]=0xfff
CLU_INSTRUMENTATION_RSTN_PFC_CNTS.CLU1[0x60e]=0xfff
CLU_INSTRUMENTATION_RSTN_PFC_CNTS.CLU2[0x60e]=0xfff
CLU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS.CLU0[0x60d]=0xfff
CLU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS.CLU1[0x60d]=0xfff
CLU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS.CLU2[0x60d]=0xfff
CLU_INSTRUMENTATION_TIME_FACTOR_FOR_PFC_CNTS.CLU0[0x606]=0xa00000000
CLU_INSTRUMENTATION_TIME_FACTOR_FOR_PFC_CNTS.CLU1[0x606]=0xa00000000
CLU_INSTRUMENTATION_TIME_FACTOR_FOR_PFC_CNTS.CLU2[0x606]=0xa00000000
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(0).CLU0[0x5be]=0x4324c26691d00000002e325b702
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(1).CLU0[0x5bf]=0x1a3ca8ae4ca00000001352b490e
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(2).CLU0[0x5c0]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(3).CLU0[0x5c1]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(4).CLU0[0x5c2]=0x55d016f593d0000000337e0c600
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(5).CLU0[0x5c3]=0x35e38863d8a00000001c3bf6765
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(6).CLU0[0x5c4]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(7).CLU0[0x5c5]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(8).CLU0[0x5c6]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(9).CLU0[0x5c7]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(10).CLU0[0x5c8]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(11).CLU0[0x5c9]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(0).CLU1[0x5be]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(1).CLU1[0x5bf]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(2).CLU1[0x5c0]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(3).CLU1[0x5c1]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(4).CLU1[0x5c2]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(5).CLU1[0x5c3]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(6).CLU1[0x5c4]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(7).CLU1[0x5c5]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(8).CLU1[0x5c6]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(9).CLU1[0x5c7]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(10).CLU1[0x5c8]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(11).CLU1[0x5c9]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(0).CLU2[0x5be]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(1).CLU2[0x5bf]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(2).CLU2[0x5c0]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(3).CLU2[0x5c1]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(4).CLU2[0x5c2]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(5).CLU2[0x5c3]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(6).CLU2[0x5c4]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(7).CLU2[0x5c5]=0x582ca9acf7f700000012ada1bc08
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(8).CLU2[0x5c6]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(9).CLU2[0x5c7]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(10).CLU2[0x5c8]=0
CLU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT(11).CLU2[0x5c9]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(0).CLU0[0x5ca]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(1).CLU0[0x5cb]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(2).CLU0[0x5cc]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(3).CLU0[0x5cd]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(4).CLU0[0x5ce]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(5).CLU0[0x5cf]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(6).CLU0[0x5d0]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(7).CLU0[0x5d1]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(8).CLU0[0x5d2]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(9).CLU0[0x5d3]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(10).CLU0[0x5d4]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(11).CLU0[0x5d5]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(0).CLU1[0x5ca]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(1).CLU1[0x5cb]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(2).CLU1[0x5cc]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(3).CLU1[0x5cd]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(4).CLU1[0x5ce]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(5).CLU1[0x5cf]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(6).CLU1[0x5d0]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(7).CLU1[0x5d1]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(8).CLU1[0x5d2]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(9).CLU1[0x5d3]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(10).CLU1[0x5d4]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(11).CLU1[0x5d5]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(0).CLU2[0x5ca]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(1).CLU2[0x5cb]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(2).CLU2[0x5cc]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(3).CLU2[0x5cd]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(4).CLU2[0x5ce]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(5).CLU2[0x5cf]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(6).CLU2[0x5d0]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(7).CLU2[0x5d1]=0x3f7e600000000000000ba100000000000000000000000000000000
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(8).CLU2[0x5d2]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(9).CLU2[0x5d3]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(10).CLU2[0x5d4]=0
CLU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT(11).CLU2[0x5d5]=0
CLU_INTERRUPT_MASK_REGISTER.CLU0[0x10]=0
CLU_INTERRUPT_MASK_REGISTER.CLU1[0x10]=0
CLU_INTERRUPT_MASK_REGISTER.CLU2[0x10]=0
CLU_INTERRUPT_REGISTER.CLU0[0x0]=2
CLU_INTERRUPT_REGISTER.CLU1[0x0]=2
CLU_INTERRUPT_REGISTER.CLU2[0x0]=2
CLU_INTERRUPT_REGISTER_TEST.CLU0[0x18]=0
CLU_INTERRUPT_REGISTER_TEST.CLU1[0x18]=0
CLU_INTERRUPT_REGISTER_TEST.CLU2[0x18]=0
CLU_LAST_RECEIVED_FROM_EGQ_CONTROLS.CLU0[0x36b]=0x8007485
CLU_LAST_RECEIVED_FROM_EGQ_CONTROLS.CLU1[0x36b]=0xbe03985
CLU_LAST_RECEIVED_FROM_EGQ_CONTROLS.CLU2[0x36b]=0x8001ff7
CLU_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP.CLU0[0x36c]=0x85531f9b5d4de26794a6d19810000030800450005d83ad140003606a850976541a40a0b78ea01bbf7edc4cfb88315c78b57801801b95d3200000101080a1db1
CLU_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP.CLU1[0x36c]=0xffffffffffff94434dbc3a858100007f080045100162000000008011397c00000000ffffffff00440043014e820201010600cf3a313c00a40000000000000000
CLU_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP.CLU2[0x36c]=0xde26794a6d19c4ad34e1e4be81000003080045000028000040003f06ce90c0a80a67113990f7c6ae146732ac471f0000000050040000edbf0000000000000000
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(0).CLU0[0x29f]=0xde26794a6d19744d28ac24d58100000208004500003f8d8b40007f11095a0a0b7615adc236e6e57a01bb002b960247edd4807cd55254950e5db2839c8668c1291
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(1).CLU0[0x2a0]=0xde26794a6d19c4ad34e1e4be81000003080045000028000040003f06ce90c0a80a67113990f7c6ae146732ac471f0000000050040000edbf00000000000000001
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(2).CLU0[0x2a1]=0xf777ce12eeeb57270fc97ed5bf8f6fffff7b3fb04c96b1f1f3d1b78c83f6fe3f35edd7c77e60a7c3925c7ac9afe3f5dfddfbb5eddd56265b0688fb5fd93b7e69c
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(3).CLU0[0x2a2]=0xbf595ae56d45ec6cc8c7367212ff9f3012b0ef3ab9b97f4ff5ae7d9fa6a6582fde6771b3fa6fd6b9f1bbf833d366acda6cdb5f7d6df3e783ffa7c68787f31f472
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(4).CLU0[0x2a3]=0xde26794a6d196c3b6ba751c38100000408004500004d000040003f11393e0a0b7906a2fddc53a488050e0039a8963088035387a58a3705e3c20675515de89a731
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(5).CLU0[0x2a4]=0xde26794a6d19cc2de0238ee981000005080045000034000040003e06e7400a0b7ad511f8beabe5e701bbf47ad3b13ae8965580100800b9dd00000101080ae3631
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(6).CLU0[0x2a5]=0xefba0bffed4b6f745f57ffe8dab9b7effee474c97e3f1ab797e86c36db576c6da9d2df8f71d4767f8c85a6e5495675fadd9abb3e8f7b12bacfeea77427adee3ee
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(7).CLU0[0x2a6]=0x614ffb6ae7a76ffc3de761edfcfb1fdc6a5bda7b36f8fc6f65f8e61f3bff0ff5f857fddefca86bbeff77eabcf35970fb4e56fec7ef7a79d3e76ed65b1d7e35c70
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(8).CLU0[0x2a7]=0x36404152aa922509602f148ae569832be9faea0dfde5fd6ec34bcce2dbf0f7ebe7ff1f1efe1d9d25d5e841eb7987e7b8667fc3fdac8dafdf1745eb9dbef9e6ca8
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(9).CLU0[0x2a8]=0x760083528a8a3608687d058aed6dc723edfeee99bdedffaec7cb4fe2dff0f7ebcfff9b1efe1d9537dcfa67e77bafffbf6e7fa3fdbecfab9f9765abdd3ffdee8a8
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(10).CLU0[0x2a9]=0xa9117ab9fe1a97f93ad63bf33e91efdbfe7de8c71bdfc056e7d67996c1f427bf0cf15af7d4327fdf9afefbbc56cfd7ad5ecdeafb9a4d75bfe4f8e6fb95dfe6dbc
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(11).CLU0[0x2aa]=0x1df6015a8e77d5d5bb16efdfdf1feaf3e1c79bb75d2ffada90aaeb8da5b6c9a0ad5bbedbbf2bb1b1c73fdbbbf1fa401b446caebd7a5c47736adb3ed74bf7fff2a
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(0).CLU1[0x29f]=0xfd397bf7f8f967fdde3bab5f5f7777f739fffe5731ed79db1df3b5ffea56b7edd5e4fbdf9d8fe9feb7ecd7bde7ff6fceef74ffffe47f3b57fff77ec77619dcef2
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(1).CLU1[0x2a0]=0x559cd9bf9dd9eaefbffa6bfd5ab67681bba7fafd3ba77d37d757a37d3fdfebffefda2ff51b75bb9ffe7cfdabe9fbde2b78fb8645ffe2d9df6fdafb7ff8fb09676
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(2).CLU1[0x2a1]=0x1bff9f4ec0f9ace2b740f69b27e9f37ae1fb9fea7ebf97fdbd2cfb2fbf7e9ef7f5d79affbe3fbba6fb76e3eead98bfbe7b77f7e31f7e76f543deb5cc54bdc4f7e
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(3).CLU1[0x2a2]=0xbefeffd7eb576d7e3dbffddebfdbe7fef3fb7fe7abf777ef741dccda2eafd5ffbff793f3faf7cf7e9b5eb43f6befecfd65ffbb8912fffabdbaf7dfc5f7efaded4
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(4).CLU1[0x2a3]=0x744979e35efcdef7ebfcfe6beea3fff0f01bf7effbffcaffd777fd7efcdfaaffcfe53fedf7dfa2f93ffda727c5afffb7df77efcff11cb3b66ef5da3d877f76f9e
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(5).CLU1[0x2a4]=0xd0c55f5fdbf7813af667ddd1ec87dfcfffffbf494ff6b36ed15d55ffbb9def77dffbbab5373af77fbfbff7baf775dfd76ffff336f2af2dbefd9ef6bffffff2fbe
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(6).CLU1[0x2a5]=0xf116d7f7b3f626ca757d7abeebbf957fcbf4faadf59b7f77ee6dfd63d352e9fdbf49fff9effbfbeffbef8fdabdba7d77d773dce81ffa6373cbda5ae6e7ffbcefe
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(7).CLU1[0x2a6]=0xab4fca5d7a7fbd71ecc7fffbfea4ff7df19779d7fb3fe2463ddfd3af76675bfecf3b2ebff7ff4def59ee27d933ef5beb37fdefefdacf17b298707b577f8dbfe76
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(8).CLU1[0x2a7]=0xbb6edb9fbeddffdefedfdffd7bb7a3ed8dbdefedfb3fd7ce3c77d65ffb4f67f1fd63edfefca27f7fdfdbddb63d7ffeef7574fdfbff8fdffffb0fb3eff7f3f7bf0
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(9).CLU1[0x2a8]=0xcffaed507f1efeeee60f4fe77dafe81adbeb5feedffb9ff755afa77edab9f7db5ffd7bef2f5fbc7a06e9478e4cb1dcf7ff1bfc5bfffbfffe7cfbf4d7fdfd50de6
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(10).CLU1[0x2a9]=0xdaed0dd1bd5deb77fffae3f95f9fffeffe38f376bbdbd7dfd55be7be7ffbd4caf5af19df53494f75736bfb5a6d231d7f7569adea37c7326eccfae967bf4ed6d0c
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(11).CLU1[0x2aa]=0x75737bfff6717d1e1f58fcffc5acbef5bffa67ff3bd5cefbf75eaed7bffdbffbffbfeaea7bec6fdbff6debf6fbfff3f17fbfad72ff2b5eef7eafbfff7affadbd0
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(0).CLU2[0x29f]=0xff339fff17eeeefff66ceffe7dfbf6ffbd6fabc5fe4ff7fb78b7d77f77de8febb36df61fffdb86ffcefa5fbf6fc5ff7fbfff9bebefdbfed5eb37f48b5ffed4ffa
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(1).CLU2[0x2a0]=0x75f77593f3fcf6b7bfa6ff377ffff7ff6667fbf77f73fbf0df7bf3a5f7fffefdde8ffa7fb1df9e7bfb39f5e5fcf7f7fa5f9ff65dbe8edccbbbfef1fd7b6f9fd76
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(2).CLU2[0x2a1]=0xbde8fa6deef7dbf3fff0affbb7ffef77edf9ff1fb5bfc7f8bfd7fc7f74fdfb747fc9dfd6ef57b9aefbeeafffde956dd5dffe77cff968fda75ffeeff797f7e3fec
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(3).CLU2[0x2a2]=0x37fbdff7feedefdaf75df8e44dedd7d7dbba2dfbd69bce7af8cfffff7ebef7dedbd7f9fafbfffbf7dfbdfddf73f9dfdeebbee535c3fb7dfafc750feffbfff3fee
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(4).CLU2[0x2a3]=0x7dfd7ff3eff2f33cfbdddffffff787fdfbffbfbf5f72fff7f3b7c4fbff4f3f6fffd7bfbedabbfc77fdf7edd7df35f6ceb0733f3fedf298ddddfcb776e9bdf5fae
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(5).CLU2[0x2a4]=0xd7feefb6da7d6ef5ffffbbfdff5afe67b1fe5fafdc7a3caf5e3dff17b7f939e2bfdfffffaed7aecefcf71fdbf1ffbefdf8f7ffdfdff7ea5ff7ffb7ff5bfb57eb4
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(6).CLU2[0x2a5]=0x7a9fffcfd7cffecd6ff6fbfff7fff5bfefaefb4f6e57b9377be5fdeeb5d9ddabbdf4e5ef75debbbf7dfdaef7a9f7bf4fd475cbff9ffff73f7cfe8b6fffeeeffc6
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(7).CLU2[0x2a6]=0x85531f9b38ede26794a6d19810000030800450005dc8385400031066d5111f8be500a0b78f201bbd594146c2bac6f6e8253801009d0b2b300000101080a79d71
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(8).CLU2[0x2a7]=0x7bffbfbf7bf6ffdaf756eedf3cfffe7fffcffaeeee7ffffd2fddbddb756cffbf7f5abffabcddf2ffbbfb9fe33be3ff2d6e5bfbafff7b5eec9f6ffdfdb8bff6df8
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(9).CLU2[0x2a8]=0xfbfdf7f96eaeedf9eaebf9d3dfefe6ba9ffbedff9f8f3ffbebfdfefffd7f9fbe5957b5db7faafef1b945eb9f7ddc7dcaf75e7577f7fedff6fde7d1feaffecb37c
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(10).CLU2[0x2a9]=0xa7defb8fff766d3fff77b52d578bf7be7ff6bdebffbfd3bcdf7df6bebdde5be75bff176fff77ffbdb3d3fdefdf157f66cde2ffcdedfd9fdff13ddf7fceeb76efc
CLU_LAST_RECEIVED_FROM_PARSER_PER_PORT(11).CLU2[0x2aa]=0xffdffffffeddfffffffffffdfffffffffcfb3dbfffeff1ff7fddffbedffbefdffbfffffbfffff7fbffef7ff7ffffeffffffffdffff7fffffffffafffffffbfff8
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(0).CLU0[0x3b5]=0x7489b0b5e0b05
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(1).CLU0[0x3b6]=0x746d942401595
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(2).CLU0[0x3b7]=0x1ff7bfff7f17be
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(0).CLU1[0x3b5]=0x10001a3a
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(1).CLU1[0x3b6]=0x1214
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(2).CLU1[0x3b7]=0x4800001a01fbe
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(0).CLU2[0x3b5]=0xfa5fdf96b0ab2
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(1).CLU2[0x3b6]=0x74a7709100f35
CLU_LAST_RECEIVED_FROM_PM_CONTROLS(2).CLU2[0x3b7]=0x210500015be
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(0).CLU0[0x3bb]=0xde26794a6d19085531f9b5d481000003080045000034000040003e06e0c50a0b78ea976541a4f7ed01bb15c78b57c4cf
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(1).CLU0[0x3bc]=0xde26794a6d19cc2de0d8e746810000050800450001092e1d40007f1198bc0a0b7afa8efb200adf7c01bb00f5baea4875
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(2).CLU0[0x3bd]=0xff0f39ffd7f96ddfb5f971dfbbfbfbfe7bf77de2f7afbe24f7c5bfd9effe3f63feaafebf87fbf7f9ffbbffffffa3b9fd
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(0).CLU1[0x3bb]=0xcebdcffd7f6fed3debf7b5fdfbfffcfffb57d6edfbbabfffffeddf3ffdfff7b6dfbef7badf7fbffbff3edbfff6ffffdb
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(1).CLU1[0x3bc]=0xbacf6fffb183ed7c7e57757c57b7fff19d51ff6777f6502ff6aff7e7fed6b39dfeef567be72f87f5fddd7cfeebe333f9
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(2).CLU1[0x3bd]=0x6a1fc43e7bdc3edf43dd6ade8fedffaf97e99cda2e7f379f6ebdf570f9a7f7f67e1deff7db66d1ebfafaf599dd9f7b7e
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(0).CLU2[0x3bb]=0xf5ef97f4b322fadee5fff9ffd06eb7bffa2ef1e6bafd3e9ded7efddd87f8ff7bdfaf7a17feefaf77ecf19ab6fee7aed9
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(1).CLU2[0x3bc]=0xdc2c6e7e8e7ede26794a6d19810000040800450005dce1ae00003706b6d308f0597c0a0b79230050adb84fa310439bb0
CLU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP(2).CLU2[0x3bd]=0xffbf7ffffffbf6f9fff3ff3fbbd7fb0ddebf78f58dbf7f6bfd7dfcdd6f875fff76f5ff7ffedefef6ffaebeb8febceff7
CLU_LAST_SENT_TO_IRE_CONTROLS.CLU0[0x37c]=0x74b2b98c3a915
CLU_LAST_SENT_TO_IRE_CONTROLS.CLU1[0x37c]=0x2717ff539d78ee9c
CLU_LAST_SENT_TO_IRE_CONTROLS.CLU2[0x37c]=0x74bc9c19bb6f5
CLU_LAST_SENT_TO_IRE_DATA_ON_SOP.CLU0[0x37e]=0xde26794a6d19085531f9b38e810000030800450005d9000040003e11fc910a0b78f28efb288ad37301bb05c5dcd37347f75a1e9177a9e9b90d7241877482fef4
CLU_LAST_SENT_TO_IRE_DATA_ON_SOP.CLU1[0x37e]=0xefff775fb57df79f7cea37dcfbf7efcbf7cfbc53e9fbb2edaf6b92ff3effefd9eb27767fcaf73fdfffbffff4f49ffbd7de35e7b92ee9fbf1c370f6defeebeee6
CLU_LAST_SENT_TO_IRE_DATA_ON_SOP.CLU2[0x37e]=0x85531f9b38ede26794a6d19810000030800450005dcf49740003106fc3e11f8be500a0b78f201bbd5921edd0d7a2536acea80100aebd19800000101080a79d7
CLU_LAST_SENT_TO_PM_CONTROLS(0).CLU0[0x38e]=0x8008f15
CLU_LAST_SENT_TO_PM_CONTROLS(1).CLU0[0x38f]=0x8008f05
CLU_LAST_SENT_TO_PM_CONTROLS(2).CLU0[0x390]=0xfc09334
CLU_LAST_SENT_TO_PM_CONTROLS(0).CLU1[0x38e]=0xfc09534
CLU_LAST_SENT_TO_PM_CONTROLS(1).CLU1[0x38f]=0xfc09534
CLU_LAST_SENT_TO_PM_CONTROLS(2).CLU1[0x390]=0xfc09534
CLU_LAST_SENT_TO_PM_CONTROLS(0).CLU2[0x38e]=0xfc09832
CLU_LAST_SENT_TO_PM_CONTROLS(1).CLU2[0x38f]=0x8009335
CLU_LAST_SENT_TO_PM_CONTROLS(2).CLU2[0x390]=0x1fea0fbe
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(0).CLU0[0x391]=0x85531f9b38ede26794a6d19810000030800450005dcf49840003106fc3d11f8be500a0b78f201bbd5921edd13222536
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(1).CLU0[0x392]=0xdc2c6e7e8e7ede26794a6d19810000040800450005dce1b200003706b6cf08f0597c0a0b79230050adb84fa326e39bb0
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(2).CLU0[0x393]=0x33330000001694434dbc3a858100007f86dd60000000004c0001fe8000000000000096434dfffebc3a85ff0200000000
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(0).CLU1[0x391]=0x33330000000194434dbc3a858100007f86dd6000000000203afffe8000000000000096434dfffebc3a85ff0200000000
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(1).CLU1[0x392]=0x33330000000194434dbc3a858100007f86dd6000000000203afffe8000000000000096434dfffebc3a85ff0200000000
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(2).CLU1[0x393]=0x33330000000194434dbc3a858100007f86dd6000000000203afffe8000000000000096434dfffebc3a85ff0200000000
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(0).CLU2[0x391]=0x33330000001694434dbc3a858100007f86dd60000000004c0001fe8000000000000096434dfffebc3a85ff0200000000
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(1).CLU2[0x392]=0xde26794a6d19085531f9b5bc810000020800450005b42c8740003e061fe30a0b761e23ba46f793ec01bb6fbd1a788313
CLU_LAST_SENT_TO_PM_DATA_ON_SOP(2).CLU2[0x393]=0x73f7f3e7bedbfdbddecfd2fd59fd97ecffefa7fefe9e3fc7dfdff27f57fffd74b75775ffa7a155fcf5dd6bd2dfeffd7d
CLU_LINK_ACTIVE.CLU0[0x29a]=0x330033
CLU_LINK_ACTIVE.CLU1[0x29a]=0
CLU_LINK_ACTIVE.CLU2[0x29a]=0x800080
CLU_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER.CLU0[0x11]=0
CLU_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER.CLU1[0x11]=0
CLU_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER.CLU2[0x11]=0
CLU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER.CLU0[0x1]=0x33
CLU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER.CLU1[0x1]=0
CLU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER.CLU2[0x1]=0x80
CLU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST.CLU0[0x19]=0
CLU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST.CLU1[0x19]=0
CLU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST.CLU2[0x19]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER.CLU0[0x12]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER.CLU1[0x12]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER.CLU2[0x12]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER.CLU0[0x2]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER.CLU1[0x2]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER.CLU2[0x2]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST.CLU0[0x1a]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST.CLU1[0x1a]=0
CLU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST.CLU2[0x1a]=0
CLU_NIF_PM_TERMINATE.CLU0[0x188]=0
CLU_NIF_PM_TERMINATE.CLU1[0x188]=0
CLU_NIF_PM_TERMINATE.CLU2[0x188]=0
CLU_PARITY_ERR_CNT.CLU0[0x98]=0
CLU_PARITY_ERR_CNT.CLU1[0x98]=0
CLU_PARITY_ERR_CNT.CLU2[0x98]=0
CLU_PARSER_HARD_CONTROL.CLU0[0x108]=0xdc0c523819c
CLU_PARSER_HARD_CONTROL.CLU1[0x108]=0xdc0c523819c
CLU_PARSER_HARD_CONTROL.CLU2[0x108]=0xdc0c523819c
CLU_PARSER_HARD_CONTROL_PLANE(0).CLU0[0x123]=0
CLU_PARSER_HARD_CONTROL_PLANE(1).CLU0[0x124]=0
CLU_PARSER_HARD_CONTROL_PLANE(2).CLU0[0x125]=0
CLU_PARSER_HARD_CONTROL_PLANE(3).CLU0[0x126]=0
CLU_PARSER_HARD_CONTROL_PLANE(0).CLU1[0x123]=0
CLU_PARSER_HARD_CONTROL_PLANE(1).CLU1[0x124]=0
CLU_PARSER_HARD_CONTROL_PLANE(2).CLU1[0x125]=0
CLU_PARSER_HARD_CONTROL_PLANE(3).CLU1[0x126]=0
CLU_PARSER_HARD_CONTROL_PLANE(0).CLU2[0x123]=0
CLU_PARSER_HARD_CONTROL_PLANE(1).CLU2[0x124]=0
CLU_PARSER_HARD_CONTROL_PLANE(2).CLU2[0x125]=0
CLU_PARSER_HARD_CONTROL_PLANE(3).CLU2[0x126]=0
CLU_PARSER_HARD_ETHER_TYPE.CLU0[0x122]=0
CLU_PARSER_HARD_ETHER_TYPE.CLU1[0x122]=0
CLU_PARSER_HARD_ETHER_TYPE.CLU2[0x122]=0
CLU_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.CLU0[0x129]=0x6db492249000
CLU_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.CLU1[0x129]=0x6db492249000
CLU_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.CLU2[0x129]=0x6db492249000
CLU_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.CLU0[0x128]=0x6db6db6db6db492492492492249249249249000000000000
CLU_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.CLU1[0x128]=0x6db6db6db6db492492492492249249249249000000000000
CLU_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.CLU2[0x128]=0x6db6db6db6db492492492492249249249249000000000000
CLU_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.CLU0[0x12a]=0x6d2240
CLU_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.CLU1[0x12a]=0x6d2240
CLU_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.CLU2[0x12a]=0x6d2240
CLU_PARSER_HARD_PORT_ETH_TPID(0).CLU0[0x10a]=0
CLU_PARSER_HARD_PORT_ETH_TPID(1).CLU0[0x10b]=0
CLU_PARSER_HARD_PORT_ETH_TPID(2).CLU0[0x10c]=0
CLU_PARSER_HARD_PORT_ETH_TPID(3).CLU0[0x10d]=0
CLU_PARSER_HARD_PORT_ETH_TPID(4).CLU0[0x10e]=0
CLU_PARSER_HARD_PORT_ETH_TPID(5).CLU0[0x10f]=0
CLU_PARSER_HARD_PORT_ETH_TPID(6).CLU0[0x110]=0
CLU_PARSER_HARD_PORT_ETH_TPID(7).CLU0[0x111]=0
CLU_PARSER_HARD_PORT_ETH_TPID(0).CLU1[0x10a]=0
CLU_PARSER_HARD_PORT_ETH_TPID(1).CLU1[0x10b]=0
CLU_PARSER_HARD_PORT_ETH_TPID(2).CLU1[0x10c]=0
CLU_PARSER_HARD_PORT_ETH_TPID(3).CLU1[0x10d]=0
CLU_PARSER_HARD_PORT_ETH_TPID(4).CLU1[0x10e]=0
CLU_PARSER_HARD_PORT_ETH_TPID(5).CLU1[0x10f]=0
CLU_PARSER_HARD_PORT_ETH_TPID(6).CLU1[0x110]=0
CLU_PARSER_HARD_PORT_ETH_TPID(7).CLU1[0x111]=0
CLU_PARSER_HARD_PORT_ETH_TPID(0).CLU2[0x10a]=0
CLU_PARSER_HARD_PORT_ETH_TPID(1).CLU2[0x10b]=0
CLU_PARSER_HARD_PORT_ETH_TPID(2).CLU2[0x10c]=0
CLU_PARSER_HARD_PORT_ETH_TPID(3).CLU2[0x10d]=0
CLU_PARSER_HARD_PORT_ETH_TPID(4).CLU2[0x10e]=0
CLU_PARSER_HARD_PORT_ETH_TPID(5).CLU2[0x10f]=0
CLU_PARSER_HARD_PORT_ETH_TPID(6).CLU2[0x110]=0
CLU_PARSER_HARD_PORT_ETH_TPID(7).CLU2[0x111]=0
CLU_PARSER_HARD_PORT_PROPERTIES(0).CLU0[0x11a]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(1).CLU0[0x11b]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(2).CLU0[0x11c]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(3).CLU0[0x11d]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(4).CLU0[0x11e]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(5).CLU0[0x11f]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(6).CLU0[0x120]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(7).CLU0[0x121]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(0).CLU1[0x11a]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(1).CLU1[0x11b]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(2).CLU1[0x11c]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(3).CLU1[0x11d]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(4).CLU1[0x11e]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(5).CLU1[0x11f]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(6).CLU1[0x120]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(7).CLU1[0x121]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(0).CLU2[0x11a]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(1).CLU2[0x11b]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(2).CLU2[0x11c]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(3).CLU2[0x11d]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(4).CLU2[0x11e]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(5).CLU2[0x11f]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(6).CLU2[0x120]=0xf
CLU_PARSER_HARD_PORT_PROPERTIES(7).CLU2[0x121]=0xf
CLU_PARSER_HARD_PORT_TYPE(0).CLU0[0x112]=7
CLU_PARSER_HARD_PORT_TYPE(1).CLU0[0x113]=7
CLU_PARSER_HARD_PORT_TYPE(2).CLU0[0x114]=7
CLU_PARSER_HARD_PORT_TYPE(3).CLU0[0x115]=7
CLU_PARSER_HARD_PORT_TYPE(4).CLU0[0x116]=7
CLU_PARSER_HARD_PORT_TYPE(5).CLU0[0x117]=7
CLU_PARSER_HARD_PORT_TYPE(6).CLU0[0x118]=7
CLU_PARSER_HARD_PORT_TYPE(7).CLU0[0x119]=7
CLU_PARSER_HARD_PORT_TYPE(0).CLU1[0x112]=7
CLU_PARSER_HARD_PORT_TYPE(1).CLU1[0x113]=7
CLU_PARSER_HARD_PORT_TYPE(2).CLU1[0x114]=7
CLU_PARSER_HARD_PORT_TYPE(3).CLU1[0x115]=7
CLU_PARSER_HARD_PORT_TYPE(4).CLU1[0x116]=7
CLU_PARSER_HARD_PORT_TYPE(5).CLU1[0x117]=7
CLU_PARSER_HARD_PORT_TYPE(6).CLU1[0x118]=7
CLU_PARSER_HARD_PORT_TYPE(7).CLU1[0x119]=7
CLU_PARSER_HARD_PORT_TYPE(0).CLU2[0x112]=7
CLU_PARSER_HARD_PORT_TYPE(1).CLU2[0x113]=7
CLU_PARSER_HARD_PORT_TYPE(2).CLU2[0x114]=7
CLU_PARSER_HARD_PORT_TYPE(3).CLU2[0x115]=7
CLU_PARSER_HARD_PORT_TYPE(4).CLU2[0x116]=7
CLU_PARSER_HARD_PORT_TYPE(5).CLU2[0x117]=7
CLU_PARSER_HARD_PORT_TYPE(6).CLU2[0x118]=7
CLU_PARSER_HARD_PORT_TYPE(7).CLU2[0x119]=7
CLU_PARSER_HARD_SPECIAL_LABEL(0).CLU0[0x12b]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(1).CLU0[0x12c]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(2).CLU0[0x12d]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(3).CLU0[0x12e]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(0).CLU1[0x12b]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(1).CLU1[0x12c]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(2).CLU1[0x12d]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(3).CLU1[0x12e]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(0).CLU2[0x12b]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(1).CLU2[0x12c]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(2).CLU2[0x12d]=0x30
CLU_PARSER_HARD_SPECIAL_LABEL(3).CLU2[0x12e]=0x30
CLU_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.CLU0[0x127]=0x6db6db6db6db492492492492249249249249000000000000
CLU_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.CLU1[0x127]=0x6db6db6db6db492492492492249249249249000000000000
CLU_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.CLU2[0x127]=0x6db6db6db6db492492492492249249249249000000000000
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).CLU0[0x147]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).CLU0[0x148]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).CLU0[0x149]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).CLU0[0x14a]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).CLU0[0x14b]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).CLU0[0x14c]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).CLU0[0x14d]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).CLU0[0x14e]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).CLU0[0x14f]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).CLU0[0x150]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).CLU0[0x151]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).CLU0[0x152]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).CLU0[0x153]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).CLU0[0x154]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).CLU0[0x155]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).CLU1[0x147]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).CLU1[0x148]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).CLU1[0x149]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).CLU1[0x14a]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).CLU1[0x14b]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).CLU1[0x14c]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).CLU1[0x14d]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).CLU1[0x14e]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).CLU1[0x14f]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).CLU1[0x150]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).CLU1[0x151]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).CLU1[0x152]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).CLU1[0x153]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).CLU1[0x154]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).CLU1[0x155]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).CLU2[0x147]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).CLU2[0x148]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).CLU2[0x149]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).CLU2[0x14a]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).CLU2[0x14b]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).CLU2[0x14c]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).CLU2[0x14d]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).CLU2[0x14e]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).CLU2[0x14f]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).CLU2[0x150]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).CLU2[0x151]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).CLU2[0x152]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).CLU2[0x153]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).CLU2[0x154]=0x20
CLU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).CLU2[0x155]=0x20
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).CLU0[0x12f]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).CLU0[0x130]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(2).CLU0[0x131]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(3).CLU0[0x132]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(4).CLU0[0x133]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(5).CLU0[0x134]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(6).CLU0[0x135]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(7).CLU0[0x136]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).CLU1[0x12f]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).CLU1[0x130]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(2).CLU1[0x131]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(3).CLU1[0x132]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(4).CLU1[0x133]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(5).CLU1[0x134]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(6).CLU1[0x135]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(7).CLU1[0x136]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).CLU2[0x12f]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).CLU2[0x130]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(2).CLU2[0x131]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(3).CLU2[0x132]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(4).CLU2[0x133]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(5).CLU2[0x134]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(6).CLU2[0x135]=1
CLU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(7).CLU2[0x136]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).CLU0[0x137]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).CLU0[0x138]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).CLU0[0x139]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).CLU0[0x13a]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).CLU0[0x13b]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).CLU0[0x13c]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).CLU0[0x13d]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).CLU0[0x13e]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).CLU0[0x13f]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).CLU0[0x140]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).CLU0[0x141]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).CLU0[0x142]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).CLU0[0x143]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).CLU0[0x144]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).CLU0[0x145]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).CLU0[0x146]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).CLU1[0x137]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).CLU1[0x138]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).CLU1[0x139]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).CLU1[0x13a]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).CLU1[0x13b]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).CLU1[0x13c]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).CLU1[0x13d]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).CLU1[0x13e]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).CLU1[0x13f]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).CLU1[0x140]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).CLU1[0x141]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).CLU1[0x142]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).CLU1[0x143]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).CLU1[0x144]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).CLU1[0x145]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).CLU1[0x146]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).CLU2[0x137]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).CLU2[0x138]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).CLU2[0x139]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).CLU2[0x13a]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).CLU2[0x13b]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).CLU2[0x13c]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).CLU2[0x13d]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).CLU2[0x13e]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).CLU2[0x13f]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).CLU2[0x140]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).CLU2[0x141]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).CLU2[0x142]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).CLU2[0x143]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).CLU2[0x144]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).CLU2[0x145]=1
CLU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).CLU2[0x146]=1
CLU_PARSER_SOFT_TCAM_0_TO_7.CLU0[0x156]=0
CLU_PARSER_SOFT_TCAM_0_TO_7.CLU1[0x156]=0
CLU_PARSER_SOFT_TCAM_0_TO_7.CLU2[0x156]=0
CLU_PARSER_SOFT_TCAM_16_TO_23.CLU0[0x158]=0
CLU_PARSER_SOFT_TCAM_16_TO_23.CLU1[0x158]=0
CLU_PARSER_SOFT_TCAM_16_TO_23.CLU2[0x158]=0
CLU_PARSER_SOFT_TCAM_24_TO_31.CLU0[0x159]=0
CLU_PARSER_SOFT_TCAM_24_TO_31.CLU1[0x159]=0
CLU_PARSER_SOFT_TCAM_24_TO_31.CLU2[0x159]=0
CLU_PARSER_SOFT_TCAM_8_TO_15.CLU0[0x157]=0
CLU_PARSER_SOFT_TCAM_8_TO_15.CLU1[0x157]=0
CLU_PARSER_SOFT_TCAM_8_TO_15.CLU2[0x157]=0
CLU_PAR_ERR_MEM_MASK.CLU0[0xa0]=0x3f
CLU_PAR_ERR_MEM_MASK.CLU1[0xa0]=0x3f
CLU_PAR_ERR_MEM_MASK.CLU2[0xa0]=0x3f
CLU_PCMI_0.CLU0[0xb0]=0x3b9aca00
CLU_PCMI_0.CLU1[0xb0]=0x3b9aca00
CLU_PCMI_0.CLU2[0xb0]=0x3b9aca00
CLU_PCMI_1.CLU0[0xb3]=0x3b9aca00
CLU_PCMI_1.CLU1[0xb3]=0x3b9aca00
CLU_PCMI_1.CLU2[0xb3]=0x3b9aca00
CLU_PCMI_2.CLU0[0xb6]=0x3b9aca00
CLU_PCMI_2.CLU1[0xb6]=0x3b9aca00
CLU_PCMI_2.CLU2[0xb6]=0x3b9aca00
CLU_PCMI_3.CLU0[0xb9]=0x3b9aca00
CLU_PCMI_3.CLU1[0xb9]=0x3b9aca00
CLU_PCMI_3.CLU2[0xb9]=0x3b9aca00
CLU_PCMI_4.CLU0[0xbc]=0x3b9aca00
CLU_PCMI_4.CLU1[0xbc]=0x3b9aca00
CLU_PCMI_4.CLU2[0xbc]=0x3b9aca00
CLU_PCMI_0_S.CLU0[0xb1]=0
CLU_PCMI_0_S.CLU1[0xb1]=0
CLU_PCMI_0_S.CLU2[0xb1]=0
CLU_PCMI_0_T.CLU0[0xb2]=0
CLU_PCMI_0_T.CLU1[0xb2]=0
CLU_PCMI_0_T.CLU2[0xb2]=0
CLU_PCMI_1_S.CLU0[0xb4]=0
CLU_PCMI_1_S.CLU1[0xb4]=0
CLU_PCMI_1_S.CLU2[0xb4]=0
CLU_PCMI_1_T.CLU0[0xb5]=0
CLU_PCMI_1_T.CLU1[0xb5]=0
CLU_PCMI_1_T.CLU2[0xb5]=0
CLU_PCMI_2_S.CLU0[0xb7]=0
CLU_PCMI_2_S.CLU1[0xb7]=0
CLU_PCMI_2_S.CLU2[0xb7]=0
CLU_PCMI_2_T.CLU0[0xb8]=0
CLU_PCMI_2_T.CLU1[0xb8]=0
CLU_PCMI_2_T.CLU2[0xb8]=0
CLU_PCMI_3_S.CLU0[0xba]=0
CLU_PCMI_3_S.CLU1[0xba]=0
CLU_PCMI_3_S.CLU2[0xba]=0
CLU_PCMI_3_T.CLU0[0xbb]=0
CLU_PCMI_3_T.CLU1[0xbb]=0
CLU_PCMI_3_T.CLU2[0xbb]=0
CLU_PCMI_4_S.CLU0[0xbd]=0
CLU_PCMI_4_S.CLU1[0xbd]=0
CLU_PCMI_4_S.CLU2[0xbd]=0
CLU_PCMI_4_T.CLU0[0xbe]=0
CLU_PCMI_4_T.CLU1[0xbe]=0
CLU_PCMI_4_T.CLU2[0xbe]=0
CLU_PM_0_RESETN.CLU0[0x547]=0xf
CLU_PM_0_RESETN.CLU1[0x547]=0xf
CLU_PM_0_RESETN.CLU2[0x547]=0xf
CLU_PM_1_RESETN.CLU0[0x548]=0xf
CLU_PM_1_RESETN.CLU1[0x548]=0xf
CLU_PM_1_RESETN.CLU2[0x548]=0xf
CLU_PM_2_RESETN.CLU0[0x549]=0xf
CLU_PM_2_RESETN.CLU1[0x549]=0xf
CLU_PM_2_RESETN.CLU2[0x549]=0
CLU_PM_BYPASS_CONFIG.CLU0[0x3df]=0
CLU_PM_BYPASS_CONFIG.CLU1[0x3df]=0
CLU_PM_BYPASS_CONFIG.CLU2[0x3df]=0
CLU_PORTS_CONFIG.CLU0[0x282]=0x12492
CLU_PORTS_CONFIG.CLU1[0x282]=0x12492
CLU_PORTS_CONFIG.CLU2[0x282]=0x12492
CLU_PORTS_INDICATIONS.CLU0[0x297]=0x33
CLU_PORTS_INDICATIONS.CLU1[0x297]=0
CLU_PORTS_INDICATIONS.CLU2[0x297]=0x80
CLU_PRD_BYPASS.CLU0[0x185]=0
CLU_PRD_BYPASS.CLU1[0x185]=0
CLU_PRD_BYPASS.CLU2[0x185]=0
CLU_PRD_CONFIG.CLU0[0x102]=3
CLU_PRD_CONFIG.CLU1[0x102]=3
CLU_PRD_CONFIG.CLU2[0x102]=3
CLU_PRD_EN.CLU0[0x107]=0
CLU_PRD_EN.CLU1[0x107]=0
CLU_PRD_EN.CLU2[0x107]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(0).CLU0[0x175]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(1).CLU0[0x176]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(2).CLU0[0x177]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(3).CLU0[0x178]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(4).CLU0[0x179]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(5).CLU0[0x17a]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(6).CLU0[0x17b]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(7).CLU0[0x17c]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(8).CLU0[0x17d]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(9).CLU0[0x17e]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(10).CLU0[0x17f]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(11).CLU0[0x180]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(12).CLU0[0x181]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(13).CLU0[0x182]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(14).CLU0[0x183]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(15).CLU0[0x184]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(0).CLU1[0x175]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(1).CLU1[0x176]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(2).CLU1[0x177]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(3).CLU1[0x178]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(4).CLU1[0x179]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(5).CLU1[0x17a]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(6).CLU1[0x17b]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(7).CLU1[0x17c]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(8).CLU1[0x17d]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(9).CLU1[0x17e]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(10).CLU1[0x17f]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(11).CLU1[0x180]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(12).CLU1[0x181]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(13).CLU1[0x182]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(14).CLU1[0x183]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(15).CLU1[0x184]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(0).CLU2[0x175]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(1).CLU2[0x176]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(2).CLU2[0x177]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(3).CLU2[0x178]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(4).CLU2[0x179]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(5).CLU2[0x17a]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(6).CLU2[0x17b]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(7).CLU2[0x17c]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(8).CLU2[0x17d]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(9).CLU2[0x17e]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(10).CLU2[0x17f]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(11).CLU2[0x180]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(12).CLU2[0x181]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(13).CLU2[0x182]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(14).CLU2[0x183]=0
CLU_PRD_ERR_PKT_DROP_CNT_PORT(15).CLU2[0x184]=0
CLU_PRD_OVERRIDES.CLU0[0x186]=0
CLU_PRD_OVERRIDES.CLU1[0x186]=0
CLU_PRD_OVERRIDES.CLU2[0x186]=0
CLU_PRD_PKT_DROP_CNT_PORT(0).CLU0[0x165]=0
CLU_PRD_PKT_DROP_CNT_PORT(1).CLU0[0x166]=0
CLU_PRD_PKT_DROP_CNT_PORT(2).CLU0[0x167]=0
CLU_PRD_PKT_DROP_CNT_PORT(3).CLU0[0x168]=0
CLU_PRD_PKT_DROP_CNT_PORT(4).CLU0[0x169]=0
CLU_PRD_PKT_DROP_CNT_PORT(5).CLU0[0x16a]=0
CLU_PRD_PKT_DROP_CNT_PORT(6).CLU0[0x16b]=0
CLU_PRD_PKT_DROP_CNT_PORT(7).CLU0[0x16c]=0
CLU_PRD_PKT_DROP_CNT_PORT(8).CLU0[0x16d]=0
CLU_PRD_PKT_DROP_CNT_PORT(9).CLU0[0x16e]=0
CLU_PRD_PKT_DROP_CNT_PORT(10).CLU0[0x16f]=0
CLU_PRD_PKT_DROP_CNT_PORT(11).CLU0[0x170]=0
CLU_PRD_PKT_DROP_CNT_PORT(12).CLU0[0x171]=0
CLU_PRD_PKT_DROP_CNT_PORT(13).CLU0[0x172]=0
CLU_PRD_PKT_DROP_CNT_PORT(14).CLU0[0x173]=0
CLU_PRD_PKT_DROP_CNT_PORT(15).CLU0[0x174]=0
CLU_PRD_PKT_DROP_CNT_PORT(0).CLU1[0x165]=0
CLU_PRD_PKT_DROP_CNT_PORT(1).CLU1[0x166]=0
CLU_PRD_PKT_DROP_CNT_PORT(2).CLU1[0x167]=0
CLU_PRD_PKT_DROP_CNT_PORT(3).CLU1[0x168]=0
CLU_PRD_PKT_DROP_CNT_PORT(4).CLU1[0x169]=0
CLU_PRD_PKT_DROP_CNT_PORT(5).CLU1[0x16a]=0
CLU_PRD_PKT_DROP_CNT_PORT(6).CLU1[0x16b]=0
CLU_PRD_PKT_DROP_CNT_PORT(7).CLU1[0x16c]=0
CLU_PRD_PKT_DROP_CNT_PORT(8).CLU1[0x16d]=0
CLU_PRD_PKT_DROP_CNT_PORT(9).CLU1[0x16e]=0
CLU_PRD_PKT_DROP_CNT_PORT(10).CLU1[0x16f]=0
CLU_PRD_PKT_DROP_CNT_PORT(11).CLU1[0x170]=0
CLU_PRD_PKT_DROP_CNT_PORT(12).CLU1[0x171]=0
CLU_PRD_PKT_DROP_CNT_PORT(13).CLU1[0x172]=0
CLU_PRD_PKT_DROP_CNT_PORT(14).CLU1[0x173]=0
CLU_PRD_PKT_DROP_CNT_PORT(15).CLU1[0x174]=0
CLU_PRD_PKT_DROP_CNT_PORT(0).CLU2[0x165]=0
CLU_PRD_PKT_DROP_CNT_PORT(1).CLU2[0x166]=0
CLU_PRD_PKT_DROP_CNT_PORT(2).CLU2[0x167]=0
CLU_PRD_PKT_DROP_CNT_PORT(3).CLU2[0x168]=0
CLU_PRD_PKT_DROP_CNT_PORT(4).CLU2[0x169]=0
CLU_PRD_PKT_DROP_CNT_PORT(5).CLU2[0x16a]=0
CLU_PRD_PKT_DROP_CNT_PORT(6).CLU2[0x16b]=0
CLU_PRD_PKT_DROP_CNT_PORT(7).CLU2[0x16c]=0
CLU_PRD_PKT_DROP_CNT_PORT(8).CLU2[0x16d]=0
CLU_PRD_PKT_DROP_CNT_PORT(9).CLU2[0x16e]=0
CLU_PRD_PKT_DROP_CNT_PORT(10).CLU2[0x16f]=0
CLU_PRD_PKT_DROP_CNT_PORT(11).CLU2[0x170]=0
CLU_PRD_PKT_DROP_CNT_PORT(12).CLU2[0x171]=0
CLU_PRD_PKT_DROP_CNT_PORT(13).CLU2[0x172]=0
CLU_PRD_PKT_DROP_CNT_PORT(14).CLU2[0x173]=0
CLU_PRD_PKT_DROP_CNT_PORT(15).CLU2[0x174]=0
CLU_REG_0041.CLU0[0x41]=0
CLU_REG_0041.CLU1[0x41]=0
CLU_REG_0041.CLU2[0x41]=0
CLU_REG_00C2.CLU0[0xc2]=0x10
CLU_REG_00C2.CLU1[0xc2]=0x10
CLU_REG_00C2.CLU2[0xc2]=0x10
CLU_REG_00C4.CLU0[0xc4]=0
CLU_REG_00C4.CLU1[0xc4]=0
CLU_REG_00C4.CLU2[0xc4]=0
CLU_RESERVED_MTCD.CLU0[0xae]=0x30
CLU_RESERVED_MTCD.CLU1[0xae]=0x30
CLU_RESERVED_MTCD.CLU2[0xae]=0x30
CLU_RESERVED_MTCP.CLU0[0xad]=0x300000600000000
CLU_RESERVED_MTCP.CLU1[0xad]=0x300000600000000
CLU_RESERVED_MTCP.CLU2[0xad]=0x300000600000000
CLU_RESERVED_SPARE_0.CLU0[0x90]=0xffffffff
CLU_RESERVED_SPARE_0.CLU1[0x90]=0xffffffff
CLU_RESERVED_SPARE_0.CLU2[0x90]=0xffffffff
CLU_RESERVED_SPARE_1.CLU0[0x91]=0xffffffff
CLU_RESERVED_SPARE_1.CLU1[0x91]=0xffffffff
CLU_RESERVED_SPARE_1.CLU2[0x91]=0xffffffff
CLU_RESERVED_SPARE_2.CLU0[0x92]=0
CLU_RESERVED_SPARE_2.CLU1[0x92]=0
CLU_RESERVED_SPARE_2.CLU2[0x92]=0
CLU_RESERVED_SPARE_3.CLU0[0x93]=0
CLU_RESERVED_SPARE_3.CLU1[0x93]=0
CLU_RESERVED_SPARE_3.CLU2[0x93]=0
CLU_RE_EN_SAMP_CFG.CLU0[0x630]=2
CLU_RE_EN_SAMP_CFG.CLU1[0x630]=2
CLU_RE_EN_SAMP_CFG.CLU2[0x630]=2
CLU_RUNT_PKT_CONFIG.CLU0[0x1dc]=3
CLU_RUNT_PKT_CONFIG.CLU1[0x1dc]=3
CLU_RUNT_PKT_CONFIG.CLU2[0x1dc]=3
CLU_RX_FIFOS_SRSTN.CLU0[0x100]=0xf
CLU_RX_FIFOS_SRSTN.CLU1[0x100]=0
CLU_RX_FIFOS_SRSTN.CLU2[0x100]=0x80
CLU_RX_FIFOS_VECTOR_PER_PORT(0).CLU0[0x52e]=1
CLU_RX_FIFOS_VECTOR_PER_PORT(1).CLU0[0x52f]=2
CLU_RX_FIFOS_VECTOR_PER_PORT(2).CLU0[0x530]=0x40
CLU_RX_FIFOS_VECTOR_PER_PORT(3).CLU0[0x531]=0x80
CLU_RX_FIFOS_VECTOR_PER_PORT(4).CLU0[0x532]=4
CLU_RX_FIFOS_VECTOR_PER_PORT(5).CLU0[0x533]=8
CLU_RX_FIFOS_VECTOR_PER_PORT(6).CLU0[0x534]=0x100
CLU_RX_FIFOS_VECTOR_PER_PORT(7).CLU0[0x535]=0x200
CLU_RX_FIFOS_VECTOR_PER_PORT(8).CLU0[0x536]=0x10
CLU_RX_FIFOS_VECTOR_PER_PORT(9).CLU0[0x537]=0x20
CLU_RX_FIFOS_VECTOR_PER_PORT(10).CLU0[0x538]=0x400
CLU_RX_FIFOS_VECTOR_PER_PORT(11).CLU0[0x539]=0x800
CLU_RX_FIFOS_VECTOR_PER_PORT(0).CLU1[0x52e]=1
CLU_RX_FIFOS_VECTOR_PER_PORT(1).CLU1[0x52f]=2
CLU_RX_FIFOS_VECTOR_PER_PORT(2).CLU1[0x530]=0x40
CLU_RX_FIFOS_VECTOR_PER_PORT(3).CLU1[0x531]=0x80
CLU_RX_FIFOS_VECTOR_PER_PORT(4).CLU1[0x532]=4
CLU_RX_FIFOS_VECTOR_PER_PORT(5).CLU1[0x533]=8
CLU_RX_FIFOS_VECTOR_PER_PORT(6).CLU1[0x534]=0x100
CLU_RX_FIFOS_VECTOR_PER_PORT(7).CLU1[0x535]=0x200
CLU_RX_FIFOS_VECTOR_PER_PORT(8).CLU1[0x536]=0x10
CLU_RX_FIFOS_VECTOR_PER_PORT(9).CLU1[0x537]=0x20
CLU_RX_FIFOS_VECTOR_PER_PORT(10).CLU1[0x538]=0x400
CLU_RX_FIFOS_VECTOR_PER_PORT(11).CLU1[0x539]=0x800
CLU_RX_FIFOS_VECTOR_PER_PORT(0).CLU2[0x52e]=1
CLU_RX_FIFOS_VECTOR_PER_PORT(1).CLU2[0x52f]=2
CLU_RX_FIFOS_VECTOR_PER_PORT(2).CLU2[0x530]=0x10
CLU_RX_FIFOS_VECTOR_PER_PORT(3).CLU2[0x531]=0x20
CLU_RX_FIFOS_VECTOR_PER_PORT(4).CLU2[0x532]=4
CLU_RX_FIFOS_VECTOR_PER_PORT(5).CLU2[0x533]=8
CLU_RX_FIFOS_VECTOR_PER_PORT(6).CLU2[0x534]=0x40
CLU_RX_FIFOS_VECTOR_PER_PORT(7).CLU2[0x535]=0x80
CLU_RX_FIFOS_VECTOR_PER_PORT(8).CLU2[0x536]=0
CLU_RX_FIFOS_VECTOR_PER_PORT(9).CLU2[0x537]=0
CLU_RX_FIFOS_VECTOR_PER_PORT(10).CLU2[0x538]=0
CLU_RX_FIFOS_VECTOR_PER_PORT(11).CLU2[0x539]=0
CLU_RX_FIFO_RANGE_RMC_0.CLU0[0x51e]=0x7c00
CLU_RX_FIFO_RANGE_RMC_0.CLU1[0x51e]=0x7c00
CLU_RX_FIFO_RANGE_RMC_0.CLU2[0x51e]=0x7c00
CLU_RX_FIFO_RANGE_RMC_1.CLU0[0x51f]=0xfc20
CLU_RX_FIFO_RANGE_RMC_1.CLU1[0x51f]=0xfc20
CLU_RX_FIFO_RANGE_RMC_1.CLU2[0x51f]=0xfc20
CLU_RX_FIFO_RANGE_RMC_2.CLU0[0x520]=0x27c80
CLU_RX_FIFO_RANGE_RMC_2.CLU1[0x520]=0x27c80
CLU_RX_FIFO_RANGE_RMC_2.CLU2[0x520]=0x27c80
CLU_RX_FIFO_RANGE_RMC_3.CLU0[0x521]=0x2fca0
CLU_RX_FIFO_RANGE_RMC_3.CLU1[0x521]=0x2fca0
CLU_RX_FIFO_RANGE_RMC_3.CLU2[0x521]=0x2fca0
CLU_RX_FIFO_RANGE_RMC_4.CLU0[0x522]=0x47d00
CLU_RX_FIFO_RANGE_RMC_4.CLU1[0x522]=0x47d00
CLU_RX_FIFO_RANGE_RMC_4.CLU2[0x522]=0x17c40
CLU_RX_FIFO_RANGE_RMC_5.CLU0[0x523]=0x4fd20
CLU_RX_FIFO_RANGE_RMC_5.CLU1[0x523]=0x4fd20
CLU_RX_FIFO_RANGE_RMC_5.CLU2[0x523]=0x1fc60
CLU_RX_FIFO_RANGE_RMC_6.CLU0[0x524]=0x17c40
CLU_RX_FIFO_RANGE_RMC_6.CLU1[0x524]=0x17c40
CLU_RX_FIFO_RANGE_RMC_6.CLU2[0x524]=0x37cc0
CLU_RX_FIFO_RANGE_RMC_7.CLU0[0x525]=0x1fc60
CLU_RX_FIFO_RANGE_RMC_7.CLU1[0x525]=0x1fc60
CLU_RX_FIFO_RANGE_RMC_7.CLU2[0x525]=0x3fce0
CLU_RX_FIFO_RANGE_RMC_8.CLU0[0x526]=0x37cc0
CLU_RX_FIFO_RANGE_RMC_8.CLU1[0x526]=0x37cc0
CLU_RX_FIFO_RANGE_RMC_8.CLU2[0x526]=0x35cc0
CLU_RX_FIFO_RANGE_RMC_9.CLU0[0x527]=0x3fce0
CLU_RX_FIFO_RANGE_RMC_9.CLU1[0x527]=0x3fce0
CLU_RX_FIFO_RANGE_RMC_9.CLU2[0x527]=0x3bcd8
CLU_RX_FIFO_RANGE_RMC_10.CLU0[0x528]=0x57d40
CLU_RX_FIFO_RANGE_RMC_10.CLU1[0x528]=0x57d40
CLU_RX_FIFO_RANGE_RMC_10.CLU2[0x528]=0x41cf0
CLU_RX_FIFO_RANGE_RMC_11.CLU0[0x529]=0x5fd60
CLU_RX_FIFO_RANGE_RMC_11.CLU1[0x529]=0x5fd60
CLU_RX_FIFO_RANGE_RMC_11.CLU2[0x529]=0x47d08
CLU_RX_FIFO_RANGE_RMC_12.CLU0[0x52a]=0x4dd20
CLU_RX_FIFO_RANGE_RMC_12.CLU1[0x52a]=0x4dd20
CLU_RX_FIFO_RANGE_RMC_12.CLU2[0x52a]=0x4dd20
CLU_RX_FIFO_RANGE_RMC_13.CLU0[0x52b]=0x53d38
CLU_RX_FIFO_RANGE_RMC_13.CLU1[0x52b]=0x53d38
CLU_RX_FIFO_RANGE_RMC_13.CLU2[0x52b]=0x53d38
CLU_RX_FIFO_RANGE_RMC_14.CLU0[0x52c]=0x59d50
CLU_RX_FIFO_RANGE_RMC_14.CLU1[0x52c]=0x59d50
CLU_RX_FIFO_RANGE_RMC_14.CLU2[0x52c]=0x59d50
CLU_RX_FIFO_RANGE_RMC_15.CLU0[0x52d]=0x5fd68
CLU_RX_FIFO_RANGE_RMC_15.CLU1[0x52d]=0x5fd68
CLU_RX_FIFO_RANGE_RMC_15.CLU2[0x52d]=0x5fd68
CLU_RX_FLEXE_L_1_RATE_MISMATCH_CONFIG.CLU0[0x27e]=0x1e003c007800f001e003c007800f001e003c007800f001e003c007800f0000000000000000
CLU_RX_FLEXE_L_1_RATE_MISMATCH_CONFIG.CLU1[0x27e]=0x1e003c007800f001e003c007800f001e003c007800f001e003c007800f0000000000000000
CLU_RX_FLEXE_L_1_RATE_MISMATCH_CONFIG.CLU2[0x27e]=0x1e003c007800f001e003c007800f001e003c007800f001e003c007800f0000000000000000
CLU_RX_FLEXE_L_1_RATE_MISMATCH_DEBUG.CLU0[0x27f]=0x438014003000000000
CLU_RX_FLEXE_L_1_RATE_MISMATCH_DEBUG.CLU1[0x27f]=0x438000000000000000
CLU_RX_FLEXE_L_1_RATE_MISMATCH_DEBUG.CLU2[0x27f]=0x438000000000000000
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(0).CLU0[0x1af]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(1).CLU0[0x1b0]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(2).CLU0[0x1b1]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(3).CLU0[0x1b2]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(4).CLU0[0x1b3]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(5).CLU0[0x1b4]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(6).CLU0[0x1b5]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(7).CLU0[0x1b6]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(8).CLU0[0x1b7]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(9).CLU0[0x1b8]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(10).CLU0[0x1b9]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(11).CLU0[0x1ba]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(0).CLU1[0x1af]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(1).CLU1[0x1b0]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(2).CLU1[0x1b1]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(3).CLU1[0x1b2]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(4).CLU1[0x1b3]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(5).CLU1[0x1b4]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(6).CLU1[0x1b5]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(7).CLU1[0x1b6]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(8).CLU1[0x1b7]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(9).CLU1[0x1b8]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(10).CLU1[0x1b9]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(11).CLU1[0x1ba]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(0).CLU2[0x1af]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(1).CLU2[0x1b0]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(2).CLU2[0x1b1]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(3).CLU2[0x1b2]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(4).CLU2[0x1b3]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(5).CLU2[0x1b4]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(6).CLU2[0x1b5]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(7).CLU2[0x1b6]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(8).CLU2[0x1b7]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(9).CLU2[0x1b8]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(10).CLU2[0x1b9]=0
CLU_RX_GS_DEBUG_DATA_WAIT_AT_GS(11).CLU2[0x1ba]=0
CLU_RX_GS_FIFO_ERR_WR(0).CLU0[0x189]=0
CLU_RX_GS_FIFO_ERR_WR(1).CLU0[0x18a]=0
CLU_RX_GS_FIFO_ERR_WR(2).CLU0[0x18b]=0
CLU_RX_GS_FIFO_ERR_WR(3).CLU0[0x18c]=0
CLU_RX_GS_FIFO_ERR_WR(4).CLU0[0x18d]=0
CLU_RX_GS_FIFO_ERR_WR(5).CLU0[0x18e]=0
CLU_RX_GS_FIFO_ERR_WR(6).CLU0[0x18f]=0
CLU_RX_GS_FIFO_ERR_WR(7).CLU0[0x190]=0
CLU_RX_GS_FIFO_ERR_WR(8).CLU0[0x191]=0
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CLU_RX_GS_MAX_OCCUPANCY.CLU0[0x1ad]=0x31800318
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CLU_RX_GS_MAX_OCCUPANCY.CLU2[0x1ad]=0xc000000000
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CLU_RX_MLF_DROP_ALL_DATA(0).CLU0[0x1cc]=0
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CLU_RX_MLF_DROP_ALL_DATA(14).CLU0[0x1da]=0
CLU_RX_MLF_DROP_ALL_DATA(15).CLU0[0x1db]=0
CLU_RX_MLF_DROP_ALL_DATA(0).CLU1[0x1cc]=0
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CLU_RX_MLF_DROP_ALL_DATA(2).CLU1[0x1ce]=0
CLU_RX_MLF_DROP_ALL_DATA(3).CLU1[0x1cf]=0
CLU_RX_MLF_DROP_ALL_DATA(4).CLU1[0x1d0]=0
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CLU_RX_MLF_DROP_ALL_DATA(6).CLU1[0x1d2]=0
CLU_RX_MLF_DROP_ALL_DATA(7).CLU1[0x1d3]=0
CLU_RX_MLF_DROP_ALL_DATA(8).CLU1[0x1d4]=0
CLU_RX_MLF_DROP_ALL_DATA(9).CLU1[0x1d5]=0
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CLU_RX_MLF_DROP_ALL_DATA(11).CLU1[0x1d7]=0
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CLU_RX_MLF_DROP_ALL_DATA(15).CLU1[0x1db]=0
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CLU_RX_MLF_DROP_ALL_DATA(3).CLU2[0x1cf]=0
CLU_RX_MLF_DROP_ALL_DATA(4).CLU2[0x1d0]=0
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CLU_RX_MLF_DROP_ALL_DATA(7).CLU2[0x1d3]=0
CLU_RX_MLF_DROP_ALL_DATA(8).CLU2[0x1d4]=0
CLU_RX_MLF_DROP_ALL_DATA(9).CLU2[0x1d5]=0
CLU_RX_MLF_DROP_ALL_DATA(10).CLU2[0x1d6]=0
CLU_RX_MLF_DROP_ALL_DATA(11).CLU2[0x1d7]=0
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CLU_RX_MLF_DROP_ALL_DATA(13).CLU2[0x1d9]=0
CLU_RX_MLF_DROP_ALL_DATA(14).CLU2[0x1da]=0
CLU_RX_MLF_DROP_ALL_DATA(15).CLU2[0x1db]=0
CLU_RX_MLF_LEVEL(0).CLU0[0x23b]=0x10000
CLU_RX_MLF_LEVEL(1).CLU0[0x23d]=0x10000
CLU_RX_MLF_LEVEL(2).CLU0[0x23f]=0x10000
CLU_RX_MLF_LEVEL(3).CLU0[0x241]=0x10000
CLU_RX_MLF_LEVEL(4).CLU0[0x243]=0
CLU_RX_MLF_LEVEL(5).CLU0[0x245]=0
CLU_RX_MLF_LEVEL(6).CLU0[0x247]=0
CLU_RX_MLF_LEVEL(7).CLU0[0x249]=0
CLU_RX_MLF_LEVEL(8).CLU0[0x24b]=0
CLU_RX_MLF_LEVEL(9).CLU0[0x24d]=0
CLU_RX_MLF_LEVEL(10).CLU0[0x24f]=0
CLU_RX_MLF_LEVEL(11).CLU0[0x251]=0
CLU_RX_MLF_LEVEL(12).CLU0[0x253]=0
CLU_RX_MLF_LEVEL(13).CLU0[0x255]=0
CLU_RX_MLF_LEVEL(14).CLU0[0x257]=0
CLU_RX_MLF_LEVEL(15).CLU0[0x259]=0
CLU_RX_MLF_LEVEL(0).CLU1[0x23b]=0
CLU_RX_MLF_LEVEL(1).CLU1[0x23d]=0
CLU_RX_MLF_LEVEL(2).CLU1[0x23f]=0
CLU_RX_MLF_LEVEL(3).CLU1[0x241]=0
CLU_RX_MLF_LEVEL(4).CLU1[0x243]=0
CLU_RX_MLF_LEVEL(5).CLU1[0x245]=0
CLU_RX_MLF_LEVEL(6).CLU1[0x247]=0
CLU_RX_MLF_LEVEL(7).CLU1[0x249]=0
CLU_RX_MLF_LEVEL(8).CLU1[0x24b]=0
CLU_RX_MLF_LEVEL(9).CLU1[0x24d]=0
CLU_RX_MLF_LEVEL(10).CLU1[0x24f]=0
CLU_RX_MLF_LEVEL(11).CLU1[0x251]=0
CLU_RX_MLF_LEVEL(12).CLU1[0x253]=0
CLU_RX_MLF_LEVEL(13).CLU1[0x255]=0
CLU_RX_MLF_LEVEL(14).CLU1[0x257]=0
CLU_RX_MLF_LEVEL(15).CLU1[0x259]=0
CLU_RX_MLF_LEVEL(0).CLU2[0x23b]=0
CLU_RX_MLF_LEVEL(1).CLU2[0x23d]=0
CLU_RX_MLF_LEVEL(2).CLU2[0x23f]=0
CLU_RX_MLF_LEVEL(3).CLU2[0x241]=0
CLU_RX_MLF_LEVEL(4).CLU2[0x243]=0
CLU_RX_MLF_LEVEL(5).CLU2[0x245]=0
CLU_RX_MLF_LEVEL(6).CLU2[0x247]=0
CLU_RX_MLF_LEVEL(7).CLU2[0x249]=0x10000
CLU_RX_MLF_LEVEL(8).CLU2[0x24b]=0
CLU_RX_MLF_LEVEL(9).CLU2[0x24d]=0
CLU_RX_MLF_LEVEL(10).CLU2[0x24f]=0
CLU_RX_MLF_LEVEL(11).CLU2[0x251]=0
CLU_RX_MLF_LEVEL(12).CLU2[0x253]=0
CLU_RX_MLF_LEVEL(13).CLU2[0x255]=0
CLU_RX_MLF_LEVEL(14).CLU2[0x257]=0
CLU_RX_MLF_LEVEL(15).CLU2[0x259]=0
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(0).CLU0[0x1fb]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(1).CLU0[0x1fc]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(2).CLU0[0x1fd]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(3).CLU0[0x1fe]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(4).CLU0[0x1ff]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(5).CLU0[0x200]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(6).CLU0[0x201]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(7).CLU0[0x202]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(8).CLU0[0x203]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(9).CLU0[0x204]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(10).CLU0[0x205]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(11).CLU0[0x206]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(12).CLU0[0x207]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(13).CLU0[0x208]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(14).CLU0[0x209]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(15).CLU0[0x20a]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(0).CLU1[0x1fb]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(1).CLU1[0x1fc]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(2).CLU1[0x1fd]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(3).CLU1[0x1fe]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(4).CLU1[0x1ff]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(5).CLU1[0x200]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(6).CLU1[0x201]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(7).CLU1[0x202]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(8).CLU1[0x203]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(9).CLU1[0x204]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(10).CLU1[0x205]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(11).CLU1[0x206]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(12).CLU1[0x207]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(13).CLU1[0x208]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(14).CLU1[0x209]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(15).CLU1[0x20a]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(0).CLU2[0x1fb]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(1).CLU2[0x1fc]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(2).CLU2[0x1fd]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(3).CLU2[0x1fe]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(4).CLU2[0x1ff]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(5).CLU2[0x200]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(6).CLU2[0x201]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(7).CLU2[0x202]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(8).CLU2[0x203]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(9).CLU2[0x204]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(10).CLU2[0x205]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(11).CLU2[0x206]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(12).CLU2[0x207]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(13).CLU2[0x208]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(14).CLU2[0x209]=0xfc0200
CLU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(15).CLU2[0x20a]=0xfc0200
CLU_RX_MLF_MAX_OCCUPANCY.CLU0[0x25b]=0x1000200040008
CLU_RX_MLF_MAX_OCCUPANCY.CLU1[0x25b]=0
CLU_RX_MLF_MAX_OCCUPANCY.CLU2[0x25b]=0x1000000000000000000000000000
CLU_RX_MLF_OVERFLOW(0).CLU0[0x22b]=0
CLU_RX_MLF_OVERFLOW(1).CLU0[0x22c]=0
CLU_RX_MLF_OVERFLOW(2).CLU0[0x22d]=0
CLU_RX_MLF_OVERFLOW(3).CLU0[0x22e]=0
CLU_RX_MLF_OVERFLOW(4).CLU0[0x22f]=0
CLU_RX_MLF_OVERFLOW(5).CLU0[0x230]=0
CLU_RX_MLF_OVERFLOW(6).CLU0[0x231]=0
CLU_RX_MLF_OVERFLOW(7).CLU0[0x232]=0
CLU_RX_MLF_OVERFLOW(8).CLU0[0x233]=0
CLU_RX_MLF_OVERFLOW(9).CLU0[0x234]=0
CLU_RX_MLF_OVERFLOW(10).CLU0[0x235]=0
CLU_RX_MLF_OVERFLOW(11).CLU0[0x236]=0
CLU_RX_MLF_OVERFLOW(12).CLU0[0x237]=0
CLU_RX_MLF_OVERFLOW(13).CLU0[0x238]=0
CLU_RX_MLF_OVERFLOW(14).CLU0[0x239]=0
CLU_RX_MLF_OVERFLOW(15).CLU0[0x23a]=0
CLU_RX_MLF_OVERFLOW(0).CLU1[0x22b]=0
CLU_RX_MLF_OVERFLOW(1).CLU1[0x22c]=0
CLU_RX_MLF_OVERFLOW(2).CLU1[0x22d]=0
CLU_RX_MLF_OVERFLOW(3).CLU1[0x22e]=0
CLU_RX_MLF_OVERFLOW(4).CLU1[0x22f]=0
CLU_RX_MLF_OVERFLOW(5).CLU1[0x230]=0
CLU_RX_MLF_OVERFLOW(6).CLU1[0x231]=0
CLU_RX_MLF_OVERFLOW(7).CLU1[0x232]=0
CLU_RX_MLF_OVERFLOW(8).CLU1[0x233]=0
CLU_RX_MLF_OVERFLOW(9).CLU1[0x234]=0
CLU_RX_MLF_OVERFLOW(10).CLU1[0x235]=0
CLU_RX_MLF_OVERFLOW(11).CLU1[0x236]=0
CLU_RX_MLF_OVERFLOW(12).CLU1[0x237]=0
CLU_RX_MLF_OVERFLOW(13).CLU1[0x238]=0
CLU_RX_MLF_OVERFLOW(14).CLU1[0x239]=0
CLU_RX_MLF_OVERFLOW(15).CLU1[0x23a]=0
CLU_RX_MLF_OVERFLOW(0).CLU2[0x22b]=0
CLU_RX_MLF_OVERFLOW(1).CLU2[0x22c]=0
CLU_RX_MLF_OVERFLOW(2).CLU2[0x22d]=0
CLU_RX_MLF_OVERFLOW(3).CLU2[0x22e]=0
CLU_RX_MLF_OVERFLOW(4).CLU2[0x22f]=0
CLU_RX_MLF_OVERFLOW(5).CLU2[0x230]=0
CLU_RX_MLF_OVERFLOW(6).CLU2[0x231]=0
CLU_RX_MLF_OVERFLOW(7).CLU2[0x232]=0
CLU_RX_MLF_OVERFLOW(8).CLU2[0x233]=0
CLU_RX_MLF_OVERFLOW(9).CLU2[0x234]=0
CLU_RX_MLF_OVERFLOW(10).CLU2[0x235]=0
CLU_RX_MLF_OVERFLOW(11).CLU2[0x236]=0
CLU_RX_MLF_OVERFLOW(12).CLU2[0x237]=0
CLU_RX_MLF_OVERFLOW(13).CLU2[0x238]=0
CLU_RX_MLF_OVERFLOW(14).CLU2[0x239]=0
CLU_RX_MLF_OVERFLOW(15).CLU2[0x23a]=0
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(0).CLU0[0x20b]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(1).CLU0[0x20c]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(2).CLU0[0x20d]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(3).CLU0[0x20e]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(4).CLU0[0x20f]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(5).CLU0[0x210]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(6).CLU0[0x211]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(7).CLU0[0x212]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(8).CLU0[0x213]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(9).CLU0[0x214]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(10).CLU0[0x215]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(11).CLU0[0x216]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(12).CLU0[0x217]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(13).CLU0[0x218]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(14).CLU0[0x219]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(15).CLU0[0x21a]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(0).CLU1[0x20b]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(1).CLU1[0x20c]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(2).CLU1[0x20d]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(3).CLU1[0x20e]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(4).CLU1[0x20f]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(5).CLU1[0x210]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(6).CLU1[0x211]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(7).CLU1[0x212]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(8).CLU1[0x213]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(9).CLU1[0x214]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(10).CLU1[0x215]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(11).CLU1[0x216]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(12).CLU1[0x217]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(13).CLU1[0x218]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(14).CLU1[0x219]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(15).CLU1[0x21a]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(0).CLU2[0x20b]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(1).CLU2[0x20c]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(2).CLU2[0x20d]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(3).CLU2[0x20e]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(4).CLU2[0x20f]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(5).CLU2[0x210]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(6).CLU2[0x211]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(7).CLU2[0x212]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(8).CLU2[0x213]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(9).CLU2[0x214]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(10).CLU2[0x215]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(11).CLU2[0x216]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(12).CLU2[0x217]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(13).CLU2[0x218]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(14).CLU2[0x219]=0x92012c
CLU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC(15).CLU2[0x21a]=0x92012c
CLU_RX_MLF_UNDERFLOW(0).CLU0[0x21b]=0
CLU_RX_MLF_UNDERFLOW(1).CLU0[0x21c]=0
CLU_RX_MLF_UNDERFLOW(2).CLU0[0x21d]=0
CLU_RX_MLF_UNDERFLOW(3).CLU0[0x21e]=0
CLU_RX_MLF_UNDERFLOW(4).CLU0[0x21f]=0
CLU_RX_MLF_UNDERFLOW(5).CLU0[0x220]=0
CLU_RX_MLF_UNDERFLOW(6).CLU0[0x221]=0
CLU_RX_MLF_UNDERFLOW(7).CLU0[0x222]=0
CLU_RX_MLF_UNDERFLOW(8).CLU0[0x223]=0
CLU_RX_MLF_UNDERFLOW(9).CLU0[0x224]=0
CLU_RX_MLF_UNDERFLOW(10).CLU0[0x225]=0
CLU_RX_MLF_UNDERFLOW(11).CLU0[0x226]=0
CLU_RX_MLF_UNDERFLOW(12).CLU0[0x227]=0
CLU_RX_MLF_UNDERFLOW(13).CLU0[0x228]=0
CLU_RX_MLF_UNDERFLOW(14).CLU0[0x229]=0
CLU_RX_MLF_UNDERFLOW(15).CLU0[0x22a]=0
CLU_RX_MLF_UNDERFLOW(0).CLU1[0x21b]=0
CLU_RX_MLF_UNDERFLOW(1).CLU1[0x21c]=0
CLU_RX_MLF_UNDERFLOW(2).CLU1[0x21d]=0
CLU_RX_MLF_UNDERFLOW(3).CLU1[0x21e]=0
CLU_RX_MLF_UNDERFLOW(4).CLU1[0x21f]=0
CLU_RX_MLF_UNDERFLOW(5).CLU1[0x220]=0
CLU_RX_MLF_UNDERFLOW(6).CLU1[0x221]=0
CLU_RX_MLF_UNDERFLOW(7).CLU1[0x222]=0
CLU_RX_MLF_UNDERFLOW(8).CLU1[0x223]=0
CLU_RX_MLF_UNDERFLOW(9).CLU1[0x224]=0
CLU_RX_MLF_UNDERFLOW(10).CLU1[0x225]=0
CLU_RX_MLF_UNDERFLOW(11).CLU1[0x226]=0
CLU_RX_MLF_UNDERFLOW(12).CLU1[0x227]=0
CLU_RX_MLF_UNDERFLOW(13).CLU1[0x228]=0
CLU_RX_MLF_UNDERFLOW(14).CLU1[0x229]=0
CLU_RX_MLF_UNDERFLOW(15).CLU1[0x22a]=0
CLU_RX_MLF_UNDERFLOW(0).CLU2[0x21b]=0
CLU_RX_MLF_UNDERFLOW(1).CLU2[0x21c]=0
CLU_RX_MLF_UNDERFLOW(2).CLU2[0x21d]=0
CLU_RX_MLF_UNDERFLOW(3).CLU2[0x21e]=0
CLU_RX_MLF_UNDERFLOW(4).CLU2[0x21f]=0
CLU_RX_MLF_UNDERFLOW(5).CLU2[0x220]=0
CLU_RX_MLF_UNDERFLOW(6).CLU2[0x221]=0
CLU_RX_MLF_UNDERFLOW(7).CLU2[0x222]=0
CLU_RX_MLF_UNDERFLOW(8).CLU2[0x223]=0
CLU_RX_MLF_UNDERFLOW(9).CLU2[0x224]=0
CLU_RX_MLF_UNDERFLOW(10).CLU2[0x225]=0
CLU_RX_MLF_UNDERFLOW(11).CLU2[0x226]=0
CLU_RX_MLF_UNDERFLOW(12).CLU2[0x227]=0
CLU_RX_MLF_UNDERFLOW(13).CLU2[0x228]=0
CLU_RX_MLF_UNDERFLOW(14).CLU2[0x229]=0
CLU_RX_MLF_UNDERFLOW(15).CLU2[0x22a]=0
CLU_RX_NUM_TOTAL_DROPPED_EOPS.CLU0[0x3e4]=0
CLU_RX_NUM_TOTAL_DROPPED_EOPS.CLU1[0x3e4]=0
CLU_RX_NUM_TOTAL_DROPPED_EOPS.CLU2[0x3e4]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(0).CLU0[0x426]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(1).CLU0[0x427]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(2).CLU0[0x428]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(3).CLU0[0x429]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(4).CLU0[0x42a]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(5).CLU0[0x42b]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(6).CLU0[0x42c]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(7).CLU0[0x42d]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(8).CLU0[0x42e]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(9).CLU0[0x42f]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(10).CLU0[0x430]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(11).CLU0[0x431]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(12).CLU0[0x432]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(13).CLU0[0x433]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(14).CLU0[0x434]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(15).CLU0[0x435]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(0).CLU1[0x426]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(1).CLU1[0x427]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(2).CLU1[0x428]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(3).CLU1[0x429]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(4).CLU1[0x42a]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(5).CLU1[0x42b]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(6).CLU1[0x42c]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(7).CLU1[0x42d]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(8).CLU1[0x42e]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(9).CLU1[0x42f]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(10).CLU1[0x430]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(11).CLU1[0x431]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(12).CLU1[0x432]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(13).CLU1[0x433]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(14).CLU1[0x434]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(15).CLU1[0x435]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(0).CLU2[0x426]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(1).CLU2[0x427]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(2).CLU2[0x428]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(3).CLU2[0x429]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(4).CLU2[0x42a]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(5).CLU2[0x42b]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(6).CLU2[0x42c]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(7).CLU2[0x42d]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(8).CLU2[0x42e]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(9).CLU2[0x42f]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(10).CLU2[0x430]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(11).CLU2[0x431]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(12).CLU2[0x432]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(13).CLU2[0x433]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(14).CLU2[0x434]=0
CLU_RX_PKT_CTRL_DROP_COUNTER(15).CLU2[0x435]=0
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CLU_RX_PKT_OVF_DROP_COUNTER(11).CLU2[0x421]=0
CLU_RX_PKT_OVF_DROP_COUNTER(12).CLU2[0x422]=0
CLU_RX_PKT_OVF_DROP_COUNTER(13).CLU2[0x423]=0
CLU_RX_PKT_OVF_DROP_COUNTER(14).CLU2[0x424]=0
CLU_RX_PKT_OVF_DROP_COUNTER(15).CLU2[0x425]=0
CLU_RX_PKT_PRD_DROP_COUNTER(0).CLU0[0x406]=0
CLU_RX_PKT_PRD_DROP_COUNTER(1).CLU0[0x407]=0
CLU_RX_PKT_PRD_DROP_COUNTER(2).CLU0[0x408]=0
CLU_RX_PKT_PRD_DROP_COUNTER(3).CLU0[0x409]=0
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CLU_RX_PKT_PRD_DROP_COUNTER(5).CLU0[0x40b]=0
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CLU_RX_PKT_PRD_DROP_COUNTER(15).CLU0[0x415]=0
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CLU_RX_PKT_PRD_DROP_COUNTER(2).CLU1[0x408]=0
CLU_RX_PKT_PRD_DROP_COUNTER(3).CLU1[0x409]=0
CLU_RX_PKT_PRD_DROP_COUNTER(4).CLU1[0x40a]=0
CLU_RX_PKT_PRD_DROP_COUNTER(5).CLU1[0x40b]=0
CLU_RX_PKT_PRD_DROP_COUNTER(6).CLU1[0x40c]=0
CLU_RX_PKT_PRD_DROP_COUNTER(7).CLU1[0x40d]=0
CLU_RX_PKT_PRD_DROP_COUNTER(8).CLU1[0x40e]=0
CLU_RX_PKT_PRD_DROP_COUNTER(9).CLU1[0x40f]=0
CLU_RX_PKT_PRD_DROP_COUNTER(10).CLU1[0x410]=0
CLU_RX_PKT_PRD_DROP_COUNTER(11).CLU1[0x411]=0
CLU_RX_PKT_PRD_DROP_COUNTER(12).CLU1[0x412]=0
CLU_RX_PKT_PRD_DROP_COUNTER(13).CLU1[0x413]=0
CLU_RX_PKT_PRD_DROP_COUNTER(14).CLU1[0x414]=0
CLU_RX_PKT_PRD_DROP_COUNTER(15).CLU1[0x415]=0
CLU_RX_PKT_PRD_DROP_COUNTER(0).CLU2[0x406]=0
CLU_RX_PKT_PRD_DROP_COUNTER(1).CLU2[0x407]=0
CLU_RX_PKT_PRD_DROP_COUNTER(2).CLU2[0x408]=0
CLU_RX_PKT_PRD_DROP_COUNTER(3).CLU2[0x409]=0
CLU_RX_PKT_PRD_DROP_COUNTER(4).CLU2[0x40a]=0
CLU_RX_PKT_PRD_DROP_COUNTER(5).CLU2[0x40b]=0
CLU_RX_PKT_PRD_DROP_COUNTER(6).CLU2[0x40c]=0
CLU_RX_PKT_PRD_DROP_COUNTER(7).CLU2[0x40d]=0
CLU_RX_PKT_PRD_DROP_COUNTER(8).CLU2[0x40e]=0
CLU_RX_PKT_PRD_DROP_COUNTER(9).CLU2[0x40f]=0
CLU_RX_PKT_PRD_DROP_COUNTER(10).CLU2[0x410]=0
CLU_RX_PKT_PRD_DROP_COUNTER(11).CLU2[0x411]=0
CLU_RX_PKT_PRD_DROP_COUNTER(12).CLU2[0x412]=0
CLU_RX_PKT_PRD_DROP_COUNTER(13).CLU2[0x413]=0
CLU_RX_PKT_PRD_DROP_COUNTER(14).CLU2[0x414]=0
CLU_RX_PKT_PRD_DROP_COUNTER(15).CLU2[0x415]=0
CLU_RX_PORT_0_MAP_TO_PARSER_PROFILE.CLU0[0x53a]=0
CLU_RX_PORT_0_MAP_TO_PARSER_PROFILE.CLU1[0x53a]=0
CLU_RX_PORT_0_MAP_TO_PARSER_PROFILE.CLU2[0x53a]=0
CLU_RX_PORT_0_MAP_TO_RMC.CLU0[0x502]=0x1084210
CLU_RX_PORT_0_MAP_TO_RMC.CLU1[0x502]=0x1084210
CLU_RX_PORT_0_MAP_TO_RMC.CLU2[0x502]=0x1084210
CLU_RX_PORT_10_MAP_TO_PARSER_PROFILE.CLU0[0x544]=2
CLU_RX_PORT_10_MAP_TO_PARSER_PROFILE.CLU1[0x544]=2
CLU_RX_PORT_10_MAP_TO_PARSER_PROFILE.CLU2[0x544]=2
CLU_RX_PORT_10_MAP_TO_RMC.CLU0[0x50c]=0x1ad6b5a
CLU_RX_PORT_10_MAP_TO_RMC.CLU1[0x50c]=0x1ad6b5a
CLU_RX_PORT_10_MAP_TO_RMC.CLU2[0x50c]=0
CLU_RX_PORT_11_MAP_TO_PARSER_PROFILE.CLU0[0x545]=2
CLU_RX_PORT_11_MAP_TO_PARSER_PROFILE.CLU1[0x545]=2
CLU_RX_PORT_11_MAP_TO_PARSER_PROFILE.CLU2[0x545]=2
CLU_RX_PORT_11_MAP_TO_RMC.CLU0[0x50d]=0x1bdef7b
CLU_RX_PORT_11_MAP_TO_RMC.CLU1[0x50d]=0x1bdef7b
CLU_RX_PORT_11_MAP_TO_RMC.CLU2[0x50d]=0
CLU_RX_PORT_1_MAP_TO_PARSER_PROFILE.CLU0[0x53b]=0
CLU_RX_PORT_1_MAP_TO_PARSER_PROFILE.CLU1[0x53b]=0
CLU_RX_PORT_1_MAP_TO_PARSER_PROFILE.CLU2[0x53b]=0
CLU_RX_PORT_1_MAP_TO_RMC.CLU0[0x503]=0x118c631
CLU_RX_PORT_1_MAP_TO_RMC.CLU1[0x503]=0x118c631
CLU_RX_PORT_1_MAP_TO_RMC.CLU2[0x503]=0x118c631
CLU_RX_PORT_2_MAP_TO_PARSER_PROFILE.CLU0[0x53c]=0
CLU_RX_PORT_2_MAP_TO_PARSER_PROFILE.CLU1[0x53c]=0
CLU_RX_PORT_2_MAP_TO_PARSER_PROFILE.CLU2[0x53c]=0
CLU_RX_PORT_2_MAP_TO_RMC.CLU0[0x504]=0x16b5ad6
CLU_RX_PORT_2_MAP_TO_RMC.CLU1[0x504]=0x16b5ad6
CLU_RX_PORT_2_MAP_TO_RMC.CLU2[0x504]=0x14a5294
CLU_RX_PORT_3_MAP_TO_PARSER_PROFILE.CLU0[0x53d]=0
CLU_RX_PORT_3_MAP_TO_PARSER_PROFILE.CLU1[0x53d]=0
CLU_RX_PORT_3_MAP_TO_PARSER_PROFILE.CLU2[0x53d]=0
CLU_RX_PORT_3_MAP_TO_RMC.CLU0[0x505]=0x17bdef7
CLU_RX_PORT_3_MAP_TO_RMC.CLU1[0x505]=0x17bdef7
CLU_RX_PORT_3_MAP_TO_RMC.CLU2[0x505]=0x15ad6b5
CLU_RX_PORT_4_MAP_TO_PARSER_PROFILE.CLU0[0x53e]=1
CLU_RX_PORT_4_MAP_TO_PARSER_PROFILE.CLU1[0x53e]=1
CLU_RX_PORT_4_MAP_TO_PARSER_PROFILE.CLU2[0x53e]=1
CLU_RX_PORT_4_MAP_TO_RMC.CLU0[0x506]=0x1294a52
CLU_RX_PORT_4_MAP_TO_RMC.CLU1[0x506]=0x1294a52
CLU_RX_PORT_4_MAP_TO_RMC.CLU2[0x506]=0x1294a52
CLU_RX_PORT_5_MAP_TO_PARSER_PROFILE.CLU0[0x53f]=1
CLU_RX_PORT_5_MAP_TO_PARSER_PROFILE.CLU1[0x53f]=1
CLU_RX_PORT_5_MAP_TO_PARSER_PROFILE.CLU2[0x53f]=1
CLU_RX_PORT_5_MAP_TO_RMC.CLU0[0x507]=0x139ce73
CLU_RX_PORT_5_MAP_TO_RMC.CLU1[0x507]=0x139ce73
CLU_RX_PORT_5_MAP_TO_RMC.CLU2[0x507]=0x139ce73
CLU_RX_PORT_6_MAP_TO_PARSER_PROFILE.CLU0[0x540]=1
CLU_RX_PORT_6_MAP_TO_PARSER_PROFILE.CLU1[0x540]=1
CLU_RX_PORT_6_MAP_TO_PARSER_PROFILE.CLU2[0x540]=1
CLU_RX_PORT_6_MAP_TO_RMC.CLU0[0x508]=0x18c6318
CLU_RX_PORT_6_MAP_TO_RMC.CLU1[0x508]=0x18c6318
CLU_RX_PORT_6_MAP_TO_RMC.CLU2[0x508]=0x16b5ad6
CLU_RX_PORT_7_MAP_TO_PARSER_PROFILE.CLU0[0x541]=1
CLU_RX_PORT_7_MAP_TO_PARSER_PROFILE.CLU1[0x541]=1
CLU_RX_PORT_7_MAP_TO_PARSER_PROFILE.CLU2[0x541]=1
CLU_RX_PORT_7_MAP_TO_RMC.CLU0[0x509]=0x19ce739
CLU_RX_PORT_7_MAP_TO_RMC.CLU1[0x509]=0x19ce739
CLU_RX_PORT_7_MAP_TO_RMC.CLU2[0x509]=0x17bdef7
CLU_RX_PORT_8_MAP_TO_PARSER_PROFILE.CLU0[0x542]=2
CLU_RX_PORT_8_MAP_TO_PARSER_PROFILE.CLU1[0x542]=2
CLU_RX_PORT_8_MAP_TO_PARSER_PROFILE.CLU2[0x542]=2
CLU_RX_PORT_8_MAP_TO_RMC.CLU0[0x50a]=0x14a5294
CLU_RX_PORT_8_MAP_TO_RMC.CLU1[0x50a]=0x14a5294
CLU_RX_PORT_8_MAP_TO_RMC.CLU2[0x50a]=0
CLU_RX_PORT_9_MAP_TO_PARSER_PROFILE.CLU0[0x543]=2
CLU_RX_PORT_9_MAP_TO_PARSER_PROFILE.CLU1[0x543]=2
CLU_RX_PORT_9_MAP_TO_PARSER_PROFILE.CLU2[0x543]=2
CLU_RX_PORT_9_MAP_TO_RMC.CLU0[0x50b]=0x15ad6b5
CLU_RX_PORT_9_MAP_TO_RMC.CLU1[0x50b]=0x15ad6b5
CLU_RX_PORT_9_MAP_TO_RMC.CLU2[0x50b]=0
CLU_RX_PORT_MAP_IS_INVALID(0).CLU0[0x495]=0
CLU_RX_PORT_MAP_IS_INVALID(1).CLU0[0x496]=0
CLU_RX_PORT_MAP_IS_INVALID(2).CLU0[0x497]=0
CLU_RX_PORT_MAP_IS_INVALID(3).CLU0[0x498]=0
CLU_RX_PORT_MAP_IS_INVALID(4).CLU0[0x499]=0
CLU_RX_PORT_MAP_IS_INVALID(5).CLU0[0x49a]=0
CLU_RX_PORT_MAP_IS_INVALID(6).CLU0[0x49b]=0
CLU_RX_PORT_MAP_IS_INVALID(7).CLU0[0x49c]=0
CLU_RX_PORT_MAP_IS_INVALID(8).CLU0[0x49d]=0
CLU_RX_PORT_MAP_IS_INVALID(9).CLU0[0x49e]=0
CLU_RX_PORT_MAP_IS_INVALID(10).CLU0[0x49f]=0
CLU_RX_PORT_MAP_IS_INVALID(11).CLU0[0x4a0]=0
CLU_RX_PORT_MAP_IS_INVALID(0).CLU1[0x495]=0
CLU_RX_PORT_MAP_IS_INVALID(1).CLU1[0x496]=0
CLU_RX_PORT_MAP_IS_INVALID(2).CLU1[0x497]=0
CLU_RX_PORT_MAP_IS_INVALID(3).CLU1[0x498]=0
CLU_RX_PORT_MAP_IS_INVALID(4).CLU1[0x499]=0
CLU_RX_PORT_MAP_IS_INVALID(5).CLU1[0x49a]=0
CLU_RX_PORT_MAP_IS_INVALID(6).CLU1[0x49b]=0
CLU_RX_PORT_MAP_IS_INVALID(7).CLU1[0x49c]=0
CLU_RX_PORT_MAP_IS_INVALID(8).CLU1[0x49d]=0
CLU_RX_PORT_MAP_IS_INVALID(9).CLU1[0x49e]=0
CLU_RX_PORT_MAP_IS_INVALID(10).CLU1[0x49f]=0
CLU_RX_PORT_MAP_IS_INVALID(11).CLU1[0x4a0]=0
CLU_RX_PORT_MAP_IS_INVALID(0).CLU2[0x495]=0
CLU_RX_PORT_MAP_IS_INVALID(1).CLU2[0x496]=0
CLU_RX_PORT_MAP_IS_INVALID(2).CLU2[0x497]=0
CLU_RX_PORT_MAP_IS_INVALID(3).CLU2[0x498]=0
CLU_RX_PORT_MAP_IS_INVALID(4).CLU2[0x499]=0
CLU_RX_PORT_MAP_IS_INVALID(5).CLU2[0x49a]=0
CLU_RX_PORT_MAP_IS_INVALID(6).CLU2[0x49b]=0
CLU_RX_PORT_MAP_IS_INVALID(7).CLU2[0x49c]=0
CLU_RX_PORT_MAP_IS_INVALID(8).CLU2[0x49d]=0
CLU_RX_PORT_MAP_IS_INVALID(9).CLU2[0x49e]=0
CLU_RX_PORT_MAP_IS_INVALID(10).CLU2[0x49f]=0
CLU_RX_PORT_MAP_IS_INVALID(11).CLU2[0x4a0]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(0).CLU0[0x4c5]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(1).CLU0[0x4c6]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(2).CLU0[0x4c7]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(3).CLU0[0x4c8]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(4).CLU0[0x4c9]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(5).CLU0[0x4ca]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(6).CLU0[0x4cb]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(7).CLU0[0x4cc]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(8).CLU0[0x4cd]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(9).CLU0[0x4ce]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(10).CLU0[0x4cf]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(11).CLU0[0x4d0]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(0).CLU1[0x4c5]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(1).CLU1[0x4c6]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(2).CLU1[0x4c7]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(3).CLU1[0x4c8]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(4).CLU1[0x4c9]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(5).CLU1[0x4ca]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(6).CLU1[0x4cb]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(7).CLU1[0x4cc]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(8).CLU1[0x4cd]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(9).CLU1[0x4ce]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(10).CLU1[0x4cf]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(11).CLU1[0x4d0]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(0).CLU2[0x4c5]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(1).CLU2[0x4c6]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(2).CLU2[0x4c7]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(3).CLU2[0x4c8]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(4).CLU2[0x4c9]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(5).CLU2[0x4ca]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(6).CLU2[0x4cb]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(7).CLU2[0x4cc]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(8).CLU2[0x4cd]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(9).CLU2[0x4ce]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(10).CLU2[0x4cf]=0
CLU_RX_PORT_MAP_IS_INVALID_PARAM(11).CLU2[0x4d0]=0
CLU_RX_PORT_MAP_MASK_PARSER_TDM.CLU0[0x501]=6
CLU_RX_PORT_MAP_MASK_PARSER_TDM.CLU1[0x501]=6
CLU_RX_PORT_MAP_MASK_PARSER_TDM.CLU2[0x501]=6
CLU_RX_PORT_OVF.CLU0[0x298]=0
CLU_RX_PORT_OVF.CLU1[0x298]=0
CLU_RX_PORT_OVF.CLU2[0x298]=0
CLU_RX_REQ_LOW_RMC_EN.CLU0[0x628]=0xffff
CLU_RX_REQ_LOW_RMC_EN.CLU1[0x628]=0xffff
CLU_RX_REQ_LOW_RMC_EN.CLU2[0x628]=0xffff
CLU_RX_RMC_0_MAP.CLU0[0x50e]=0
CLU_RX_RMC_0_MAP.CLU1[0x50e]=0
CLU_RX_RMC_0_MAP.CLU2[0x50e]=0
CLU_RX_RMC_0_PRD_THRESHOLDS_CONFIG.CLU0[0x25d]=0x800100020004000
CLU_RX_RMC_0_PRD_THRESHOLDS_CONFIG.CLU1[0x25d]=0x800100020004000
CLU_RX_RMC_0_PRD_THRESHOLDS_CONFIG.CLU2[0x25d]=0x800100020004000
CLU_RX_RMC_10_MAP.CLU0[0x518]=0xa
CLU_RX_RMC_10_MAP.CLU1[0x518]=0xa
CLU_RX_RMC_10_MAP.CLU2[0x518]=0xa
CLU_RX_RMC_10_PRD_THRESHOLDS_CONFIG.CLU0[0x271]=0x800100020004000
CLU_RX_RMC_10_PRD_THRESHOLDS_CONFIG.CLU1[0x271]=0x800100020004000
CLU_RX_RMC_10_PRD_THRESHOLDS_CONFIG.CLU2[0x271]=0x800100020004000
CLU_RX_RMC_11_MAP.CLU0[0x519]=0xb
CLU_RX_RMC_11_MAP.CLU1[0x519]=0xb
CLU_RX_RMC_11_MAP.CLU2[0x519]=0xb
CLU_RX_RMC_11_PRD_THRESHOLDS_CONFIG.CLU0[0x273]=0x800100020004000
CLU_RX_RMC_11_PRD_THRESHOLDS_CONFIG.CLU1[0x273]=0x800100020004000
CLU_RX_RMC_11_PRD_THRESHOLDS_CONFIG.CLU2[0x273]=0x800100020004000
CLU_RX_RMC_12_MAP.CLU0[0x51a]=0xc
CLU_RX_RMC_12_MAP.CLU1[0x51a]=0xc
CLU_RX_RMC_12_MAP.CLU2[0x51a]=0xc
CLU_RX_RMC_12_PRD_THRESHOLDS_CONFIG.CLU0[0x275]=0x800100020004000
CLU_RX_RMC_12_PRD_THRESHOLDS_CONFIG.CLU1[0x275]=0x800100020004000
CLU_RX_RMC_12_PRD_THRESHOLDS_CONFIG.CLU2[0x275]=0x800100020004000
CLU_RX_RMC_13_MAP.CLU0[0x51b]=0xd
CLU_RX_RMC_13_MAP.CLU1[0x51b]=0xd
CLU_RX_RMC_13_MAP.CLU2[0x51b]=0xd
CLU_RX_RMC_13_PRD_THRESHOLDS_CONFIG.CLU0[0x277]=0x800100020004000
CLU_RX_RMC_13_PRD_THRESHOLDS_CONFIG.CLU1[0x277]=0x800100020004000
CLU_RX_RMC_13_PRD_THRESHOLDS_CONFIG.CLU2[0x277]=0x800100020004000
CLU_RX_RMC_14_MAP.CLU0[0x51c]=0xe
CLU_RX_RMC_14_MAP.CLU1[0x51c]=0xe
CLU_RX_RMC_14_MAP.CLU2[0x51c]=0xe
CLU_RX_RMC_14_PRD_THRESHOLDS_CONFIG.CLU0[0x279]=0x800100020004000
CLU_RX_RMC_14_PRD_THRESHOLDS_CONFIG.CLU1[0x279]=0x800100020004000
CLU_RX_RMC_14_PRD_THRESHOLDS_CONFIG.CLU2[0x279]=0x800100020004000
CLU_RX_RMC_15_MAP.CLU0[0x51d]=0xf
CLU_RX_RMC_15_MAP.CLU1[0x51d]=0xf
CLU_RX_RMC_15_MAP.CLU2[0x51d]=0xf
CLU_RX_RMC_15_PRD_THRESHOLDS_CONFIG.CLU0[0x27b]=0x800100020004000
CLU_RX_RMC_15_PRD_THRESHOLDS_CONFIG.CLU1[0x27b]=0x800100020004000
CLU_RX_RMC_15_PRD_THRESHOLDS_CONFIG.CLU2[0x27b]=0x800100020004000
CLU_RX_RMC_1_MAP.CLU0[0x50f]=1
CLU_RX_RMC_1_MAP.CLU1[0x50f]=1
CLU_RX_RMC_1_MAP.CLU2[0x50f]=1
CLU_RX_RMC_1_PRD_THRESHOLDS_CONFIG.CLU0[0x25f]=0x800100020004000
CLU_RX_RMC_1_PRD_THRESHOLDS_CONFIG.CLU1[0x25f]=0x800100020004000
CLU_RX_RMC_1_PRD_THRESHOLDS_CONFIG.CLU2[0x25f]=0x800100020004000
CLU_RX_RMC_2_MAP.CLU0[0x510]=4
CLU_RX_RMC_2_MAP.CLU1[0x510]=4
CLU_RX_RMC_2_MAP.CLU2[0x510]=4
CLU_RX_RMC_2_PRD_THRESHOLDS_CONFIG.CLU0[0x261]=0x800100020004000
CLU_RX_RMC_2_PRD_THRESHOLDS_CONFIG.CLU1[0x261]=0x800100020004000
CLU_RX_RMC_2_PRD_THRESHOLDS_CONFIG.CLU2[0x261]=0x800100020004000
CLU_RX_RMC_3_MAP.CLU0[0x511]=5
CLU_RX_RMC_3_MAP.CLU1[0x511]=5
CLU_RX_RMC_3_MAP.CLU2[0x511]=5
CLU_RX_RMC_3_PRD_THRESHOLDS_CONFIG.CLU0[0x263]=0x800100020004000
CLU_RX_RMC_3_PRD_THRESHOLDS_CONFIG.CLU1[0x263]=0x800100020004000
CLU_RX_RMC_3_PRD_THRESHOLDS_CONFIG.CLU2[0x263]=0x800100020004000
CLU_RX_RMC_4_MAP.CLU0[0x512]=8
CLU_RX_RMC_4_MAP.CLU1[0x512]=8
CLU_RX_RMC_4_MAP.CLU2[0x512]=2
CLU_RX_RMC_4_PRD_THRESHOLDS_CONFIG.CLU0[0x265]=0x800100020004000
CLU_RX_RMC_4_PRD_THRESHOLDS_CONFIG.CLU1[0x265]=0x800100020004000
CLU_RX_RMC_4_PRD_THRESHOLDS_CONFIG.CLU2[0x265]=0x800100020004000
CLU_RX_RMC_5_MAP.CLU0[0x513]=9
CLU_RX_RMC_5_MAP.CLU1[0x513]=9
CLU_RX_RMC_5_MAP.CLU2[0x513]=3
CLU_RX_RMC_5_PRD_THRESHOLDS_CONFIG.CLU0[0x267]=0x800100020004000
CLU_RX_RMC_5_PRD_THRESHOLDS_CONFIG.CLU1[0x267]=0x800100020004000
CLU_RX_RMC_5_PRD_THRESHOLDS_CONFIG.CLU2[0x267]=0x800100020004000
CLU_RX_RMC_6_MAP.CLU0[0x514]=2
CLU_RX_RMC_6_MAP.CLU1[0x514]=2
CLU_RX_RMC_6_MAP.CLU2[0x514]=6
CLU_RX_RMC_6_PRD_THRESHOLDS_CONFIG.CLU0[0x269]=0x800100020004000
CLU_RX_RMC_6_PRD_THRESHOLDS_CONFIG.CLU1[0x269]=0x800100020004000
CLU_RX_RMC_6_PRD_THRESHOLDS_CONFIG.CLU2[0x269]=0x800100020004000
CLU_RX_RMC_7_MAP.CLU0[0x515]=3
CLU_RX_RMC_7_MAP.CLU1[0x515]=3
CLU_RX_RMC_7_MAP.CLU2[0x515]=7
CLU_RX_RMC_7_PRD_THRESHOLDS_CONFIG.CLU0[0x26b]=0x800100020004000
CLU_RX_RMC_7_PRD_THRESHOLDS_CONFIG.CLU1[0x26b]=0x800100020004000
CLU_RX_RMC_7_PRD_THRESHOLDS_CONFIG.CLU2[0x26b]=0x800100020004000
CLU_RX_RMC_8_MAP.CLU0[0x516]=6
CLU_RX_RMC_8_MAP.CLU1[0x516]=6
CLU_RX_RMC_8_MAP.CLU2[0x516]=8
CLU_RX_RMC_8_PRD_THRESHOLDS_CONFIG.CLU0[0x26d]=0x800100020004000
CLU_RX_RMC_8_PRD_THRESHOLDS_CONFIG.CLU1[0x26d]=0x800100020004000
CLU_RX_RMC_8_PRD_THRESHOLDS_CONFIG.CLU2[0x26d]=0x800100020004000
CLU_RX_RMC_9_MAP.CLU0[0x517]=7
CLU_RX_RMC_9_MAP.CLU1[0x517]=7
CLU_RX_RMC_9_MAP.CLU2[0x517]=9
CLU_RX_RMC_9_PRD_THRESHOLDS_CONFIG.CLU0[0x26f]=0x800100020004000
CLU_RX_RMC_9_PRD_THRESHOLDS_CONFIG.CLU1[0x26f]=0x800100020004000
CLU_RX_RMC_9_PRD_THRESHOLDS_CONFIG.CLU2[0x26f]=0x800100020004000
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(0).CLU0[0x4d1]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(1).CLU0[0x4d2]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(2).CLU0[0x4d3]=0x34bb1c327
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(3).CLU0[0x4d4]=0x34bb1c327
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(4).CLU0[0x4d5]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(5).CLU0[0x4d6]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(6).CLU0[0x4d7]=0x34bb1c32f
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(7).CLU0[0x4d8]=0x34bb1c32f
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(8).CLU0[0x4d9]=0x34bb1c32f
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(9).CLU0[0x4da]=0x34bb1c32f
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(10).CLU0[0x4db]=0x34bb1c338
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(11).CLU0[0x4dc]=0x34bb1c338
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(0).CLU1[0x4d1]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(1).CLU1[0x4d2]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(2).CLU1[0x4d3]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(3).CLU1[0x4d4]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(4).CLU1[0x4d5]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(5).CLU1[0x4d6]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(6).CLU1[0x4d7]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(7).CLU1[0x4d8]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(8).CLU1[0x4d9]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(9).CLU1[0x4da]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(10).CLU1[0x4db]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(11).CLU1[0x4dc]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(0).CLU2[0x4d1]=0x10b4726733
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(1).CLU2[0x4d2]=0x10b4726731
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(2).CLU2[0x4d3]=0x10b4726736
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(3).CLU2[0x4d4]=0x10b4726737
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(4).CLU2[0x4d5]=0x10b4726738
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(5).CLU2[0x4d6]=0x10b4726738
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(6).CLU2[0x4d7]=0x10b4726738
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(7).CLU2[0x4d8]=0
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(8).CLU2[0x4d9]=0x10b4726739
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(9).CLU2[0x4da]=0x10b4726739
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(10).CLU2[0x4db]=0x10b4726733
CLU_RX_RMC_MAP_TO_PORT_IS_INVALID(11).CLU2[0x4dc]=0x10b472672d
CLU_RX_RMC_PRIORITY_MAP.CLU0[0x546]=0xffff00000000
CLU_RX_RMC_PRIORITY_MAP.CLU1[0x546]=0xffff00000000
CLU_RX_RMC_PRIORITY_MAP.CLU2[0x546]=0xffff00000000
CLU_RX_RUNT_PKT_COUNTER(0).CLU0[0x446]=0
CLU_RX_RUNT_PKT_COUNTER(1).CLU0[0x447]=0
CLU_RX_RUNT_PKT_COUNTER(2).CLU0[0x448]=0
CLU_RX_RUNT_PKT_COUNTER(3).CLU0[0x449]=0
CLU_RX_RUNT_PKT_COUNTER(4).CLU0[0x44a]=0
CLU_RX_RUNT_PKT_COUNTER(5).CLU0[0x44b]=0
CLU_RX_RUNT_PKT_COUNTER(6).CLU0[0x44c]=0
CLU_RX_RUNT_PKT_COUNTER(7).CLU0[0x44d]=0
CLU_RX_RUNT_PKT_COUNTER(8).CLU0[0x44e]=0
CLU_RX_RUNT_PKT_COUNTER(9).CLU0[0x44f]=0
CLU_RX_RUNT_PKT_COUNTER(10).CLU0[0x450]=0
CLU_RX_RUNT_PKT_COUNTER(11).CLU0[0x451]=0
CLU_RX_RUNT_PKT_COUNTER(12).CLU0[0x452]=0
CLU_RX_RUNT_PKT_COUNTER(13).CLU0[0x453]=0
CLU_RX_RUNT_PKT_COUNTER(14).CLU0[0x454]=0
CLU_RX_RUNT_PKT_COUNTER(15).CLU0[0x455]=0
CLU_RX_RUNT_PKT_COUNTER(0).CLU1[0x446]=0
CLU_RX_RUNT_PKT_COUNTER(1).CLU1[0x447]=0
CLU_RX_RUNT_PKT_COUNTER(2).CLU1[0x448]=0
CLU_RX_RUNT_PKT_COUNTER(3).CLU1[0x449]=0
CLU_RX_RUNT_PKT_COUNTER(4).CLU1[0x44a]=0
CLU_RX_RUNT_PKT_COUNTER(5).CLU1[0x44b]=0
CLU_RX_RUNT_PKT_COUNTER(6).CLU1[0x44c]=0
CLU_RX_RUNT_PKT_COUNTER(7).CLU1[0x44d]=0
CLU_RX_RUNT_PKT_COUNTER(8).CLU1[0x44e]=0
CLU_RX_RUNT_PKT_COUNTER(9).CLU1[0x44f]=0
CLU_RX_RUNT_PKT_COUNTER(10).CLU1[0x450]=0
CLU_RX_RUNT_PKT_COUNTER(11).CLU1[0x451]=0
CLU_RX_RUNT_PKT_COUNTER(12).CLU1[0x452]=0
CLU_RX_RUNT_PKT_COUNTER(13).CLU1[0x453]=0
CLU_RX_RUNT_PKT_COUNTER(14).CLU1[0x454]=0
CLU_RX_RUNT_PKT_COUNTER(15).CLU1[0x455]=0
CLU_RX_RUNT_PKT_COUNTER(0).CLU2[0x446]=0
CLU_RX_RUNT_PKT_COUNTER(1).CLU2[0x447]=0
CLU_RX_RUNT_PKT_COUNTER(2).CLU2[0x448]=0
CLU_RX_RUNT_PKT_COUNTER(3).CLU2[0x449]=0
CLU_RX_RUNT_PKT_COUNTER(4).CLU2[0x44a]=0
CLU_RX_RUNT_PKT_COUNTER(5).CLU2[0x44b]=0
CLU_RX_RUNT_PKT_COUNTER(6).CLU2[0x44c]=0
CLU_RX_RUNT_PKT_COUNTER(7).CLU2[0x44d]=0
CLU_RX_RUNT_PKT_COUNTER(8).CLU2[0x44e]=0
CLU_RX_RUNT_PKT_COUNTER(9).CLU2[0x44f]=0
CLU_RX_RUNT_PKT_COUNTER(10).CLU2[0x450]=0
CLU_RX_RUNT_PKT_COUNTER(11).CLU2[0x451]=0
CLU_RX_RUNT_PKT_COUNTER(12).CLU2[0x452]=0
CLU_RX_RUNT_PKT_COUNTER(13).CLU2[0x453]=0
CLU_RX_RUNT_PKT_COUNTER(14).CLU2[0x454]=0
CLU_RX_RUNT_PKT_COUNTER(15).CLU2[0x455]=0
CLU_RX_SCH_DEBUG_CONF.CLU0[0x625]=2
CLU_RX_SCH_DEBUG_CONF.CLU1[0x625]=0xb
CLU_RX_SCH_DEBUG_CONF.CLU2[0x625]=7
CLU_RX_SCH_DEBUG_RESULT.CLU0[0x623]=0xf0000000
CLU_RX_SCH_DEBUG_RESULT.CLU1[0x623]=0xf0000000
CLU_RX_SCH_DEBUG_RESULT.CLU2[0x623]=0xf0000000
CLU_RX_SCH_MORE_THAN_ONE_RD_FROM_MAIN_SCH.CLU0[0x62a]=0
CLU_RX_SCH_MORE_THAN_ONE_RD_FROM_MAIN_SCH.CLU1[0x62a]=0
CLU_RX_SCH_MORE_THAN_ONE_RD_FROM_MAIN_SCH.CLU2[0x62a]=0
CLU_RX_SCH_WIN_PRIOR_HIGH_WITH_NO_WIN_RMC_CNT.CLU0[0x62c]=0
CLU_RX_SCH_WIN_PRIOR_HIGH_WITH_NO_WIN_RMC_CNT.CLU1[0x62c]=0
CLU_RX_SCH_WIN_PRIOR_HIGH_WITH_NO_WIN_RMC_CNT.CLU2[0x62c]=0
CLU_RX_SCH_WIN_PRIOR_LOW_WITH_NO_WIN_RMC_CNT.CLU0[0x62d]=0
CLU_RX_SCH_WIN_PRIOR_LOW_WITH_NO_WIN_RMC_CNT.CLU1[0x62d]=0
CLU_RX_SCH_WIN_PRIOR_LOW_WITH_NO_WIN_RMC_CNT.CLU2[0x62d]=0
CLU_RX_SCH_WIN_PRIOR_TDM_WITH_NO_WIN_RMC_CNT.CLU0[0x62b]=0
CLU_RX_SCH_WIN_PRIOR_TDM_WITH_NO_WIN_RMC_CNT.CLU1[0x62b]=0
CLU_RX_SCH_WIN_PRIOR_TDM_WITH_NO_WIN_RMC_CNT.CLU2[0x62b]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(0).CLU0[0x3f6]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(1).CLU0[0x3f7]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(2).CLU0[0x3f8]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(3).CLU0[0x3f9]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(4).CLU0[0x3fa]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(5).CLU0[0x3fb]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(6).CLU0[0x3fc]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(7).CLU0[0x3fd]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(8).CLU0[0x3fe]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(9).CLU0[0x3ff]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(10).CLU0[0x400]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(11).CLU0[0x401]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(12).CLU0[0x402]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(13).CLU0[0x403]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(14).CLU0[0x404]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(15).CLU0[0x405]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(0).CLU1[0x3f6]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(1).CLU1[0x3f7]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(2).CLU1[0x3f8]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(3).CLU1[0x3f9]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(4).CLU1[0x3fa]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(5).CLU1[0x3fb]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(6).CLU1[0x3fc]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(7).CLU1[0x3fd]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(8).CLU1[0x3fe]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(9).CLU1[0x3ff]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(10).CLU1[0x400]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(11).CLU1[0x401]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(12).CLU1[0x402]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(13).CLU1[0x403]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(14).CLU1[0x404]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(15).CLU1[0x405]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(0).CLU2[0x3f6]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(1).CLU2[0x3f7]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(2).CLU2[0x3f8]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(3).CLU2[0x3f9]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(4).CLU2[0x3fa]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(5).CLU2[0x3fb]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(6).CLU2[0x3fc]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(7).CLU2[0x3fd]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(8).CLU2[0x3fe]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(9).CLU2[0x3ff]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(10).CLU2[0x400]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(11).CLU2[0x401]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(12).CLU2[0x402]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(13).CLU2[0x403]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(14).CLU2[0x404]=0
CLU_RX_SMALL_PKT_ERR_DROP_COUNTER(15).CLU2[0x405]=0
CLU_RX_TDM_BYTE_COUNTER.CLU0[0x480]=0
CLU_RX_TDM_BYTE_COUNTER.CLU1[0x480]=0
CLU_RX_TDM_BYTE_COUNTER.CLU2[0x480]=0
CLU_RX_TDM_PKT_COUNTER.CLU0[0x47e]=0
CLU_RX_TDM_PKT_COUNTER.CLU1[0x47e]=0
CLU_RX_TDM_PKT_COUNTER.CLU2[0x47e]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(0).CLU0[0x1eb]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(1).CLU0[0x1ec]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(2).CLU0[0x1ed]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(3).CLU0[0x1ee]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(4).CLU0[0x1ef]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(5).CLU0[0x1f0]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(6).CLU0[0x1f1]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(7).CLU0[0x1f2]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(8).CLU0[0x1f3]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(9).CLU0[0x1f4]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(10).CLU0[0x1f5]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(11).CLU0[0x1f6]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(12).CLU0[0x1f7]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(13).CLU0[0x1f8]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(14).CLU0[0x1f9]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(15).CLU0[0x1fa]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(0).CLU1[0x1eb]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(1).CLU1[0x1ec]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(2).CLU1[0x1ed]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(3).CLU1[0x1ee]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(4).CLU1[0x1ef]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(5).CLU1[0x1f0]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(6).CLU1[0x1f1]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(7).CLU1[0x1f2]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(8).CLU1[0x1f3]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(9).CLU1[0x1f4]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(10).CLU1[0x1f5]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(11).CLU1[0x1f6]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(12).CLU1[0x1f7]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(13).CLU1[0x1f8]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(14).CLU1[0x1f9]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(15).CLU1[0x1fa]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(0).CLU2[0x1eb]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(1).CLU2[0x1ec]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(2).CLU2[0x1ed]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(3).CLU2[0x1ee]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(4).CLU2[0x1ef]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(5).CLU2[0x1f0]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(6).CLU2[0x1f1]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(7).CLU2[0x1f2]=0x19
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(8).CLU2[0x1f3]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(9).CLU2[0x1f4]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(10).CLU2[0x1f5]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(11).CLU2[0x1f6]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(12).CLU2[0x1f7]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(13).CLU2[0x1f8]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(14).CLU2[0x1f9]=0
CLU_RX_THRESHOLD_AFTER_OVERFLOW_RMC(15).CLU2[0x1fa]=0
CLU_RX_TOTAL_BYTE_COUNTER.CLU0[0x478]=0x25e2b187b5e
CLU_RX_TOTAL_BYTE_COUNTER.CLU1[0x478]=0
CLU_RX_TOTAL_BYTE_COUNTER.CLU2[0x478]=0xfd3ebcd0cfd
CLU_RX_TOTAL_BYTE_WITH_ERR_COUNTER.CLU0[0x47d]=0
CLU_RX_TOTAL_BYTE_WITH_ERR_COUNTER.CLU1[0x47d]=0
CLU_RX_TOTAL_BYTE_WITH_ERR_COUNTER.CLU2[0x47d]=0
CLU_RX_TOTAL_PKT_COUNTER.CLU0[0x476]=0x197d54f4f
CLU_RX_TOTAL_PKT_COUNTER.CLU1[0x476]=0
CLU_RX_TOTAL_PKT_COUNTER.CLU2[0x476]=0x3465632a2
CLU_RX_TOTAL_PKT_WITH_ERR_COUNTER.CLU0[0x47c]=0
CLU_RX_TOTAL_PKT_WITH_ERR_COUNTER.CLU1[0x47c]=0
CLU_RX_TOTAL_PKT_WITH_ERR_COUNTER.CLU2[0x47c]=0
CLU_SBUS_BROADCAST_ID.CLU0[0x86]=0x7ff
CLU_SBUS_BROADCAST_ID.CLU1[0x86]=0x7ff
CLU_SBUS_BROADCAST_ID.CLU2[0x86]=0x7ff
CLU_SBUS_LAST_IN_CHAIN.CLU0[0x87]=0
CLU_SBUS_LAST_IN_CHAIN.CLU1[0x87]=0
CLU_SBUS_LAST_IN_CHAIN.CLU2[0x87]=0
CLU_SCH_CNT_DEC_TH.CLU0[0x622]=0
CLU_SCH_CNT_DEC_TH.CLU1[0x622]=0
CLU_SCH_CNT_DEC_TH.CLU2[0x622]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(0).CLU0[0x612]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(1).CLU0[0x613]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(2).CLU0[0x614]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(3).CLU0[0x615]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(4).CLU0[0x616]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(5).CLU0[0x617]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(6).CLU0[0x618]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(7).CLU0[0x619]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(8).CLU0[0x61a]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(9).CLU0[0x61b]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(10).CLU0[0x61c]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(11).CLU0[0x61d]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(12).CLU0[0x61e]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(13).CLU0[0x61f]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(14).CLU0[0x620]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(15).CLU0[0x621]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(0).CLU1[0x612]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(1).CLU1[0x613]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(2).CLU1[0x614]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(3).CLU1[0x615]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(4).CLU1[0x616]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(5).CLU1[0x617]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(6).CLU1[0x618]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(7).CLU1[0x619]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(8).CLU1[0x61a]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(9).CLU1[0x61b]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(10).CLU1[0x61c]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(11).CLU1[0x61d]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(12).CLU1[0x61e]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(13).CLU1[0x61f]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(14).CLU1[0x620]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(15).CLU1[0x621]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(0).CLU2[0x612]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(1).CLU2[0x613]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(2).CLU2[0x614]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(3).CLU2[0x615]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(4).CLU2[0x616]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(5).CLU2[0x617]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(6).CLU2[0x618]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(7).CLU2[0x619]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(8).CLU2[0x61a]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(9).CLU2[0x61b]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(10).CLU2[0x61c]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(11).CLU2[0x61d]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(12).CLU2[0x61e]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(13).CLU2[0x61f]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(14).CLU2[0x620]=0
CLU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(15).CLU2[0x621]=0
CLU_SPECIAL_CLOCK_CONTROLS.CLU0[0xc1]=2
CLU_SPECIAL_CLOCK_CONTROLS.CLU1[0xc1]=2
CLU_SPECIAL_CLOCK_CONTROLS.CLU2[0xc1]=2
CLU_TX_EGRESS_CREDITS_DEBUG_PM.CLU0[0x28b]=0x555050
CLU_TX_EGRESS_CREDITS_DEBUG_PM.CLU1[0x28b]=0x555555
CLU_TX_EGRESS_CREDITS_DEBUG_PM.CLU2[0x28b]=0x1555
CLU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE.CLU0[0x293]=0
CLU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE.CLU1[0x293]=0
CLU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE.CLU2[0x293]=0
CLU_TX_FIFO_FLUSH_AND_STOP_TOOL.CLU0[0x284]=0
CLU_TX_FIFO_FLUSH_AND_STOP_TOOL.CLU1[0x284]=0
CLU_TX_FIFO_FLUSH_AND_STOP_TOOL.CLU2[0x284]=0
CLU_TX_MLF_CONFIG.CLU0[0x1ea]=0xd0340d0340d0340d0000d0340d0340d
CLU_TX_MLF_CONFIG.CLU1[0x1ea]=0xd0340d0340d0340d0000d0340d0340d
CLU_TX_MLF_CONFIG.CLU2[0x1ea]=0x9024090240d0340d0000d0340d0340d
CLU_TX_MLF_ERR_ON_MOP_FROM_EGQ.CLU0[0x295]=0
CLU_TX_MLF_ERR_ON_MOP_FROM_EGQ.CLU1[0x295]=0
CLU_TX_MLF_ERR_ON_MOP_FROM_EGQ.CLU2[0x295]=0
CLU_TX_MLF_FIFO_FLUSH(0).CLU0[0x1de]=0
CLU_TX_MLF_FIFO_FLUSH(1).CLU0[0x1df]=0
CLU_TX_MLF_FIFO_FLUSH(2).CLU0[0x1e0]=0
CLU_TX_MLF_FIFO_FLUSH(3).CLU0[0x1e1]=0
CLU_TX_MLF_FIFO_FLUSH(4).CLU0[0x1e2]=0
CLU_TX_MLF_FIFO_FLUSH(5).CLU0[0x1e3]=0
CLU_TX_MLF_FIFO_FLUSH(6).CLU0[0x1e4]=0
CLU_TX_MLF_FIFO_FLUSH(7).CLU0[0x1e5]=0
CLU_TX_MLF_FIFO_FLUSH(8).CLU0[0x1e6]=0
CLU_TX_MLF_FIFO_FLUSH(9).CLU0[0x1e7]=0
CLU_TX_MLF_FIFO_FLUSH(10).CLU0[0x1e8]=0
CLU_TX_MLF_FIFO_FLUSH(11).CLU0[0x1e9]=0
CLU_TX_MLF_FIFO_FLUSH(0).CLU1[0x1de]=0
CLU_TX_MLF_FIFO_FLUSH(1).CLU1[0x1df]=0
CLU_TX_MLF_FIFO_FLUSH(2).CLU1[0x1e0]=0
CLU_TX_MLF_FIFO_FLUSH(3).CLU1[0x1e1]=0
CLU_TX_MLF_FIFO_FLUSH(4).CLU1[0x1e2]=0
CLU_TX_MLF_FIFO_FLUSH(5).CLU1[0x1e3]=0
CLU_TX_MLF_FIFO_FLUSH(6).CLU1[0x1e4]=0
CLU_TX_MLF_FIFO_FLUSH(7).CLU1[0x1e5]=0
CLU_TX_MLF_FIFO_FLUSH(8).CLU1[0x1e6]=0
CLU_TX_MLF_FIFO_FLUSH(9).CLU1[0x1e7]=0
CLU_TX_MLF_FIFO_FLUSH(10).CLU1[0x1e8]=0
CLU_TX_MLF_FIFO_FLUSH(11).CLU1[0x1e9]=0
CLU_TX_MLF_FIFO_FLUSH(0).CLU2[0x1de]=0
CLU_TX_MLF_FIFO_FLUSH(1).CLU2[0x1df]=0
CLU_TX_MLF_FIFO_FLUSH(2).CLU2[0x1e0]=0
CLU_TX_MLF_FIFO_FLUSH(3).CLU2[0x1e1]=0
CLU_TX_MLF_FIFO_FLUSH(4).CLU2[0x1e2]=0
CLU_TX_MLF_FIFO_FLUSH(5).CLU2[0x1e3]=0
CLU_TX_MLF_FIFO_FLUSH(6).CLU2[0x1e4]=0
CLU_TX_MLF_FIFO_FLUSH(7).CLU2[0x1e5]=0
CLU_TX_MLF_FIFO_FLUSH(8).CLU2[0x1e6]=0
CLU_TX_MLF_FIFO_FLUSH(9).CLU2[0x1e7]=0
CLU_TX_MLF_FIFO_FLUSH(10).CLU2[0x1e8]=0
CLU_TX_MLF_FIFO_FLUSH(11).CLU2[0x1e9]=0
CLU_TX_MLF_LEVEL_PM.CLU0[0x28d]=0x7801e007801e007801e0000000007801e0000000
CLU_TX_MLF_LEVEL_PM.CLU1[0x28d]=0x7c01f007801e007c01f007801e007c01e007801e
CLU_TX_MLF_LEVEL_PM.CLU2[0x28d]=0x1d007801e007401d007801e
CLU_TX_MLF_MAX_OCCUPANCY.CLU0[0x28f]=0x7801e007801e007801e0080020007801e0080020
CLU_TX_MLF_MAX_OCCUPANCY.CLU1[0x28f]=0x7c01f007801e007c01f007801e007c01e007801e
CLU_TX_MLF_MAX_OCCUPANCY.CLU2[0x28f]=0x8001d007801e007401d007801e
CLU_TX_MLF_NUM_CREDITS_FROM_PM.CLU0[0x291]=0x80800000808
CLU_TX_MLF_NUM_CREDITS_FROM_PM.CLU1[0x291]=0
CLU_TX_MLF_NUM_CREDITS_FROM_PM.CLU2[0x291]=0x800000000000000
CLU_TX_MLF_OVERFLOW_PM.CLU0[0x28c]=0xfcc
CLU_TX_MLF_OVERFLOW_PM.CLU1[0x28c]=0xfff
CLU_TX_MLF_OVERFLOW_PM.CLU2[0x28c]=0x7f
CLU_TX_NO_DATA_IN_BUFFER.CLU0[0x292]=0
CLU_TX_NO_DATA_IN_BUFFER.CLU1[0x292]=0
CLU_TX_NO_DATA_IN_BUFFER.CLU2[0x292]=0
CLU_TX_PORTS_CONFIG_PM(0).CLU0[0x286]=2
CLU_TX_PORTS_CONFIG_PM(1).CLU0[0x287]=2
CLU_TX_PORTS_CONFIG_PM(2).CLU0[0x288]=2
CLU_TX_PORTS_CONFIG_PM(0).CLU1[0x286]=2
CLU_TX_PORTS_CONFIG_PM(1).CLU1[0x287]=2
CLU_TX_PORTS_CONFIG_PM(2).CLU1[0x288]=2
CLU_TX_PORTS_CONFIG_PM(0).CLU2[0x286]=2
CLU_TX_PORTS_CONFIG_PM(1).CLU2[0x287]=2
CLU_TX_PORTS_CONFIG_PM(2).CLU2[0x288]=2
CLU_TX_PORTS_SRSTN.CLU0[0x101]=0xfff
CLU_TX_PORTS_SRSTN.CLU1[0x101]=0xfff
CLU_TX_PORTS_SRSTN.CLU2[0x101]=0xff
CLU_TX_PORT_OVF.CLU0[0x299]=0xfcc
CLU_TX_PORT_OVF.CLU1[0x299]=0xfff
CLU_TX_PORT_OVF.CLU2[0x299]=0x7f
CLU_TX_QMLF_CONFIG.CLU0[0x289]=0
CLU_TX_QMLF_CONFIG.CLU1[0x289]=0
CLU_TX_QMLF_CONFIG.CLU2[0x289]=0xf000000000000
CLU_TX_TMC_RATE_LIMITER_LEVEL.CLU0[0x29b]=0
CLU_TX_TMC_RATE_LIMITER_LEVEL.CLU1[0x29b]=0
CLU_TX_TMC_RATE_LIMITER_LEVEL.CLU2[0x29b]=0
CLU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY.CLU0[0x29d]=0
CLU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY.CLU1[0x29d]=0
CLU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY.CLU2[0x29d]=0
CLU_TX_TOTAL_BYTE_COUNTER.CLU0[0x486]=0xfd4c6737e70
CLU_TX_TOTAL_BYTE_COUNTER.CLU1[0x486]=0x8a386a0
CLU_TX_TOTAL_BYTE_COUNTER.CLU2[0x486]=0x25ced4bc7ad
CLU_TX_TOTAL_BYTE_WITH_ERR_COUNTER.CLU0[0x491]=0
CLU_TX_TOTAL_BYTE_WITH_ERR_COUNTER.CLU1[0x491]=0
CLU_TX_TOTAL_BYTE_WITH_ERR_COUNTER.CLU2[0x491]=0
CLU_TX_TOTAL_ERR_ON_SOP_BYTE_COUNTER.CLU0[0x48c]=0
CLU_TX_TOTAL_ERR_ON_SOP_BYTE_COUNTER.CLU1[0x48c]=0
CLU_TX_TOTAL_ERR_ON_SOP_BYTE_COUNTER.CLU2[0x48c]=0
CLU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER.CLU0[0x48a]=0
CLU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER.CLU1[0x48a]=0
CLU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER.CLU2[0x48a]=0
CLU_TX_TOTAL_PKT_COUNTER.CLU0[0x484]=0x34929e517
CLU_TX_TOTAL_PKT_COUNTER.CLU1[0x484]=0x6a818
CLU_TX_TOTAL_PKT_COUNTER.CLU2[0x484]=0x1948390e6
CLU_TX_TOTAL_PKT_WITH_ERR_COUNTER.CLU0[0x490]=0
CLU_TX_TOTAL_PKT_WITH_ERR_COUNTER.CLU1[0x490]=0
CLU_TX_TOTAL_PKT_WITH_ERR_COUNTER.CLU2[0x490]=0
CLU_TX_WRONG_PORT_FROM_EGQ_QMLF.CLU0[0x294]=0
CLU_TX_WRONG_PORT_FROM_EGQ_QMLF.CLU1[0x294]=0
CLU_TX_WRONG_PORT_FROM_EGQ_QMLF.CLU2[0x294]=0
CLU_UNIT_LOW_RMC_EN_IS_ALL_MASKED.CLU0[0x627]=0
CLU_UNIT_LOW_RMC_EN_IS_ALL_MASKED.CLU1[0x627]=0
CLU_UNIT_LOW_RMC_EN_IS_ALL_MASKED.CLU2[0x627]=0
CMIC_CMC0_CCMDMA_CH0_CFG.CMIC0[0x3418]=0
CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_HI.CMIC0[0x3424]=0
CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_LO.CMIC0[0x3420]=0
CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_HI.CMIC0[0x342c]=0
CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_LO.CMIC0[0x3428]=0
CMIC_CMC0_CCMDMA_CH0_ECC_CONTROL.CMIC0[0x3430]=0
CMIC_CMC0_CCMDMA_CH0_ECC_STATUS.CMIC0[0x3434]=0
CMIC_CMC0_CCMDMA_CH0_ECC_STATUS_CLR.CMIC0[0x3438]=0
CMIC_CMC0_CCMDMA_CH0_ENTRY_COUNT.CMIC0[0x3414]=0
CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI.CMIC0[0x3408]=0
CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO.CMIC0[0x3404]=0
CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI.CMIC0[0x3410]=0
CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO.CMIC0[0x340c]=0
CMIC_CMC0_CCMDMA_CH0_STAT.CMIC0[0x341c]=0
CMIC_CMC0_CCMDMA_CH0_TM_CONTROL.CMIC0[0x343c]=0
CMIC_CMC0_CCMDMA_CH1_CFG.CMIC0[0x3498]=0
CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_HI.CMIC0[0x34a4]=0
CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_LO.CMIC0[0x34a0]=0
CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_HI.CMIC0[0x34ac]=0
CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_LO.CMIC0[0x34a8]=0
CMIC_CMC0_CCMDMA_CH1_ECC_CONTROL.CMIC0[0x34b0]=0
CMIC_CMC0_CCMDMA_CH1_ECC_STATUS.CMIC0[0x34b4]=0
CMIC_CMC0_CCMDMA_CH1_ECC_STATUS_CLR.CMIC0[0x34b8]=0
CMIC_CMC0_CCMDMA_CH1_ENTRY_COUNT.CMIC0[0x3494]=0
CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI.CMIC0[0x3488]=0
CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO.CMIC0[0x3484]=0
CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI.CMIC0[0x3490]=0
CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO.CMIC0[0x348c]=0
CMIC_CMC0_CCMDMA_CH1_STAT.CMIC0[0x349c]=0
CMIC_CMC0_CCMDMA_CH1_TM_CONTROL.CMIC0[0x34bc]=0
CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0.CMIC0[0x2118]=0
CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1.CMIC0[0x211c]=0
CMIC_CMC0_PKTDMA_CH0_CTRL.CMIC0[0x2100]=1
CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HI.CMIC0[0x2128]=0x10000000
CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LO.CMIC0[0x2124]=0xc06eeb20
CMIC_CMC0_PKTDMA_CH0_DEBUG_CONTROL.CMIC0[0x2130]=0x3f
CMIC_CMC0_PKTDMA_CH0_DEBUG_SM_STATUS.CMIC0[0x2134]=1
CMIC_CMC0_PKTDMA_CH0_DEBUG_STATUS.CMIC0[0x2138]=0
CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI.CMIC0[0x2108]=0x10000000
CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO.CMIC0[0x2104]=0xc06eeb00
CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_REQ.CMIC0[0x2148]=0x33e7f2cf
CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_RX.CMIC0[0x214c]=0x33e7f2cf
CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_STATUS_WR.CMIC0[0x2150]=0x33e7f2cf
CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI.CMIC0[0x2110]=0
CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO.CMIC0[0x210c]=0
CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_CONTROL.CMIC0[0x2158]=0
CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_STATUS.CMIC0[0x2154]=0
CMIC_CMC0_PKTDMA_CH0_DESC_MEM_TM_CONTROL.CMIC0[0x215c]=0
CMIC_CMC0_PKTDMA_CH0_INTR_COAL.CMIC0[0x2120]=0
CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT.CMIC0[0x213c]=0
CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP.CMIC0[0x2144]=0
CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKT.CMIC0[0x2140]=0x1a0bfa89
CMIC_CMC0_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG.CMIC0[0x212c]=0x110
CMIC_CMC0_PKTDMA_CH0_STAT.CMIC0[0x2114]=0
CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0.CMIC0[0x2198]=0x3ff03
CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1.CMIC0[0x219c]=0
CMIC_CMC0_PKTDMA_CH1_CTRL.CMIC0[0x2180]=2
CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HI.CMIC0[0x21a8]=0x10000000
CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LO.CMIC0[0x21a4]=0xc0733cf0
CMIC_CMC0_PKTDMA_CH1_DEBUG_CONTROL.CMIC0[0x21b0]=0x3f
CMIC_CMC0_PKTDMA_CH1_DEBUG_SM_STATUS.CMIC0[0x21b4]=0x40
CMIC_CMC0_PKTDMA_CH1_DEBUG_STATUS.CMIC0[0x21b8]=0xc
CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HI.CMIC0[0x2188]=0x10000000
CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LO.CMIC0[0x2184]=0xc0733c00
CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_REQ.CMIC0[0x21c8]=0x1d827284
CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_RX.CMIC0[0x21cc]=0x1d827284
CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_STATUS_WR.CMIC0[0x21d0]=0x1d827277
CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HI.CMIC0[0x2190]=0
CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LO.CMIC0[0x218c]=0
CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_CONTROL.CMIC0[0x21d8]=0
CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_STATUS.CMIC0[0x21d4]=0
CMIC_CMC0_PKTDMA_CH1_DESC_MEM_TM_CONTROL.CMIC0[0x21dc]=0
CMIC_CMC0_PKTDMA_CH1_INTR_COAL.CMIC0[0x21a0]=0
CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT.CMIC0[0x21bc]=0x1d827277
CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP.CMIC0[0x21c4]=0
CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKT.CMIC0[0x21c0]=0
CMIC_CMC0_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG.CMIC0[0x21ac]=0x110
CMIC_CMC0_PKTDMA_CH1_STAT.CMIC0[0x2194]=2
CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0.CMIC0[0x2218]=0x3000000
CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1.CMIC0[0x221c]=0
CMIC_CMC0_PKTDMA_CH2_CTRL.CMIC0[0x2200]=2
CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HI.CMIC0[0x2228]=0x10000000
CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LO.CMIC0[0x2224]=0xc07322f0
CMIC_CMC0_PKTDMA_CH2_DEBUG_CONTROL.CMIC0[0x2230]=0x3f
CMIC_CMC0_PKTDMA_CH2_DEBUG_SM_STATUS.CMIC0[0x2234]=0x40
CMIC_CMC0_PKTDMA_CH2_DEBUG_STATUS.CMIC0[0x2238]=0xe
CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HI.CMIC0[0x2208]=0x10000000
CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LO.CMIC0[0x2204]=0xc0732200
CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_REQ.CMIC0[0x2248]=0xf
CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_RX.CMIC0[0x224c]=0xf
CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_STATUS_WR.CMIC0[0x2250]=0
CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HI.CMIC0[0x2210]=0
CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LO.CMIC0[0x220c]=0
CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_CONTROL.CMIC0[0x2258]=0
CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_STATUS.CMIC0[0x2254]=0
CMIC_CMC0_PKTDMA_CH2_DESC_MEM_TM_CONTROL.CMIC0[0x225c]=0
CMIC_CMC0_PKTDMA_CH2_INTR_COAL.CMIC0[0x2220]=0
CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT.CMIC0[0x223c]=0
CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP.CMIC0[0x2244]=0
CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKT.CMIC0[0x2240]=0
CMIC_CMC0_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG.CMIC0[0x222c]=0x110
CMIC_CMC0_PKTDMA_CH2_STAT.CMIC0[0x2214]=2
CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0.CMIC0[0x2298]=0
CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1.CMIC0[0x229c]=0
CMIC_CMC0_PKTDMA_CH3_CTRL.CMIC0[0x2280]=0
CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HI.CMIC0[0x22a8]=0
CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LO.CMIC0[0x22a4]=0
CMIC_CMC0_PKTDMA_CH3_DEBUG_CONTROL.CMIC0[0x22b0]=0x3f
CMIC_CMC0_PKTDMA_CH3_DEBUG_SM_STATUS.CMIC0[0x22b4]=1
CMIC_CMC0_PKTDMA_CH3_DEBUG_STATUS.CMIC0[0x22b8]=0
CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HI.CMIC0[0x2288]=0
CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LO.CMIC0[0x2284]=0
CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_REQ.CMIC0[0x22c8]=0
CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_RX.CMIC0[0x22cc]=0
CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_STATUS_WR.CMIC0[0x22d0]=0
CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HI.CMIC0[0x2290]=0
CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LO.CMIC0[0x228c]=0
CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_CONTROL.CMIC0[0x22d8]=0
CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_STATUS.CMIC0[0x22d4]=0
CMIC_CMC0_PKTDMA_CH3_DESC_MEM_TM_CONTROL.CMIC0[0x22dc]=0
CMIC_CMC0_PKTDMA_CH3_INTR_COAL.CMIC0[0x22a0]=0
CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT.CMIC0[0x22bc]=0
CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP.CMIC0[0x22c4]=0
CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKT.CMIC0[0x22c0]=0
CMIC_CMC0_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG.CMIC0[0x22ac]=0x110
CMIC_CMC0_PKTDMA_CH3_STAT.CMIC0[0x2294]=0
CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0.CMIC0[0x2318]=0
CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1.CMIC0[0x231c]=0
CMIC_CMC0_PKTDMA_CH4_CTRL.CMIC0[0x2300]=0
CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HI.CMIC0[0x2328]=0
CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LO.CMIC0[0x2324]=0
CMIC_CMC0_PKTDMA_CH4_DEBUG_CONTROL.CMIC0[0x2330]=0x3f
CMIC_CMC0_PKTDMA_CH4_DEBUG_SM_STATUS.CMIC0[0x2334]=1
CMIC_CMC0_PKTDMA_CH4_DEBUG_STATUS.CMIC0[0x2338]=0
CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HI.CMIC0[0x2308]=0
CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LO.CMIC0[0x2304]=0
CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_REQ.CMIC0[0x2348]=0
CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_RX.CMIC0[0x234c]=0
CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_STATUS_WR.CMIC0[0x2350]=0
CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HI.CMIC0[0x2310]=0
CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LO.CMIC0[0x230c]=0
CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_CONTROL.CMIC0[0x2358]=0
CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_STATUS.CMIC0[0x2354]=0
CMIC_CMC0_PKTDMA_CH4_DESC_MEM_TM_CONTROL.CMIC0[0x235c]=0
CMIC_CMC0_PKTDMA_CH4_INTR_COAL.CMIC0[0x2320]=0
CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT.CMIC0[0x233c]=0
CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP.CMIC0[0x2344]=0
CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKT.CMIC0[0x2340]=0
CMIC_CMC0_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG.CMIC0[0x232c]=0x110
CMIC_CMC0_PKTDMA_CH4_STAT.CMIC0[0x2314]=0
CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0.CMIC0[0x2398]=0
CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1.CMIC0[0x239c]=0
CMIC_CMC0_PKTDMA_CH5_CTRL.CMIC0[0x2380]=0
CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HI.CMIC0[0x23a8]=0
CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LO.CMIC0[0x23a4]=0
CMIC_CMC0_PKTDMA_CH5_DEBUG_CONTROL.CMIC0[0x23b0]=0x3f
CMIC_CMC0_PKTDMA_CH5_DEBUG_SM_STATUS.CMIC0[0x23b4]=1
CMIC_CMC0_PKTDMA_CH5_DEBUG_STATUS.CMIC0[0x23b8]=0
CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HI.CMIC0[0x2388]=0
CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LO.CMIC0[0x2384]=0
CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_REQ.CMIC0[0x23c8]=0
CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_RX.CMIC0[0x23cc]=0
CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_STATUS_WR.CMIC0[0x23d0]=0
CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HI.CMIC0[0x2390]=0
CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LO.CMIC0[0x238c]=0
CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_CONTROL.CMIC0[0x23d8]=0
CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_STATUS.CMIC0[0x23d4]=0
CMIC_CMC0_PKTDMA_CH5_DESC_MEM_TM_CONTROL.CMIC0[0x23dc]=0
CMIC_CMC0_PKTDMA_CH5_INTR_COAL.CMIC0[0x23a0]=0
CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT.CMIC0[0x23bc]=0
CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP.CMIC0[0x23c4]=0
CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKT.CMIC0[0x23c0]=0
CMIC_CMC0_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG.CMIC0[0x23ac]=0x110
CMIC_CMC0_PKTDMA_CH5_STAT.CMIC0[0x2394]=0
CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0.CMIC0[0x2418]=0
CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1.CMIC0[0x241c]=0
CMIC_CMC0_PKTDMA_CH6_CTRL.CMIC0[0x2400]=0
CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HI.CMIC0[0x2428]=0
CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LO.CMIC0[0x2424]=0
CMIC_CMC0_PKTDMA_CH6_DEBUG_CONTROL.CMIC0[0x2430]=0x3f
CMIC_CMC0_PKTDMA_CH6_DEBUG_SM_STATUS.CMIC0[0x2434]=1
CMIC_CMC0_PKTDMA_CH6_DEBUG_STATUS.CMIC0[0x2438]=0
CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HI.CMIC0[0x2408]=0
CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LO.CMIC0[0x2404]=0
CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_REQ.CMIC0[0x2448]=0
CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_RX.CMIC0[0x244c]=0
CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_STATUS_WR.CMIC0[0x2450]=0
CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HI.CMIC0[0x2410]=0
CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LO.CMIC0[0x240c]=0
CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_CONTROL.CMIC0[0x2458]=0
CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_STATUS.CMIC0[0x2454]=0
CMIC_CMC0_PKTDMA_CH6_DESC_MEM_TM_CONTROL.CMIC0[0x245c]=0
CMIC_CMC0_PKTDMA_CH6_INTR_COAL.CMIC0[0x2420]=0
CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT.CMIC0[0x243c]=0
CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP.CMIC0[0x2444]=0
CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKT.CMIC0[0x2440]=0
CMIC_CMC0_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG.CMIC0[0x242c]=0x110
CMIC_CMC0_PKTDMA_CH6_STAT.CMIC0[0x2414]=0
CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0.CMIC0[0x2498]=0
CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1.CMIC0[0x249c]=0
CMIC_CMC0_PKTDMA_CH7_CTRL.CMIC0[0x2480]=0
CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HI.CMIC0[0x24a8]=0
CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LO.CMIC0[0x24a4]=0
CMIC_CMC0_PKTDMA_CH7_DEBUG_CONTROL.CMIC0[0x24b0]=0x3f
CMIC_CMC0_PKTDMA_CH7_DEBUG_SM_STATUS.CMIC0[0x24b4]=1
CMIC_CMC0_PKTDMA_CH7_DEBUG_STATUS.CMIC0[0x24b8]=0
CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HI.CMIC0[0x2488]=0
CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LO.CMIC0[0x2484]=0
CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_REQ.CMIC0[0x24c8]=0
CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_RX.CMIC0[0x24cc]=0
CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_STATUS_WR.CMIC0[0x24d0]=0
CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HI.CMIC0[0x2490]=0
CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LO.CMIC0[0x248c]=0
CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_CONTROL.CMIC0[0x24d8]=0
CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_STATUS.CMIC0[0x24d4]=0
CMIC_CMC0_PKTDMA_CH7_DESC_MEM_TM_CONTROL.CMIC0[0x24dc]=0
CMIC_CMC0_PKTDMA_CH7_INTR_COAL.CMIC0[0x24a0]=0
CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT.CMIC0[0x24bc]=0
CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP.CMIC0[0x24c4]=0
CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKT.CMIC0[0x24c0]=0
CMIC_CMC0_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG.CMIC0[0x24ac]=0x110
CMIC_CMC0_PKTDMA_CH7_STAT.CMIC0[0x2494]=0
CMIC_CMC0_SBUSDMA_CH0_CONTROL.CMIC0[0x3000]=0x14
CMIC_CMC0_SBUSDMA_CH0_COUNT.CMIC0[0x3008]=0x4b3
CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI.CMIC0[0x3038]=0x10000000
CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO.CMIC0[0x3034]=0xc07d7500
CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x302c]=0x10000000
CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x3028]=0xc07e6f00
CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x3050]=1
CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x304c]=0x10000000
CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3048]=0xc07e6f00
CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x3040]=0x249c2200
CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x303c]=0x220
CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x3044]=0x6000000
CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS.CMIC0[0x3030]=0x6000001
CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI.CMIC0[0x3020]=0x10000000
CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO.CMIC0[0x301c]=0xc07d7500
CMIC_CMC0_SBUSDMA_CH0_ECC_CONTROL.CMIC0[0x3064]=0
CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS.CMIC0[0x3068]=0
CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS_CLR.CMIC0[0x306c]=0
CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI.CMIC0[0x3018]=0x10000000
CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3014]=0xc0736300
CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT.CMIC0[0x3074]=1
CMIC_CMC0_SBUSDMA_CH0_OPCODE.CMIC0[0x300c]=0x26200808
CMIC_CMC0_SBUSDMA_CH0_REQUEST.CMIC0[0x3004]=0x80
CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG.CMIC0[0x3054]=0
CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR.CMIC0[0x3058]=0
CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x3060]=0
CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x305c]=0
CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS.CMIC0[0x3010]=0x4000000
CMIC_CMC0_SBUSDMA_CH0_STATUS.CMIC0[0x3024]=0
CMIC_CMC0_SBUSDMA_CH0_TIMER.CMIC0[0x3070]=0
CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL.CMIC0[0x3078]=0
CMIC_CMC0_SBUSDMA_CH1_CONTROL.CMIC0[0x3100]=0
CMIC_CMC0_SBUSDMA_CH1_COUNT.CMIC0[0x3108]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI.CMIC0[0x3138]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO.CMIC0[0x3134]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x312c]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x3128]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x3150]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x314c]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3148]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x3140]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x313c]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x3144]=0
CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS.CMIC0[0x3130]=0
CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HI.CMIC0[0x3120]=0
CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LO.CMIC0[0x311c]=0
CMIC_CMC0_SBUSDMA_CH1_ECC_CONTROL.CMIC0[0x3164]=0
CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS.CMIC0[0x3168]=0
CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS_CLR.CMIC0[0x316c]=0
CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI.CMIC0[0x3118]=0
CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3114]=0
CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT.CMIC0[0x3174]=0
CMIC_CMC0_SBUSDMA_CH1_OPCODE.CMIC0[0x310c]=0
CMIC_CMC0_SBUSDMA_CH1_REQUEST.CMIC0[0x3104]=0
CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG.CMIC0[0x3154]=0
CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR.CMIC0[0x3158]=0
CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x3160]=0
CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x315c]=0
CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS.CMIC0[0x3110]=0
CMIC_CMC0_SBUSDMA_CH1_STATUS.CMIC0[0x3124]=0
CMIC_CMC0_SBUSDMA_CH1_TIMER.CMIC0[0x3170]=0
CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL.CMIC0[0x3178]=0
CMIC_CMC0_SBUSDMA_CH2_CONTROL.CMIC0[0x3200]=0
CMIC_CMC0_SBUSDMA_CH2_COUNT.CMIC0[0x3208]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI.CMIC0[0x3238]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO.CMIC0[0x3234]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x322c]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x3228]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x3250]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x324c]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3248]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x3240]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x323c]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x3244]=0
CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS.CMIC0[0x3230]=0
CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HI.CMIC0[0x3220]=0
CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LO.CMIC0[0x321c]=0
CMIC_CMC0_SBUSDMA_CH2_ECC_CONTROL.CMIC0[0x3264]=0
CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS.CMIC0[0x3268]=0
CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS_CLR.CMIC0[0x326c]=0
CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI.CMIC0[0x3218]=0
CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3214]=0
CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT.CMIC0[0x3274]=0
CMIC_CMC0_SBUSDMA_CH2_OPCODE.CMIC0[0x320c]=0
CMIC_CMC0_SBUSDMA_CH2_REQUEST.CMIC0[0x3204]=0
CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG.CMIC0[0x3254]=0
CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR.CMIC0[0x3258]=0
CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x3260]=0
CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x325c]=0
CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS.CMIC0[0x3210]=0
CMIC_CMC0_SBUSDMA_CH2_STATUS.CMIC0[0x3224]=0
CMIC_CMC0_SBUSDMA_CH2_TIMER.CMIC0[0x3270]=0
CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL.CMIC0[0x3278]=0
CMIC_CMC0_SBUSDMA_CH3_CONTROL.CMIC0[0x3300]=0
CMIC_CMC0_SBUSDMA_CH3_COUNT.CMIC0[0x3308]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI.CMIC0[0x3338]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO.CMIC0[0x3334]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x332c]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x3328]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x3350]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x334c]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3348]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x3340]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x333c]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x3344]=0
CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESS.CMIC0[0x3330]=0
CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HI.CMIC0[0x3320]=0
CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LO.CMIC0[0x331c]=0
CMIC_CMC0_SBUSDMA_CH3_ECC_CONTROL.CMIC0[0x3364]=0
CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS.CMIC0[0x3368]=0
CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS_CLR.CMIC0[0x336c]=0
CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI.CMIC0[0x3318]=0
CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO.CMIC0[0x3314]=0
CMIC_CMC0_SBUSDMA_CH3_ITER_COUNT.CMIC0[0x3374]=0
CMIC_CMC0_SBUSDMA_CH3_OPCODE.CMIC0[0x330c]=0
CMIC_CMC0_SBUSDMA_CH3_REQUEST.CMIC0[0x3304]=0
CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG.CMIC0[0x3354]=0
CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR.CMIC0[0x3358]=0
CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x3360]=0
CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x335c]=0
CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESS.CMIC0[0x3310]=0
CMIC_CMC0_SBUSDMA_CH3_STATUS.CMIC0[0x3324]=0
CMIC_CMC0_SBUSDMA_CH3_TIMER.CMIC0[0x3370]=0
CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL.CMIC0[0x3378]=0
CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS.CMIC0[0x1064]=0
CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0x1068]=0x1ffff
CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS.CMIC0[0x105c]=0
CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0x1060]=0x1ffff
CMIC_CMC0_SHARED_AXI_AR_COUNT_SPLIT_TX.CMIC0[0x1098]=0x16f
CMIC_CMC0_SHARED_AXI_AR_COUNT_TX.CMIC0[0x1094]=0x85871315
CMIC_CMC0_SHARED_AXI_PER_ID_STAT.CMIC0[0x1080]=0
CMIC_CMC0_SHARED_AXI_STAT.CMIC0[0x107c]=0
CMIC_CMC0_SHARED_CCMDMA_READ_ARB_CTRL.CMIC0[0x1034]=0x11
CMIC_CMC0_SHARED_CCMDMA_READ_AXI_MAP_CTRL.CMIC0[0x102c]=0x2d
CMIC_CMC0_SHARED_CCMDMA_WRITE_ARB_CTRL.CMIC0[0x1038]=0x11
CMIC_CMC0_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL.CMIC0[0x1030]=0x2d
CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_CONTROL.CMIC0[0x1048]=0
CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_STATUS.CMIC0[0x1044]=0
CMIC_CMC0_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES.CMIC0[0x103c]=5
CMIC_CMC0_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES.CMIC0[0x1040]=0x20
CMIC_CMC0_SHARED_COMPLETION_BUF_TM_CONTROL.CMIC0[0x104c]=0
CMIC_CMC0_SHARED_CONFIG.CMIC0[0x1078]=0
CMIC_CMC0_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT.CMIC0[0x1004]=0x88888888
CMIC_CMC0_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT.CMIC0[0x1000]=0x208
CMIC_CMC0_SHARED_IRQ_STAT0.CMIC0[0x106c]=0
CMIC_CMC0_SHARED_IRQ_STAT1.CMIC0[0x1070]=0
CMIC_CMC0_SHARED_IRQ_STAT_CLR0.CMIC0[0x1074]=0
CMIC_CMC0_SHARED_PACKET_DMA_READ_ARB_CTRL.CMIC0[0x1014]=0xf8f8f8f8
CMIC_CMC0_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL.CMIC0[0x1008]=0x8e2860
CMIC_CMC0_SHARED_PACKET_DMA_WRITE_ARB_CTRL.CMIC0[0x1018]=0xf8f8f8f8
CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0.CMIC0[0x100c]=0x22861820
CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1.CMIC0[0x1010]=0x238e2
CMIC_CMC0_SHARED_PKT_COUNT_RXPKT.CMIC0[0x1084]=0x1d827277
CMIC_CMC0_SHARED_PKT_COUNT_RXPKT_ERR.CMIC0[0x1088]=0
CMIC_CMC0_SHARED_PKT_COUNT_TXPKT.CMIC0[0x108c]=0x1a0bfa89
CMIC_CMC0_SHARED_PKT_COUNT_TXPKT_ERR.CMIC0[0x1090]=0
CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK0.CMIC0[0x1050]=0
CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK1.CMIC0[0x1054]=0
CMIC_CMC0_SHARED_RXBUF_BLOCK_DATABUF_ALLOC.CMIC0[0x2088]=0
CMIC_CMC0_SHARED_RXBUF_CONFIG.CMIC0[0x208c]=0xf
CMIC_CMC0_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES.CMIC0[0x2080]=8
CMIC_CMC0_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES.CMIC0[0x2084]=0x100
CMIC_CMC0_SHARED_RXBUF_ECC_CONTROL.CMIC0[0x2090]=0
CMIC_CMC0_SHARED_RXBUF_ECC_STATUS.CMIC0[0x2098]=0
CMIC_CMC0_SHARED_RXBUF_ECC_STATUS_CLR.CMIC0[0x209c]=0
CMIC_CMC0_SHARED_RXBUF_THRESHOLD_CONFIG.CMIC0[0x1058]=0x180
CMIC_CMC0_SHARED_RXBUF_TM_CONTROL.CMIC0[0x2094]=0
CMIC_CMC0_SHARED_SBUS_DMA_READ_ARB_CTRL.CMIC0[0x1024]=0xf1f1f1f1
CMIC_CMC0_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL.CMIC0[0x101c]=0xd75d75
CMIC_CMC0_SHARED_SBUS_DMA_WRITE_ARB_CTRL.CMIC0[0x1028]=0x1111
CMIC_CMC0_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL.CMIC0[0x1020]=0xb6d
CMIC_CMC0_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES.CMIC0[0x2028]=6
CMIC_CMC0_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES.CMIC0[0x2024]=0x40
CMIC_CMC0_SHARED_TXBUF_DEBUG.CMIC0[0x2020]=0
CMIC_CMC0_SHARED_TXBUF_ECC_CONTROL.CMIC0[0x2034]=0
CMIC_CMC0_SHARED_TXBUF_ECC_STATUS.CMIC0[0x202c]=0
CMIC_CMC0_SHARED_TXBUF_ECC_STATUS_CLR.CMIC0[0x2030]=0
CMIC_CMC0_SHARED_TXBUF_MAX_BUF_LIMITS.CMIC0[0x2000]=0x2040810
CMIC_CMC0_SHARED_TXBUF_MIN_BUF_LIMITS.CMIC0[0x2004]=0x810204
CMIC_CMC0_SHARED_TXBUF_RD_THRESHOLD_CONFIG.CMIC0[0x2008]=0x208208
CMIC_CMC0_SHARED_TXBUF_RD_WRR_ARB_CTRL.CMIC0[0x200c]=0xeeee
CMIC_CMC0_SHARED_TXBUF_SLICE0_PKT_CNT.CMIC0[0x201c]=0x1a0bfa89
CMIC_CMC0_SHARED_TXBUF_SLICE1_PKT_CNT.CMIC0[0x2018]=0
CMIC_CMC0_SHARED_TXBUF_SLICE2_PKT_CNT.CMIC0[0x2014]=0
CMIC_CMC0_SHARED_TXBUF_SLICE3_PKT_CNT.CMIC0[0x2010]=0
CMIC_CMC0_SHARED_TXBUF_TM_CONTROL.CMIC0[0x2038]=0
CMIC_CMC1_CCMDMA_CH0_CFG.CMIC0[0x6418]=0
CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_HI.CMIC0[0x6424]=0
CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_LO.CMIC0[0x6420]=0
CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_HI.CMIC0[0x642c]=0
CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_LO.CMIC0[0x6428]=0
CMIC_CMC1_CCMDMA_CH0_ECC_CONTROL.CMIC0[0x6430]=0
CMIC_CMC1_CCMDMA_CH0_ECC_STATUS.CMIC0[0x6434]=0
CMIC_CMC1_CCMDMA_CH0_ECC_STATUS_CLR.CMIC0[0x6438]=0
CMIC_CMC1_CCMDMA_CH0_ENTRY_COUNT.CMIC0[0x6414]=0
CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI.CMIC0[0x6408]=0
CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO.CMIC0[0x6404]=0
CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI.CMIC0[0x6410]=0
CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO.CMIC0[0x640c]=0
CMIC_CMC1_CCMDMA_CH0_STAT.CMIC0[0x641c]=0
CMIC_CMC1_CCMDMA_CH0_TM_CONTROL.CMIC0[0x643c]=0
CMIC_CMC1_CCMDMA_CH1_CFG.CMIC0[0x6498]=0
CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_HI.CMIC0[0x64a4]=0
CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_LO.CMIC0[0x64a0]=0
CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_HI.CMIC0[0x64ac]=0
CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_LO.CMIC0[0x64a8]=0
CMIC_CMC1_CCMDMA_CH1_ECC_CONTROL.CMIC0[0x64b0]=0
CMIC_CMC1_CCMDMA_CH1_ECC_STATUS.CMIC0[0x64b4]=0
CMIC_CMC1_CCMDMA_CH1_ECC_STATUS_CLR.CMIC0[0x64b8]=0
CMIC_CMC1_CCMDMA_CH1_ENTRY_COUNT.CMIC0[0x6494]=0
CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI.CMIC0[0x6488]=0
CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO.CMIC0[0x6484]=0
CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI.CMIC0[0x6490]=0
CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO.CMIC0[0x648c]=0
CMIC_CMC1_CCMDMA_CH1_STAT.CMIC0[0x649c]=0
CMIC_CMC1_CCMDMA_CH1_TM_CONTROL.CMIC0[0x64bc]=0
CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0.CMIC0[0x5118]=0
CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1.CMIC0[0x511c]=0
CMIC_CMC1_PKTDMA_CH0_CTRL.CMIC0[0x5100]=0
CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HI.CMIC0[0x5128]=0
CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LO.CMIC0[0x5124]=0
CMIC_CMC1_PKTDMA_CH0_DEBUG_CONTROL.CMIC0[0x5130]=0x3f
CMIC_CMC1_PKTDMA_CH0_DEBUG_SM_STATUS.CMIC0[0x5134]=1
CMIC_CMC1_PKTDMA_CH0_DEBUG_STATUS.CMIC0[0x5138]=0
CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HI.CMIC0[0x5108]=0
CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LO.CMIC0[0x5104]=0
CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_REQ.CMIC0[0x5148]=0
CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_RX.CMIC0[0x514c]=0
CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_STATUS_WR.CMIC0[0x5150]=0
CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HI.CMIC0[0x5110]=0
CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LO.CMIC0[0x510c]=0
CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_CONTROL.CMIC0[0x5158]=0
CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_STATUS.CMIC0[0x5154]=0
CMIC_CMC1_PKTDMA_CH0_DESC_MEM_TM_CONTROL.CMIC0[0x515c]=0
CMIC_CMC1_PKTDMA_CH0_INTR_COAL.CMIC0[0x5120]=0
CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT.CMIC0[0x513c]=0
CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP.CMIC0[0x5144]=0
CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKT.CMIC0[0x5140]=0
CMIC_CMC1_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG.CMIC0[0x512c]=0x110
CMIC_CMC1_PKTDMA_CH0_STAT.CMIC0[0x5114]=0
CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0.CMIC0[0x5198]=0
CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1.CMIC0[0x519c]=0
CMIC_CMC1_PKTDMA_CH1_CTRL.CMIC0[0x5180]=0
CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HI.CMIC0[0x51a8]=0
CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LO.CMIC0[0x51a4]=0
CMIC_CMC1_PKTDMA_CH1_DEBUG_CONTROL.CMIC0[0x51b0]=0x3f
CMIC_CMC1_PKTDMA_CH1_DEBUG_SM_STATUS.CMIC0[0x51b4]=1
CMIC_CMC1_PKTDMA_CH1_DEBUG_STATUS.CMIC0[0x51b8]=0
CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HI.CMIC0[0x5188]=0
CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LO.CMIC0[0x5184]=0
CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_REQ.CMIC0[0x51c8]=0
CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_RX.CMIC0[0x51cc]=0
CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_STATUS_WR.CMIC0[0x51d0]=0
CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HI.CMIC0[0x5190]=0
CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LO.CMIC0[0x518c]=0
CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_CONTROL.CMIC0[0x51d8]=0
CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_STATUS.CMIC0[0x51d4]=0
CMIC_CMC1_PKTDMA_CH1_DESC_MEM_TM_CONTROL.CMIC0[0x51dc]=0
CMIC_CMC1_PKTDMA_CH1_INTR_COAL.CMIC0[0x51a0]=0
CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT.CMIC0[0x51bc]=0
CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP.CMIC0[0x51c4]=0
CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKT.CMIC0[0x51c0]=0
CMIC_CMC1_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG.CMIC0[0x51ac]=0x110
CMIC_CMC1_PKTDMA_CH1_STAT.CMIC0[0x5194]=0
CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0.CMIC0[0x5218]=0
CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1.CMIC0[0x521c]=0
CMIC_CMC1_PKTDMA_CH2_CTRL.CMIC0[0x5200]=0
CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HI.CMIC0[0x5228]=0
CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LO.CMIC0[0x5224]=0
CMIC_CMC1_PKTDMA_CH2_DEBUG_CONTROL.CMIC0[0x5230]=0x3f
CMIC_CMC1_PKTDMA_CH2_DEBUG_SM_STATUS.CMIC0[0x5234]=1
CMIC_CMC1_PKTDMA_CH2_DEBUG_STATUS.CMIC0[0x5238]=0
CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HI.CMIC0[0x5208]=0
CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LO.CMIC0[0x5204]=0
CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_REQ.CMIC0[0x5248]=0
CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_RX.CMIC0[0x524c]=0
CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_STATUS_WR.CMIC0[0x5250]=0
CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HI.CMIC0[0x5210]=0
CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LO.CMIC0[0x520c]=0
CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_CONTROL.CMIC0[0x5258]=0
CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_STATUS.CMIC0[0x5254]=0
CMIC_CMC1_PKTDMA_CH2_DESC_MEM_TM_CONTROL.CMIC0[0x525c]=0
CMIC_CMC1_PKTDMA_CH2_INTR_COAL.CMIC0[0x5220]=0
CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT.CMIC0[0x523c]=0
CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP.CMIC0[0x5244]=0
CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKT.CMIC0[0x5240]=0
CMIC_CMC1_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG.CMIC0[0x522c]=0x110
CMIC_CMC1_PKTDMA_CH2_STAT.CMIC0[0x5214]=0
CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0.CMIC0[0x5298]=0
CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1.CMIC0[0x529c]=0
CMIC_CMC1_PKTDMA_CH3_CTRL.CMIC0[0x5280]=0
CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HI.CMIC0[0x52a8]=0
CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LO.CMIC0[0x52a4]=0
CMIC_CMC1_PKTDMA_CH3_DEBUG_CONTROL.CMIC0[0x52b0]=0x3f
CMIC_CMC1_PKTDMA_CH3_DEBUG_SM_STATUS.CMIC0[0x52b4]=1
CMIC_CMC1_PKTDMA_CH3_DEBUG_STATUS.CMIC0[0x52b8]=0
CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HI.CMIC0[0x5288]=0
CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LO.CMIC0[0x5284]=0
CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_REQ.CMIC0[0x52c8]=0
CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_RX.CMIC0[0x52cc]=0
CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_STATUS_WR.CMIC0[0x52d0]=0
CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HI.CMIC0[0x5290]=0
CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LO.CMIC0[0x528c]=0
CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_CONTROL.CMIC0[0x52d8]=0
CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_STATUS.CMIC0[0x52d4]=0
CMIC_CMC1_PKTDMA_CH3_DESC_MEM_TM_CONTROL.CMIC0[0x52dc]=0
CMIC_CMC1_PKTDMA_CH3_INTR_COAL.CMIC0[0x52a0]=0
CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT.CMIC0[0x52bc]=0
CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP.CMIC0[0x52c4]=0
CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKT.CMIC0[0x52c0]=0
CMIC_CMC1_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG.CMIC0[0x52ac]=0x110
CMIC_CMC1_PKTDMA_CH3_STAT.CMIC0[0x5294]=0
CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0.CMIC0[0x5318]=0
CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1.CMIC0[0x531c]=0
CMIC_CMC1_PKTDMA_CH4_CTRL.CMIC0[0x5300]=0
CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HI.CMIC0[0x5328]=0
CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LO.CMIC0[0x5324]=0
CMIC_CMC1_PKTDMA_CH4_DEBUG_CONTROL.CMIC0[0x5330]=0x3f
CMIC_CMC1_PKTDMA_CH4_DEBUG_SM_STATUS.CMIC0[0x5334]=1
CMIC_CMC1_PKTDMA_CH4_DEBUG_STATUS.CMIC0[0x5338]=0
CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HI.CMIC0[0x5308]=0
CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LO.CMIC0[0x5304]=0
CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_REQ.CMIC0[0x5348]=0
CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_RX.CMIC0[0x534c]=0
CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_STATUS_WR.CMIC0[0x5350]=0
CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HI.CMIC0[0x5310]=0
CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LO.CMIC0[0x530c]=0
CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_CONTROL.CMIC0[0x5358]=0
CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_STATUS.CMIC0[0x5354]=0
CMIC_CMC1_PKTDMA_CH4_DESC_MEM_TM_CONTROL.CMIC0[0x535c]=0
CMIC_CMC1_PKTDMA_CH4_INTR_COAL.CMIC0[0x5320]=0
CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT.CMIC0[0x533c]=0
CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP.CMIC0[0x5344]=0
CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKT.CMIC0[0x5340]=0
CMIC_CMC1_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG.CMIC0[0x532c]=0x110
CMIC_CMC1_PKTDMA_CH4_STAT.CMIC0[0x5314]=0
CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0.CMIC0[0x5398]=0
CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1.CMIC0[0x539c]=0
CMIC_CMC1_PKTDMA_CH5_CTRL.CMIC0[0x5380]=0
CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HI.CMIC0[0x53a8]=0
CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LO.CMIC0[0x53a4]=0
CMIC_CMC1_PKTDMA_CH5_DEBUG_CONTROL.CMIC0[0x53b0]=0x3f
CMIC_CMC1_PKTDMA_CH5_DEBUG_SM_STATUS.CMIC0[0x53b4]=1
CMIC_CMC1_PKTDMA_CH5_DEBUG_STATUS.CMIC0[0x53b8]=0
CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HI.CMIC0[0x5388]=0
CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LO.CMIC0[0x5384]=0
CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_REQ.CMIC0[0x53c8]=0
CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_RX.CMIC0[0x53cc]=0
CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_STATUS_WR.CMIC0[0x53d0]=0
CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HI.CMIC0[0x5390]=0
CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LO.CMIC0[0x538c]=0
CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_CONTROL.CMIC0[0x53d8]=0
CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_STATUS.CMIC0[0x53d4]=0
CMIC_CMC1_PKTDMA_CH5_DESC_MEM_TM_CONTROL.CMIC0[0x53dc]=0
CMIC_CMC1_PKTDMA_CH5_INTR_COAL.CMIC0[0x53a0]=0
CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT.CMIC0[0x53bc]=0
CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP.CMIC0[0x53c4]=0
CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKT.CMIC0[0x53c0]=0
CMIC_CMC1_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG.CMIC0[0x53ac]=0x110
CMIC_CMC1_PKTDMA_CH5_STAT.CMIC0[0x5394]=0
CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0.CMIC0[0x5418]=0
CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1.CMIC0[0x541c]=0
CMIC_CMC1_PKTDMA_CH6_CTRL.CMIC0[0x5400]=0
CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HI.CMIC0[0x5428]=0
CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LO.CMIC0[0x5424]=0
CMIC_CMC1_PKTDMA_CH6_DEBUG_CONTROL.CMIC0[0x5430]=0x3f
CMIC_CMC1_PKTDMA_CH6_DEBUG_SM_STATUS.CMIC0[0x5434]=1
CMIC_CMC1_PKTDMA_CH6_DEBUG_STATUS.CMIC0[0x5438]=0
CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HI.CMIC0[0x5408]=0
CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LO.CMIC0[0x5404]=0
CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_REQ.CMIC0[0x5448]=0
CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_RX.CMIC0[0x544c]=0
CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_STATUS_WR.CMIC0[0x5450]=0
CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HI.CMIC0[0x5410]=0
CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LO.CMIC0[0x540c]=0
CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_CONTROL.CMIC0[0x5458]=0
CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_STATUS.CMIC0[0x5454]=0
CMIC_CMC1_PKTDMA_CH6_DESC_MEM_TM_CONTROL.CMIC0[0x545c]=0
CMIC_CMC1_PKTDMA_CH6_INTR_COAL.CMIC0[0x5420]=0
CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT.CMIC0[0x543c]=0
CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP.CMIC0[0x5444]=0
CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKT.CMIC0[0x5440]=0
CMIC_CMC1_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG.CMIC0[0x542c]=0x110
CMIC_CMC1_PKTDMA_CH6_STAT.CMIC0[0x5414]=0
CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0.CMIC0[0x5498]=0
CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1.CMIC0[0x549c]=0
CMIC_CMC1_PKTDMA_CH7_CTRL.CMIC0[0x5480]=0
CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HI.CMIC0[0x54a8]=0
CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LO.CMIC0[0x54a4]=0
CMIC_CMC1_PKTDMA_CH7_DEBUG_CONTROL.CMIC0[0x54b0]=0x3f
CMIC_CMC1_PKTDMA_CH7_DEBUG_SM_STATUS.CMIC0[0x54b4]=1
CMIC_CMC1_PKTDMA_CH7_DEBUG_STATUS.CMIC0[0x54b8]=0
CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HI.CMIC0[0x5488]=0
CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LO.CMIC0[0x5484]=0
CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_REQ.CMIC0[0x54c8]=0
CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_RX.CMIC0[0x54cc]=0
CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_STATUS_WR.CMIC0[0x54d0]=0
CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HI.CMIC0[0x5490]=0
CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LO.CMIC0[0x548c]=0
CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_CONTROL.CMIC0[0x54d8]=0
CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_STATUS.CMIC0[0x54d4]=0
CMIC_CMC1_PKTDMA_CH7_DESC_MEM_TM_CONTROL.CMIC0[0x54dc]=0
CMIC_CMC1_PKTDMA_CH7_INTR_COAL.CMIC0[0x54a0]=0
CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT.CMIC0[0x54bc]=0
CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP.CMIC0[0x54c4]=0
CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKT.CMIC0[0x54c0]=0
CMIC_CMC1_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG.CMIC0[0x54ac]=0x110
CMIC_CMC1_PKTDMA_CH7_STAT.CMIC0[0x5494]=0
CMIC_CMC1_SBUSDMA_CH0_CONTROL.CMIC0[0x6000]=0
CMIC_CMC1_SBUSDMA_CH0_COUNT.CMIC0[0x6008]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI.CMIC0[0x6038]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO.CMIC0[0x6034]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x602c]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x6028]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x6050]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x604c]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6048]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x6040]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x603c]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x6044]=0
CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS.CMIC0[0x6030]=0
CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HI.CMIC0[0x6020]=0
CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LO.CMIC0[0x601c]=0
CMIC_CMC1_SBUSDMA_CH0_ECC_CONTROL.CMIC0[0x6064]=0
CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS.CMIC0[0x6068]=0
CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS_CLR.CMIC0[0x606c]=0
CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI.CMIC0[0x6018]=0
CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6014]=0
CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT.CMIC0[0x6074]=0
CMIC_CMC1_SBUSDMA_CH0_OPCODE.CMIC0[0x600c]=0
CMIC_CMC1_SBUSDMA_CH0_REQUEST.CMIC0[0x6004]=0
CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG.CMIC0[0x6054]=0
CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR.CMIC0[0x6058]=0
CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x6060]=0
CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x605c]=0
CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS.CMIC0[0x6010]=0
CMIC_CMC1_SBUSDMA_CH0_STATUS.CMIC0[0x6024]=0
CMIC_CMC1_SBUSDMA_CH0_TIMER.CMIC0[0x6070]=0
CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL.CMIC0[0x6078]=0
CMIC_CMC1_SBUSDMA_CH1_CONTROL.CMIC0[0x6100]=0
CMIC_CMC1_SBUSDMA_CH1_COUNT.CMIC0[0x6108]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI.CMIC0[0x6138]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO.CMIC0[0x6134]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x612c]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x6128]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x6150]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x614c]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6148]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x6140]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x613c]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x6144]=0
CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS.CMIC0[0x6130]=0
CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HI.CMIC0[0x6120]=0
CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LO.CMIC0[0x611c]=0
CMIC_CMC1_SBUSDMA_CH1_ECC_CONTROL.CMIC0[0x6164]=0
CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS.CMIC0[0x6168]=0
CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS_CLR.CMIC0[0x616c]=0
CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI.CMIC0[0x6118]=0
CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6114]=0
CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT.CMIC0[0x6174]=0
CMIC_CMC1_SBUSDMA_CH1_OPCODE.CMIC0[0x610c]=0
CMIC_CMC1_SBUSDMA_CH1_REQUEST.CMIC0[0x6104]=0
CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG.CMIC0[0x6154]=0
CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR.CMIC0[0x6158]=0
CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x6160]=0
CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x615c]=0
CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS.CMIC0[0x6110]=0
CMIC_CMC1_SBUSDMA_CH1_STATUS.CMIC0[0x6124]=0
CMIC_CMC1_SBUSDMA_CH1_TIMER.CMIC0[0x6170]=0
CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL.CMIC0[0x6178]=0
CMIC_CMC1_SBUSDMA_CH2_CONTROL.CMIC0[0x6200]=0
CMIC_CMC1_SBUSDMA_CH2_COUNT.CMIC0[0x6208]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI.CMIC0[0x6238]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO.CMIC0[0x6234]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x622c]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x6228]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x6250]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x624c]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6248]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x6240]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x623c]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x6244]=0
CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS.CMIC0[0x6230]=0
CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HI.CMIC0[0x6220]=0
CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LO.CMIC0[0x621c]=0
CMIC_CMC1_SBUSDMA_CH2_ECC_CONTROL.CMIC0[0x6264]=0
CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS.CMIC0[0x6268]=0
CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS_CLR.CMIC0[0x626c]=0
CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI.CMIC0[0x6218]=0
CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6214]=0
CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT.CMIC0[0x6274]=0
CMIC_CMC1_SBUSDMA_CH2_OPCODE.CMIC0[0x620c]=0
CMIC_CMC1_SBUSDMA_CH2_REQUEST.CMIC0[0x6204]=0
CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG.CMIC0[0x6254]=0
CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR.CMIC0[0x6258]=0
CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x6260]=0
CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x625c]=0
CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS.CMIC0[0x6210]=0
CMIC_CMC1_SBUSDMA_CH2_STATUS.CMIC0[0x6224]=0
CMIC_CMC1_SBUSDMA_CH2_TIMER.CMIC0[0x6270]=0
CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL.CMIC0[0x6278]=0
CMIC_CMC1_SBUSDMA_CH3_CONTROL.CMIC0[0x6300]=0
CMIC_CMC1_SBUSDMA_CH3_COUNT.CMIC0[0x6308]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI.CMIC0[0x6338]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO.CMIC0[0x6334]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI.CMIC0[0x632c]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO.CMIC0[0x6328]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT.CMIC0[0x6350]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI.CMIC0[0x634c]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6348]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE.CMIC0[0x6340]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST.CMIC0[0x633c]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS.CMIC0[0x6344]=0
CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESS.CMIC0[0x6330]=0
CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HI.CMIC0[0x6320]=0
CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LO.CMIC0[0x631c]=0
CMIC_CMC1_SBUSDMA_CH3_ECC_CONTROL.CMIC0[0x6364]=0
CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS.CMIC0[0x6368]=0
CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS_CLR.CMIC0[0x636c]=0
CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI.CMIC0[0x6318]=0
CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO.CMIC0[0x6314]=0
CMIC_CMC1_SBUSDMA_CH3_ITER_COUNT.CMIC0[0x6374]=0
CMIC_CMC1_SBUSDMA_CH3_OPCODE.CMIC0[0x630c]=0
CMIC_CMC1_SBUSDMA_CH3_REQUEST.CMIC0[0x6304]=0
CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG.CMIC0[0x6354]=0
CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR.CMIC0[0x6358]=0
CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI.CMIC0[0x6360]=0
CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO.CMIC0[0x635c]=0
CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESS.CMIC0[0x6310]=0
CMIC_CMC1_SBUSDMA_CH3_STATUS.CMIC0[0x6324]=0
CMIC_CMC1_SBUSDMA_CH3_TIMER.CMIC0[0x6370]=0
CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL.CMIC0[0x6378]=0
CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS.CMIC0[0x4064]=0
CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0x4068]=0x1ffff
CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS.CMIC0[0x405c]=0
CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0x4060]=0x1ffff
CMIC_CMC1_SHARED_AXI_AR_COUNT_SPLIT_TX.CMIC0[0x4098]=0
CMIC_CMC1_SHARED_AXI_AR_COUNT_TX.CMIC0[0x4094]=0
CMIC_CMC1_SHARED_AXI_PER_ID_STAT.CMIC0[0x4080]=0
CMIC_CMC1_SHARED_AXI_STAT.CMIC0[0x407c]=0
CMIC_CMC1_SHARED_CCMDMA_READ_ARB_CTRL.CMIC0[0x4034]=0x11
CMIC_CMC1_SHARED_CCMDMA_READ_AXI_MAP_CTRL.CMIC0[0x402c]=0x2d
CMIC_CMC1_SHARED_CCMDMA_WRITE_ARB_CTRL.CMIC0[0x4038]=0x11
CMIC_CMC1_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL.CMIC0[0x4030]=0x2d
CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_CONTROL.CMIC0[0x4048]=0
CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_STATUS.CMIC0[0x4044]=0
CMIC_CMC1_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES.CMIC0[0x403c]=5
CMIC_CMC1_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES.CMIC0[0x4040]=0x20
CMIC_CMC1_SHARED_COMPLETION_BUF_TM_CONTROL.CMIC0[0x404c]=0
CMIC_CMC1_SHARED_CONFIG.CMIC0[0x4078]=0
CMIC_CMC1_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT.CMIC0[0x4004]=0x88888888
CMIC_CMC1_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT.CMIC0[0x4000]=0x208
CMIC_CMC1_SHARED_IRQ_STAT0.CMIC0[0x406c]=0
CMIC_CMC1_SHARED_IRQ_STAT1.CMIC0[0x4070]=0
CMIC_CMC1_SHARED_IRQ_STAT_CLR0.CMIC0[0x4074]=0
CMIC_CMC1_SHARED_PACKET_DMA_READ_ARB_CTRL.CMIC0[0x4014]=0xf8f8f8f8
CMIC_CMC1_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL.CMIC0[0x4008]=0x8e2860
CMIC_CMC1_SHARED_PACKET_DMA_WRITE_ARB_CTRL.CMIC0[0x4018]=0xf8f8f8f8
CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0.CMIC0[0x400c]=0x22861820
CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1.CMIC0[0x4010]=0x238e2
CMIC_CMC1_SHARED_PKT_COUNT_RXPKT.CMIC0[0x4084]=0
CMIC_CMC1_SHARED_PKT_COUNT_RXPKT_ERR.CMIC0[0x4088]=0
CMIC_CMC1_SHARED_PKT_COUNT_TXPKT.CMIC0[0x408c]=0
CMIC_CMC1_SHARED_PKT_COUNT_TXPKT_ERR.CMIC0[0x4090]=0
CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK0.CMIC0[0x4050]=0
CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK1.CMIC0[0x4054]=0
CMIC_CMC1_SHARED_RXBUF_BLOCK_DATABUF_ALLOC.CMIC0[0x5088]=0
CMIC_CMC1_SHARED_RXBUF_CONFIG.CMIC0[0x508c]=0xf
CMIC_CMC1_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES.CMIC0[0x5080]=8
CMIC_CMC1_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES.CMIC0[0x5084]=0x100
CMIC_CMC1_SHARED_RXBUF_ECC_CONTROL.CMIC0[0x5090]=0
CMIC_CMC1_SHARED_RXBUF_ECC_STATUS.CMIC0[0x5098]=0
CMIC_CMC1_SHARED_RXBUF_ECC_STATUS_CLR.CMIC0[0x509c]=0
CMIC_CMC1_SHARED_RXBUF_THRESHOLD_CONFIG.CMIC0[0x4058]=0x180
CMIC_CMC1_SHARED_RXBUF_TM_CONTROL.CMIC0[0x5094]=0
CMIC_CMC1_SHARED_SBUS_DMA_READ_ARB_CTRL.CMIC0[0x4024]=0xf1f1f1f1
CMIC_CMC1_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL.CMIC0[0x401c]=0xd75d75
CMIC_CMC1_SHARED_SBUS_DMA_WRITE_ARB_CTRL.CMIC0[0x4028]=0x1111
CMIC_CMC1_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL.CMIC0[0x4020]=0xb6d
CMIC_CMC1_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES.CMIC0[0x5028]=6
CMIC_CMC1_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES.CMIC0[0x5024]=0x40
CMIC_CMC1_SHARED_TXBUF_DEBUG.CMIC0[0x5020]=0
CMIC_CMC1_SHARED_TXBUF_ECC_CONTROL.CMIC0[0x5034]=0
CMIC_CMC1_SHARED_TXBUF_ECC_STATUS.CMIC0[0x502c]=0
CMIC_CMC1_SHARED_TXBUF_ECC_STATUS_CLR.CMIC0[0x5030]=0
CMIC_CMC1_SHARED_TXBUF_MAX_BUF_LIMITS.CMIC0[0x5000]=0x2040810
CMIC_CMC1_SHARED_TXBUF_MIN_BUF_LIMITS.CMIC0[0x5004]=0x810204
CMIC_CMC1_SHARED_TXBUF_RD_THRESHOLD_CONFIG.CMIC0[0x5008]=0x208208
CMIC_CMC1_SHARED_TXBUF_RD_WRR_ARB_CTRL.CMIC0[0x500c]=0xeeee
CMIC_CMC1_SHARED_TXBUF_SLICE0_PKT_CNT.CMIC0[0x501c]=0
CMIC_CMC1_SHARED_TXBUF_SLICE1_PKT_CNT.CMIC0[0x5018]=0
CMIC_CMC1_SHARED_TXBUF_SLICE2_PKT_CNT.CMIC0[0x5014]=0
CMIC_CMC1_SHARED_TXBUF_SLICE3_PKT_CNT.CMIC0[0x5010]=0
CMIC_CMC1_SHARED_TXBUF_TM_CONTROL.CMIC0[0x5038]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG.CMIC0[0x11000]=0x30d4353
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_1.CMIC0[0x11004]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x11048]=0x10000000
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x11044]=0xc0753e80
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x11030]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x1102c]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_CONTROL.CMIC0[0x11034]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS.CMIC0[0x11038]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS_CLR.CMIC0[0x1103c]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11010]=0x10000000
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1100c]=0xc0753e80
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1101c]=0x20
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11014]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11018]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_OPCODE.CMIC0[0x11028]=0xa8a40200
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11008]=0x13d
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT.CMIC0[0x11020]=2
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_CLR.CMIC0[0x11024]=0
CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_TM_CONTROL.CMIC0[0x11040]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG.CMIC0[0x11500]=0x88
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG_1.CMIC0[0x11504]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x11548]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x11544]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x11530]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x1152c]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_CONTROL.CMIC0[0x11534]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS.CMIC0[0x11538]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS_CLR.CMIC0[0x1153c]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11510]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1150c]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1151c]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11514]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11518]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_OPCODE.CMIC0[0x11528]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11508]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT.CMIC0[0x11520]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT_CLR.CMIC0[0x11524]=0
CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_TM_CONTROL.CMIC0[0x11540]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG.CMIC0[0x11580]=0x88
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG_1.CMIC0[0x11584]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x115c8]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x115c4]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x115b0]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x115ac]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_CONTROL.CMIC0[0x115b4]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS.CMIC0[0x115b8]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS_CLR.CMIC0[0x115bc]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11590]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1158c]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1159c]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11594]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11598]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_OPCODE.CMIC0[0x115a8]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11588]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT.CMIC0[0x115a0]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT_CLR.CMIC0[0x115a4]=0
CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_TM_CONTROL.CMIC0[0x115c0]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG.CMIC0[0x11080]=0x88
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG_1.CMIC0[0x11084]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x110c8]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x110c4]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x110b0]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x110ac]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_CONTROL.CMIC0[0x110b4]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS.CMIC0[0x110b8]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS_CLR.CMIC0[0x110bc]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11090]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1108c]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1109c]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11094]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11098]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_OPCODE.CMIC0[0x110a8]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11088]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT.CMIC0[0x110a0]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT_CLR.CMIC0[0x110a4]=0
CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_TM_CONTROL.CMIC0[0x110c0]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG.CMIC0[0x11100]=0x3fe739b
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG_1.CMIC0[0x11104]=0x310
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x11148]=0x10000000
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x11144]=0xc07a7400
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x11130]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x1112c]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_CONTROL.CMIC0[0x11134]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS.CMIC0[0x11138]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS_CLR.CMIC0[0x1113c]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11110]=0x10000000
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1110c]=0xc07a7400
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1111c]=4
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11114]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11118]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_OPCODE.CMIC0[0x11128]=0xa8aa0200
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11108]=0x154
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT.CMIC0[0x11120]=2
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT_CLR.CMIC0[0x11124]=0
CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_TM_CONTROL.CMIC0[0x11140]=0
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG.CMIC0[0x11180]=0x21a8413
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG_1.CMIC0[0x11184]=0x10
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x111c8]=0x10000000
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x111c4]=0xc06f1c70
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x111b0]=0
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x111ac]=0
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_CONTROL.CMIC0[0x111b4]=0
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS.CMIC0[0x111b8]=0
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS_CLR.CMIC0[0x111bc]=0
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11190]=0x10000000
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1118c]=0xc06f1500
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1119c]=1
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11194]=0x16b
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11198]=0xac
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_OPCODE.CMIC0[0x111a8]=0xa8800200
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11188]=0x15a
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT.CMIC0[0x111a0]=0xe
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT_CLR.CMIC0[0x111a4]=0
CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_TM_CONTROL.CMIC0[0x111c0]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG.CMIC0[0x11200]=0x88
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG_1.CMIC0[0x11204]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x11248]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x11244]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x11230]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x1122c]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_CONTROL.CMIC0[0x11234]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS.CMIC0[0x11238]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS_CLR.CMIC0[0x1123c]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11210]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1120c]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1121c]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11214]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11218]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_OPCODE.CMIC0[0x11228]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11208]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT.CMIC0[0x11220]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT_CLR.CMIC0[0x11224]=0
CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_TM_CONTROL.CMIC0[0x11240]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG.CMIC0[0x11280]=0x88
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG_1.CMIC0[0x11284]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x112c8]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x112c4]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x112b0]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x112ac]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_CONTROL.CMIC0[0x112b4]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS.CMIC0[0x112b8]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS_CLR.CMIC0[0x112bc]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11290]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1128c]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1129c]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11294]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11298]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_OPCODE.CMIC0[0x112a8]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11288]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT.CMIC0[0x112a0]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT_CLR.CMIC0[0x112a4]=0
CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_TM_CONTROL.CMIC0[0x112c0]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG.CMIC0[0x11300]=0x88
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG_1.CMIC0[0x11304]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x11348]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x11344]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x11330]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x1132c]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_CONTROL.CMIC0[0x11334]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS.CMIC0[0x11338]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS_CLR.CMIC0[0x1133c]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11310]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1130c]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1131c]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11314]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11318]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_OPCODE.CMIC0[0x11328]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11308]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT.CMIC0[0x11320]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT_CLR.CMIC0[0x11324]=0
CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_TM_CONTROL.CMIC0[0x11340]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG.CMIC0[0x11380]=0x8000009a
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG_1.CMIC0[0x11384]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x113c8]=0x10000000
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x113c4]=0xc07a6800
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x113b0]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x113ac]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_CONTROL.CMIC0[0x113b4]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS.CMIC0[0x113b8]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS_CLR.CMIC0[0x113bc]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11390]=0x10000000
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1138c]=0xc07a6800
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1139c]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11394]=0x1f
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11398]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_OPCODE.CMIC0[0x113a8]=0xa8a80200
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11388]=0x228
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT.CMIC0[0x113a0]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT_CLR.CMIC0[0x113a4]=0
CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_TM_CONTROL.CMIC0[0x113c0]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG.CMIC0[0x11400]=0x88
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG_1.CMIC0[0x11404]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x11448]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x11444]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x11430]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x1142c]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_CONTROL.CMIC0[0x11434]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS.CMIC0[0x11438]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS_CLR.CMIC0[0x1143c]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11410]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1140c]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1141c]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11414]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11418]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_OPCODE.CMIC0[0x11428]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11408]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT.CMIC0[0x11420]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT_CLR.CMIC0[0x11424]=0
CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_TM_CONTROL.CMIC0[0x11440]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG.CMIC0[0x11480]=0x88
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG_1.CMIC0[0x11484]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI.CMIC0[0x114c8]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO.CMIC0[0x114c4]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_HI.CMIC0[0x114b0]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_LO.CMIC0[0x114ac]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_CONTROL.CMIC0[0x114b4]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS.CMIC0[0x114b8]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS_CLR.CMIC0[0x114bc]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_HI.CMIC0[0x11490]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_LO.CMIC0[0x1148c]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_THRESHOLD.CMIC0[0x1149c]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM.CMIC0[0x11494]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM.CMIC0[0x11498]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_OPCODE.CMIC0[0x114a8]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_SBUS_START_ADDRESS.CMIC0[0x11488]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT.CMIC0[0x114a0]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT_CLR.CMIC0[0x114a4]=0
CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_TM_CONTROL.CMIC0[0x114c0]=0
CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT.CMIC0[0x10004]=2
CMIC_COMMON_POOL_SCHAN_CH0_CTRL.CMIC0[0x10000]=2
CMIC_COMMON_POOL_SCHAN_CH0_ERR.CMIC0[0x10008]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE0.CMIC0[0x1000c]=0x30380400
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE1.CMIC0[0x10010]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE2.CMIC0[0x10014]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE3.CMIC0[0x10018]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE4.CMIC0[0x1001c]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE5.CMIC0[0x10020]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE6.CMIC0[0x10024]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE7.CMIC0[0x10028]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE8.CMIC0[0x1002c]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE9.CMIC0[0x10030]=0x3c0078
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE10.CMIC0[0x10034]=0x1e
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE11.CMIC0[0x10038]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE12.CMIC0[0x1003c]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE13.CMIC0[0x10040]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE14.CMIC0[0x10044]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE15.CMIC0[0x10048]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE16.CMIC0[0x1004c]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE17.CMIC0[0x10050]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE18.CMIC0[0x10054]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE19.CMIC0[0x10058]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE20.CMIC0[0x1005c]=0
CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE21.CMIC0[0x10060]=0
CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNT.CMIC0[0x10104]=2
CMIC_COMMON_POOL_SCHAN_CH1_CTRL.CMIC0[0x10100]=2
CMIC_COMMON_POOL_SCHAN_CH1_ERR.CMIC0[0x10108]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE0.CMIC0[0x1010c]=0x30380400
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE1.CMIC0[0x10110]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE2.CMIC0[0x10114]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE3.CMIC0[0x10118]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE4.CMIC0[0x1011c]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE5.CMIC0[0x10120]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE6.CMIC0[0x10124]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE7.CMIC0[0x10128]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE8.CMIC0[0x1012c]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE9.CMIC0[0x10130]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE10.CMIC0[0x10134]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE11.CMIC0[0x10138]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE12.CMIC0[0x1013c]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE13.CMIC0[0x10140]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE14.CMIC0[0x10144]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE15.CMIC0[0x10148]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE16.CMIC0[0x1014c]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE17.CMIC0[0x10150]=0xf3b00940
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE18.CMIC0[0x10154]=0xbf
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE19.CMIC0[0x10158]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE20.CMIC0[0x1015c]=0
CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE21.CMIC0[0x10160]=0
CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNT.CMIC0[0x10204]=2
CMIC_COMMON_POOL_SCHAN_CH2_CTRL.CMIC0[0x10200]=2
CMIC_COMMON_POOL_SCHAN_CH2_ERR.CMIC0[0x10208]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE0.CMIC0[0x1020c]=0x30380400
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE1.CMIC0[0x10210]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE2.CMIC0[0x10214]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE3.CMIC0[0x10218]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE4.CMIC0[0x1021c]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE5.CMIC0[0x10220]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE6.CMIC0[0x10224]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE7.CMIC0[0x10228]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE8.CMIC0[0x1022c]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE9.CMIC0[0x10230]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE10.CMIC0[0x10234]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE11.CMIC0[0x10238]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE12.CMIC0[0x1023c]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE13.CMIC0[0x10240]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE14.CMIC0[0x10244]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE15.CMIC0[0x10248]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE16.CMIC0[0x1024c]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE17.CMIC0[0x10250]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE18.CMIC0[0x10254]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE19.CMIC0[0x10258]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE20.CMIC0[0x1025c]=0
CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE21.CMIC0[0x10260]=0x2900
CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNT.CMIC0[0x10304]=0
CMIC_COMMON_POOL_SCHAN_CH3_CTRL.CMIC0[0x10300]=0
CMIC_COMMON_POOL_SCHAN_CH3_ERR.CMIC0[0x10308]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE0.CMIC0[0x1030c]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE1.CMIC0[0x10310]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE2.CMIC0[0x10314]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE3.CMIC0[0x10318]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE4.CMIC0[0x1031c]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE5.CMIC0[0x10320]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE6.CMIC0[0x10324]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE7.CMIC0[0x10328]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE8.CMIC0[0x1032c]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE9.CMIC0[0x10330]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE10.CMIC0[0x10334]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE11.CMIC0[0x10338]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE12.CMIC0[0x1033c]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE13.CMIC0[0x10340]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE14.CMIC0[0x10344]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE15.CMIC0[0x10348]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE16.CMIC0[0x1034c]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE17.CMIC0[0x10350]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE18.CMIC0[0x10354]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE19.CMIC0[0x10358]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE20.CMIC0[0x1035c]=0
CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE21.CMIC0[0x10360]=0
CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNT.CMIC0[0x10404]=0
CMIC_COMMON_POOL_SCHAN_CH4_CTRL.CMIC0[0x10400]=0
CMIC_COMMON_POOL_SCHAN_CH4_ERR.CMIC0[0x10408]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE0.CMIC0[0x1040c]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE1.CMIC0[0x10410]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE2.CMIC0[0x10414]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE3.CMIC0[0x10418]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE4.CMIC0[0x1041c]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE5.CMIC0[0x10420]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE6.CMIC0[0x10424]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE7.CMIC0[0x10428]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE8.CMIC0[0x1042c]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE9.CMIC0[0x10430]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE10.CMIC0[0x10434]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE11.CMIC0[0x10438]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE12.CMIC0[0x1043c]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE13.CMIC0[0x10440]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE14.CMIC0[0x10444]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE15.CMIC0[0x10448]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE16.CMIC0[0x1044c]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE17.CMIC0[0x10450]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE18.CMIC0[0x10454]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE19.CMIC0[0x10458]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE20.CMIC0[0x1045c]=0
CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE21.CMIC0[0x10460]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY0.CMIC0[0x12100]=0xf94d2f6c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY1.CMIC0[0x12104]=0xba57ffa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY2.CMIC0[0x12108]=0xe39b7ffd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY3.CMIC0[0x1210c]=0xf2dffd8d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY4.CMIC0[0x12110]=0xdf4ed9e0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY5.CMIC0[0x12114]=0xaffde76a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY6.CMIC0[0x12118]=0xbe1fef47
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY7.CMIC0[0x1211c]=0xe771d57b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY8.CMIC0[0x12120]=0x9f5fed7c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY9.CMIC0[0x12124]=0xf6fe97f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY10.CMIC0[0x12128]=0xeadeddf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY11.CMIC0[0x1212c]=0xfbee7eaf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY12.CMIC0[0x12130]=0x97547fce
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY13.CMIC0[0x12134]=0xda757dbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY14.CMIC0[0x12138]=0xefa5fc97
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY15.CMIC0[0x1213c]=0xb78e71df
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY16.CMIC0[0x12140]=0xdfef93ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY17.CMIC0[0x12144]=0xfe99b7bf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY18.CMIC0[0x12148]=0xffafd1dd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY19.CMIC0[0x1214c]=0x1fff9f5d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY20.CMIC0[0x12150]=0xaf4eff6d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY21.CMIC0[0x12154]=0x5fe5ef7a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY22.CMIC0[0x12158]=0xbdfbfd7b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY23.CMIC0[0x1215c]=0xbaef1763
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY24.CMIC0[0x12160]=0xf8f9e7fe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY25.CMIC0[0x12164]=0x7f7436d9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY26.CMIC0[0x12168]=0x1cedbfdf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY27.CMIC0[0x1216c]=0xaff7f60f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY28.CMIC0[0x12170]=0x7e7edbd8
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY29.CMIC0[0x12174]=0x1fbdabdf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY30.CMIC0[0x12178]=0xfecb5eb7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY31.CMIC0[0x1217c]=0xdf7fab77
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY32.CMIC0[0x12180]=0xa9debbd7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY33.CMIC0[0x12184]=0x797a6ff7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY34.CMIC0[0x12188]=0xbc7b7977
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY35.CMIC0[0x1218c]=0xc6ebdf7d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY36.CMIC0[0x12190]=0xedfefbfb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY37.CMIC0[0x12194]=0x7efbbb9d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY38.CMIC0[0x12198]=0xd2db86ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY39.CMIC0[0x1219c]=0x597ddebf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY40.CMIC0[0x121a0]=0xf75bfbc7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY41.CMIC0[0x121a4]=0x65effff7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY42.CMIC0[0x121a8]=0xefbfdfcf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY43.CMIC0[0x121ac]=0x6bfe7e2a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY44.CMIC0[0x121b0]=0x77bbd5bf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY45.CMIC0[0x121b4]=0x1ed7ee3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY46.CMIC0[0x121b8]=0xfecee78a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY47.CMIC0[0x121bc]=0x74ff5133
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY48.CMIC0[0x121c0]=0xcdaf3fb3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY49.CMIC0[0x121c4]=0xedaa7aab
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY50.CMIC0[0x121c8]=0xdb28cfcc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY51.CMIC0[0x121cc]=0xf8ef9ebf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY52.CMIC0[0x121d0]=0xe823643f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY53.CMIC0[0x121d4]=0x7b5ddef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY54.CMIC0[0x121d8]=0xa25f5f65
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY55.CMIC0[0x121dc]=0x16edcef6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY56.CMIC0[0x121e0]=0xeeb7edcc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY57.CMIC0[0x121e4]=0xfb7dff78
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY58.CMIC0[0x121e8]=0xd6ddcad
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY59.CMIC0[0x121ec]=0xcf482fce
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY60.CMIC0[0x121f0]=0xea37a6fb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY61.CMIC0[0x121f4]=0x21efdfe2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY62.CMIC0[0x121f8]=0xd3ff6163
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY63.CMIC0[0x121fc]=0xebbdff62
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY64.CMIC0[0x12200]=0xbeeeeb35
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY65.CMIC0[0x12204]=0xf17bfba7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY66.CMIC0[0x12208]=0xbf69e7d5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY67.CMIC0[0x1220c]=0xc0ef9577
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY68.CMIC0[0x12210]=0x35f7fff4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY69.CMIC0[0x12214]=0x3fc6cfff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY70.CMIC0[0x12218]=0x7da597ac
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY71.CMIC0[0x1221c]=0xf8ff45b9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY72.CMIC0[0x12220]=0xb7a1df77
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY73.CMIC0[0x12224]=0xabb3c1a3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY74.CMIC0[0x12228]=0xff755b6c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY75.CMIC0[0x1222c]=0xbffd627f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY76.CMIC0[0x12230]=0x3b3bfef5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY77.CMIC0[0x12234]=0xe5cacfb2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY78.CMIC0[0x12238]=0xfed44efe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY79.CMIC0[0x1223c]=0x5c5bdd35
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY80.CMIC0[0x12240]=0xdff7fbfd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY81.CMIC0[0x12244]=0xfe76d7dd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY82.CMIC0[0x12248]=0xf7fafff2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY83.CMIC0[0x1224c]=0x4beeffe5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY84.CMIC0[0x12250]=0xfaee93f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY85.CMIC0[0x12254]=0xebd7ee3b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY86.CMIC0[0x12258]=0xb7ed3f22
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY87.CMIC0[0x1225c]=0x73fbe5be
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY88.CMIC0[0x12260]=0x73ef7df2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY89.CMIC0[0x12264]=0xd3fff04f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY90.CMIC0[0x12268]=0x2fb8efb5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY91.CMIC0[0x1226c]=0xcdfd4baa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY92.CMIC0[0x12270]=0x3abfcfed
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY93.CMIC0[0x12274]=0xfe7f3ffd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY94.CMIC0[0x12278]=0xfb7e836e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY95.CMIC0[0x1227c]=0xf67f7ed6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY96.CMIC0[0x12280]=0xbe5f8fd5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY97.CMIC0[0x12284]=0xa578fe8e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY98.CMIC0[0x12288]=0xbafa377d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY99.CMIC0[0x1228c]=0xeebaf72d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY100.CMIC0[0x12290]=0x4fd9fa76
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY101.CMIC0[0x12294]=0xf6e5fd4e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY102.CMIC0[0x12298]=0xee6abbef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY103.CMIC0[0x1229c]=0x128aff3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY104.CMIC0[0x122a0]=0x7fffd577
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY105.CMIC0[0x122a4]=0xde777b3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY106.CMIC0[0x122a8]=0x7ebeb93b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY107.CMIC0[0x122ac]=0xff7fcb5f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY108.CMIC0[0x122b0]=0xc3f0a47f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY109.CMIC0[0x122b4]=0xde7def04
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY110.CMIC0[0x122b8]=0xeeddcbbe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY111.CMIC0[0x122bc]=0x7d66dc15
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY112.CMIC0[0x122c0]=0xabdd3f73
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY113.CMIC0[0x122c4]=0x755fffa3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY114.CMIC0[0x122c8]=0xbfb7bfbb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY115.CMIC0[0x122cc]=0xbd6fe9f3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY116.CMIC0[0x122d0]=0xdff6fc95
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY117.CMIC0[0x122d4]=0xe0ee17de
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY118.CMIC0[0x122d8]=0xfe77e5bf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY119.CMIC0[0x122dc]=0xbddaff57
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY120.CMIC0[0x122e0]=0xf7eabb4e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY121.CMIC0[0x122e4]=0xff8bbeff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY122.CMIC0[0x122e8]=0xbdeefffb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY123.CMIC0[0x122ec]=0x73deff5f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY124.CMIC0[0x122f0]=0xfbf719be
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY125.CMIC0[0x122f4]=0xf8befb9e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY126.CMIC0[0x122f8]=0x6af9f6ac
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY127.CMIC0[0x122fc]=0xff5f7baf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY128.CMIC0[0x12300]=0x9efff935
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY129.CMIC0[0x12304]=0xfaf5ef4b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY130.CMIC0[0x12308]=0x6be9a7ae
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY131.CMIC0[0x1230c]=0xcf7ffc3d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY132.CMIC0[0x12310]=0x8dbfb5d7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY133.CMIC0[0x12314]=0xf72fba11
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY134.CMIC0[0x12318]=0xb7eff3ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY135.CMIC0[0x1231c]=0xffcf9cbb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY136.CMIC0[0x12320]=0x75fffbd5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY137.CMIC0[0x12324]=0xffff774f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY138.CMIC0[0x12328]=0x3d7fdafb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY139.CMIC0[0x1232c]=0xff6fe63f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY140.CMIC0[0x12330]=0xa836efff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY141.CMIC0[0x12334]=0x3fda77f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY142.CMIC0[0x12338]=0xfddb7fe9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY143.CMIC0[0x1233c]=0xd7bd4665
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY144.CMIC0[0x12340]=0xddadf7ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY145.CMIC0[0x12344]=0xb3dbcd5e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY146.CMIC0[0x12348]=0xef6ff5d6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY147.CMIC0[0x1234c]=0x61e7eda9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY148.CMIC0[0x12350]=0x629e3baf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY149.CMIC0[0x12354]=0xff9d7cfd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY150.CMIC0[0x12358]=0xe3eb2c67
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY151.CMIC0[0x1235c]=0x7e98b5aa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY152.CMIC0[0x12360]=0xaedf9767
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY153.CMIC0[0x12364]=0x9eddffd4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY154.CMIC0[0x12368]=0xa77bfbbb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY155.CMIC0[0x1236c]=0xe5bcfbed
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY156.CMIC0[0x12370]=0x6bbdcbbd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY157.CMIC0[0x12374]=0x7fcdd8ab
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY158.CMIC0[0x12378]=0x7e7e7387
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY159.CMIC0[0x1237c]=0xc9c25e7c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY160.CMIC0[0x12380]=0x2e86abff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY161.CMIC0[0x12384]=0xfa662edf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY162.CMIC0[0x12388]=0xfdcab717
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY163.CMIC0[0x1238c]=0x6ff6aebc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY164.CMIC0[0x12390]=0xf7df9dfe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY165.CMIC0[0x12394]=0x70ff70b3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY166.CMIC0[0x12398]=0xbbef39db
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY167.CMIC0[0x1239c]=0x3f7c1764
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY168.CMIC0[0x123a0]=0x7c3df57b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY169.CMIC0[0x123a4]=0xf7bffbaa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY170.CMIC0[0x123a8]=0x87cf6eff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY171.CMIC0[0x123ac]=0x6fafbfd3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY172.CMIC0[0x123b0]=0x7bb67aff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY173.CMIC0[0x123b4]=0xaff9bf77
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY174.CMIC0[0x123b8]=0xfcba6dc5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY175.CMIC0[0x123bc]=0xcf5ff75f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY176.CMIC0[0x123c0]=0xfbd899ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY177.CMIC0[0x123c4]=0xfc27eaff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY178.CMIC0[0x123c8]=0xdc77dc16
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY179.CMIC0[0x123cc]=0xedc9b9cf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY180.CMIC0[0x123d0]=0xb5cdbb2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY181.CMIC0[0x123d4]=0x9af4bebf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY182.CMIC0[0x123d8]=0xb9f5f7b3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY183.CMIC0[0x123dc]=0x797efcfd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY184.CMIC0[0x123e0]=0x1bf3fef9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY185.CMIC0[0x123e4]=0xb2fff2ad
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY186.CMIC0[0x123e8]=0xf79cbb7d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY187.CMIC0[0x123ec]=0x1ad9ddfa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY188.CMIC0[0x123f0]=0xbdaefdef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY189.CMIC0[0x123f4]=0x1fefe4eb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY190.CMIC0[0x123f8]=0xfeffb171
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY191.CMIC0[0x123fc]=0xff2318ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY192.CMIC0[0x12400]=0xb57767cb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY193.CMIC0[0x12404]=0xeb3f59da
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY194.CMIC0[0x12408]=0xff7d5dfc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY195.CMIC0[0x1240c]=0xdae40c32
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY196.CMIC0[0x12410]=0xf98a82e7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY197.CMIC0[0x12414]=0xf3ef5fbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY198.CMIC0[0x12418]=0xfb73887f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY199.CMIC0[0x1241c]=0x6bb9dfd8
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY200.CMIC0[0x12420]=0xd2e37a4a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY201.CMIC0[0x12424]=0x6a2a62cc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY202.CMIC0[0x12428]=0x6c2bbd97
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY203.CMIC0[0x1242c]=0xafbc7f7f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY204.CMIC0[0x12430]=0xfae4ddfe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY205.CMIC0[0x12434]=0x7ffeebff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY206.CMIC0[0x12438]=0xdfb9cff4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY207.CMIC0[0x1243c]=0x3d77ef37
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY208.CMIC0[0x12440]=0xf374ecff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY209.CMIC0[0x12444]=0xef57aef3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY210.CMIC0[0x12448]=0x756fefab
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY211.CMIC0[0x1244c]=0xdebff67
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY212.CMIC0[0x12450]=0xdfe7ffff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY213.CMIC0[0x12454]=0xf7d73d1a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY214.CMIC0[0x12458]=0x98f7befb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY215.CMIC0[0x1245c]=0xdd3af8cf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY216.CMIC0[0x12460]=0x79f7feff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY217.CMIC0[0x12464]=0xff7aaf7b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY218.CMIC0[0x12468]=0x77bdeffb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY219.CMIC0[0x1246c]=0x7bfdff7b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY220.CMIC0[0x12470]=0x6efbdf7f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY221.CMIC0[0x12474]=0xdf5e673e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY222.CMIC0[0x12478]=0xf3bb3794
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY223.CMIC0[0x1247c]=0xcf7d75ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY224.CMIC0[0x12480]=0xf57c9e77
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY225.CMIC0[0x12484]=0x3befcbf3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY226.CMIC0[0x12488]=0xf7bf6851
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY227.CMIC0[0x1248c]=0x8ff9ff72
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY228.CMIC0[0x12490]=0xfbf7ebef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY229.CMIC0[0x12494]=0xb32fc3f1
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY230.CMIC0[0x12498]=0x91fdb577
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY231.CMIC0[0x1249c]=0x7f8ad3db
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY232.CMIC0[0x124a0]=0xb7fcddfe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY233.CMIC0[0x124a4]=0x7c65dbeb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY234.CMIC0[0x124a8]=0xff9f9f7e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY235.CMIC0[0x124ac]=0xefd3bf2f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY236.CMIC0[0x124b0]=0xe3fd8bee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY237.CMIC0[0x124b4]=0xbeeffeef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY238.CMIC0[0x124b8]=0xfb739d1b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY239.CMIC0[0x124bc]=0xfdfdc347
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY240.CMIC0[0x124c0]=0xe3fd18df
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY241.CMIC0[0x124c4]=0x2fefdd5c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY242.CMIC0[0x124c8]=0xaffffff3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY243.CMIC0[0x124cc]=0xf7bafff7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY244.CMIC0[0x124d0]=0x4bb952ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY245.CMIC0[0x124d4]=0xf7e3af22
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY246.CMIC0[0x124d8]=0xfbacfdbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY247.CMIC0[0x124dc]=0x9f137e1f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY248.CMIC0[0x124e0]=0xb733d7e5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY249.CMIC0[0x124e4]=0xbfb5beff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY250.CMIC0[0x124e8]=0xee6fbe3d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY251.CMIC0[0x124ec]=0xdd3ef3c7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY252.CMIC0[0x124f0]=0x7f13fff7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY253.CMIC0[0x124f4]=0xe3df5a7a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY254.CMIC0[0x124f8]=0x91addfce
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY255.CMIC0[0x124fc]=0xfd4f7669
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY256.CMIC0[0x12500]=0xaff975c7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY257.CMIC0[0x12504]=0xb7f79769
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY258.CMIC0[0x12508]=0xf7f77e37
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY259.CMIC0[0x1250c]=0xdae9b53f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY260.CMIC0[0x12510]=0xaffbd7fb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY261.CMIC0[0x12514]=0xcdfbbf65
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY262.CMIC0[0x12518]=0xbf7ed3ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY263.CMIC0[0x1251c]=0x387d37cf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY264.CMIC0[0x12520]=0x1be3bfdb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY265.CMIC0[0x12524]=0x814bebbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY266.CMIC0[0x12528]=0xcb7c7273
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY267.CMIC0[0x1252c]=0x70559d4f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY268.CMIC0[0x12530]=0x3be7eee4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY269.CMIC0[0x12534]=0xdfb8adbc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY270.CMIC0[0x12538]=0xd35ffaff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY271.CMIC0[0x1253c]=0xff6b5cbb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY272.CMIC0[0x12540]=0xd89eea3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY273.CMIC0[0x12544]=0xcf76ebe0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY274.CMIC0[0x12548]=0xb3169b2d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY275.CMIC0[0x1254c]=0xee78ff6d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY276.CMIC0[0x12550]=0x9f7ebf7f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY277.CMIC0[0x12554]=0xc97cfb3b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY278.CMIC0[0x12558]=0x7fa77dfa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY279.CMIC0[0x1255c]=0x1fb2df7a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY280.CMIC0[0x12560]=0xb3bdd6fd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY281.CMIC0[0x12564]=0xe9bdffd5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY282.CMIC0[0x12568]=0xfb4c7bed
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY283.CMIC0[0x1256c]=0xbef9b9ba
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY284.CMIC0[0x12570]=0xbee77f77
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY285.CMIC0[0x12574]=0xf37dcfff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY286.CMIC0[0x12578]=0x7e33597f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY287.CMIC0[0x1257c]=0xfff6f0e1
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY288.CMIC0[0x12580]=0xfbf7bfe2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY289.CMIC0[0x12584]=0x866f9bff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY290.CMIC0[0x12588]=0xfa76fef7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY291.CMIC0[0x1258c]=0x3b2175de
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY292.CMIC0[0x12590]=0x2f1b61ec
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY293.CMIC0[0x12594]=0x968ff777
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY294.CMIC0[0x12598]=0x6dffe2ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY295.CMIC0[0x1259c]=0xebefbfe9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY296.CMIC0[0x125a0]=0x3ec2bdff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY297.CMIC0[0x125a4]=0xb9f7eff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY298.CMIC0[0x125a8]=0xff958fb8
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY299.CMIC0[0x125ac]=0xf957ab7f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY300.CMIC0[0x125b0]=0xbabd7fce
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY301.CMIC0[0x125b4]=0xde7fe7fe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY302.CMIC0[0x125b8]=0xeff4f7ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY303.CMIC0[0x125bc]=0xfb885e6c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY304.CMIC0[0x125c0]=0x35fbab4d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY305.CMIC0[0x125c4]=0xf717eea9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY306.CMIC0[0x125c8]=0x6abeacdf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY307.CMIC0[0x125cc]=0xef2973a7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY308.CMIC0[0x125d0]=0x6d632ebc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY309.CMIC0[0x125d4]=0x5fcdbfd9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY310.CMIC0[0x125d8]=0x7fefbfdd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY311.CMIC0[0x125dc]=0x744e772f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY312.CMIC0[0x125e0]=0xeef16b47
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY313.CMIC0[0x125e4]=0xb4dbf9db
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY314.CMIC0[0x125e8]=0xbfdbede7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY315.CMIC0[0x125ec]=0x7e16de78
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY316.CMIC0[0x125f0]=0xdfef93cc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY317.CMIC0[0x125f4]=0x37bdef73
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY318.CMIC0[0x125f8]=0x9a6d35f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY319.CMIC0[0x125fc]=0xfbbdcea7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY320.CMIC0[0x12600]=0xe7d6f7bc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY321.CMIC0[0x12604]=0xfbdbb2cf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY322.CMIC0[0x12608]=0x7ffe7efe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY323.CMIC0[0x1260c]=0xcfdabfdc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY324.CMIC0[0x12610]=0x3dd53fda
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY325.CMIC0[0x12614]=0xf67dece3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY326.CMIC0[0x12618]=0x75fcfb56
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY327.CMIC0[0x1261c]=0x86efddef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY328.CMIC0[0x12620]=0xe9dcffab
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY329.CMIC0[0x12624]=0xff6fcd78
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY330.CMIC0[0x12628]=0xc778e7d7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY331.CMIC0[0x1262c]=0x6aedf3dd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY332.CMIC0[0x12630]=0xf77cf2c4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY333.CMIC0[0x12634]=0x699fe8fe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY334.CMIC0[0x12638]=0x1c6eb99f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY335.CMIC0[0x1263c]=0x95e4da2c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY336.CMIC0[0x12640]=0xa7fb7ddf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY337.CMIC0[0x12644]=0xf7c97fdf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY338.CMIC0[0x12648]=0xbb6f97df
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY339.CMIC0[0x1264c]=0xfd9c9b9d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY340.CMIC0[0x12650]=0xabffabbd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY341.CMIC0[0x12654]=0xd7bebc5e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY342.CMIC0[0x12658]=0xfabef4be
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY343.CMIC0[0x1265c]=0xbc9c5ffd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY344.CMIC0[0x12660]=0x7736afff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY345.CMIC0[0x12664]=0xf7df2b6b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY346.CMIC0[0x12668]=0xcebd37f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY347.CMIC0[0x1266c]=0xfb7fd49e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY348.CMIC0[0x12670]=0xeedffcaf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY349.CMIC0[0x12674]=0xfcffdbee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY350.CMIC0[0x12678]=0xf9fede64
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY351.CMIC0[0x1267c]=0xad2b77fe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_CTRL.CMIC0[0x1200c]=0x105000
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_LOWER.CMIC0[0x12014]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_UPPER.CMIC0[0x12010]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_STATUS.CMIC0[0x12020]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_LOWER.CMIC0[0x1201c]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_UPPER.CMIC0[0x12018]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY0.CMIC0[0x12680]=0xebdbcd63
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY1.CMIC0[0x12684]=0xffbeddd6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY2.CMIC0[0x12688]=0x6f3ffffe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY3.CMIC0[0x1268c]=0x3cf7b7aa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY4.CMIC0[0x12690]=0x2d32ebdf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY5.CMIC0[0x12694]=0xacf3777c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY6.CMIC0[0x12698]=0x7fb773d3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY7.CMIC0[0x1269c]=0xbc6de7ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY8.CMIC0[0x126a0]=0xb77baefd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY9.CMIC0[0x126a4]=0x7f8ddbf7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY10.CMIC0[0x126a8]=0xfeef7eee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY11.CMIC0[0x126ac]=0x93fb59f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY12.CMIC0[0x126b0]=0xcfb6fad7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY13.CMIC0[0x126b4]=0xf5f38dcb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY14.CMIC0[0x126b8]=0x2fadfd95
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY15.CMIC0[0x126bc]=0xd3ef7d85
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY16.CMIC0[0x126c0]=0xe9ddff7d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY17.CMIC0[0x126c4]=0xfc2f6b82
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY18.CMIC0[0x126c8]=0xbaef7fa8
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY19.CMIC0[0x126cc]=0x9bdf7b9e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY20.CMIC0[0x126d0]=0xdbffeb6f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY21.CMIC0[0x126d4]=0xdffa0cda
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY22.CMIC0[0x126d8]=0xa77efdda
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY23.CMIC0[0x126dc]=0xcf5dee5f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY24.CMIC0[0x126e0]=0x7fdf5fca
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY25.CMIC0[0x126e4]=0xff5f9e5d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY26.CMIC0[0x126e8]=0xef6c3df4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY27.CMIC0[0x126ec]=0x5fff59c7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY28.CMIC0[0x126f0]=0xebfadaf1
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY29.CMIC0[0x126f4]=0xa5dc26de
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY30.CMIC0[0x126f8]=0xecffb98d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY31.CMIC0[0x126fc]=0xe36572ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY32.CMIC0[0x12700]=0xbfeeefe5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY33.CMIC0[0x12704]=0xf79fb7b1
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY34.CMIC0[0x12708]=0xf3ed8ee7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY35.CMIC0[0x1270c]=0xafdafbb3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY36.CMIC0[0x12710]=0x9bfc6cba
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY37.CMIC0[0x12714]=0x97e66dde
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY38.CMIC0[0x12718]=0xfd729bd7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY39.CMIC0[0x1271c]=0xbf7f7cc3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY40.CMIC0[0x12720]=0xd43bc8ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY41.CMIC0[0x12724]=0xfdfeb65d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY42.CMIC0[0x12728]=0xed3b3f9e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY43.CMIC0[0x1272c]=0xdef7ef9b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY44.CMIC0[0x12730]=0xbd575ddf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY45.CMIC0[0x12734]=0xbeefb95f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY46.CMIC0[0x12738]=0xdf7aebef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY47.CMIC0[0x1273c]=0xdffed9cf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY48.CMIC0[0x12740]=0x37fdeafe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY49.CMIC0[0x12744]=0x9ffcafef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY50.CMIC0[0x12748]=0xfe453ff2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY51.CMIC0[0x1274c]=0xe47bdafd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY52.CMIC0[0x12750]=0xbf76f794
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY53.CMIC0[0x12754]=0xd927e3f3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY54.CMIC0[0x12758]=0xfa729269
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY55.CMIC0[0x1275c]=0x9847e5e7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY56.CMIC0[0x12760]=0xa97ae5ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY57.CMIC0[0x12764]=0x573913ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY58.CMIC0[0x12768]=0xe7c9fd3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY59.CMIC0[0x1276c]=0xffdeb9db
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY60.CMIC0[0x12770]=0xb7faf6f2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY61.CMIC0[0x12774]=0xfadfd24f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY62.CMIC0[0x12778]=0x7dfff2ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY63.CMIC0[0x1277c]=0x5af0ddb6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY64.CMIC0[0x12780]=0x7fefbfad
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY65.CMIC0[0x12784]=0xfc23ff73
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY66.CMIC0[0x12788]=0xffbdfd75
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY67.CMIC0[0x1278c]=0xeffffa15
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY68.CMIC0[0x12790]=0xdefb9fbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY69.CMIC0[0x12794]=0xfffe75f3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY70.CMIC0[0x12798]=0xefecf1b6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY71.CMIC0[0x1279c]=0x9ecd877f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY72.CMIC0[0x127a0]=0xdbfb2cec
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY73.CMIC0[0x127a4]=0xddfb6fe2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY74.CMIC0[0x127a8]=0xa5df6fae
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY75.CMIC0[0x127ac]=0x5f77e2f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY76.CMIC0[0x127b0]=0xfef57c96
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY77.CMIC0[0x127b4]=0xabfebfff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY78.CMIC0[0x127b8]=0x766dde1e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY79.CMIC0[0x127bc]=0xe5ff7a87
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY80.CMIC0[0x127c0]=0x33dffceb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY81.CMIC0[0x127c4]=0x7ee7f5bc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY82.CMIC0[0x127c8]=0xf361b3bf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY83.CMIC0[0x127cc]=0xafad7fbb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY84.CMIC0[0x127d0]=0x57c7df2e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY85.CMIC0[0x127d4]=0xf4cffe7f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY86.CMIC0[0x127d8]=0x7ef286e7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY87.CMIC0[0x127dc]=0xbdf775c6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY88.CMIC0[0x127e0]=0xd3fdf9fb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY89.CMIC0[0x127e4]=0x3ef7fd3c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY90.CMIC0[0x127e8]=0xbb9f5fff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY91.CMIC0[0x127ec]=0xfbbe21f6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY92.CMIC0[0x127f0]=0xde22e6f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY93.CMIC0[0x127f4]=0xdfff477b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY94.CMIC0[0x127f8]=0xeeff7f1e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY95.CMIC0[0x127fc]=0xf9ff3eb5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY96.CMIC0[0x12800]=0xe797a7fb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY97.CMIC0[0x12804]=0x912e8f95
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY98.CMIC0[0x12808]=0xf79d7cbc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY99.CMIC0[0x1280c]=0x31dfdfe4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY100.CMIC0[0x12810]=0x4b6ff1bf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY101.CMIC0[0x12814]=0xfdf6e82f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY102.CMIC0[0x12818]=0xdcddfcfd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY103.CMIC0[0x1281c]=0x99eeda3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY104.CMIC0[0x12820]=0xf7ce357e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY105.CMIC0[0x12824]=0xc679eef6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY106.CMIC0[0x12828]=0x9a6f7fdb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY107.CMIC0[0x1282c]=0x5ffbffe7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY108.CMIC0[0x12830]=0xbede38db
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY109.CMIC0[0x12834]=0xa5fe5cf0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY110.CMIC0[0x12838]=0xf5e7dff9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY111.CMIC0[0x1283c]=0xbbc81b42
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY112.CMIC0[0x12840]=0x77ffd9e8
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY113.CMIC0[0x12844]=0x7efbe677
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY114.CMIC0[0x12848]=0x2bffd3fd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY115.CMIC0[0x1284c]=0x2f1ff87e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY116.CMIC0[0x12850]=0xf6fbbff5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY117.CMIC0[0x12854]=0xf2fefbf6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY118.CMIC0[0x12858]=0xffeb27f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY119.CMIC0[0x1285c]=0x2f8bef6f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY120.CMIC0[0x12860]=0xa43bf7ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY121.CMIC0[0x12864]=0x3ccedf7e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY122.CMIC0[0x12868]=0xc6beb736
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY123.CMIC0[0x1286c]=0x6979cd3c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY124.CMIC0[0x12870]=0xf536bdf7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY125.CMIC0[0x12874]=0xbf7bfff7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY126.CMIC0[0x12878]=0xc67deb89
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY127.CMIC0[0x1287c]=0x19fb7235
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY128.CMIC0[0x12880]=0xbfbb0dff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY129.CMIC0[0x12884]=0x3d3c651d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY130.CMIC0[0x12888]=0x778ee6bb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY131.CMIC0[0x1288c]=0x7988e3ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY132.CMIC0[0x12890]=0x39f776ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY133.CMIC0[0x12894]=0x7f392b07
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY134.CMIC0[0x12898]=0xfd6fefef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY135.CMIC0[0x1289c]=0x4ed6e95f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY136.CMIC0[0x128a0]=0xf7bb75db
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY137.CMIC0[0x128a4]=0xeda9bfee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY138.CMIC0[0x128a8]=0xfd2bffeb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY139.CMIC0[0x128ac]=0xe92eced0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY140.CMIC0[0x128b0]=0x5f9fb25e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY141.CMIC0[0x128b4]=0x179ffae5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY142.CMIC0[0x128b8]=0x5f7ffa79
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY143.CMIC0[0x128bc]=0xce3bdb06
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY144.CMIC0[0x128c0]=0xee6e2e7c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY145.CMIC0[0x128c4]=0xbfdaf7fc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY146.CMIC0[0x128c8]=0xfb5fbeef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY147.CMIC0[0x128cc]=0xb92357fa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY148.CMIC0[0x128d0]=0x6977adf6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY149.CMIC0[0x128d4]=0xe774939e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY150.CMIC0[0x128d8]=0x7fbfe3df
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY151.CMIC0[0x128dc]=0xc7d9f93f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY152.CMIC0[0x128e0]=0x6df933ed
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY153.CMIC0[0x128e4]=0x5efcdf2f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY154.CMIC0[0x128e8]=0xffdbfbf9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY155.CMIC0[0x128ec]=0x7d7456fd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY156.CMIC0[0x128f0]=0x8f7f37f9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY157.CMIC0[0x128f4]=0xf7bf51ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY158.CMIC0[0x128f8]=0x3eb32d0e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY159.CMIC0[0x128fc]=0x6d6fb7fe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY160.CMIC0[0x12900]=0x971b5db7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY161.CMIC0[0x12904]=0xdfffffbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY162.CMIC0[0x12908]=0xfaffdf8f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY163.CMIC0[0x1290c]=0xf3dc4457
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY164.CMIC0[0x12910]=0xdbff5a7e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY165.CMIC0[0x12914]=0xf69ff2e0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY166.CMIC0[0x12918]=0x7d8fa8ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY167.CMIC0[0x1291c]=0x62df21ec
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY168.CMIC0[0x12920]=0x7a78b3ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY169.CMIC0[0x12924]=0xb6f7b4ae
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY170.CMIC0[0x12928]=0xdeffde3b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY171.CMIC0[0x1292c]=0xffb38b21
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY172.CMIC0[0x12930]=0xd9f6eefb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY173.CMIC0[0x12934]=0xcfaf1fb7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY174.CMIC0[0x12938]=0x5fef9ff2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY175.CMIC0[0x1293c]=0x1deffcfd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY176.CMIC0[0x12940]=0xbfff5bde
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY177.CMIC0[0x12944]=0x9adfeeee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY178.CMIC0[0x12948]=0x3ededffc
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY179.CMIC0[0x1294c]=0xd3681e66
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY180.CMIC0[0x12950]=0x7e5fc9de
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY181.CMIC0[0x12954]=0x56baaf7f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY182.CMIC0[0x12958]=0x7c4f9fd4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY183.CMIC0[0x1295c]=0xc99ff7ae
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY184.CMIC0[0x12960]=0xfbdbedf6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY185.CMIC0[0x12964]=0xc2e5fd6f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY186.CMIC0[0x12968]=0x5f6ff7da
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY187.CMIC0[0x1296c]=0x9ef63dde
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY188.CMIC0[0x12970]=0x3faffffe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY189.CMIC0[0x12974]=0xdfeff354
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY190.CMIC0[0x12978]=0xddafdfda
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY191.CMIC0[0x1297c]=0x9f3fd5ed
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY192.CMIC0[0x12980]=0xf54dbf6d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY193.CMIC0[0x12984]=0x47fd97fd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY194.CMIC0[0x12988]=0x7ba3fffe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY195.CMIC0[0x1298c]=0x8edffdd9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY196.CMIC0[0x12990]=0xff45f3d3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY197.CMIC0[0x12994]=0xddde7ef7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY198.CMIC0[0x12998]=0x9bb91d6a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY199.CMIC0[0x1299c]=0xfbcff1fe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY200.CMIC0[0x129a0]=0x7a5ebbae
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY201.CMIC0[0x129a4]=0xec79ec7f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY202.CMIC0[0x129a8]=0x7f1cc8be
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY203.CMIC0[0x129ac]=0xb9d96b3d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY204.CMIC0[0x129b0]=0xef677f6c
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY205.CMIC0[0x129b4]=0xb77e6af8
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY206.CMIC0[0x129b8]=0x39f458a2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY207.CMIC0[0x129bc]=0xafc7dd37
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY208.CMIC0[0x129c0]=0xbd7edfcd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY209.CMIC0[0x129c4]=0x5eb677ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY210.CMIC0[0x129c8]=0xb7fff6ea
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY211.CMIC0[0x129cc]=0x35c2736f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY212.CMIC0[0x129d0]=0xff6fc6f5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY213.CMIC0[0x129d4]=0xaf8ec697
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY214.CMIC0[0x129d8]=0x7f0d6ee6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY215.CMIC0[0x129dc]=0xfd3e7f59
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY216.CMIC0[0x129e0]=0xfcc6cfd0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY217.CMIC0[0x129e4]=0xde3deeee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY218.CMIC0[0x129e8]=0x6737fcbb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY219.CMIC0[0x129ec]=0xf6d7b2ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY220.CMIC0[0x129f0]=0x7377e3ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY221.CMIC0[0x129f4]=0xb9d9cbbe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY222.CMIC0[0x129f8]=0xbbff79b7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY223.CMIC0[0x129fc]=0xadfdf966
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY224.CMIC0[0x12a00]=0xea3efde6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY225.CMIC0[0x12a04]=0xd1f978e1
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY226.CMIC0[0x12a08]=0xffe3fffb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY227.CMIC0[0x12a0c]=0x35adf257
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY228.CMIC0[0x12a10]=0xea3379bd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY229.CMIC0[0x12a14]=0xbdbdffdd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY230.CMIC0[0x12a18]=0x5bcfcf4e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY231.CMIC0[0x12a1c]=0x155873ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY232.CMIC0[0x12a20]=0x3efd7df2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY233.CMIC0[0x12a24]=0xded87dfd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY234.CMIC0[0x12a28]=0xfa6bff3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY235.CMIC0[0x12a2c]=0xb81efff7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY236.CMIC0[0x12a30]=0x89ffffdf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY237.CMIC0[0x12a34]=0xddcfdf4d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY238.CMIC0[0x12a38]=0x7fdefcbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY239.CMIC0[0x12a3c]=0x7f36f9ee
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY240.CMIC0[0x12a40]=0x9abecf67
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY241.CMIC0[0x12a44]=0x2aeee64f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY242.CMIC0[0x12a48]=0xeb3befdd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY243.CMIC0[0x12a4c]=0x5f7df3ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY244.CMIC0[0x12a50]=0xafcf9edf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY245.CMIC0[0x12a54]=0xf62ffdfe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY246.CMIC0[0x12a58]=0x767ffddd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY247.CMIC0[0x12a5c]=0xfaebb987
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY248.CMIC0[0x12a60]=0x27fe43ef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY249.CMIC0[0x12a64]=0xcadef71d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY250.CMIC0[0x12a68]=0xcebf7fef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY251.CMIC0[0x12a6c]=0xec7f5ad9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY252.CMIC0[0x12a70]=0xfb7fee3e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY253.CMIC0[0x12a74]=0xffbc3fbe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY254.CMIC0[0x12a78]=0xc9e3aff4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY255.CMIC0[0x12a7c]=0x77f5d879
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY256.CMIC0[0x12a80]=0xbb59fdea
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY257.CMIC0[0x12a84]=0xc2c2ebbb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY258.CMIC0[0x12a88]=0x6ff6d6ce
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY259.CMIC0[0x12a8c]=0xa7a6591d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY260.CMIC0[0x12a90]=0x9aedfde9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY261.CMIC0[0x12a94]=0xe7be973d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY262.CMIC0[0x12a98]=0xb93ffb7e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY263.CMIC0[0x12a9c]=0xed6f7fd2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY264.CMIC0[0x12aa0]=0x6ef83be5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY265.CMIC0[0x12aa4]=0xb577e097
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY266.CMIC0[0x12aa8]=0x7765ed6e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY267.CMIC0[0x12aac]=0xd7ec6bc7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY268.CMIC0[0x12ab0]=0xdfffeddf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY269.CMIC0[0x12ab4]=0x977bd29f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY270.CMIC0[0x12ab8]=0x7f3ff2b9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY271.CMIC0[0x12abc]=0xf6dfc9ab
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY272.CMIC0[0x12ac0]=0x37ffdf3f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY273.CMIC0[0x12ac4]=0x3b537f8b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY274.CMIC0[0x12ac8]=0x6efccfbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY275.CMIC0[0x12acc]=0x51f77fef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY276.CMIC0[0x12ad0]=0x613699e5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY277.CMIC0[0x12ad4]=0x2fd77fe9
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY278.CMIC0[0x12ad8]=0x99feff2f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY279.CMIC0[0x12adc]=0xd39fef67
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY280.CMIC0[0x12ae0]=0xfbfd8764
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY281.CMIC0[0x12ae4]=0x19ffedbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY282.CMIC0[0x12ae8]=0x69e7ddaf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY283.CMIC0[0x12aec]=0xf26d73f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY284.CMIC0[0x12af0]=0xfab3ff55
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY285.CMIC0[0x12af4]=0x12f7ecfb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY286.CMIC0[0x12af8]=0xf93ff6ad
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY287.CMIC0[0x12afc]=0xb0fddb7b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY288.CMIC0[0x12b00]=0xefbfef6f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY289.CMIC0[0x12b04]=0xbce1f7d5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY290.CMIC0[0x12b08]=0xeb3dfceb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY291.CMIC0[0x12b0c]=0x68fb9bdb
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY292.CMIC0[0x12b10]=0xbc3bbdff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY293.CMIC0[0x12b14]=0x6f7df8db
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY294.CMIC0[0x12b18]=0xfd7ee37b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY295.CMIC0[0x12b1c]=0x41d5e786
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY296.CMIC0[0x12b20]=0xe3dfeb7d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY297.CMIC0[0x12b24]=0xe126f3bf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY298.CMIC0[0x12b28]=0xaf156e77
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY299.CMIC0[0x12b2c]=0x5dfbe7f3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY300.CMIC0[0x12b30]=0xf6bb7dff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY301.CMIC0[0x12b34]=0xfadfefd7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY302.CMIC0[0x12b38]=0xfeaa59ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY303.CMIC0[0x12b3c]=0xef7dd7ed
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY304.CMIC0[0x12b40]=0x9bef56f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY305.CMIC0[0x12b44]=0x6e8eee46
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY306.CMIC0[0x12b48]=0x3b7f7a53
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY307.CMIC0[0x12b4c]=0xfc4dfa8e
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY308.CMIC0[0x12b50]=0xd676e2e3
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY309.CMIC0[0x12b54]=0x1a93fcbe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY310.CMIC0[0x12b58]=0xd3f3396a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY311.CMIC0[0x12b5c]=0xceaf7b95
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY312.CMIC0[0x12b60]=0xf4e91e71
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY313.CMIC0[0x12b64]=0x7dffffbd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY314.CMIC0[0x12b68]=0xf9fff96d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY315.CMIC0[0x12b6c]=0x88fefff5
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY316.CMIC0[0x12b70]=0xdd7ed9f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY317.CMIC0[0x12b74]=0xf0b46be6
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY318.CMIC0[0x12b78]=0xc3bf821f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY319.CMIC0[0x12b7c]=0x1a5d7f72
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY320.CMIC0[0x12b80]=0x353feb9a
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY321.CMIC0[0x12b84]=0xff5afff0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY322.CMIC0[0x12b88]=0x8d3f05ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY323.CMIC0[0x12b8c]=0x70ff37ab
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY324.CMIC0[0x12b90]=0xbdfeb5ce
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY325.CMIC0[0x12b94]=0xff7febe8
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY326.CMIC0[0x12b98]=0x68a7ddff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY327.CMIC0[0x12b9c]=0xfdcfab71
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY328.CMIC0[0x12ba0]=0xbdbbd9d4
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY329.CMIC0[0x12ba4]=0xeffbbf13
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY330.CMIC0[0x12ba8]=0xddee7f7d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY331.CMIC0[0x12bac]=0xd7adfe5d
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY332.CMIC0[0x12bb0]=0x93eefb4b
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY333.CMIC0[0x12bb4]=0xbafb5b6f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY334.CMIC0[0x12bb8]=0x707e6de7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY335.CMIC0[0x12bbc]=0x57cfc2fa
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY336.CMIC0[0x12bc0]=0x3d457f8f
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY337.CMIC0[0x12bc4]=0x1bf7eedd
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY338.CMIC0[0x12bc8]=0xac32d1ac
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY339.CMIC0[0x12bcc]=0x55326f7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY340.CMIC0[0x12bd0]=0xbfe699ff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY341.CMIC0[0x12bd4]=0xee95ea54
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY342.CMIC0[0x12bd8]=0xeffb3dbf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY343.CMIC0[0x12bdc]=0x7bafecb2
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY344.CMIC0[0x12be0]=0xf944ecef
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY345.CMIC0[0x12be4]=0xbeff7cf7
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY346.CMIC0[0x12be8]=0xd8fd5afe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY347.CMIC0[0x12bec]=0xea7ee5bf
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY348.CMIC0[0x12bf0]=0xbaffce33
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY349.CMIC0[0x12bf4]=0xaf9fafff
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY350.CMIC0[0x12bf8]=0xf4effbfe
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY351.CMIC0[0x12bfc]=0xbfe6f797
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_CTRL.CMIC0[0x12024]=0x105000
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_LOWER.CMIC0[0x1202c]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_UPPER.CMIC0[0x12028]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_STATUS.CMIC0[0x12038]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_LOWER.CMIC0[0x12034]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_UPPER.CMIC0[0x12030]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_CTRL.CMIC0[0x12000]=0
CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_STATUS.CMIC0[0x12004]=0x27
CMIC_COMMON_POOL_SCHAN_FIFO_0_TM_CTRL.CMIC0[0x12008]=0
CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS.CMIC0[0xd018]=0x1000
CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0xd01c]=0x1fff
CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS.CMIC0[0xd010]=0x1000
CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0xd014]=0x1fff
CMIC_COMMON_POOL_SHARED_CONFIG.CMIC0[0xd024]=0
CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_ARB_CTRL.CMIC0[0xd008]=0xeee
CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL.CMIC0[0xd000]=0x36db6db6
CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL_1.CMIC0[0xd004]=0x36
CMIC_COMMON_POOL_SHARED_IRQ_STAT0.CMIC0[0xd020]=0x187008
CMIC_COMMON_POOL_SHARED_SCHAN_FIFO_WRITE_ARB_CTRL.CMIC0[0xd00c]=2
CMIC_IPROC_TO_RCPU_IRQ_ENABLE0.CMIC0[0x16218]=0
CMIC_IPROC_TO_RCPU_IRQ_ENABLE1.CMIC0[0x1621c]=0
CMIC_IPROC_TO_RCPU_IRQ_ENABLE2.CMIC0[0x16220]=0
CMIC_IPROC_TO_RCPU_IRQ_ENABLE3.CMIC0[0x16224]=0
CMIC_IPROC_TO_RCPU_IRQ_ENABLE4.CMIC0[0x16228]=0
CMIC_IPROC_TO_RCPU_IRQ_ENABLE5.CMIC0[0x1622c]=0
CMIC_IPROC_TO_RCPU_IRQ_ENABLE6.CMIC0[0x16230]=0
CMIC_IPROC_TO_RCPU_IRQ_ENABLE7.CMIC0[0x16234]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT0.CMIC0[0x161f8]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT1.CMIC0[0x161fc]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT2.CMIC0[0x16200]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT3.CMIC0[0x16204]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT4.CMIC0[0x16208]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT5.CMIC0[0x1620c]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT6.CMIC0[0x16210]=0
CMIC_IPROC_TO_RCPU_IRQ_STAT7.CMIC0[0x16214]=0x187008
CMIC_REG_00040004.CMIC0[0x40004]=0
CMIC_REG_00040040.CMIC0[0x40040]=0x29
CMIC_REG_0004003C.CMIC0[0x4003c]=0
CMIC_RPE_1BIT_ECC_ERROR_STATUS.CMIC0[0x16194]=0
CMIC_RPE_1BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0x16198]=0x1f
CMIC_RPE_2BIT_ECC_ERROR_STATUS.CMIC0[0x1618c]=0
CMIC_RPE_2BIT_ECC_ERROR_STATUS_ENABLE.CMIC0[0x16190]=0x1f
CMIC_RPE_AXI_AR_COUNT_SPLIT_TX.CMIC0[0x161f4]=0
CMIC_RPE_AXI_AR_COUNT_TX.CMIC0[0x161f0]=0
CMIC_RPE_AXI_STAT.CMIC0[0x16274]=0
CMIC_RPE_COMPLETION_BUF_ECC_CONTROL.CMIC0[0x1626c]=0
CMIC_RPE_COMPLETION_BUF_ECC_STATUS.CMIC0[0x16268]=0
CMIC_RPE_COMPLETION_BUF_MAX_FLIST_ENTRIES.CMIC0[0x16260]=3
CMIC_RPE_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES.CMIC0[0x16264]=8
CMIC_RPE_COMPLETION_BUF_TM_CONTROL.CMIC0[0x16270]=0
CMIC_RPE_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT.CMIC0[0x1625c]=0x88
CMIC_RPE_INTR_PKT_PACING_DELAY.CMIC0[0x16178]=0xfffffff
CMIC_RPE_IRQ_STAT.CMIC0[0x16184]=0
CMIC_RPE_IRQ_STAT_CLR.CMIC0[0x16188]=0
CMIC_RPE_PIO_MEMDMA_COS_0.CMIC0[0x1612c]=0
CMIC_RPE_PIO_MEMDMA_COS_1.CMIC0[0x16130]=0
CMIC_RPE_PIO_MEMDMA_MEM_ECC_CONTROL.CMIC0[0x16250]=0
CMIC_RPE_PIO_MEMDMA_MEM_ECC_STATUS.CMIC0[0x16258]=0
CMIC_RPE_PIO_MEMDMA_MEM_TM_CONTROL.CMIC0[0x16254]=0
CMIC_RPE_PIO_MEMDMA_RXBUF_THRESHOLD_CONFIG.CMIC0[0x1623c]=0x12a
CMIC_RPE_PKTDMA_COS_0.CMIC0[0x1611c]=0
CMIC_RPE_PKTDMA_COS_1.CMIC0[0x16120]=0
CMIC_RPE_PKTDMA_RXBUF_THRESHOLD_CONFIG.CMIC0[0x16238]=0x12a
CMIC_RPE_PKT_COS_QUEUES_HI.CMIC0[0x1617c]=0
CMIC_RPE_PKT_COS_QUEUES_LO.CMIC0[0x16180]=0
CMIC_RPE_PKT_COUNT_FROMCPU.CMIC0[0x161a8]=0
CMIC_RPE_PKT_COUNT_FROMCPU_MH.CMIC0[0x161a4]=0
CMIC_RPE_PKT_COUNT_INTR.CMIC0[0x161d4]=0
CMIC_RPE_PKT_COUNT_MEMDMA.CMIC0[0x161d0]=0
CMIC_RPE_PKT_COUNT_MEMDMA_REPLY.CMIC0[0x161cc]=0
CMIC_RPE_PKT_COUNT_PIO.CMIC0[0x161c0]=0
CMIC_RPE_PKT_COUNT_PIO_MEMDMA_DROP.CMIC0[0x161dc]=0
CMIC_RPE_PKT_COUNT_PIO_REPLY.CMIC0[0x161bc]=0
CMIC_RPE_PKT_COUNT_RXPKT.CMIC0[0x161e0]=0
CMIC_RPE_PKT_COUNT_RXPKT_ERR.CMIC0[0x161e4]=0
CMIC_RPE_PKT_COUNT_SBUSDMA.CMIC0[0x161c8]=0
CMIC_RPE_PKT_COUNT_SBUSDMA_REPLY.CMIC0[0x161c4]=0
CMIC_RPE_PKT_COUNT_SCHAN.CMIC0[0x1619c]=0
CMIC_RPE_PKT_COUNT_SCHAN_REP.CMIC0[0x161a0]=0
CMIC_RPE_PKT_COUNT_SCHAN_SBUSDMA_DROP.CMIC0[0x161d8]=0
CMIC_RPE_PKT_COUNT_TOCPUD.CMIC0[0x161b0]=0
CMIC_RPE_PKT_COUNT_TOCPUDM.CMIC0[0x161ac]=0
CMIC_RPE_PKT_COUNT_TOCPUE.CMIC0[0x161b8]=0
CMIC_RPE_PKT_COUNT_TOCPUEM.CMIC0[0x161b4]=0
CMIC_RPE_PKT_COUNT_TXPKT.CMIC0[0x161e8]=0
CMIC_RPE_PKT_COUNT_TXPKT_ERR.CMIC0[0x161ec]=0
CMIC_RPE_PKT_CTRL.CMIC0[0x16100]=0
CMIC_RPE_PKT_ETHER_SIG.CMIC0[0x16118]=0
CMIC_RPE_PKT_LMAC0_HI.CMIC0[0x16104]=0
CMIC_RPE_PKT_LMAC0_LO.CMIC0[0x16108]=0
CMIC_RPE_PKT_LMAC1_HI.CMIC0[0x1610c]=0
CMIC_RPE_PKT_LMAC1_LO.CMIC0[0x16110]=0
CMIC_RPE_PKT_PORTS_0.CMIC0[0x16140]=0
CMIC_RPE_PKT_PORTS_1.CMIC0[0x16144]=0
CMIC_RPE_PKT_PORTS_2.CMIC0[0x16148]=0
CMIC_RPE_PKT_PORTS_3.CMIC0[0x1614c]=0
CMIC_RPE_PKT_PORTS_4.CMIC0[0x16150]=0
CMIC_RPE_PKT_PORTS_5.CMIC0[0x16154]=0
CMIC_RPE_PKT_PORTS_6.CMIC0[0x16158]=0
CMIC_RPE_PKT_PORTS_7.CMIC0[0x1615c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_0.CMIC0[0x16000]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_1.CMIC0[0x16004]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_2.CMIC0[0x16008]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_3.CMIC0[0x1600c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_4.CMIC0[0x16010]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_5.CMIC0[0x16014]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_6.CMIC0[0x16018]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_7.CMIC0[0x1601c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_8.CMIC0[0x16020]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_9.CMIC0[0x16024]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_10.CMIC0[0x16028]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_11.CMIC0[0x1602c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_12.CMIC0[0x16030]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_13.CMIC0[0x16034]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_14.CMIC0[0x16038]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_15.CMIC0[0x1603c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_16.CMIC0[0x16040]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_17.CMIC0[0x16044]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_18.CMIC0[0x16048]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_19.CMIC0[0x1604c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_20.CMIC0[0x16050]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_21.CMIC0[0x16054]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_22.CMIC0[0x16058]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_23.CMIC0[0x1605c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_24.CMIC0[0x16060]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_25.CMIC0[0x16064]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_26.CMIC0[0x16068]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_27.CMIC0[0x1606c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_28.CMIC0[0x16070]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_29.CMIC0[0x16074]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_30.CMIC0[0x16078]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_31.CMIC0[0x1607c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_32.CMIC0[0x16080]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_33.CMIC0[0x16084]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_34.CMIC0[0x16088]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_35.CMIC0[0x1608c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_36.CMIC0[0x16090]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_37.CMIC0[0x16094]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_38.CMIC0[0x16098]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_39.CMIC0[0x1609c]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_40.CMIC0[0x160a0]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_41.CMIC0[0x160a4]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_42.CMIC0[0x160a8]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_43.CMIC0[0x160ac]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_44.CMIC0[0x160b0]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_45.CMIC0[0x160b4]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_46.CMIC0[0x160b8]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_47.CMIC0[0x160bc]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_48.CMIC0[0x160c0]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_49.CMIC0[0x160c4]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_50.CMIC0[0x160c8]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_51.CMIC0[0x160cc]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_52.CMIC0[0x160d0]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_53.CMIC0[0x160d4]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_54.CMIC0[0x160d8]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_55.CMIC0[0x160dc]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_56.CMIC0[0x160e0]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_57.CMIC0[0x160e4]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_58.CMIC0[0x160e8]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_59.CMIC0[0x160ec]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_60.CMIC0[0x160f0]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_61.CMIC0[0x160f4]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_62.CMIC0[0x160f8]=0
CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_63.CMIC0[0x160fc]=0
CMIC_RPE_PKT_REASON_0_TYPE0.CMIC0[0x16500]=0
CMIC_RPE_PKT_REASON_0_TYPE1.CMIC0[0x16504]=0
CMIC_RPE_PKT_REASON_0_TYPE2.CMIC0[0x16508]=0
CMIC_RPE_PKT_REASON_0_TYPE3.CMIC0[0x1650c]=0
CMIC_RPE_PKT_REASON_0_TYPE4.CMIC0[0x16510]=0
CMIC_RPE_PKT_REASON_0_TYPE5.CMIC0[0x16514]=0
CMIC_RPE_PKT_REASON_0_TYPE6.CMIC0[0x16518]=0
CMIC_RPE_PKT_REASON_0_TYPE7.CMIC0[0x1651c]=0
CMIC_RPE_PKT_REASON_0_TYPE8.CMIC0[0x16520]=0
CMIC_RPE_PKT_REASON_0_TYPE9.CMIC0[0x16524]=0
CMIC_RPE_PKT_REASON_0_TYPE10.CMIC0[0x16528]=0
CMIC_RPE_PKT_REASON_0_TYPE11.CMIC0[0x1652c]=0
CMIC_RPE_PKT_REASON_0_TYPE12.CMIC0[0x16530]=0
CMIC_RPE_PKT_REASON_0_TYPE13.CMIC0[0x16534]=0
CMIC_RPE_PKT_REASON_0_TYPE14.CMIC0[0x16538]=0
CMIC_RPE_PKT_REASON_0_TYPE15.CMIC0[0x1653c]=0
CMIC_RPE_PKT_REASON_1_TYPE0.CMIC0[0x16540]=0
CMIC_RPE_PKT_REASON_1_TYPE1.CMIC0[0x16544]=0
CMIC_RPE_PKT_REASON_1_TYPE2.CMIC0[0x16548]=0
CMIC_RPE_PKT_REASON_1_TYPE3.CMIC0[0x1654c]=0
CMIC_RPE_PKT_REASON_1_TYPE4.CMIC0[0x16550]=0
CMIC_RPE_PKT_REASON_1_TYPE5.CMIC0[0x16554]=0
CMIC_RPE_PKT_REASON_1_TYPE6.CMIC0[0x16558]=0
CMIC_RPE_PKT_REASON_1_TYPE7.CMIC0[0x1655c]=0
CMIC_RPE_PKT_REASON_1_TYPE8.CMIC0[0x16560]=0
CMIC_RPE_PKT_REASON_1_TYPE9.CMIC0[0x16564]=0
CMIC_RPE_PKT_REASON_1_TYPE10.CMIC0[0x16568]=0
CMIC_RPE_PKT_REASON_1_TYPE11.CMIC0[0x1656c]=0
CMIC_RPE_PKT_REASON_1_TYPE12.CMIC0[0x16570]=0
CMIC_RPE_PKT_REASON_1_TYPE13.CMIC0[0x16574]=0
CMIC_RPE_PKT_REASON_1_TYPE14.CMIC0[0x16578]=0
CMIC_RPE_PKT_REASON_1_TYPE15.CMIC0[0x1657c]=0
CMIC_RPE_PKT_REASON_2_TYPE0.CMIC0[0x16680]=0
CMIC_RPE_PKT_REASON_2_TYPE1.CMIC0[0x16684]=0
CMIC_RPE_PKT_REASON_2_TYPE2.CMIC0[0x16688]=0
CMIC_RPE_PKT_REASON_2_TYPE3.CMIC0[0x1668c]=0
CMIC_RPE_PKT_REASON_2_TYPE4.CMIC0[0x16690]=0
CMIC_RPE_PKT_REASON_2_TYPE5.CMIC0[0x16694]=0
CMIC_RPE_PKT_REASON_2_TYPE6.CMIC0[0x16698]=0
CMIC_RPE_PKT_REASON_2_TYPE7.CMIC0[0x1669c]=0
CMIC_RPE_PKT_REASON_2_TYPE8.CMIC0[0x166a0]=0
CMIC_RPE_PKT_REASON_2_TYPE9.CMIC0[0x166a4]=0
CMIC_RPE_PKT_REASON_2_TYPE10.CMIC0[0x166a8]=0
CMIC_RPE_PKT_REASON_2_TYPE11.CMIC0[0x166ac]=0
CMIC_RPE_PKT_REASON_2_TYPE12.CMIC0[0x166b0]=0
CMIC_RPE_PKT_REASON_2_TYPE13.CMIC0[0x166b4]=0
CMIC_RPE_PKT_REASON_2_TYPE14.CMIC0[0x166b8]=0
CMIC_RPE_PKT_REASON_2_TYPE15.CMIC0[0x166bc]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE0.CMIC0[0x16580]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE1.CMIC0[0x16584]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE2.CMIC0[0x16588]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE3.CMIC0[0x1658c]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE4.CMIC0[0x16590]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE5.CMIC0[0x16594]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE6.CMIC0[0x16598]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE7.CMIC0[0x1659c]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE8.CMIC0[0x165a0]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE9.CMIC0[0x165a4]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE10.CMIC0[0x165a8]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE11.CMIC0[0x165ac]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE12.CMIC0[0x165b0]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE13.CMIC0[0x165b4]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE14.CMIC0[0x165b8]=0
CMIC_RPE_PKT_REASON_DIRECT_0_TYPE15.CMIC0[0x165bc]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE0.CMIC0[0x165c0]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE1.CMIC0[0x165c4]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE2.CMIC0[0x165c8]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE3.CMIC0[0x165cc]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE4.CMIC0[0x165d0]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE5.CMIC0[0x165d4]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE6.CMIC0[0x165d8]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE7.CMIC0[0x165dc]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE8.CMIC0[0x165e0]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE9.CMIC0[0x165e4]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE10.CMIC0[0x165e8]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE11.CMIC0[0x165ec]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE12.CMIC0[0x165f0]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE13.CMIC0[0x165f4]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE14.CMIC0[0x165f8]=0
CMIC_RPE_PKT_REASON_DIRECT_1_TYPE15.CMIC0[0x165fc]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE0.CMIC0[0x166c0]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE1.CMIC0[0x166c4]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE2.CMIC0[0x166c8]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE3.CMIC0[0x166cc]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE4.CMIC0[0x166d0]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE5.CMIC0[0x166d4]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE6.CMIC0[0x166d8]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE7.CMIC0[0x166dc]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE8.CMIC0[0x166e0]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE9.CMIC0[0x166e4]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE10.CMIC0[0x166e8]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE11.CMIC0[0x166ec]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE12.CMIC0[0x166f0]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE13.CMIC0[0x166f4]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE14.CMIC0[0x166f8]=0
CMIC_RPE_PKT_REASON_DIRECT_2_TYPE15.CMIC0[0x166fc]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE0.CMIC0[0x16600]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE1.CMIC0[0x16604]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE2.CMIC0[0x16608]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE3.CMIC0[0x1660c]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE4.CMIC0[0x16610]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE5.CMIC0[0x16614]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE6.CMIC0[0x16618]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE7.CMIC0[0x1661c]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE8.CMIC0[0x16620]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE9.CMIC0[0x16624]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE10.CMIC0[0x16628]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE11.CMIC0[0x1662c]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE12.CMIC0[0x16630]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE13.CMIC0[0x16634]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE14.CMIC0[0x16638]=0
CMIC_RPE_PKT_REASON_MINI_0_TYPE15.CMIC0[0x1663c]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE0.CMIC0[0x16640]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE1.CMIC0[0x16644]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE2.CMIC0[0x16648]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE3.CMIC0[0x1664c]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE4.CMIC0[0x16650]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE5.CMIC0[0x16654]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE6.CMIC0[0x16658]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE7.CMIC0[0x1665c]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE8.CMIC0[0x16660]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE9.CMIC0[0x16664]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE10.CMIC0[0x16668]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE11.CMIC0[0x1666c]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE12.CMIC0[0x16670]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE13.CMIC0[0x16674]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE14.CMIC0[0x16678]=0
CMIC_RPE_PKT_REASON_MINI_1_TYPE15.CMIC0[0x1667c]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE0.CMIC0[0x16700]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE1.CMIC0[0x16704]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE2.CMIC0[0x16708]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE3.CMIC0[0x1670c]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE4.CMIC0[0x16710]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE5.CMIC0[0x16714]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE6.CMIC0[0x16718]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE7.CMIC0[0x1671c]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE8.CMIC0[0x16720]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE9.CMIC0[0x16724]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE10.CMIC0[0x16728]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE11.CMIC0[0x1672c]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE12.CMIC0[0x16730]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE13.CMIC0[0x16734]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE14.CMIC0[0x16738]=0
CMIC_RPE_PKT_REASON_MINI_2_TYPE15.CMIC0[0x1673c]=0
CMIC_RPE_PKT_RMAC.CMIC0[0x16160]=0
CMIC_RPE_PKT_RMAC_HI.CMIC0[0x16164]=0
CMIC_RPE_PKT_RMH0.CMIC0[0x16168]=0
CMIC_RPE_PKT_RMH1.CMIC0[0x1616c]=0
CMIC_RPE_PKT_RMH2.CMIC0[0x16170]=0
CMIC_RPE_PKT_RMH3.CMIC0[0x16174]=0
CMIC_RPE_PKT_VLAN.CMIC0[0x16114]=0
CMIC_RPE_SCHAN_SBUSDMA_COS_0.CMIC0[0x16124]=0
CMIC_RPE_SCHAN_SBUSDMA_COS_1.CMIC0[0x16128]=0
CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_CONTROL.CMIC0[0x16244]=0
CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_STATUS.CMIC0[0x1624c]=0
CMIC_RPE_SCHAN_SBUSDMA_MEM_TM_CONTROL.CMIC0[0x16248]=0
CMIC_RPE_SCHAN_SBUSDMA_RXBUF_THRESHOLD_CONFIG.CMIC0[0x16240]=0x12a
CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK0.CMIC0[0x16134]=0
CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK1.CMIC0[0x16138]=0
CMIC_RPE_SHARED_RXBUF_BLOCK_DATABUF_ALLOC.CMIC0[0x16488]=0
CMIC_RPE_SHARED_RXBUF_CONFIG.CMIC0[0x1648c]=0xf
CMIC_RPE_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES.CMIC0[0x16480]=8
CMIC_RPE_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES.CMIC0[0x16484]=0x100
CMIC_RPE_SHARED_RXBUF_ECC_CONTROL.CMIC0[0x16490]=0
CMIC_RPE_SHARED_RXBUF_ECC_STATUS.CMIC0[0x16498]=0
CMIC_RPE_SHARED_RXBUF_ECC_STATUS_CLR.CMIC0[0x1649c]=0
CMIC_RPE_SHARED_RXBUF_THRESHOLD_CONFIG.CMIC0[0x1613c]=0x180
CMIC_RPE_SHARED_RXBUF_TM_CONTROL.CMIC0[0x16494]=0
CMIC_RPE_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES.CMIC0[0x16428]=6
CMIC_RPE_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES.CMIC0[0x16424]=0x40
CMIC_RPE_SHARED_TXBUF_DEBUG.CMIC0[0x16420]=0
CMIC_RPE_SHARED_TXBUF_ECC_CONTROL.CMIC0[0x16434]=0
CMIC_RPE_SHARED_TXBUF_ECC_STATUS.CMIC0[0x1642c]=0
CMIC_RPE_SHARED_TXBUF_ECC_STATUS_CLR.CMIC0[0x16430]=0
CMIC_RPE_SHARED_TXBUF_MAX_BUF_LIMITS.CMIC0[0x16400]=0x2040810
CMIC_RPE_SHARED_TXBUF_MIN_BUF_LIMITS.CMIC0[0x16404]=0x810204
CMIC_RPE_SHARED_TXBUF_RD_THRESHOLD_CONFIG.CMIC0[0x16408]=0x208208
CMIC_RPE_SHARED_TXBUF_RD_WRR_ARB_CTRL.CMIC0[0x1640c]=0xeeee
CMIC_RPE_SHARED_TXBUF_SLICE0_PKT_CNT.CMIC0[0x1641c]=0
CMIC_RPE_SHARED_TXBUF_SLICE1_PKT_CNT.CMIC0[0x16418]=0
CMIC_RPE_SHARED_TXBUF_SLICE2_PKT_CNT.CMIC0[0x16414]=0
CMIC_RPE_SHARED_TXBUF_SLICE3_PKT_CNT.CMIC0[0x16410]=0
CMIC_RPE_SHARED_TXBUF_TM_CONTROL.CMIC0[0x16438]=0
CMIC_TOP_CONFIG.CMIC0[0x8]=0x1fc
CMIC_TOP_EPINTF_BUF_DEPTH.CMIC0[0x74]=0x1000
CMIC_TOP_EPINTF_MAX_INTERFACE_CREDITS.CMIC0[0x70]=0x20
CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS.CMIC0[0x6c]=1
CMIC_TOP_EP_TO_CPU_HEADER_SIZE.CMIC0[0x4]=0
CMIC_TOP_IPINTF_BUF_DEPTH.CMIC0[0x64]=0x1000
CMIC_TOP_IPINTF_INTERFACE_CREDITS.CMIC0[0x68]=0
CMIC_TOP_IPINTF_WRR_ARB_CTRL.CMIC0[0x60]=0xeee
CMIC_TOP_PKT_COUNT_RXPKT.CMIC0[0x78]=0x1d827282
CMIC_TOP_PKT_COUNT_RXPKT_DROP.CMIC0[0x80]=0
CMIC_TOP_PKT_COUNT_RXPKT_ERR.CMIC0[0x7c]=0
CMIC_TOP_PKT_COUNT_TXPKT.CMIC0[0x84]=0x1a0bfa93
CMIC_TOP_PKT_COUNT_TXPKT_ERR.CMIC0[0x88]=0
CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA.CMIC0[0x54]=0xeeeeeeee
CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA_1.CMIC0[0x58]=0xeeee
CMIC_TOP_SBUS_RING_ARB_CTRL_RPE_SCHAN.CMIC0[0x5c]=0xe
CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA.CMIC0[0x4c]=0xeeeeeeee
CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN.CMIC0[0x50]=0xeeeeee
CMIC_TOP_SBUS_RING_MAP_0_7.CMIC0[0xc]=0x33000007
CMIC_TOP_SBUS_RING_MAP_104_111.CMIC0[0x40]=0
CMIC_TOP_SBUS_RING_MAP_112_119.CMIC0[0x44]=5
CMIC_TOP_SBUS_RING_MAP_120_127.CMIC0[0x48]=0
CMIC_TOP_SBUS_RING_MAP_16_23.CMIC0[0x14]=0x555444
CMIC_TOP_SBUS_RING_MAP_24_31.CMIC0[0x18]=0x20000000
CMIC_TOP_SBUS_RING_MAP_32_39.CMIC0[0x1c]=0x22222
CMIC_TOP_SBUS_RING_MAP_40_47.CMIC0[0x20]=0
CMIC_TOP_SBUS_RING_MAP_48_55.CMIC0[0x24]=0
CMIC_TOP_SBUS_RING_MAP_56_63.CMIC0[0x28]=0
CMIC_TOP_SBUS_RING_MAP_64_71.CMIC0[0x2c]=0x20022000
CMIC_TOP_SBUS_RING_MAP_72_79.CMIC0[0x30]=0x22222222
CMIC_TOP_SBUS_RING_MAP_80_87.CMIC0[0x34]=0
CMIC_TOP_SBUS_RING_MAP_88_95.CMIC0[0x38]=0
CMIC_TOP_SBUS_RING_MAP_8_15.CMIC0[0x10]=0x44443333
CMIC_TOP_SBUS_RING_MAP_96_103.CMIC0[0x3c]=0
CMIC_TOP_SBUS_TIMEOUT.CMIC0[0x0]=0x80befc0
CMIC_TOP_TO_MMU_COS_MASK_LSB_BITS.CMIC0[0x8c]=0xfcfc00fc
CMIC_TOP_TO_MMU_COS_MASK_MSB_BITS.CMIC0[0x90]=0xffffffff
CRPS_CONDITIONAL_TRIGGER_OCCURED_INTERRUPT_REGISTER.CRPS0[0x10c]=0
CRPS_CONDITIONAL_TRIGGER_OCCURED_INTERRUPT_REGISTER_MASK.CRPS0[0x10d]=0
CRPS_CONDITIONAL_TRIGGER_OCCURED_INTERRUPT_REGISTER_TEST.CRPS0[0x10e]=0
CRPS_CONDITIONAL_TRIGGER_WHILE_FIFO_IS_FULL_INTERRUPT_REGISTER.CRPS0[0x10f]=0
CRPS_CONDITIONAL_TRIGGER_WHILE_FIFO_IS_FULL_INTERRUPT_REGISTER_MASK.CRPS0[0x110]=0
CRPS_CONDITIONAL_TRIGGER_WHILE_FIFO_IS_FULL_INTERRUPT_REGISTER_TEST.CRPS0[0x111]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(0).CRPS0[0x178]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(1).CRPS0[0x179]=0x200020
CRPS_CRPS_DEBUG_LAST_COMMAND(2).CRPS0[0x17a]=0x45800e
CRPS_CRPS_DEBUG_LAST_COMMAND(3).CRPS0[0x17b]=0x11e0000
CRPS_CRPS_DEBUG_LAST_COMMAND(4).CRPS0[0x17c]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(5).CRPS0[0x17d]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(6).CRPS0[0x17e]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(7).CRPS0[0x17f]=0x2b0005
CRPS_CRPS_DEBUG_LAST_COMMAND(8).CRPS0[0x180]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(9).CRPS0[0x181]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(10).CRPS0[0x182]=0xd20014
CRPS_CRPS_DEBUG_LAST_COMMAND(11).CRPS0[0x183]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(12).CRPS0[0x184]=0
CRPS_CRPS_DEBUG_LAST_COMMAND(13).CRPS0[0x185]=0
CRPS_CRPS_DMA_ACCESS(0).CRPS0[0x15a]=0
CRPS_CRPS_DMA_ACCESS(1).CRPS0[0x15c]=0
CRPS_CRPS_DMA_ALMOST_FULL_INT_THRESHOLD(0).CRPS0[0x168]=1
CRPS_CRPS_DMA_ALMOST_FULL_INT_THRESHOLD(1).CRPS0[0x16a]=1
CRPS_CRPS_DMA_FIFO_STATUS(0).CRPS0[0x13c]=0
CRPS_CRPS_DMA_FIFO_STATUS(1).CRPS0[0x13d]=0
CRPS_CRPS_ENGINES_DMA_SELECT.CRPS0[0x166]=0
CRPS_CRPS_ENGINE_CFG(0).CRPS0[0x120]=0x1fffe0000000000000000000000000000000000000000000000203ffff000
CRPS_CRPS_ENGINE_CFG(1).CRPS0[0x121]=0x1fe0001000010880c07d007d000493e00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(2).CRPS0[0x122]=0x3fe0001000050880c07d007d000493e00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(3).CRPS0[0x123]=0x1ffe0001000110880c07d007d000493e00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(4).CRPS0[0x124]=0x1fffe0000000000000000000000000000000000000000000000203ffff000
CRPS_CRPS_ENGINE_CFG(5).CRPS0[0x125]=0x1ffe00010000b0880c07d007d000493e00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(6).CRPS0[0x126]=0x7ffe0001000090880c07d007d000493e00016e36040000000034fffff00e
CRPS_CRPS_ENGINE_CFG(7).CRPS0[0x127]=0x3ffe00010000d0880c07d007d000249f00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(8).CRPS0[0x128]=0x3ffe00010000f0880c07d007d000493e00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(9).CRPS0[0x129]=0x7ffe0001000130880c07d007d000493e00016e36040000000034fffff00e
CRPS_CRPS_ENGINE_CFG(10).CRPS0[0x12a]=0x7ffe0001000030880c07d007d000249f00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(11).CRPS0[0x12b]=0x7ffe0001000070880c07d007d000493e00016e36040000000034fffff009
CRPS_CRPS_ENGINE_CFG(12).CRPS0[0x12c]=0x1fffe0000000000000000000000000000000000000000000000203ffff000
CRPS_CRPS_ENGINE_CFG(13).CRPS0[0x12d]=0x1fffe0000000000000000000000000000000000000000000000203ffff000
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(0).CRPS0[0x199]=0
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(1).CRPS0[0x19a]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(2).CRPS0[0x19b]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(3).CRPS0[0x19c]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(4).CRPS0[0x19d]=0
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(5).CRPS0[0x19e]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(6).CRPS0[0x19f]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(7).CRPS0[0x1a0]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(8).CRPS0[0x1a1]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(9).CRPS0[0x1a2]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(10).CRPS0[0x1a3]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(11).CRPS0[0x1a4]=0x104000000001
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(12).CRPS0[0x1a5]=0
CRPS_CRPS_ENGINE_CONDITIONAL_TRIGGER_CFG(13).CRPS0[0x1a6]=0
CRPS_CRPS_ENGINE_ERROR(0).CRPS0[0x12e]=0
CRPS_CRPS_ENGINE_ERROR(1).CRPS0[0x12f]=0
CRPS_CRPS_ENGINE_ERROR(2).CRPS0[0x130]=0
CRPS_CRPS_ENGINE_ERROR(3).CRPS0[0x131]=0
CRPS_CRPS_ENGINE_ERROR(4).CRPS0[0x132]=0
CRPS_CRPS_ENGINE_ERROR(5).CRPS0[0x133]=0
CRPS_CRPS_ENGINE_ERROR(6).CRPS0[0x134]=0
CRPS_CRPS_ENGINE_ERROR(7).CRPS0[0x135]=0
CRPS_CRPS_ENGINE_ERROR(8).CRPS0[0x136]=0
CRPS_CRPS_ENGINE_ERROR(9).CRPS0[0x137]=0
CRPS_CRPS_ENGINE_ERROR(10).CRPS0[0x138]=0
CRPS_CRPS_ENGINE_ERROR(11).CRPS0[0x139]=0
CRPS_CRPS_ENGINE_ERROR(12).CRPS0[0x13a]=0
CRPS_CRPS_ENGINE_ERROR(13).CRPS0[0x13b]=0
CRPS_CRPS_ENGINE_INIT_DONE.CRPS0[0x160]=0xfee
CRPS_CRPS_ENGINE_INIT_REQUEST.CRPS0[0x15e]=0xfee
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(0).CRPS0[0x112]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(1).CRPS0[0x113]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(2).CRPS0[0x114]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(3).CRPS0[0x115]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(4).CRPS0[0x116]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(5).CRPS0[0x117]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(6).CRPS0[0x118]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(7).CRPS0[0x119]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(8).CRPS0[0x11a]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(9).CRPS0[0x11b]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(10).CRPS0[0x11c]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(11).CRPS0[0x11d]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(12).CRPS0[0x11e]=0
CRPS_CRPS_ENGINE_LAST_CONDITIONAL_TRIGGER_DATA(13).CRPS0[0x11f]=0
CRPS_CRPS_ENGINE_MMUX_EN.CRPS0[0x16c]=0xfee
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(0).CRPS0[0x18b]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(1).CRPS0[0x18c]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(2).CRPS0[0x18d]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(3).CRPS0[0x18e]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(4).CRPS0[0x18f]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(5).CRPS0[0x190]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(6).CRPS0[0x191]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(7).CRPS0[0x192]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(8).CRPS0[0x193]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(9).CRPS0[0x194]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(10).CRPS0[0x195]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(11).CRPS0[0x196]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(12).CRPS0[0x197]=0
CRPS_CRPS_ENGINE_PACKET_SIZE_QUANTIZATION(13).CRPS0[0x198]=0
CRPS_CRPS_ENGINE_SCAN_ENABLE.CRPS0[0x162]=0xfee
CRPS_CRPS_ENGINE_WRITE_TOD_ENABLE.CRPS0[0x164]=0
CRPS_CRPS_IF_ADAPTER_CFG.CRPS0[0x16e]=1
CRPS_CRPS_IF_ADAPTER_CGM_IRPP_0_CFG.CRPS0[0x172]=0x2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000
CRPS_CRPS_IF_ADAPTER_CGM_IRPP_1_CFG.CRPS0[0x174]=0xe000000000000000000000000000000000000000000000000000000000000000000000002000
CRPS_CRPS_IF_ADAPTER_CGM_IRPP_2_CFG.CRPS0[0x176]=0
CRPS_CRPS_IF_ADAPTER_ETPP_CTR_CFG.CRPS0[0x170]=0
CRPS_CRPS_IRPP_2_IF_OVERRIDE.CRPS0[0x188]=0
CRPS_CRPS_IRPP_5_IF_OVERRIDE.CRPS0[0x189]=0
CRPS_CRPS_IRPP_9_IF_OVERRIDE.CRPS0[0x18a]=0
CRPS_CRPS_LAST_INPUT_COMMAND.CRPS0[0x187]=0
CRPS_CRPS_LM_DUMMY_REPLY.CRPS0[0x186]=0x7000000000000000000000000
CRPS_CRPS_MODULESRC_CFG(0).CRPS0[0x13e]=0
CRPS_CRPS_MODULESRC_CFG(1).CRPS0[0x140]=0x822
CRPS_CRPS_MODULESRC_CFG(2).CRPS0[0x142]=0x846
CRPS_CRPS_MODULESRC_CFG(3).CRPS0[0x144]=0x831
CRPS_CRPS_MODULESRC_CFG(4).CRPS0[0x146]=0
CRPS_CRPS_MODULESRC_CFG(5).CRPS0[0x148]=0x1000000000840
CRPS_CRPS_MODULESRC_CFG(6).CRPS0[0x14a]=0x200080000083c
CRPS_CRPS_MODULESRC_CFG(7).CRPS0[0x14c]=0x833
CRPS_CRPS_MODULESRC_CFG(8).CRPS0[0x14e]=0x834
CRPS_CRPS_MODULESRC_CFG(9).CRPS0[0x150]=0x80000083c
CRPS_CRPS_MODULESRC_CFG(10).CRPS0[0x152]=0x888
CRPS_CRPS_MODULESRC_CFG(11).CRPS0[0x154]=0x845
CRPS_CRPS_MODULESRC_CFG(12).CRPS0[0x156]=0
CRPS_CRPS_MODULESRC_CFG(13).CRPS0[0x158]=0
CRPS_DMA_0_FULLNESS_INTERRUPT_REGISTER.CRPS0[0x106]=1
CRPS_DMA_0_FULLNESS_INTERRUPT_REGISTER_MASK.CRPS0[0x107]=0
CRPS_DMA_0_FULLNESS_INTERRUPT_REGISTER_TEST.CRPS0[0x108]=0
CRPS_DMA_1_FULLNESS_INTERRUPT_REGISTER.CRPS0[0x109]=1
CRPS_DMA_1_FULLNESS_INTERRUPT_REGISTER_MASK.CRPS0[0x10a]=0
CRPS_DMA_1_FULLNESS_INTERRUPT_REGISTER_TEST.CRPS0[0x10b]=0
CRPS_ECC_1B_ERR_CNT.CRPS0[0x94]=0
CRPS_ECC_2B_ERR_CNT.CRPS0[0x96]=0
CRPS_ECC_ERR_1B_MONITOR_MEM_MASK.CRPS0[0x9a]=0x3fffffff
CRPS_ECC_ERR_2B_MONITOR_MEM_MASK.CRPS0[0x9c]=0x3fffffff
CRPS_ECC_INTERRUPT_REGISTER.CRPS0[0x7]=0
CRPS_ECC_INTERRUPT_REGISTER_MASK.CRPS0[0x17]=0
CRPS_ECC_INTERRUPT_REGISTER_TEST.CRPS0[0x1f]=0
CRPS_ENABLE_DYNAMIC_MEMORY_ACCESS.CRPS0[0x84]=0xffff
CRPS_ERROR_COUNTER_OVF_ERROR_INTERRUPT_REGISTER.CRPS0[0x103]=0
CRPS_ERROR_COUNTER_OVF_ERROR_INTERRUPT_REGISTER_MASK.CRPS0[0x104]=0
CRPS_ERROR_COUNTER_OVF_ERROR_INTERRUPT_REGISTER_TEST.CRPS0[0x105]=0
CRPS_GTIMER_CONFIGURATION.CRPS0[0x89]=0
CRPS_GTIMER_CYCLE.CRPS0[0x88]=0x3b9aca00
CRPS_INDIRECT_COMMAND.CRPS0[0x80]=0xe000002
CRPS_INDIRECT_COMMAND_ADDRESS.CRPS0[0x81]=0x7401
CRPS_INDIRECT_COMMAND_RD_DATA.CRPS0[0x60]=0
CRPS_INDIRECT_COMMAND_WR_DATA.CRPS0[0x20]=0x7ffe0001000130880c07d007d000493e00016e3604000000003400000020
CRPS_INDIRECT_FORCE_BUBBLE.CRPS0[0x83]=0x20019
CRPS_INTERRUPT_MASK_REGISTER.CRPS0[0x10]=0
CRPS_INTERRUPT_REGISTER.CRPS0[0x0]=0
CRPS_INTERRUPT_REGISTER_TEST.CRPS0[0x18]=0
CRPS_LM_COLLISION_ERROR_INTERRUPT_REGISTER.CRPS0[0x100]=0
CRPS_LM_COLLISION_ERROR_INTERRUPT_REGISTER_MASK.CRPS0[0x101]=0
CRPS_LM_COLLISION_ERROR_INTERRUPT_REGISTER_TEST.CRPS0[0x102]=0
CRPS_REG_0041.CRPS0[0x41]=0
CRPS_REG_00C2.CRPS0[0xc2]=0x10
CRPS_RESERVED_MTCD.CRPS0[0xae]=0x30
CRPS_RESERVED_MTCP.CRPS0[0xad]=0x300000600000000
CRPS_RESERVED_SPARE_0.CRPS0[0x90]=0xffffffff
CRPS_RESERVED_SPARE_1.CRPS0[0x91]=0xffffffff
CRPS_RESERVED_SPARE_2.CRPS0[0x92]=0
CRPS_RESERVED_SPARE_3.CRPS0[0x93]=0
CRPS_SBUS_BROADCAST_ID.CRPS0[0x86]=0x7ff
CRPS_SBUS_LAST_IN_CHAIN.CRPS0[0x87]=0
CRPS_SPECIAL_CLOCK_CONTROLS.CRPS0[0xc1]=2
DCC_BANK_ORDER_FIFO_WMK.DCC0[0x122]=0
DCC_BANK_ORDER_FIFO_WMK.DCC1[0x122]=0
DCC_BANK_ORDER_FIFO_WMK.DCC2[0x122]=0
DCC_BANK_ORDER_FIFO_WMK.DCC3[0x122]=0
DCC_BIST_ADDR_CONFIG.DCC0[0x13e]=0x3fff0000007e001e0
DCC_BIST_ADDR_CONFIG.DCC1[0x13e]=0x3fff0000007e001e0
DCC_BIST_ADDR_CONFIG.DCC2[0x13e]=0x3fff0000007e001e0
DCC_BIST_ADDR_CONFIG.DCC3[0x13e]=0x3fff0000007e001e0
DCC_BIST_BANK_REORDER.DCC0[0x13f]=0x53
DCC_BIST_BANK_REORDER.DCC1[0x13f]=0x53
DCC_BIST_BANK_REORDER.DCC2[0x13f]=0x53
DCC_BIST_BANK_REORDER.DCC3[0x13f]=0x53
DCC_BIST_COMMAND_CONFIG.DCC0[0x13a]=0x800ff00ff0010000000
DCC_BIST_COMMAND_CONFIG.DCC1[0x13a]=0x800ff00ff0010000000
DCC_BIST_COMMAND_CONFIG.DCC2[0x13a]=0x800ff00ff0010000000
DCC_BIST_COMMAND_CONFIG.DCC3[0x13a]=0x800ff00ff0010000000
DCC_BIST_CONTROL.DCC0[0x137]=8
DCC_BIST_CONTROL.DCC1[0x137]=8
DCC_BIST_CONTROL.DCC2[0x137]=8
DCC_BIST_CONTROL.DCC3[0x137]=8
DCC_BIST_DATA_CONFIG.DCC0[0x140]=0xffff
DCC_BIST_DATA_CONFIG.DCC1[0x140]=0xffff
DCC_BIST_DATA_CONFIG.DCC2[0x140]=0xffff
DCC_BIST_DATA_CONFIG.DCC3[0x140]=0xffff
DCC_BIST_ERR_COUNTERS.DCC0[0x15a]=0
DCC_BIST_ERR_COUNTERS.DCC1[0x15a]=0
DCC_BIST_ERR_COUNTERS.DCC2[0x15a]=0
DCC_BIST_ERR_COUNTERS.DCC3[0x15a]=0
DCC_BIST_INTERRUPT_MASK_REGISTER.DCC0[0x107]=0
DCC_BIST_INTERRUPT_MASK_REGISTER.DCC1[0x107]=0
DCC_BIST_INTERRUPT_MASK_REGISTER.DCC2[0x107]=0
DCC_BIST_INTERRUPT_MASK_REGISTER.DCC3[0x107]=0
DCC_BIST_INTERRUPT_REGISTER.DCC0[0x106]=0
DCC_BIST_INTERRUPT_REGISTER.DCC1[0x106]=0
DCC_BIST_INTERRUPT_REGISTER.DCC2[0x106]=0
DCC_BIST_INTERRUPT_REGISTER.DCC3[0x106]=0
DCC_BIST_INTERRUPT_REGISTER_TEST.DCC0[0x108]=0
DCC_BIST_INTERRUPT_REGISTER_TEST.DCC1[0x108]=0
DCC_BIST_INTERRUPT_REGISTER_TEST.DCC2[0x108]=0
DCC_BIST_INTERRUPT_REGISTER_TEST.DCC3[0x108]=0
DCC_BIST_LAST_RETURNED_DATA.DCC0[0x134]=0x4b2dc1db000000002142c2f9d405cd24cb51bdd9b9ac0a537b9ac0a531a84d01450b65db1149e7d3
DCC_BIST_LAST_RETURNED_DATA.DCC1[0x134]=0x4b2de3d9000000002142c2f9d405cd24cb51bdd9b9ac0a537b9ac0a531a84d01450b65db1149a7d3
DCC_BIST_LAST_RETURNED_DATA.DCC2[0x134]=0x4b2de3d9000000002142c2f9d405cd24cb51bdd9b9ac0a537b9ac0a531a84d01450b65db1149a7d3
DCC_BIST_LAST_RETURNED_DATA.DCC3[0x134]=0x4b2de3d9000000002142c2f9d405cd24cb51bdd9b9ac0a537b9ac0a531a84d01450b65db1149a7d3
DCC_BIST_PATTERN(0).DCC0[0x141]=0
DCC_BIST_PATTERN(1).DCC0[0x142]=0
DCC_BIST_PATTERN(2).DCC0[0x143]=0
DCC_BIST_PATTERN(3).DCC0[0x144]=0
DCC_BIST_PATTERN(4).DCC0[0x145]=0
DCC_BIST_PATTERN(5).DCC0[0x146]=0
DCC_BIST_PATTERN(6).DCC0[0x147]=0
DCC_BIST_PATTERN(7).DCC0[0x148]=0
DCC_BIST_PATTERN(0).DCC1[0x141]=0
DCC_BIST_PATTERN(1).DCC1[0x142]=0
DCC_BIST_PATTERN(2).DCC1[0x143]=0
DCC_BIST_PATTERN(3).DCC1[0x144]=0
DCC_BIST_PATTERN(4).DCC1[0x145]=0
DCC_BIST_PATTERN(5).DCC1[0x146]=0
DCC_BIST_PATTERN(6).DCC1[0x147]=0
DCC_BIST_PATTERN(7).DCC1[0x148]=0
DCC_BIST_PATTERN(0).DCC2[0x141]=0
DCC_BIST_PATTERN(1).DCC2[0x142]=0
DCC_BIST_PATTERN(2).DCC2[0x143]=0
DCC_BIST_PATTERN(3).DCC2[0x144]=0
DCC_BIST_PATTERN(4).DCC2[0x145]=0
DCC_BIST_PATTERN(5).DCC2[0x146]=0
DCC_BIST_PATTERN(6).DCC2[0x147]=0
DCC_BIST_PATTERN(7).DCC2[0x148]=0
DCC_BIST_PATTERN(0).DCC3[0x141]=0
DCC_BIST_PATTERN(1).DCC3[0x142]=0
DCC_BIST_PATTERN(2).DCC3[0x143]=0
DCC_BIST_PATTERN(3).DCC3[0x144]=0
DCC_BIST_PATTERN(4).DCC3[0x145]=0
DCC_BIST_PATTERN(5).DCC3[0x146]=0
DCC_BIST_PATTERN(6).DCC3[0x147]=0
DCC_BIST_PATTERN(7).DCC3[0x148]=0
DCC_BIST_STATUS.DCC0[0x138]=0xdafd622800dafd622800dafd6228000000000000dafd6228000000000000000000000000000000
DCC_BIST_STATUS.DCC1[0x138]=0xdafd622800dafd622800dafd6228000000000000dafd6228000000000000000000000000000000
DCC_BIST_STATUS.DCC2[0x138]=0xdafd622800dafd622800dafd6228000000000000dafd6228000000000000000000000000000000
DCC_BIST_STATUS.DCC3[0x138]=0xdafd622e00dafd622e00dafd622e000000000000dafd622e000000000000000000000000000000
DCC_CADT_TRAINING_PATTERN(0).DCC0[0x151]=0
DCC_CADT_TRAINING_PATTERN(1).DCC0[0x152]=0
DCC_CADT_TRAINING_PATTERN(2).DCC0[0x153]=0
DCC_CADT_TRAINING_PATTERN(3).DCC0[0x154]=0
DCC_CADT_TRAINING_PATTERN(4).DCC0[0x155]=0
DCC_CADT_TRAINING_PATTERN(5).DCC0[0x156]=0
DCC_CADT_TRAINING_PATTERN(6).DCC0[0x157]=0
DCC_CADT_TRAINING_PATTERN(7).DCC0[0x158]=0
DCC_CADT_TRAINING_PATTERN(0).DCC1[0x151]=0
DCC_CADT_TRAINING_PATTERN(1).DCC1[0x152]=0
DCC_CADT_TRAINING_PATTERN(2).DCC1[0x153]=0
DCC_CADT_TRAINING_PATTERN(3).DCC1[0x154]=0
DCC_CADT_TRAINING_PATTERN(4).DCC1[0x155]=0
DCC_CADT_TRAINING_PATTERN(5).DCC1[0x156]=0
DCC_CADT_TRAINING_PATTERN(6).DCC1[0x157]=0
DCC_CADT_TRAINING_PATTERN(7).DCC1[0x158]=0
DCC_CADT_TRAINING_PATTERN(0).DCC2[0x151]=0
DCC_CADT_TRAINING_PATTERN(1).DCC2[0x152]=0
DCC_CADT_TRAINING_PATTERN(2).DCC2[0x153]=0
DCC_CADT_TRAINING_PATTERN(3).DCC2[0x154]=0
DCC_CADT_TRAINING_PATTERN(4).DCC2[0x155]=0
DCC_CADT_TRAINING_PATTERN(5).DCC2[0x156]=0
DCC_CADT_TRAINING_PATTERN(6).DCC2[0x157]=0
DCC_CADT_TRAINING_PATTERN(7).DCC2[0x158]=0
DCC_CADT_TRAINING_PATTERN(0).DCC3[0x151]=0
DCC_CADT_TRAINING_PATTERN(1).DCC3[0x152]=0
DCC_CADT_TRAINING_PATTERN(2).DCC3[0x153]=0
DCC_CADT_TRAINING_PATTERN(3).DCC3[0x154]=0
DCC_CADT_TRAINING_PATTERN(4).DCC3[0x155]=0
DCC_CADT_TRAINING_PATTERN(5).DCC3[0x156]=0
DCC_CADT_TRAINING_PATTERN(6).DCC3[0x157]=0
DCC_CADT_TRAINING_PATTERN(7).DCC3[0x158]=0
DCC_CA_BIT_MAP.DCC0[0x12f]=0xba9876543210
DCC_CA_BIT_MAP.DCC1[0x12f]=0xba9876543210
DCC_CA_BIT_MAP.DCC2[0x12f]=0xba9876543210
DCC_CA_BIT_MAP.DCC3[0x12f]=0xba9876543210
DCC_CDR_WRAPAROUND_UPDATE_CONFIG.DCC0[0x16c]=0x1915
DCC_CDR_WRAPAROUND_UPDATE_CONFIG.DCC1[0x16c]=0x1915
DCC_CDR_WRAPAROUND_UPDATE_CONFIG.DCC2[0x16c]=0x1915
DCC_CDR_WRAPAROUND_UPDATE_CONFIG.DCC3[0x16c]=0x1915
DCC_COMMON_DYNAMIC_CALIBRATION_CONFIG.DCC0[0x16d]=0xc80023fffe642
DCC_COMMON_DYNAMIC_CALIBRATION_CONFIG.DCC1[0x16d]=0xc80023fffe642
DCC_COMMON_DYNAMIC_CALIBRATION_CONFIG.DCC2[0x16d]=0xc80023fffe642
DCC_COMMON_DYNAMIC_CALIBRATION_CONFIG.DCC3[0x16d]=0xc80023fffe642
DCC_DATA_SOURCE_CONFIG(0).DCC0[0x115]=0x20100
DCC_DATA_SOURCE_CONFIG(0).DCC1[0x115]=0x20100
DCC_DATA_SOURCE_CONFIG(0).DCC2[0x115]=0x20100
DCC_DATA_SOURCE_CONFIG(0).DCC3[0x115]=0x20100
DCC_DQ_BIT_MAP.DCC0[0x12e]=0x97e60a0ca977
DCC_DQ_BIT_MAP.DCC1[0x12e]=0x21ab37f35688
DCC_DQ_BIT_MAP.DCC2[0x12e]=0x97e60a2c2977
DCC_DQ_BIT_MAP.DCC3[0x12e]=0x53b37f354c1
DCC_DRAM_COMMAND_COUNTERS.DCC0[0x133]=0xdafd624600dafd624600000000009b534b7c2d0048ff20c200000000000000000000000000000000000000000000000000
DCC_DRAM_COMMAND_COUNTERS.DCC1[0x133]=0xdafd624600dafd624600000000009b534b7c300048ff20c200000000000000000000000000000000000000000000000000
DCC_DRAM_COMMAND_COUNTERS.DCC2[0x133]=0xdafd624600dafd624600000000009b534b7c380048ff20c200000000000000000000000000000000000000000000000000
DCC_DRAM_COMMAND_COUNTERS.DCC3[0x133]=0xdafd624600dafd624600000000009b534b7c3d0048ff20c200000000000000000000000000000000000000000000000000
DCC_DRAM_ERR_COUNTERS.DCC0[0x132]=0
DCC_DRAM_ERR_COUNTERS.DCC1[0x132]=0
DCC_DRAM_ERR_COUNTERS.DCC2[0x132]=0
DCC_DRAM_ERR_COUNTERS.DCC3[0x132]=0
DCC_DRAM_GENERAL_TIMINGS.DCC0[0x127]=0xa
DCC_DRAM_GENERAL_TIMINGS.DCC1[0x127]=0xa
DCC_DRAM_GENERAL_TIMINGS.DCC2[0x127]=0xa
DCC_DRAM_GENERAL_TIMINGS.DCC3[0x127]=0xa
DCC_DRAM_MODE_REGISTER_MANAGER_CONFIG.DCC0[0x114]=0x1ffff
DCC_DRAM_MODE_REGISTER_MANAGER_CONFIG.DCC1[0x114]=0x1ffff
DCC_DRAM_MODE_REGISTER_MANAGER_CONFIG.DCC2[0x114]=0x1ffff
DCC_DRAM_MODE_REGISTER_MANAGER_CONFIG.DCC3[0x114]=0x1ffff
DCC_DRAM_READ_FIFO_CNTRL.DCC0[0x139]=0x19049600000000a1efbf3b3cc596e72517347a0fe7a8d930fe7a8d75d48abc618625bf4baeb9c51
DCC_DRAM_READ_FIFO_CNTRL.DCC1[0x139]=0x19049600000000a1efbf3b3cc596e72517347a0fe7a8d930fe7a8d75d48abc618625bf4baeb9c51
DCC_DRAM_READ_FIFO_CNTRL.DCC2[0x139]=0x19049600000000a1efbf3b3cc596e72517347a0fe7a8d930fe7a8d75d48abc618625bf4baeb9c51
DCC_DRAM_READ_FIFO_CNTRL.DCC3[0x139]=0x19049600000000a1efbf3b3cc596e72517347a0fe7a8d930fe7a8d75d48abc618625bf4baeb9c51
DCC_DRAM_REFRESH_INTERVALS.DCC0[0x129]=0x7610aae60
DCC_DRAM_REFRESH_INTERVALS.DCC1[0x129]=0x7610aae60
DCC_DRAM_REFRESH_INTERVALS.DCC2[0x129]=0x7610aae60
DCC_DRAM_REFRESH_INTERVALS.DCC3[0x129]=0x7610aae60
DCC_DRAM_TRAINING_GENERAL_TIMINGS.DCC0[0x128]=0x40c402041428086
DCC_DRAM_TRAINING_GENERAL_TIMINGS.DCC1[0x128]=0x40c402041428086
DCC_DRAM_TRAINING_GENERAL_TIMINGS.DCC2[0x128]=0x40c402041428086
DCC_DRAM_TRAINING_GENERAL_TIMINGS.DCC3[0x128]=0x40c402041428086
DCC_DSI_INTERRUPT_MASK_REGISTER.DCC0[0x101]=0
DCC_DSI_INTERRUPT_MASK_REGISTER.DCC1[0x101]=0
DCC_DSI_INTERRUPT_MASK_REGISTER.DCC2[0x101]=0
DCC_DSI_INTERRUPT_MASK_REGISTER.DCC3[0x101]=0
DCC_DSI_INTERRUPT_REGISTER.DCC0[0x100]=0
DCC_DSI_INTERRUPT_REGISTER.DCC1[0x100]=0
DCC_DSI_INTERRUPT_REGISTER.DCC2[0x100]=0
DCC_DSI_INTERRUPT_REGISTER.DCC3[0x100]=0
DCC_DSI_INTERRUPT_REGISTER_TEST.DCC0[0x102]=0
DCC_DSI_INTERRUPT_REGISTER_TEST.DCC1[0x102]=0
DCC_DSI_INTERRUPT_REGISTER_TEST.DCC2[0x102]=0
DCC_DSI_INTERRUPT_REGISTER_TEST.DCC3[0x102]=0
DCC_DYNAMIC_CALIBRATION_MONITOR(0).DCC0[0x170]=0xdf000000c8000000d3000000d3
DCC_DYNAMIC_CALIBRATION_MONITOR(1).DCC0[0x171]=0xea000000d1000000dd000000de
DCC_DYNAMIC_CALIBRATION_MONITOR(2).DCC0[0x172]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(3).DCC0[0x173]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(4).DCC0[0x174]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(5).DCC0[0x175]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(6).DCC0[0x176]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(7).DCC0[0x177]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(8).DCC0[0x178]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(9).DCC0[0x179]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(10).DCC0[0x17a]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(11).DCC0[0x17b]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(12).DCC0[0x17c]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(13).DCC0[0x17d]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(14).DCC0[0x17e]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(15).DCC0[0x17f]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(0).DCC1[0x170]=0x13d000001230000013000000130
DCC_DYNAMIC_CALIBRATION_MONITOR(1).DCC1[0x171]=0x14a000001300000013d0000013d
DCC_DYNAMIC_CALIBRATION_MONITOR(2).DCC1[0x172]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(3).DCC1[0x173]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(4).DCC1[0x174]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(5).DCC1[0x175]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(6).DCC1[0x176]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(7).DCC1[0x177]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(8).DCC1[0x178]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(9).DCC1[0x179]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(10).DCC1[0x17a]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(11).DCC1[0x17b]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(12).DCC1[0x17c]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(13).DCC1[0x17d]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(14).DCC1[0x17e]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(15).DCC1[0x17f]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(0).DCC2[0x170]=0x143000001270000013500000134
DCC_DYNAMIC_CALIBRATION_MONITOR(1).DCC2[0x171]=0x143000001270000013500000135
DCC_DYNAMIC_CALIBRATION_MONITOR(2).DCC2[0x172]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(3).DCC2[0x173]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(4).DCC2[0x174]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(5).DCC2[0x175]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(6).DCC2[0x176]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(7).DCC2[0x177]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(8).DCC2[0x178]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(9).DCC2[0x179]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(10).DCC2[0x17a]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(11).DCC2[0x17b]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(12).DCC2[0x17c]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(13).DCC2[0x17d]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(14).DCC2[0x17e]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(15).DCC2[0x17f]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(0).DCC3[0x170]=0x140000001260000013300000133
DCC_DYNAMIC_CALIBRATION_MONITOR(1).DCC3[0x171]=0x14a000001300000013d0000013d
DCC_DYNAMIC_CALIBRATION_MONITOR(2).DCC3[0x172]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(3).DCC3[0x173]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(4).DCC3[0x174]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(5).DCC3[0x175]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(6).DCC3[0x176]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(7).DCC3[0x177]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(8).DCC3[0x178]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(9).DCC3[0x179]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(10).DCC3[0x17a]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(11).DCC3[0x17b]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(12).DCC3[0x17c]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(13).DCC3[0x17d]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(14).DCC3[0x17e]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_MONITOR(15).DCC3[0x17f]=0x800000007fffffff7fffffff7fffffff
DCC_DYNAMIC_CALIBRATION_STATUS.DCC0[0x16f]=0x100041
DCC_DYNAMIC_CALIBRATION_STATUS.DCC1[0x16f]=0x100000
DCC_DYNAMIC_CALIBRATION_STATUS.DCC2[0x16f]=0x185ff3
DCC_DYNAMIC_CALIBRATION_STATUS.DCC3[0x16f]=0x100000
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(0).DCC0[0x15b]=0xb00000000000000d2000000d4000000a10000010500a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(1).DCC0[0x15c]=0x10b00000000000000dd000000df000000ac0000011010a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(2).DCC0[0x15d]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(3).DCC0[0x15e]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(4).DCC0[0x15f]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(5).DCC0[0x160]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(6).DCC0[0x161]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(7).DCC0[0x162]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(8).DCC0[0x163]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(9).DCC0[0x164]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(10).DCC0[0x165]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(11).DCC0[0x166]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(12).DCC0[0x167]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(13).DCC0[0x168]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(14).DCC0[0x169]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(15).DCC0[0x16a]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(0).DCC1[0x15b]=0x20b000000000000012d0000012f000000fc0000016020a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(1).DCC1[0x15c]=0x30b000000000000013a0000013c000001090000016d30a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(2).DCC1[0x15d]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(3).DCC1[0x15e]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(4).DCC1[0x15f]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(5).DCC1[0x160]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(6).DCC1[0x161]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(7).DCC1[0x162]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(8).DCC1[0x163]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(9).DCC1[0x164]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(10).DCC1[0x165]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(11).DCC1[0x166]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(12).DCC1[0x167]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(13).DCC1[0x168]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(14).DCC1[0x169]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(15).DCC1[0x16a]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(0).DCC2[0x15b]=0xb000000000000013300000135000001020000016600a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(1).DCC2[0x15c]=0x10b000000000000013500000137000001040000016810a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(2).DCC2[0x15d]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(3).DCC2[0x15e]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(4).DCC2[0x15f]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(5).DCC2[0x160]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(6).DCC2[0x161]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(7).DCC2[0x162]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(8).DCC2[0x163]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(9).DCC2[0x164]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(10).DCC2[0x165]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(11).DCC2[0x166]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(12).DCC2[0x167]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(13).DCC2[0x168]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(14).DCC2[0x169]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(15).DCC2[0x16a]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(0).DCC3[0x15b]=0x20b000000000000013200000134000001010000016520a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(1).DCC3[0x15c]=0x30b000000000000013c0000013e0000010b0000016f30a
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(2).DCC3[0x15d]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(3).DCC3[0x15e]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(4).DCC3[0x15f]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(5).DCC3[0x160]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(6).DCC3[0x161]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(7).DCC3[0x162]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(8).DCC3[0x163]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(9).DCC3[0x164]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(10).DCC3[0x165]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(11).DCC3[0x166]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(12).DCC3[0x167]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(13).DCC3[0x168]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(14).DCC3[0x169]=0
DCC_DYNAMIC_CALIBRATION_VDL_CTRL(15).DCC3[0x16a]=0
DCC_ECC_1B_ERR_CNT.DCC0[0x94]=0
DCC_ECC_1B_ERR_CNT.DCC1[0x94]=0
DCC_ECC_1B_ERR_CNT.DCC2[0x94]=0
DCC_ECC_1B_ERR_CNT.DCC3[0x94]=0
DCC_ECC_2B_ERR_CNT.DCC0[0x96]=0
DCC_ECC_2B_ERR_CNT.DCC1[0x96]=0
DCC_ECC_2B_ERR_CNT.DCC2[0x96]=0
DCC_ECC_2B_ERR_CNT.DCC3[0x96]=0
DCC_ECC_ERR_1B_MONITOR_MEM_MASK.DCC0[0x9a]=0xf
DCC_ECC_ERR_1B_MONITOR_MEM_MASK.DCC1[0x9a]=0xf
DCC_ECC_ERR_1B_MONITOR_MEM_MASK.DCC2[0x9a]=0xf
DCC_ECC_ERR_1B_MONITOR_MEM_MASK.DCC3[0x9a]=0xf
DCC_ECC_ERR_2B_MONITOR_MEM_MASK.DCC0[0x9c]=0xf
DCC_ECC_ERR_2B_MONITOR_MEM_MASK.DCC1[0x9c]=0xf
DCC_ECC_ERR_2B_MONITOR_MEM_MASK.DCC2[0x9c]=0xf
DCC_ECC_ERR_2B_MONITOR_MEM_MASK.DCC3[0x9c]=0xf
DCC_ECC_INTERRUPT_REGISTER.DCC0[0x7]=0
DCC_ECC_INTERRUPT_REGISTER.DCC1[0x7]=0
DCC_ECC_INTERRUPT_REGISTER.DCC2[0x7]=0
DCC_ECC_INTERRUPT_REGISTER.DCC3[0x7]=0
DCC_ECC_INTERRUPT_REGISTER_MASK.DCC0[0x17]=0
DCC_ECC_INTERRUPT_REGISTER_MASK.DCC1[0x17]=0
DCC_ECC_INTERRUPT_REGISTER_MASK.DCC2[0x17]=0
DCC_ECC_INTERRUPT_REGISTER_MASK.DCC3[0x17]=0
DCC_ECC_INTERRUPT_REGISTER_TEST.DCC0[0x1f]=0
DCC_ECC_INTERRUPT_REGISTER_TEST.DCC1[0x1f]=0
DCC_ECC_INTERRUPT_REGISTER_TEST.DCC2[0x1f]=0
DCC_ECC_INTERRUPT_REGISTER_TEST.DCC3[0x1f]=0
DCC_ENABLE_DYNAMIC_MEMORY_ACCESS.DCC0[0x84]=1
DCC_ENABLE_DYNAMIC_MEMORY_ACCESS.DCC1[0x84]=1
DCC_ENABLE_DYNAMIC_MEMORY_ACCESS.DCC2[0x84]=1
DCC_ENABLE_DYNAMIC_MEMORY_ACCESS.DCC3[0x84]=1
DCC_GTIMER_CONFIGURATION.DCC0[0x89]=0
DCC_GTIMER_CONFIGURATION.DCC1[0x89]=0
DCC_GTIMER_CONFIGURATION.DCC2[0x89]=0
DCC_GTIMER_CONFIGURATION.DCC3[0x89]=0
DCC_GTIMER_CYCLE.DCC0[0x88]=0x3b9aca00
DCC_GTIMER_CYCLE.DCC1[0x88]=0x3b9aca00
DCC_GTIMER_CYCLE.DCC2[0x88]=0x3b9aca00
DCC_GTIMER_CYCLE.DCC3[0x88]=0x3b9aca00
DCC_HBM_COLUMN_ACCESS_TIMINGS.DCC0[0x125]=0x1a452083
DCC_HBM_COLUMN_ACCESS_TIMINGS.DCC1[0x125]=0x1a452083
DCC_HBM_COLUMN_ACCESS_TIMINGS.DCC2[0x125]=0x1a452083
DCC_HBM_COLUMN_ACCESS_TIMINGS.DCC3[0x125]=0x1a452083
DCC_HBM_CONFIG.DCC0[0x112]=0x19c83fd4
DCC_HBM_CONFIG.DCC1[0x112]=0x19c83fd4
DCC_HBM_CONFIG.DCC2[0x112]=0x19c83fd4
DCC_HBM_CONFIG.DCC3[0x112]=0x19c83fd4
DCC_HBM_CPU_CONTROL.DCC0[0x131]=0x1bfffff00cccc0bfffbc
DCC_HBM_CPU_CONTROL.DCC1[0x131]=0x1bfffff00cccc0bfffbc
DCC_HBM_CPU_CONTROL.DCC2[0x131]=0x1bfffff00cccc0bfffbc
DCC_HBM_CPU_CONTROL.DCC3[0x131]=0x1bfffff00cccc0bfffbc
DCC_HBM_MODE_REGISTERS.DCC0[0x113]=0x1004000000000d41f0a82a001f5ad002ea00000000bebd
DCC_HBM_MODE_REGISTERS.DCC1[0x113]=0x1004000000000c01f0a82a001f5ed002ea00000000bebd
DCC_HBM_MODE_REGISTERS.DCC2[0x113]=0x1004000000000c01f0a82a001f5ed002ea00000000bebd
DCC_HBM_MODE_REGISTERS.DCC3[0x113]=0x1004000000000d41f0a82a001f5ad002ea00000000bebd
DCC_HBM_REFRESH_TIMINGS.DCC0[0x126]=0xc0fc63
DCC_HBM_REFRESH_TIMINGS.DCC1[0x126]=0xc0fc63
DCC_HBM_REFRESH_TIMINGS.DCC2[0x126]=0xc0fc63
DCC_HBM_REFRESH_TIMINGS.DCC3[0x126]=0xc0fc63
DCC_HBM_ROW_ACCESS_TIMINGS.DCC0[0x124]=0x79e4030cf1042916a9
DCC_HBM_ROW_ACCESS_TIMINGS.DCC1[0x124]=0x79e4030cf1042916a9
DCC_HBM_ROW_ACCESS_TIMINGS.DCC2[0x124]=0x79e4030cf1042916a9
DCC_HBM_ROW_ACCESS_TIMINGS.DCC3[0x124]=0x79e4030cf1042916a9
DCC_HW_DYNAMIC_CALIBRATION_CONFIG.DCC0[0x16b]=0x3c00000003c000000011c2
DCC_HW_DYNAMIC_CALIBRATION_CONFIG.DCC1[0x16b]=0x3c00000003c000000011c2
DCC_HW_DYNAMIC_CALIBRATION_CONFIG.DCC2[0x16b]=0x3c00000003c000000011c2
DCC_HW_DYNAMIC_CALIBRATION_CONFIG.DCC3[0x16b]=0x3c00000003c000000011c2
DCC_INDIRECT_COMMAND.DCC0[0x80]=0xe000000
DCC_INDIRECT_COMMAND.DCC1[0x80]=0xe000000
DCC_INDIRECT_COMMAND.DCC2[0x80]=0xe000000
DCC_INDIRECT_COMMAND.DCC3[0x80]=0xe000000
DCC_INDIRECT_COMMAND_ADDRESS.DCC0[0x81]=0
DCC_INDIRECT_COMMAND_ADDRESS.DCC1[0x81]=0
DCC_INDIRECT_COMMAND_ADDRESS.DCC2[0x81]=0
DCC_INDIRECT_COMMAND_ADDRESS.DCC3[0x81]=0
DCC_INDIRECT_COMMAND_RD_DATA.DCC0[0x60]=0xffffffffffffffffff7ffffffffffbfbfffffffffffffffffdffffffffffffff
DCC_INDIRECT_COMMAND_RD_DATA.DCC1[0x60]=0xffbffefbfebbeffffffdfffffffbfddffffffffffef73ffffffffffdffffffff
DCC_INDIRECT_COMMAND_RD_DATA.DCC2[0x60]=0xfffffeffffeffd7fffffbfffffffffffffff5ffdffffffffefffffffffffffff
DCC_INDIRECT_COMMAND_RD_DATA.DCC3[0x60]=0x22605004000616037469488a811500322c20000d48a08c08800020000408788e
DCC_INDIRECT_COMMAND_WR_DATA.DCC0[0x20]=0
DCC_INDIRECT_COMMAND_WR_DATA.DCC1[0x20]=0
DCC_INDIRECT_COMMAND_WR_DATA.DCC2[0x20]=0
DCC_INDIRECT_COMMAND_WR_DATA.DCC3[0x20]=0
DCC_INDIRECT_FORCE_BUBBLE.DCC0[0x83]=0
DCC_INDIRECT_FORCE_BUBBLE.DCC1[0x83]=0
DCC_INDIRECT_FORCE_BUBBLE.DCC2[0x83]=0
DCC_INDIRECT_FORCE_BUBBLE.DCC3[0x83]=0
DCC_INFLIGHTS_WMK.DCC0[0x123]=0
DCC_INFLIGHTS_WMK.DCC1[0x123]=0
DCC_INFLIGHTS_WMK.DCC2[0x123]=0
DCC_INFLIGHTS_WMK.DCC3[0x123]=0
DCC_INTERRUPT_MASK_REGISTER.DCC0[0x10]=0
DCC_INTERRUPT_MASK_REGISTER.DCC1[0x10]=0
DCC_INTERRUPT_MASK_REGISTER.DCC2[0x10]=0
DCC_INTERRUPT_MASK_REGISTER.DCC3[0x10]=0
DCC_INTERRUPT_REGISTER.DCC0[0x0]=0
DCC_INTERRUPT_REGISTER.DCC1[0x0]=0
DCC_INTERRUPT_REGISTER.DCC2[0x0]=0
DCC_INTERRUPT_REGISTER.DCC3[0x0]=0
DCC_INTERRUPT_REGISTER_TEST.DCC0[0x18]=0
DCC_INTERRUPT_REGISTER_TEST.DCC1[0x18]=0
DCC_INTERRUPT_REGISTER_TEST.DCC2[0x18]=0
DCC_INTERRUPT_REGISTER_TEST.DCC3[0x18]=0
DCC_LAST_RETURNED_DATA.DCC0[0x135]=0xe3d90000de693095c4451d8015e055eb84c267ab
DCC_LAST_RETURNED_DATA.DCC1[0x135]=0xe3d90000eeca03954c987201520b5aeb4429d9e3
DCC_LAST_RETURNED_DATA.DCC2[0x135]=0xe3d90000dec93035c4451d2015e055eb846267ab
DCC_LAST_RETURNED_DATA.DCC3[0x135]=0xe3d90000dec5039a8c94b202a207aae78426e9e3
DCC_LAST_SLICE_FIFO_WMK.DCC0[0x121]=0
DCC_LAST_SLICE_FIFO_WMK.DCC1[0x121]=0
DCC_LAST_SLICE_FIFO_WMK.DCC2[0x121]=0
DCC_LAST_SLICE_FIFO_WMK.DCC3[0x121]=0
DCC_LDFF_TRAINING_PATTERN(0).DCC0[0x149]=0
DCC_LDFF_TRAINING_PATTERN(1).DCC0[0x14a]=0
DCC_LDFF_TRAINING_PATTERN(2).DCC0[0x14b]=0
DCC_LDFF_TRAINING_PATTERN(3).DCC0[0x14c]=0
DCC_LDFF_TRAINING_PATTERN(4).DCC0[0x14d]=0
DCC_LDFF_TRAINING_PATTERN(5).DCC0[0x14e]=0
DCC_LDFF_TRAINING_PATTERN(6).DCC0[0x14f]=0
DCC_LDFF_TRAINING_PATTERN(7).DCC0[0x150]=0
DCC_LDFF_TRAINING_PATTERN(0).DCC1[0x149]=0
DCC_LDFF_TRAINING_PATTERN(1).DCC1[0x14a]=0
DCC_LDFF_TRAINING_PATTERN(2).DCC1[0x14b]=0
DCC_LDFF_TRAINING_PATTERN(3).DCC1[0x14c]=0
DCC_LDFF_TRAINING_PATTERN(4).DCC1[0x14d]=0
DCC_LDFF_TRAINING_PATTERN(5).DCC1[0x14e]=0
DCC_LDFF_TRAINING_PATTERN(6).DCC1[0x14f]=0
DCC_LDFF_TRAINING_PATTERN(7).DCC1[0x150]=0
DCC_LDFF_TRAINING_PATTERN(0).DCC2[0x149]=0
DCC_LDFF_TRAINING_PATTERN(1).DCC2[0x14a]=0
DCC_LDFF_TRAINING_PATTERN(2).DCC2[0x14b]=0
DCC_LDFF_TRAINING_PATTERN(3).DCC2[0x14c]=0
DCC_LDFF_TRAINING_PATTERN(4).DCC2[0x14d]=0
DCC_LDFF_TRAINING_PATTERN(5).DCC2[0x14e]=0
DCC_LDFF_TRAINING_PATTERN(6).DCC2[0x14f]=0
DCC_LDFF_TRAINING_PATTERN(7).DCC2[0x150]=0
DCC_LDFF_TRAINING_PATTERN(0).DCC3[0x149]=0
DCC_LDFF_TRAINING_PATTERN(1).DCC3[0x14a]=0
DCC_LDFF_TRAINING_PATTERN(2).DCC3[0x14b]=0
DCC_LDFF_TRAINING_PATTERN(3).DCC3[0x14c]=0
DCC_LDFF_TRAINING_PATTERN(4).DCC3[0x14d]=0
DCC_LDFF_TRAINING_PATTERN(5).DCC3[0x14e]=0
DCC_LDFF_TRAINING_PATTERN(6).DCC3[0x14f]=0
DCC_LDFF_TRAINING_PATTERN(7).DCC3[0x150]=0
DCC_PARITY_ERR_CNT.DCC0[0x98]=0
DCC_PARITY_ERR_CNT.DCC1[0x98]=0
DCC_PARITY_ERR_CNT.DCC2[0x98]=0
DCC_PARITY_ERR_CNT.DCC3[0x98]=0
DCC_PAR_ERR_MEM_MASK.DCC0[0xa0]=0xff
DCC_PAR_ERR_MEM_MASK.DCC1[0xa0]=0xff
DCC_PAR_ERR_MEM_MASK.DCC2[0xa0]=0xff
DCC_PAR_ERR_MEM_MASK.DCC3[0xa0]=0xff
DCC_PERIODIC_TEMPERATURE_READOUT_CFG.DCC0[0x180]=0x888410504
DCC_PERIODIC_TEMPERATURE_READOUT_CFG.DCC1[0x180]=0x888410504
DCC_PERIODIC_TEMPERATURE_READOUT_CFG.DCC2[0x180]=0x888410504
DCC_PERIODIC_TEMPERATURE_READOUT_CFG.DCC3[0x180]=0x888410504
DCC_PIPELINES_BANK_REMAPPING.DCC0[0x130]=0x688
DCC_PIPELINES_BANK_REMAPPING.DCC1[0x130]=0x688
DCC_PIPELINES_BANK_REMAPPING.DCC2[0x130]=0x688
DCC_PIPELINES_BANK_REMAPPING.DCC3[0x130]=0x688
DCC_PIPELINES_CONFIG.DCC0[0x12d]=0x22d8
DCC_PIPELINES_CONFIG.DCC1[0x12d]=0x22d8
DCC_PIPELINES_CONFIG.DCC2[0x12d]=0x22d8
DCC_PIPELINES_CONFIG.DCC3[0x12d]=0x22d8
DCC_PIPELINES_DEBUG.DCC0[0x136]=0
DCC_PIPELINES_DEBUG.DCC1[0x136]=0
DCC_PIPELINES_DEBUG.DCC2[0x136]=0
DCC_PIPELINES_DEBUG.DCC3[0x136]=0
DCC_PIPELINES_INTERRUPT_MASK_REGISTER.DCC0[0x110]=0
DCC_PIPELINES_INTERRUPT_MASK_REGISTER.DCC1[0x110]=0
DCC_PIPELINES_INTERRUPT_MASK_REGISTER.DCC2[0x110]=0
DCC_PIPELINES_INTERRUPT_MASK_REGISTER.DCC3[0x110]=0
DCC_PIPELINES_INTERRUPT_REGISTER.DCC0[0x10f]=0
DCC_PIPELINES_INTERRUPT_REGISTER.DCC1[0x10f]=0
DCC_PIPELINES_INTERRUPT_REGISTER.DCC2[0x10f]=0
DCC_PIPELINES_INTERRUPT_REGISTER.DCC3[0x10f]=0
DCC_PIPELINES_INTERRUPT_REGISTER_TEST.DCC0[0x111]=0
DCC_PIPELINES_INTERRUPT_REGISTER_TEST.DCC1[0x111]=0
DCC_PIPELINES_INTERRUPT_REGISTER_TEST.DCC2[0x111]=0
DCC_PIPELINES_INTERRUPT_REGISTER_TEST.DCC3[0x111]=0
DCC_PRBS_SEED.DCC0[0x159]=0x89abcdef789abcde6789abcd56789abc456789ab3456789a2345678912345678
DCC_PRBS_SEED.DCC1[0x159]=0x89abcdef789abcde6789abcd56789abc456789ab3456789a2345678912345678
DCC_PRBS_SEED.DCC2[0x159]=0x89abcdef789abcde6789abcd56789abc456789ab3456789a2345678912345678
DCC_PRBS_SEED.DCC3[0x159]=0x89abcdef789abcde6789abcd56789abc456789ab3456789a2345678912345678
DCC_RDR_ASYNC_FIFO_CONFIG(0).DCC0[0x118]=0
DCC_RDR_ASYNC_FIFO_CONFIG(0).DCC1[0x118]=0
DCC_RDR_ASYNC_FIFO_CONFIG(0).DCC2[0x118]=0
DCC_RDR_ASYNC_FIFO_CONFIG(0).DCC3[0x118]=0
DCC_RDR_INTERRUPT_MASK_REGISTER.DCC0[0x104]=0
DCC_RDR_INTERRUPT_MASK_REGISTER.DCC1[0x104]=0
DCC_RDR_INTERRUPT_MASK_REGISTER.DCC2[0x104]=0
DCC_RDR_INTERRUPT_MASK_REGISTER.DCC3[0x104]=0
DCC_RDR_INTERRUPT_REGISTER.DCC0[0x103]=0
DCC_RDR_INTERRUPT_REGISTER.DCC1[0x103]=0
DCC_RDR_INTERRUPT_REGISTER.DCC2[0x103]=0
DCC_RDR_INTERRUPT_REGISTER.DCC3[0x103]=0
DCC_RDR_INTERRUPT_REGISTER_TEST.DCC0[0x105]=0
DCC_RDR_INTERRUPT_REGISTER_TEST.DCC1[0x105]=0
DCC_RDR_INTERRUPT_REGISTER_TEST.DCC2[0x105]=0
DCC_RDR_INTERRUPT_REGISTER_TEST.DCC3[0x105]=0
DCC_RDR_RD_INFO_WMK.DCC0[0x120]=0
DCC_RDR_RD_INFO_WMK.DCC1[0x120]=0
DCC_RDR_RD_INFO_WMK.DCC2[0x120]=0
DCC_RDR_RD_INFO_WMK.DCC3[0x120]=0
DCC_RDR_TOT_TRANS_CNT.DCC0[0x11f]=0
DCC_RDR_TOT_TRANS_CNT.DCC1[0x11f]=0
DCC_RDR_TOT_TRANS_CNT.DCC2[0x11f]=0
DCC_RDR_TOT_TRANS_CNT.DCC3[0x11f]=0
DCC_READ_DATA_REORDER_STATUS(0).DCC0[0x119]=0
DCC_READ_DATA_REORDER_STATUS(0).DCC1[0x119]=0
DCC_READ_DATA_REORDER_STATUS(0).DCC2[0x119]=0
DCC_READ_DATA_REORDER_STATUS(0).DCC3[0x119]=0
DCC_REG_0041.DCC0[0x41]=0
DCC_REG_0041.DCC1[0x41]=0
DCC_REG_0041.DCC2[0x41]=0
DCC_REG_0041.DCC3[0x41]=0
DCC_REG_00C2.DCC0[0xc2]=0x10
DCC_REG_00C2.DCC1[0xc2]=0x10
DCC_REG_00C2.DCC2[0xc2]=0x10
DCC_REG_00C2.DCC3[0xc2]=0x10
DCC_REQ_ARB_ASYNC_FIFO_CONFIG.DCC0[0x116]=0
DCC_REQ_ARB_ASYNC_FIFO_CONFIG.DCC1[0x116]=0
DCC_REQ_ARB_ASYNC_FIFO_CONFIG.DCC2[0x116]=0
DCC_REQ_ARB_ASYNC_FIFO_CONFIG.DCC3[0x116]=0
DCC_RESERVED_MTCD.DCC0[0xae]=0x30
DCC_RESERVED_MTCD.DCC1[0xae]=0x30
DCC_RESERVED_MTCD.DCC2[0xae]=0x30
DCC_RESERVED_MTCD.DCC3[0xae]=0x30
DCC_RESERVED_MTCP.DCC0[0xad]=0x300000600000000
DCC_RESERVED_MTCP.DCC1[0xad]=0x300000600000000
DCC_RESERVED_MTCP.DCC2[0xad]=0x300000600000000
DCC_RESERVED_MTCP.DCC3[0xad]=0x300000600000000
DCC_RESERVED_SPARE_0.DCC0[0x90]=0xffffffff
DCC_RESERVED_SPARE_0.DCC1[0x90]=0xffffffff
DCC_RESERVED_SPARE_0.DCC2[0x90]=0xffffffff
DCC_RESERVED_SPARE_0.DCC3[0x90]=0xffffffff
DCC_RESERVED_SPARE_1.DCC0[0x91]=0xffffffff
DCC_RESERVED_SPARE_1.DCC1[0x91]=0xffffffff
DCC_RESERVED_SPARE_1.DCC2[0x91]=0xffffffff
DCC_RESERVED_SPARE_1.DCC3[0x91]=0xffffffff
DCC_RESERVED_SPARE_2.DCC0[0x92]=0
DCC_RESERVED_SPARE_2.DCC1[0x92]=0
DCC_RESERVED_SPARE_2.DCC2[0x92]=0
DCC_RESERVED_SPARE_2.DCC3[0x92]=0
DCC_RESERVED_SPARE_3.DCC0[0x93]=0
DCC_RESERVED_SPARE_3.DCC1[0x93]=0
DCC_RESERVED_SPARE_3.DCC2[0x93]=0
DCC_RESERVED_SPARE_3.DCC3[0x93]=0
DCC_RPBQ_CONFIG.DCC0[0x11d]=0x110
DCC_RPBQ_CONFIG.DCC1[0x11d]=0x110
DCC_RPBQ_CONFIG.DCC2[0x11d]=0x110
DCC_RPBQ_CONFIG.DCC3[0x11d]=0x110
DCC_RPBQ_STATUS.DCC0[0x11e]=0
DCC_RPBQ_STATUS.DCC1[0x11e]=0
DCC_RPBQ_STATUS.DCC2[0x11e]=0
DCC_RPBQ_STATUS.DCC3[0x11e]=0
DCC_SBUS_BROADCAST_ID.DCC0[0x86]=0x7a0
DCC_SBUS_BROADCAST_ID.DCC1[0x86]=0x7a0
DCC_SBUS_BROADCAST_ID.DCC2[0x86]=0x7a0
DCC_SBUS_BROADCAST_ID.DCC3[0x86]=0x7a0
DCC_SBUS_LAST_IN_CHAIN.DCC0[0x87]=0
DCC_SBUS_LAST_IN_CHAIN.DCC1[0x87]=0
DCC_SBUS_LAST_IN_CHAIN.DCC2[0x87]=0
DCC_SBUS_LAST_IN_CHAIN.DCC3[0x87]=0
DCC_SPECIAL_CLOCK_CONTROLS.DCC0[0xc1]=2
DCC_SPECIAL_CLOCK_CONTROLS.DCC1[0xc1]=2
DCC_SPECIAL_CLOCK_CONTROLS.DCC2[0xc1]=2
DCC_SPECIAL_CLOCK_CONTROLS.DCC3[0xc1]=2
DCC_SW_DYNAMIC_CALIBRATION_CONTROL.DCC0[0x16e]=0
DCC_SW_DYNAMIC_CALIBRATION_CONTROL.DCC1[0x16e]=0
DCC_SW_DYNAMIC_CALIBRATION_CONTROL.DCC2[0x16e]=0
DCC_SW_DYNAMIC_CALIBRATION_CONTROL.DCC3[0x16e]=0
DCC_SW_TEMPERATURE_READOUT_CONTROL.DCC0[0x181]=0
DCC_SW_TEMPERATURE_READOUT_CONTROL.DCC1[0x181]=0
DCC_SW_TEMPERATURE_READOUT_CONTROL.DCC2[0x181]=0
DCC_SW_TEMPERATURE_READOUT_CONTROL.DCC3[0x181]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_MASK_REGISTER.DCC0[0x10a]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_MASK_REGISTER.DCC1[0x10a]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_MASK_REGISTER.DCC2[0x10a]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_MASK_REGISTER.DCC3[0x10a]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER.DCC0[0x109]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER.DCC1[0x109]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER.DCC2[0x109]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER.DCC3[0x109]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER_TEST.DCC0[0x10b]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER_TEST.DCC1[0x10b]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER_TEST.DCC2[0x10b]=0
DCC_TEMPERATURE_READOUT_INTERRUPT_REGISTER_TEST.DCC3[0x10b]=0
DCC_TEMPERATURE_READOUT_STATUS.DCC0[0x183]=0
DCC_TEMPERATURE_READOUT_STATUS.DCC1[0x183]=0
DCC_TEMPERATURE_READOUT_STATUS.DCC2[0x183]=0
DCC_TEMPERATURE_READOUT_STATUS.DCC3[0x183]=0
DCC_TEMPERATURE_READOUT_WMK.DCC0[0x182]=0
DCC_TEMPERATURE_READOUT_WMK.DCC1[0x182]=0
DCC_TEMPERATURE_READOUT_WMK.DCC2[0x182]=0
DCC_TEMPERATURE_READOUT_WMK.DCC3[0x182]=0
DCC_TRAINING_BIST_COMMAND_CONFIG.DCC0[0x13b]=0x3d5b6000000000c
DCC_TRAINING_BIST_COMMAND_CONFIG.DCC1[0x13b]=0x3d5b6000000000c
DCC_TRAINING_BIST_COMMAND_CONFIG.DCC2[0x13b]=0x3d5b6000000000c
DCC_TRAINING_BIST_COMMAND_CONFIG.DCC3[0x13b]=0x3d5b6000000000c
DCC_TRAINING_CADT_CONFIG.DCC0[0x13c]=0x20000000c0
DCC_TRAINING_CADT_CONFIG.DCC1[0x13c]=0x30000000c0
DCC_TRAINING_CADT_CONFIG.DCC2[0x13c]=0x20000000c0
DCC_TRAINING_CADT_CONFIG.DCC3[0x13c]=0x30000000c0
DCC_TSM_CONFIG.DCC0[0x12a]=0x694000800f0000
DCC_TSM_CONFIG.DCC1[0x12a]=0x694000800f0000
DCC_TSM_CONFIG.DCC2[0x12a]=0x694000800f0000
DCC_TSM_CONFIG.DCC3[0x12a]=0x694000800f0000
DCC_TSM_DEBUG.DCC0[0x12c]=0x1000000000000000000b0149c5993
DCC_TSM_DEBUG.DCC1[0x12c]=0x1000000000000000000b0149cb264
DCC_TSM_DEBUG.DCC2[0x12c]=0x1000000000000000000b0149d0f83
DCC_TSM_DEBUG.DCC3[0x12c]=0x1000000000000000000b0149d6df8
DCC_TSM_INTERRUPT_MASK_REGISTER.DCC0[0x10d]=0
DCC_TSM_INTERRUPT_MASK_REGISTER.DCC1[0x10d]=0
DCC_TSM_INTERRUPT_MASK_REGISTER.DCC2[0x10d]=0
DCC_TSM_INTERRUPT_MASK_REGISTER.DCC3[0x10d]=0
DCC_TSM_INTERRUPT_REGISTER.DCC0[0x10c]=0
DCC_TSM_INTERRUPT_REGISTER.DCC1[0x10c]=0
DCC_TSM_INTERRUPT_REGISTER.DCC2[0x10c]=0
DCC_TSM_INTERRUPT_REGISTER.DCC3[0x10c]=0
DCC_TSM_INTERRUPT_REGISTER_TEST.DCC0[0x10e]=0
DCC_TSM_INTERRUPT_REGISTER_TEST.DCC1[0x10e]=0
DCC_TSM_INTERRUPT_REGISTER_TEST.DCC2[0x10e]=0
DCC_TSM_INTERRUPT_REGISTER_TEST.DCC3[0x10e]=0
DCC_TSM_READ_WRITE_SWITCH_CONFIG.DCC0[0x12b]=0x320c350108805c082082
DCC_TSM_READ_WRITE_SWITCH_CONFIG.DCC1[0x12b]=0x320c350108805c082082
DCC_TSM_READ_WRITE_SWITCH_CONFIG.DCC2[0x12b]=0x320c350108805c082082
DCC_TSM_READ_WRITE_SWITCH_CONFIG.DCC3[0x12b]=0x320c350108805c082082
DCC_VENDOR_ID_CONFIG.DCC0[0x13d]=0xa1
DCC_VENDOR_ID_CONFIG.DCC1[0x13d]=0xa1
DCC_VENDOR_ID_CONFIG.DCC2[0x13d]=0xa1
DCC_VENDOR_ID_CONFIG.DCC3[0x13d]=0xa1
DCC_WDB_STATUS.DCC0[0x11a]=0
DCC_WDB_STATUS.DCC1[0x11a]=0
DCC_WDB_STATUS.DCC2[0x11a]=0
DCC_WDB_STATUS.DCC3[0x11a]=0
DCC_WDS_ASYNC_FIFO_CONFI.DCC0[0x117]=0
DCC_WDS_ASYNC_FIFO_CONFI.DCC1[0x117]=0
DCC_WDS_ASYNC_FIFO_CONFI.DCC2[0x117]=0
DCC_WDS_ASYNC_FIFO_CONFI.DCC3[0x117]=0
DCC_WPBQ_CONFIG.DCC0[0x11b]=0x10
DCC_WPBQ_CONFIG.DCC1[0x11b]=0x10
DCC_WPBQ_CONFIG.DCC2[0x11b]=0x10
DCC_WPBQ_CONFIG.DCC3[0x11b]=0x10
DCC_WPBQ_STATUS.DCC0[0x11c]=0
DCC_WPBQ_STATUS.DCC1[0x11c]=0
DCC_WPBQ_STATUS.DCC2[0x11c]=0
DCC_WPBQ_STATUS.DCC3[0x11c]=0
DDHA_ECC_1B_ERR_CNT.DDHA0[0x94]=0
DDHA_ECC_2B_ERR_CNT.DDHA0[0x96]=0
DDHA_ECC_ERR_1B_MONITOR_MEM_MASK.DDHA0[0x9a]=0xffffffff
DDHA_ECC_ERR_2B_MONITOR_MEM_MASK.DDHA0[0x9c]=0xffffffff
DDHA_ECC_INTERRUPT_REGISTER.DDHA0[0x7]=0
DDHA_ECC_INTERRUPT_REGISTER_MASK.DDHA0[0x17]=0
DDHA_ECC_INTERRUPT_REGISTER_TEST.DDHA0[0x1f]=0
DDHA_ENABLE_DYNAMIC_MEMORY_ACCESS.DDHA0[0x84]=0xffffff
DDHA_GTIMER_CONFIGURATION.DDHA0[0x89]=0
DDHA_GTIMER_CYCLE.DDHA0[0x88]=0x3b9aca00
DDHA_INDIRECT_COMMAND.DDHA0[0x80]=0x58200002
DDHA_INDIRECT_COMMAND_ADDRESS.DDHA0[0x81]=0x1f8028
DDHA_INDIRECT_COMMAND_RD_DATA.DDHA0[0x60]=0
DDHA_INDIRECT_COMMAND_WR_DATA.DDHA0[0x20]=0
DDHA_INDIRECT_FORCE_BUBBLE.DDHA0[0x83]=0x20019
DDHA_INDIRECT_WR_MASK.DDHA0[0x40]=0xffffffffffffffffffffffffffffff
DDHA_INTERRUPT_MASK_REGISTER.DDHA0[0x10]=0
DDHA_INTERRUPT_REGISTER.DDHA0[0x0]=0
DDHA_INTERRUPT_REGISTER_TEST.DDHA0[0x18]=0
DDHA_PCMI_0.DDHA0[0xb0]=0x3b9aca00
DDHA_PCMI_1.DDHA0[0xb3]=0x3b9aca00
DDHA_PCMI_2.DDHA0[0xb6]=0x3b9aca00
DDHA_PCMI_3.DDHA0[0xb9]=0x3b9aca00
DDHA_PCMI_4.DDHA0[0xbc]=0x3b9aca00
DDHA_PCMI_0_S.DDHA0[0xb1]=0
DDHA_PCMI_0_T.DDHA0[0xb2]=0
DDHA_PCMI_1_S.DDHA0[0xb4]=0
DDHA_PCMI_1_T.DDHA0[0xb5]=0
DDHA_PCMI_2_S.DDHA0[0xb7]=0
DDHA_PCMI_2_T.DDHA0[0xb8]=0
DDHA_PCMI_3_S.DDHA0[0xba]=0
DDHA_PCMI_3_T.DDHA0[0xbb]=0
DDHA_PCMI_4_S.DDHA0[0xbd]=0
DDHA_PCMI_4_T.DDHA0[0xbe]=0
DDHA_REG_0041.DDHA0[0x41]=0
DDHA_REG_0098.DDHA0[0x98]=0
DDHA_REG_0100.DDHA0[0x100]=0x688
DDHA_REG_0101.DDHA0[0x101]=0x8688
DDHA_REG_0102.DDHA0[0x102]=0x7113333
DDHA_REG_0103.DDHA0[0x103]=0x3764ac71c71
DDHA_REG_0105.DDHA0[0x105]=0
DDHA_REG_0106.DDHA0[0x106]=0x49b924
DDHA_REG_0107.DDHA0[0x107]=0x14
DDHA_REG_0108.DDHA0[0x108]=0x7dff1e7
DDHA_REG_0109.DDHA0[0x109]=0x37a000000006208017b569f
DDHA_REG_0134(0).DDHA0[0x134]=0
DDHA_REG_0134(1).DDHA0[0x135]=0
DDHA_REG_0134(2).DDHA0[0x136]=0
DDHA_REG_0134(3).DDHA0[0x137]=0
DDHA_REG_0154.DDHA0[0x154]=0x2c0000
DDHA_REG_0155.DDHA0[0x155]=0x680000
DDHA_REG_0156(0).DDHA0[0x156]=0
DDHA_REG_0156(1).DDHA0[0x157]=0
DDHA_REG_0156(2).DDHA0[0x158]=0
DDHA_REG_0156(3).DDHA0[0x159]=0
DDHA_REG_0156(4).DDHA0[0x15a]=0
DDHA_REG_0156(5).DDHA0[0x15b]=0
DDHA_REG_0156(6).DDHA0[0x15c]=0
DDHA_REG_0156(7).DDHA0[0x15d]=0
DDHA_REG_0166(0).DDHA0[0x166]=0
DDHA_REG_0166(1).DDHA0[0x167]=0
DDHA_REG_0166(2).DDHA0[0x168]=0
DDHA_REG_0166(3).DDHA0[0x169]=0
DDHA_REG_0166(4).DDHA0[0x16a]=0
DDHA_REG_0166(5).DDHA0[0x16b]=0
DDHA_REG_0166(6).DDHA0[0x16c]=0
DDHA_REG_0166(7).DDHA0[0x16d]=0
DDHA_REG_0176(0).DDHA0[0x176]=0
DDHA_REG_0176(1).DDHA0[0x177]=0
DDHA_REG_0176(2).DDHA0[0x178]=0
DDHA_REG_0176(3).DDHA0[0x179]=0
DDHA_REG_0176(4).DDHA0[0x17a]=0
DDHA_REG_0176(5).DDHA0[0x17b]=0
DDHA_REG_0176(6).DDHA0[0x17c]=0
DDHA_REG_0176(7).DDHA0[0x17d]=0
DDHA_REG_0200.DDHA0[0x200]=0
DDHA_REG_0201.DDHA0[0x201]=0x208
DDHA_REG_0202.DDHA0[0x202]=0x10473388
DDHA_REG_0203.DDHA0[0x203]=0x14018b45a7a2b6
DDHA_REG_0205.DDHA0[0x205]=0
DDHA_REG_0206.DDHA0[0x206]=0x4926db
DDHA_REG_0207.DDHA0[0x207]=3
DDHA_REG_0208.DDHA0[0x208]=0x9fd5fe
DDHA_REG_0209.DDHA0[0x209]=0x734c000000000017b3dcd603fb
DDHA_REG_0235(0).DDHA0[0x235]=0
DDHA_REG_0235(1).DDHA0[0x236]=0
DDHA_REG_0235(2).DDHA0[0x237]=0
DDHA_REG_0235(3).DDHA0[0x238]=0
DDHA_REG_0255.DDHA0[0x255]=0x25c000
DDHA_REG_0256.DDHA0[0x256]=0x6d3009
DDHA_REG_0257(0).DDHA0[0x257]=0
DDHA_REG_0257(1).DDHA0[0x258]=0
DDHA_REG_0257(2).DDHA0[0x259]=0
DDHA_REG_0257(3).DDHA0[0x25a]=0
DDHA_REG_0257(4).DDHA0[0x25b]=0
DDHA_REG_0257(5).DDHA0[0x25c]=0
DDHA_REG_0257(6).DDHA0[0x25d]=0
DDHA_REG_0257(7).DDHA0[0x25e]=0
DDHA_REG_0267(0).DDHA0[0x267]=0
DDHA_REG_0267(1).DDHA0[0x268]=0
DDHA_REG_0267(2).DDHA0[0x269]=0
DDHA_REG_0267(3).DDHA0[0x26a]=0
DDHA_REG_0267(4).DDHA0[0x26b]=0
DDHA_REG_0267(5).DDHA0[0x26c]=0
DDHA_REG_0267(6).DDHA0[0x26d]=0
DDHA_REG_0267(7).DDHA0[0x26e]=0
DDHA_REG_0277(0).DDHA0[0x277]=0
DDHA_REG_0277(1).DDHA0[0x278]=0
DDHA_REG_0277(2).DDHA0[0x279]=0
DDHA_REG_0277(3).DDHA0[0x27a]=0
DDHA_REG_0277(4).DDHA0[0x27b]=0
DDHA_REG_0277(5).DDHA0[0x27c]=0
DDHA_REG_0277(6).DDHA0[0x27d]=0
DDHA_REG_0277(7).DDHA0[0x27e]=0
DDHA_REG_0300.DDHA0[0x300]=0xe00240
DDHA_REG_0301.DDHA0[0x301]=0xe08688
DDHA_REG_0302.DDHA0[0x302]=0xc0924
DDHA_REG_0303.DDHA0[0x303]=0x27000c30c30
DDHA_REG_0305.DDHA0[0x305]=0xf
DDHA_REG_0306.DDHA0[0x306]=0xad6db
DDHA_REG_0307.DDHA0[0x307]=0x14
DDHA_REG_0308.DDHA0[0x308]=0xff8dfc
DDHA_REG_0309.DDHA0[0x309]=0x1cdbd0000002f6ad272
DDHA_REG_0335(0).DDHA0[0x335]=0
DDHA_REG_0335(1).DDHA0[0x336]=0
DDHA_REG_0335(2).DDHA0[0x337]=0
DDHA_REG_0335(3).DDHA0[0x338]=0
DDHA_REG_0355.DDHA0[0x355]=0x40249
DDHA_REG_0356.DDHA0[0x356]=0x40249
DDHA_REG_0357(0).DDHA0[0x357]=0
DDHA_REG_0357(1).DDHA0[0x358]=0
DDHA_REG_0357(2).DDHA0[0x359]=0
DDHA_REG_0357(3).DDHA0[0x35a]=0
DDHA_REG_0357(4).DDHA0[0x35b]=0
DDHA_REG_0357(5).DDHA0[0x35c]=0
DDHA_REG_0357(6).DDHA0[0x35d]=0
DDHA_REG_0357(7).DDHA0[0x35e]=0
DDHA_REG_0367(0).DDHA0[0x367]=0
DDHA_REG_0367(1).DDHA0[0x368]=0
DDHA_REG_0367(2).DDHA0[0x369]=0
DDHA_REG_0367(3).DDHA0[0x36a]=0
DDHA_REG_0367(4).DDHA0[0x36b]=0
DDHA_REG_0367(5).DDHA0[0x36c]=0
DDHA_REG_0367(6).DDHA0[0x36d]=0
DDHA_REG_0367(7).DDHA0[0x36e]=0
DDHA_REG_0377(0).DDHA0[0x377]=0
DDHA_REG_0377(1).DDHA0[0x378]=0
DDHA_REG_0377(2).DDHA0[0x379]=0
DDHA_REG_0377(3).DDHA0[0x37a]=0
DDHA_REG_0377(4).DDHA0[0x37b]=0
DDHA_REG_0377(5).DDHA0[0x37c]=0
DDHA_REG_0377(6).DDHA0[0x37d]=0
DDHA_REG_0377(7).DDHA0[0x37e]=0
DDHA_REG_0400.DDHA0[0x400]=0x240
DDHA_REG_0401.DDHA0[0x401]=0x208688
DDHA_REG_0402.DDHA0[0x402]=0xb64000
DDHA_REG_0403.DDHA0[0x403]=0xcf3aaa3c03c0
DDHA_REG_0405.DDHA0[0x405]=0xf0
DDHA_REG_0406.DDHA0[0x406]=0x6db6db
DDHA_REG_0407.DDHA0[0x407]=0x34
DDHA_REG_0408.DDHA0[0x408]=0xff4ff8
DDHA_REG_0409.DDHA0[0x409]=0xffaf60000000000398a4
DDHA_REG_0435(0).DDHA0[0x435]=0
DDHA_REG_0435(1).DDHA0[0x436]=0
DDHA_REG_0435(2).DDHA0[0x437]=0
DDHA_REG_0435(3).DDHA0[0x438]=0
DDHA_REG_0455.DDHA0[0x455]=0x249000
DDHA_REG_0456.DDHA0[0x456]=0x249000
DDHA_REG_0457(0).DDHA0[0x457]=0
DDHA_REG_0457(1).DDHA0[0x458]=0
DDHA_REG_0457(2).DDHA0[0x459]=0
DDHA_REG_0457(3).DDHA0[0x45a]=0
DDHA_REG_0457(4).DDHA0[0x45b]=0
DDHA_REG_0457(5).DDHA0[0x45c]=0
DDHA_REG_0457(6).DDHA0[0x45d]=0
DDHA_REG_0457(7).DDHA0[0x45e]=0
DDHA_REG_0467(0).DDHA0[0x467]=0
DDHA_REG_0467(1).DDHA0[0x468]=0
DDHA_REG_0467(2).DDHA0[0x469]=0
DDHA_REG_0467(3).DDHA0[0x46a]=0
DDHA_REG_0467(4).DDHA0[0x46b]=0
DDHA_REG_0467(5).DDHA0[0x46c]=0
DDHA_REG_0467(6).DDHA0[0x46d]=0
DDHA_REG_0467(7).DDHA0[0x46e]=0
DDHA_REG_0477(0).DDHA0[0x477]=0
DDHA_REG_0477(1).DDHA0[0x478]=0
DDHA_REG_0477(2).DDHA0[0x479]=0
DDHA_REG_0477(3).DDHA0[0x47a]=0
DDHA_REG_0477(4).DDHA0[0x47b]=0
DDHA_REG_0477(5).DDHA0[0x47c]=0
DDHA_REG_0477(6).DDHA0[0x47d]=0
DDHA_REG_0477(7).DDHA0[0x47e]=0
DDHA_REG_00A0.DDHA0[0xa0]=0
DDHA_REG_00C2.DDHA0[0xc2]=0x10
DDHA_REG_010C(0).DDHA0[0x10c]=0
DDHA_REG_010C(1).DDHA0[0x10d]=0
DDHA_REG_010C(2).DDHA0[0x10e]=0
DDHA_REG_010C(3).DDHA0[0x10f]=0
DDHA_REG_010C(4).DDHA0[0x110]=0x33333333222222220000000000000000
DDHA_REG_010C(5).DDHA0[0x111]=0x33333333333333333333333344444444
DDHA_REG_010C(6).DDHA0[0x112]=0xffffffffaaaaaaaa0000000000000000
DDHA_REG_010C(7).DDHA0[0x113]=0xffffffffaaaaaaaa0000000000000000
DDHA_REG_012C(0).DDHA0[0x12c]=0
DDHA_REG_012C(1).DDHA0[0x12d]=0
DDHA_REG_012C(2).DDHA0[0x12e]=0
DDHA_REG_012C(3).DDHA0[0x12f]=0
DDHA_REG_012C(4).DDHA0[0x130]=0
DDHA_REG_012C(5).DDHA0[0x131]=0
DDHA_REG_012C(6).DDHA0[0x132]=0
DDHA_REG_012C(7).DDHA0[0x133]=0
DDHA_REG_015E(0).DDHA0[0x15e]=0
DDHA_REG_015E(1).DDHA0[0x15f]=0
DDHA_REG_015E(2).DDHA0[0x160]=0
DDHA_REG_015E(3).DDHA0[0x161]=0
DDHA_REG_015E(4).DDHA0[0x162]=0
DDHA_REG_015E(5).DDHA0[0x163]=0
DDHA_REG_015E(6).DDHA0[0x164]=0
DDHA_REG_015E(7).DDHA0[0x165]=0
DDHA_REG_016E(0).DDHA0[0x16e]=0
DDHA_REG_016E(1).DDHA0[0x16f]=0
DDHA_REG_016E(2).DDHA0[0x170]=0
DDHA_REG_016E(3).DDHA0[0x171]=0
DDHA_REG_016E(4).DDHA0[0x172]=0
DDHA_REG_016E(5).DDHA0[0x173]=0
DDHA_REG_016E(6).DDHA0[0x174]=0
DDHA_REG_016E(7).DDHA0[0x175]=0
DDHA_REG_017E(0).DDHA0[0x17e]=0
DDHA_REG_017E(1).DDHA0[0x17f]=0
DDHA_REG_017E(2).DDHA0[0x180]=0
DDHA_REG_017E(3).DDHA0[0x181]=0
DDHA_REG_017E(4).DDHA0[0x182]=0
DDHA_REG_017E(5).DDHA0[0x183]=0
DDHA_REG_017E(6).DDHA0[0x184]=0
DDHA_REG_017E(7).DDHA0[0x185]=0
DDHA_REG_020D(0).DDHA0[0x20d]=0x44332200000000004433220000
DDHA_REG_020D(1).DDHA0[0x20e]=0x44332200000000004433220000
DDHA_REG_020D(2).DDHA0[0x20f]=0x33333333222222220000000000000000
DDHA_REG_020D(3).DDHA0[0x210]=0x33333333333333333333333344444444
DDHA_REG_020D(4).DDHA0[0x211]=0x55555555555555550000000000000000
DDHA_REG_020D(5).DDHA0[0x212]=0xffffffffaaaaaaaa0000000000000000
DDHA_REG_020D(6).DDHA0[0x213]=0xffffffffaaaaaaaa0000000000000000
DDHA_REG_020D(7).DDHA0[0x214]=0xffffffffaaaaaaaa0000000000000000
DDHA_REG_022D(0).DDHA0[0x22d]=0
DDHA_REG_022D(1).DDHA0[0x22e]=0
DDHA_REG_022D(2).DDHA0[0x22f]=0
DDHA_REG_022D(3).DDHA0[0x230]=0
DDHA_REG_022D(4).DDHA0[0x231]=0
DDHA_REG_022D(5).DDHA0[0x232]=0
DDHA_REG_022D(6).DDHA0[0x233]=0
DDHA_REG_022D(7).DDHA0[0x234]=0
DDHA_REG_025F(0).DDHA0[0x25f]=0
DDHA_REG_025F(1).DDHA0[0x260]=0
DDHA_REG_025F(2).DDHA0[0x261]=0
DDHA_REG_025F(3).DDHA0[0x262]=0
DDHA_REG_025F(4).DDHA0[0x263]=0
DDHA_REG_025F(5).DDHA0[0x264]=0
DDHA_REG_025F(6).DDHA0[0x265]=0
DDHA_REG_025F(7).DDHA0[0x266]=0
DDHA_REG_026F(0).DDHA0[0x26f]=0
DDHA_REG_026F(1).DDHA0[0x270]=0
DDHA_REG_026F(2).DDHA0[0x271]=0
DDHA_REG_026F(3).DDHA0[0x272]=0
DDHA_REG_026F(4).DDHA0[0x273]=0
DDHA_REG_026F(5).DDHA0[0x274]=0
DDHA_REG_026F(6).DDHA0[0x275]=0
DDHA_REG_026F(7).DDHA0[0x276]=0
DDHA_REG_027F(0).DDHA0[0x27f]=0
DDHA_REG_027F(1).DDHA0[0x280]=0
DDHA_REG_027F(2).DDHA0[0x281]=0
DDHA_REG_027F(3).DDHA0[0x282]=0
DDHA_REG_027F(4).DDHA0[0x283]=0
DDHA_REG_027F(5).DDHA0[0x284]=0
DDHA_REG_027F(6).DDHA0[0x285]=0
DDHA_REG_027F(7).DDHA0[0x286]=0
DDHA_REG_030D(0).DDHA0[0x30d]=0x11113333222200001111333322220000
DDHA_REG_030D(1).DDHA0[0x30e]=0x11113333222200001111333322220000
DDHA_REG_030D(2).DDHA0[0x30f]=0x11113333222200001111333322220000
DDHA_REG_030D(3).DDHA0[0x310]=0x11113333222200001111333322220000
DDHA_REG_030D(4).DDHA0[0x311]=0
DDHA_REG_030D(5).DDHA0[0x312]=0
DDHA_REG_030D(6).DDHA0[0x313]=0x55555555ffffffffaaaaaaaa00000000
DDHA_REG_030D(7).DDHA0[0x314]=0
DDHA_REG_032D(0).DDHA0[0x32d]=0
DDHA_REG_032D(1).DDHA0[0x32e]=0
DDHA_REG_032D(2).DDHA0[0x32f]=0
DDHA_REG_032D(3).DDHA0[0x330]=0
DDHA_REG_032D(4).DDHA0[0x331]=0
DDHA_REG_032D(5).DDHA0[0x332]=0x50505050
DDHA_REG_032D(6).DDHA0[0x333]=0
DDHA_REG_032D(7).DDHA0[0x334]=0
DDHA_REG_035F(0).DDHA0[0x35f]=0
DDHA_REG_035F(1).DDHA0[0x360]=0
DDHA_REG_035F(2).DDHA0[0x361]=0
DDHA_REG_035F(3).DDHA0[0x362]=0
DDHA_REG_035F(4).DDHA0[0x363]=0
DDHA_REG_035F(5).DDHA0[0x364]=0
DDHA_REG_035F(6).DDHA0[0x365]=0
DDHA_REG_035F(7).DDHA0[0x366]=0
DDHA_REG_036F(0).DDHA0[0x36f]=0
DDHA_REG_036F(1).DDHA0[0x370]=0
DDHA_REG_036F(2).DDHA0[0x371]=0
DDHA_REG_036F(3).DDHA0[0x372]=0
DDHA_REG_036F(4).DDHA0[0x373]=0
DDHA_REG_036F(5).DDHA0[0x374]=0
DDHA_REG_036F(6).DDHA0[0x375]=0
DDHA_REG_036F(7).DDHA0[0x376]=0
DDHA_REG_037F(0).DDHA0[0x37f]=0
DDHA_REG_037F(1).DDHA0[0x380]=0
DDHA_REG_037F(2).DDHA0[0x381]=0
DDHA_REG_037F(3).DDHA0[0x382]=0
DDHA_REG_037F(4).DDHA0[0x383]=0
DDHA_REG_037F(5).DDHA0[0x384]=0
DDHA_REG_037F(6).DDHA0[0x385]=0
DDHA_REG_037F(7).DDHA0[0x386]=0
DDHA_REG_040D(0).DDHA0[0x40d]=0x33333333222222220000000000000000
DDHA_REG_040D(1).DDHA0[0x40e]=0x33333333333333333333333344444444
DDHA_REG_040D(2).DDHA0[0x40f]=0x33333333222222220000000000000000
DDHA_REG_040D(3).DDHA0[0x410]=0x33333333333333333333333344444444
DDHA_REG_040D(4).DDHA0[0x411]=0x22222222222222220000000000000000
DDHA_REG_040D(5).DDHA0[0x412]=0x11111111111111113333333333333333
DDHA_REG_040D(6).DDHA0[0x413]=0x11113333222200001111333322220000
DDHA_REG_040D(7).DDHA0[0x414]=0x11113333222200001111333322220000
DDHA_REG_042D(0).DDHA0[0x42d]=0
DDHA_REG_042D(1).DDHA0[0x42e]=0
DDHA_REG_042D(2).DDHA0[0x42f]=0
DDHA_REG_042D(3).DDHA0[0x430]=0
DDHA_REG_042D(4).DDHA0[0x431]=0
DDHA_REG_042D(5).DDHA0[0x432]=0
DDHA_REG_042D(6).DDHA0[0x433]=0
DDHA_REG_042D(7).DDHA0[0x434]=0
DDHA_REG_045F(0).DDHA0[0x45f]=0
DDHA_REG_045F(1).DDHA0[0x460]=0
DDHA_REG_045F(2).DDHA0[0x461]=0
DDHA_REG_045F(3).DDHA0[0x462]=0
DDHA_REG_045F(4).DDHA0[0x463]=0
DDHA_REG_045F(5).DDHA0[0x464]=0
DDHA_REG_045F(6).DDHA0[0x465]=0
DDHA_REG_045F(7).DDHA0[0x466]=0
DDHA_REG_046F(0).DDHA0[0x46f]=0
DDHA_REG_046F(1).DDHA0[0x470]=0
DDHA_REG_046F(2).DDHA0[0x471]=0
DDHA_REG_046F(3).DDHA0[0x472]=0
DDHA_REG_046F(4).DDHA0[0x473]=0
DDHA_REG_046F(5).DDHA0[0x474]=0
DDHA_REG_046F(6).DDHA0[0x475]=0
DDHA_REG_046F(7).DDHA0[0x476]=0
DDHA_REG_047F(0).DDHA0[0x47f]=0
DDHA_REG_047F(1).DDHA0[0x480]=0
DDHA_REG_047F(2).DDHA0[0x481]=0
DDHA_REG_047F(3).DDHA0[0x482]=0
DDHA_REG_047F(4).DDHA0[0x483]=0
DDHA_REG_047F(5).DDHA0[0x484]=0
DDHA_REG_047F(6).DDHA0[0x485]=0
DDHA_REG_047F(7).DDHA0[0x486]=0
DDHA_RESERVED_MIRROR_ADDR.DDHA0[0x85]=0
DDHA_RESERVED_MTCD.DDHA0[0xae]=0x30
DDHA_RESERVED_MTCP.DDHA0[0xad]=0x300000600000000
DDHA_RESERVED_SPARE_0.DDHA0[0x90]=0xffffffff
DDHA_RESERVED_SPARE_1.DDHA0[0x91]=0xffffffff
DDHA_RESERVED_SPARE_2.DDHA0[0x92]=0
DDHA_RESERVED_SPARE_3.DDHA0[0x93]=0
DDHA_SBUS_BROADCAST_ID.DDHA0[0x86]=0x7ff
DDHA_SBUS_LAST_IN_CHAIN.DDHA0[0x87]=0
DDHA_SPECIAL_CLOCK_CONTROLS.DDHA0[0xc1]=2
DDHB_ECC_1B_ERR_CNT.DDHB0[0x94]=0
DDHB_ECC_1B_ERR_CNT.DDHB1[0x94]=0
DDHB_ECC_1B_ERR_CNT.DDHB2[0x94]=0
DDHB_ECC_1B_ERR_CNT.DDHB3[0x94]=0
DDHB_ECC_2B_ERR_CNT.DDHB0[0x96]=0
DDHB_ECC_2B_ERR_CNT.DDHB1[0x96]=0
DDHB_ECC_2B_ERR_CNT.DDHB2[0x96]=0
DDHB_ECC_2B_ERR_CNT.DDHB3[0x96]=0
DDHB_ECC_ERR_1B_MONITOR_MEM_MASK.DDHB0[0x9a]=0xffffffff
DDHB_ECC_ERR_1B_MONITOR_MEM_MASK.DDHB1[0x9a]=0xffffffff
DDHB_ECC_ERR_1B_MONITOR_MEM_MASK.DDHB2[0x9a]=0xffffffff
DDHB_ECC_ERR_1B_MONITOR_MEM_MASK.DDHB3[0x9a]=0xffffffff
DDHB_ECC_ERR_2B_MONITOR_MEM_MASK.DDHB0[0x9c]=0xffffffff
DDHB_ECC_ERR_2B_MONITOR_MEM_MASK.DDHB1[0x9c]=0xffffffff
DDHB_ECC_ERR_2B_MONITOR_MEM_MASK.DDHB2[0x9c]=0xffffffff
DDHB_ECC_ERR_2B_MONITOR_MEM_MASK.DDHB3[0x9c]=0xffffffff
DDHB_ECC_INTERRUPT_REGISTER.DDHB0[0x7]=0
DDHB_ECC_INTERRUPT_REGISTER.DDHB1[0x7]=0
DDHB_ECC_INTERRUPT_REGISTER.DDHB2[0x7]=0
DDHB_ECC_INTERRUPT_REGISTER.DDHB3[0x7]=0
DDHB_ECC_INTERRUPT_REGISTER_MASK.DDHB0[0x17]=0
DDHB_ECC_INTERRUPT_REGISTER_MASK.DDHB1[0x17]=0
DDHB_ECC_INTERRUPT_REGISTER_MASK.DDHB2[0x17]=0
DDHB_ECC_INTERRUPT_REGISTER_MASK.DDHB3[0x17]=0
DDHB_ECC_INTERRUPT_REGISTER_TEST.DDHB0[0x1f]=0
DDHB_ECC_INTERRUPT_REGISTER_TEST.DDHB1[0x1f]=0
DDHB_ECC_INTERRUPT_REGISTER_TEST.DDHB2[0x1f]=0
DDHB_ECC_INTERRUPT_REGISTER_TEST.DDHB3[0x1f]=0
DDHB_ENABLE_DYNAMIC_MEMORY_ACCESS.DDHB0[0x84]=0xffffff
DDHB_ENABLE_DYNAMIC_MEMORY_ACCESS.DDHB1[0x84]=0xffffff
DDHB_ENABLE_DYNAMIC_MEMORY_ACCESS.DDHB2[0x84]=0xffffff
DDHB_ENABLE_DYNAMIC_MEMORY_ACCESS.DDHB3[0x84]=0xffffff
DDHB_GTIMER_CONFIGURATION.DDHB0[0x89]=0
DDHB_GTIMER_CONFIGURATION.DDHB1[0x89]=0
DDHB_GTIMER_CONFIGURATION.DDHB2[0x89]=0
DDHB_GTIMER_CONFIGURATION.DDHB3[0x89]=0
DDHB_GTIMER_CYCLE.DDHB0[0x88]=0x3b9aca00
DDHB_GTIMER_CYCLE.DDHB1[0x88]=0x3b9aca00
DDHB_GTIMER_CYCLE.DDHB2[0x88]=0x3b9aca00
DDHB_GTIMER_CYCLE.DDHB3[0x88]=0x3b9aca00
DDHB_INDIRECT_COMMAND.DDHB0[0x80]=0x58200002
DDHB_INDIRECT_COMMAND.DDHB1[0x80]=0x58200002
DDHB_INDIRECT_COMMAND.DDHB2[0x80]=0x58200002
DDHB_INDIRECT_COMMAND.DDHB3[0x80]=0x58200002
DDHB_INDIRECT_COMMAND_ADDRESS.DDHB0[0x81]=0x639e001
DDHB_INDIRECT_COMMAND_ADDRESS.DDHB1[0x81]=0x619e060
DDHB_INDIRECT_COMMAND_ADDRESS.DDHB2[0x81]=0x6000001
DDHB_INDIRECT_COMMAND_ADDRESS.DDHB3[0x81]=0x853e6006
DDHB_INDIRECT_COMMAND_RD_DATA.DDHB0[0x60]=2
DDHB_INDIRECT_COMMAND_RD_DATA.DDHB1[0x60]=2
DDHB_INDIRECT_COMMAND_RD_DATA.DDHB2[0x60]=2
DDHB_INDIRECT_COMMAND_RD_DATA.DDHB3[0x60]=0xdf00
DDHB_INDIRECT_COMMAND_WR_DATA.DDHB0[0x20]=0x4000a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000
DDHB_INDIRECT_COMMAND_WR_DATA.DDHB1[0x20]=0x180443300fe0a0000000100004c000000000000000000000000000000000000000000000000000000000000000
DDHB_INDIRECT_COMMAND_WR_DATA.DDHB2[0x20]=0x40004282ddbee040004282ddc0000000000000000000000000000000000000000000000000000000000000000000000000000000000005333553334
DDHB_INDIRECT_COMMAND_WR_DATA.DDHB3[0x20]=0x540000017f0000000000000000
DDHB_INDIRECT_FORCE_BUBBLE.DDHB0[0x83]=0x20019
DDHB_INDIRECT_FORCE_BUBBLE.DDHB1[0x83]=0x20019
DDHB_INDIRECT_FORCE_BUBBLE.DDHB2[0x83]=0x20019
DDHB_INDIRECT_FORCE_BUBBLE.DDHB3[0x83]=0x20019
DDHB_INDIRECT_WR_MASK.DDHB0[0x40]=0xffffffffffffffffffffffffffffff
DDHB_INDIRECT_WR_MASK.DDHB1[0x40]=0xffffffffffffffffffffffffffffff
DDHB_INDIRECT_WR_MASK.DDHB2[0x40]=0xffffffffffffffffffffffffffffff
DDHB_INDIRECT_WR_MASK.DDHB3[0x40]=0xffffffffffffffffffffffffffffff
DDHB_INTERRUPT_MASK_REGISTER.DDHB0[0x10]=0
DDHB_INTERRUPT_MASK_REGISTER.DDHB1[0x10]=0
DDHB_INTERRUPT_MASK_REGISTER.DDHB2[0x10]=0
DDHB_INTERRUPT_MASK_REGISTER.DDHB3[0x10]=0
DDHB_INTERRUPT_REGISTER.DDHB0[0x0]=0
DDHB_INTERRUPT_REGISTER.DDHB1[0x0]=0
DDHB_INTERRUPT_REGISTER.DDHB2[0x0]=0
DDHB_INTERRUPT_REGISTER.DDHB3[0x0]=0
DDHB_INTERRUPT_REGISTER_TEST.DDHB0[0x18]=0
DDHB_INTERRUPT_REGISTER_TEST.DDHB1[0x18]=0
DDHB_INTERRUPT_REGISTER_TEST.DDHB2[0x18]=0
DDHB_INTERRUPT_REGISTER_TEST.DDHB3[0x18]=0
DDHB_PCMI_0.DDHB0[0xb0]=0x3b9aca00
DDHB_PCMI_0.DDHB1[0xb0]=0x3b9aca00
DDHB_PCMI_0.DDHB2[0xb0]=0x3b9aca00
DDHB_PCMI_0.DDHB3[0xb0]=0x3b9aca00
DDHB_PCMI_1.DDHB0[0xb3]=0x3b9aca00
DDHB_PCMI_1.DDHB1[0xb3]=0x3b9aca00
DDHB_PCMI_1.DDHB2[0xb3]=0x3b9aca00
DDHB_PCMI_1.DDHB3[0xb3]=0x3b9aca00
DDHB_PCMI_2.DDHB0[0xb6]=0x3b9aca00
DDHB_PCMI_2.DDHB1[0xb6]=0x3b9aca00
DDHB_PCMI_2.DDHB2[0xb6]=0x3b9aca00
DDHB_PCMI_2.DDHB3[0xb6]=0x3b9aca00
DDHB_PCMI_3.DDHB0[0xb9]=0x3b9aca00
DDHB_PCMI_3.DDHB1[0xb9]=0x3b9aca00
DDHB_PCMI_3.DDHB2[0xb9]=0x3b9aca00
DDHB_PCMI_3.DDHB3[0xb9]=0x3b9aca00
DDHB_PCMI_4.DDHB0[0xbc]=0x3b9aca00
DDHB_PCMI_4.DDHB1[0xbc]=0x3b9aca00
DDHB_PCMI_4.DDHB2[0xbc]=0x3b9aca00
DDHB_PCMI_4.DDHB3[0xbc]=0x3b9aca00
DDHB_PCMI_0_S.DDHB0[0xb1]=0
DDHB_PCMI_0_S.DDHB1[0xb1]=0
DDHB_PCMI_0_S.DDHB2[0xb1]=0
DDHB_PCMI_0_S.DDHB3[0xb1]=0
DDHB_PCMI_0_T.DDHB0[0xb2]=0
DDHB_PCMI_0_T.DDHB1[0xb2]=0
DDHB_PCMI_0_T.DDHB2[0xb2]=0
DDHB_PCMI_0_T.DDHB3[0xb2]=0
DDHB_PCMI_1_S.DDHB0[0xb4]=0
DDHB_PCMI_1_S.DDHB1[0xb4]=0
DDHB_PCMI_1_S.DDHB2[0xb4]=0
DDHB_PCMI_1_S.DDHB3[0xb4]=0
DDHB_PCMI_1_T.DDHB0[0xb5]=0
DDHB_PCMI_1_T.DDHB1[0xb5]=0
DDHB_PCMI_1_T.DDHB2[0xb5]=0
DDHB_PCMI_1_T.DDHB3[0xb5]=0
DDHB_PCMI_2_S.DDHB0[0xb7]=0
DDHB_PCMI_2_S.DDHB1[0xb7]=0
DDHB_PCMI_2_S.DDHB2[0xb7]=0
DDHB_PCMI_2_S.DDHB3[0xb7]=0
DDHB_PCMI_2_T.DDHB0[0xb8]=0
DDHB_PCMI_2_T.DDHB1[0xb8]=0
DDHB_PCMI_2_T.DDHB2[0xb8]=0
DDHB_PCMI_2_T.DDHB3[0xb8]=0
DDHB_PCMI_3_S.DDHB0[0xba]=0
DDHB_PCMI_3_S.DDHB1[0xba]=0
DDHB_PCMI_3_S.DDHB2[0xba]=0
DDHB_PCMI_3_S.DDHB3[0xba]=0
DDHB_PCMI_3_T.DDHB0[0xbb]=0
DDHB_PCMI_3_T.DDHB1[0xbb]=0
DDHB_PCMI_3_T.DDHB2[0xbb]=0
DDHB_PCMI_3_T.DDHB3[0xbb]=0
DDHB_PCMI_4_S.DDHB0[0xbd]=0
DDHB_PCMI_4_S.DDHB1[0xbd]=0
DDHB_PCMI_4_S.DDHB2[0xbd]=0
DDHB_PCMI_4_S.DDHB3[0xbd]=0
DDHB_PCMI_4_T.DDHB0[0xbe]=0
DDHB_PCMI_4_T.DDHB1[0xbe]=0
DDHB_PCMI_4_T.DDHB2[0xbe]=0
DDHB_PCMI_4_T.DDHB3[0xbe]=0
DDHB_REG_0041.DDHB0[0x41]=0
DDHB_REG_0041.DDHB1[0x41]=0
DDHB_REG_0041.DDHB2[0x41]=0
DDHB_REG_0041.DDHB3[0x41]=0
DDHB_REG_0098.DDHB0[0x98]=0
DDHB_REG_0098.DDHB1[0x98]=0
DDHB_REG_0098.DDHB2[0x98]=0
DDHB_REG_0098.DDHB3[0x98]=0
DDHB_REG_0100.DDHB0[0x100]=0x249000
DDHB_REG_0100.DDHB1[0x100]=0x240
DDHB_REG_0100.DDHB2[0x100]=0xff8240
DDHB_REG_0100.DDHB3[0x100]=0xfe46c0
DDHB_REG_0101.DDHB0[0x101]=0xfac688
DDHB_REG_0101.DDHB1[0x101]=0x688
DDHB_REG_0101.DDHB2[0x101]=0xff8688
DDHB_REG_0101.DDHB3[0x101]=0xf88f88
DDHB_REG_0102.DDHB0[0x102]=0x492492
DDHB_REG_0102.DDHB1[0x102]=0x2f4000
DDHB_REG_0102.DDHB2[0x102]=0x3000
DDHB_REG_0102.DDHB3[0x102]=0x91b6db
DDHB_REG_0103.DDHB0[0x103]=0x505505505505
DDHB_REG_0103.DDHB1[0x103]=0x15989c000000
DDHB_REG_0103.DDHB2[0x103]=0x28000000
DDHB_REG_0103.DDHB3[0x103]=0x32032032032
DDHB_REG_0105.DDHB0[0x105]=0
DDHB_REG_0105.DDHB1[0x105]=0xf
DDHB_REG_0105.DDHB2[0x105]=0
DDHB_REG_0105.DDHB3[0x105]=0
DDHB_REG_0106.DDHB0[0x106]=0
DDHB_REG_0106.DDHB1[0x106]=0x4926db
DDHB_REG_0106.DDHB2[0x106]=0x2b6d
DDHB_REG_0106.DDHB3[0x106]=0xb6db6d
DDHB_REG_0107.DDHB0[0x107]=0x4c
DDHB_REG_0107.DDHB1[0x107]=4
DDHB_REG_0107.DDHB2[0x107]=4
DDHB_REG_0107.DDHB3[0x107]=0x3c
DDHB_REG_0108.DDHB0[0x108]=0xfffe3f
DDHB_REG_0108.DDHB1[0x108]=0xf7cdf8
DDHB_REG_0108.DDHB2[0x108]=0xfff9f8
DDHB_REG_0108.DDHB3[0x108]=0xffe1ff
DDHB_REG_0109.DDHB0[0x109]=0
DDHB_REG_0109.DDHB1[0x109]=0x5ec004e5bd03e7
DDHB_REG_0109.DDHB2[0x109]=0x9ca30000e629062
DDHB_REG_0109.DDHB3[0x109]=0x1ff779b398a418000
DDHB_REG_0134(0).DDHB0[0x134]=0
DDHB_REG_0134(1).DDHB0[0x135]=0
DDHB_REG_0134(2).DDHB0[0x136]=0
DDHB_REG_0134(3).DDHB0[0x137]=0
DDHB_REG_0134(0).DDHB1[0x134]=0
DDHB_REG_0134(1).DDHB1[0x135]=0
DDHB_REG_0134(2).DDHB1[0x136]=0
DDHB_REG_0134(3).DDHB1[0x137]=0
DDHB_REG_0134(0).DDHB2[0x134]=0
DDHB_REG_0134(1).DDHB2[0x135]=0
DDHB_REG_0134(2).DDHB2[0x136]=0
DDHB_REG_0134(3).DDHB2[0x137]=0
DDHB_REG_0134(0).DDHB3[0x134]=0
DDHB_REG_0134(1).DDHB3[0x135]=0
DDHB_REG_0134(2).DDHB3[0x136]=0
DDHB_REG_0134(3).DDHB3[0x137]=0
DDHB_REG_0154.DDHB0[0x154]=0
DDHB_REG_0154.DDHB1[0x154]=0x2db492
DDHB_REG_0154.DDHB2[0x154]=0x4000
DDHB_REG_0154.DDHB3[0x154]=0
DDHB_REG_0155.DDHB0[0x155]=0
DDHB_REG_0155.DDHB1[0x155]=0x6926db
DDHB_REG_0155.DDHB2[0x155]=0x1000
DDHB_REG_0155.DDHB3[0x155]=0
DDHB_REG_0156(0).DDHB0[0x156]=0
DDHB_REG_0156(1).DDHB0[0x157]=0
DDHB_REG_0156(2).DDHB0[0x158]=0
DDHB_REG_0156(3).DDHB0[0x159]=0
DDHB_REG_0156(4).DDHB0[0x15a]=0
DDHB_REG_0156(5).DDHB0[0x15b]=0
DDHB_REG_0156(6).DDHB0[0x15c]=0
DDHB_REG_0156(7).DDHB0[0x15d]=0
DDHB_REG_0156(0).DDHB1[0x156]=0
DDHB_REG_0156(1).DDHB1[0x157]=0
DDHB_REG_0156(2).DDHB1[0x158]=0
DDHB_REG_0156(3).DDHB1[0x159]=0
DDHB_REG_0156(4).DDHB1[0x15a]=0
DDHB_REG_0156(5).DDHB1[0x15b]=0
DDHB_REG_0156(6).DDHB1[0x15c]=0
DDHB_REG_0156(7).DDHB1[0x15d]=0
DDHB_REG_0156(0).DDHB2[0x156]=0
DDHB_REG_0156(1).DDHB2[0x157]=0
DDHB_REG_0156(2).DDHB2[0x158]=0
DDHB_REG_0156(3).DDHB2[0x159]=0
DDHB_REG_0156(4).DDHB2[0x15a]=0
DDHB_REG_0156(5).DDHB2[0x15b]=0
DDHB_REG_0156(6).DDHB2[0x15c]=0
DDHB_REG_0156(7).DDHB2[0x15d]=0
DDHB_REG_0156(0).DDHB3[0x156]=0
DDHB_REG_0156(1).DDHB3[0x157]=0
DDHB_REG_0156(2).DDHB3[0x158]=0
DDHB_REG_0156(3).DDHB3[0x159]=0
DDHB_REG_0156(4).DDHB3[0x15a]=0
DDHB_REG_0156(5).DDHB3[0x15b]=0
DDHB_REG_0156(6).DDHB3[0x15c]=0
DDHB_REG_0156(7).DDHB3[0x15d]=0
DDHB_REG_0166(0).DDHB0[0x166]=0
DDHB_REG_0166(1).DDHB0[0x167]=0
DDHB_REG_0166(2).DDHB0[0x168]=0
DDHB_REG_0166(3).DDHB0[0x169]=0
DDHB_REG_0166(4).DDHB0[0x16a]=0
DDHB_REG_0166(5).DDHB0[0x16b]=0
DDHB_REG_0166(6).DDHB0[0x16c]=0
DDHB_REG_0166(7).DDHB0[0x16d]=0
DDHB_REG_0166(0).DDHB1[0x166]=0
DDHB_REG_0166(1).DDHB1[0x167]=0
DDHB_REG_0166(2).DDHB1[0x168]=0
DDHB_REG_0166(3).DDHB1[0x169]=0
DDHB_REG_0166(4).DDHB1[0x16a]=0
DDHB_REG_0166(5).DDHB1[0x16b]=0
DDHB_REG_0166(6).DDHB1[0x16c]=0
DDHB_REG_0166(7).DDHB1[0x16d]=0
DDHB_REG_0166(0).DDHB2[0x166]=0
DDHB_REG_0166(1).DDHB2[0x167]=0
DDHB_REG_0166(2).DDHB2[0x168]=0
DDHB_REG_0166(3).DDHB2[0x169]=0
DDHB_REG_0166(4).DDHB2[0x16a]=0
DDHB_REG_0166(5).DDHB2[0x16b]=0
DDHB_REG_0166(6).DDHB2[0x16c]=0
DDHB_REG_0166(7).DDHB2[0x16d]=0
DDHB_REG_0166(0).DDHB3[0x166]=0
DDHB_REG_0166(1).DDHB3[0x167]=0
DDHB_REG_0166(2).DDHB3[0x168]=0
DDHB_REG_0166(3).DDHB3[0x169]=0
DDHB_REG_0166(4).DDHB3[0x16a]=0
DDHB_REG_0166(5).DDHB3[0x16b]=0
DDHB_REG_0166(6).DDHB3[0x16c]=0
DDHB_REG_0166(7).DDHB3[0x16d]=0
DDHB_REG_0176(0).DDHB0[0x176]=0
DDHB_REG_0176(1).DDHB0[0x177]=0
DDHB_REG_0176(2).DDHB0[0x178]=0
DDHB_REG_0176(3).DDHB0[0x179]=0
DDHB_REG_0176(4).DDHB0[0x17a]=0
DDHB_REG_0176(5).DDHB0[0x17b]=0
DDHB_REG_0176(6).DDHB0[0x17c]=0
DDHB_REG_0176(7).DDHB0[0x17d]=0
DDHB_REG_0176(0).DDHB1[0x176]=0
DDHB_REG_0176(1).DDHB1[0x177]=0
DDHB_REG_0176(2).DDHB1[0x178]=0
DDHB_REG_0176(3).DDHB1[0x179]=0
DDHB_REG_0176(4).DDHB1[0x17a]=0
DDHB_REG_0176(5).DDHB1[0x17b]=0
DDHB_REG_0176(6).DDHB1[0x17c]=0
DDHB_REG_0176(7).DDHB1[0x17d]=0
DDHB_REG_0176(0).DDHB2[0x176]=0
DDHB_REG_0176(1).DDHB2[0x177]=0
DDHB_REG_0176(2).DDHB2[0x178]=0
DDHB_REG_0176(3).DDHB2[0x179]=0
DDHB_REG_0176(4).DDHB2[0x17a]=0
DDHB_REG_0176(5).DDHB2[0x17b]=0
DDHB_REG_0176(6).DDHB2[0x17c]=0
DDHB_REG_0176(7).DDHB2[0x17d]=0
DDHB_REG_0176(0).DDHB3[0x176]=0
DDHB_REG_0176(1).DDHB3[0x177]=0
DDHB_REG_0176(2).DDHB3[0x178]=0
DDHB_REG_0176(3).DDHB3[0x179]=0
DDHB_REG_0176(4).DDHB3[0x17a]=0
DDHB_REG_0176(5).DDHB3[0x17b]=0
DDHB_REG_0176(6).DDHB3[0x17c]=0
DDHB_REG_0176(7).DDHB3[0x17d]=0
DDHB_REG_0200.DDHB0[0x200]=0x86d2
DDHB_REG_0200.DDHB1[0x200]=0xb64
DDHB_REG_0200.DDHB2[0x200]=0x3e688
DDHB_REG_0200.DDHB3[0x200]=0x688
DDHB_REG_0201.DDHB0[0x201]=0x8fac
DDHB_REG_0201.DDHB1[0x201]=0x8688
DDHB_REG_0201.DDHB2[0x201]=0x3e688
DDHB_REG_0201.DDHB3[0x201]=0x688
DDHB_REG_0202.DDHB0[0x202]=0x13f249
DDHB_REG_0202.DDHB1[0x202]=0xbd2000
DDHB_REG_0202.DDHB2[0x202]=0x624249
DDHB_REG_0202.DDHB3[0x202]=0xf44db6
DDHB_REG_0203.DDHB0[0x203]=0x23a69005005
DDHB_REG_0203.DDHB1[0x203]=0x865000000000
DDHB_REG_0203.DDHB2[0x203]=0x78082028a28a
DDHB_REG_0203.DDHB3[0x203]=0x553010555555
DDHB_REG_0205.DDHB0[0x205]=0
DDHB_REG_0205.DDHB1[0x205]=0x30
DDHB_REG_0205.DDHB2[0x205]=0
DDHB_REG_0205.DDHB3[0x205]=0
DDHB_REG_0206.DDHB0[0x206]=0x4a4b6d
DDHB_REG_0206.DDHB1[0x206]=0x49bb6d
DDHB_REG_0206.DDHB2[0x206]=0x4a4924
DDHB_REG_0206.DDHB3[0x206]=0x492924
DDHB_REG_0207.DDHB0[0x207]=0x14
DDHB_REG_0207.DDHB1[0x207]=0x14
DDHB_REG_0207.DDHB2[0x207]=0x14
DDHB_REG_0207.DDHB3[0x207]=4
DDHB_REG_0208.DDHB0[0x208]=0x9fefc7
DDHB_REG_0208.DDHB1[0x208]=0xdfff38
DDHB_REG_0208.DDHB2[0x208]=0xffcfc6
DDHB_REG_0208.DDHB3[0x208]=0xe34ffd
DDHB_REG_0209.DDHB0[0x209]=0x4c000000006f4001cc520c5f
DDHB_REG_0209.DDHB1[0x209]=0x37ac83e0002e0000e629062
DDHB_REG_0209.DDHB2[0x209]=0x2728c3feef0031041b
DDHB_REG_0209.DDHB3[0x209]=0xffbbc18820deb389c80000017
DDHB_REG_0235(0).DDHB0[0x235]=0
DDHB_REG_0235(1).DDHB0[0x236]=0
DDHB_REG_0235(2).DDHB0[0x237]=0
DDHB_REG_0235(3).DDHB0[0x238]=0
DDHB_REG_0235(0).DDHB1[0x235]=0
DDHB_REG_0235(1).DDHB1[0x236]=0
DDHB_REG_0235(2).DDHB1[0x237]=0
DDHB_REG_0235(3).DDHB1[0x238]=0
DDHB_REG_0235(0).DDHB2[0x235]=0
DDHB_REG_0235(1).DDHB2[0x236]=0
DDHB_REG_0235(2).DDHB2[0x237]=0
DDHB_REG_0235(3).DDHB2[0x238]=0
DDHB_REG_0235(0).DDHB3[0x235]=0
DDHB_REG_0235(1).DDHB3[0x236]=0
DDHB_REG_0235(2).DDHB3[0x237]=0
DDHB_REG_0235(3).DDHB3[0x238]=0
DDHB_REG_0255.DDHB0[0x255]=0x4c0000
DDHB_REG_0255.DDHB1[0x255]=0x889000
DDHB_REG_0255.DDHB2[0x255]=0x840000
DDHB_REG_0255.DDHB3[0x255]=0x513000
DDHB_REG_0256.DDHB0[0x256]=0x680000
DDHB_REG_0256.DDHB1[0x256]=0x65b000
DDHB_REG_0256.DDHB2[0x256]=0x2c0000
DDHB_REG_0256.DDHB3[0x256]=0x25a000
DDHB_REG_0257(0).DDHB0[0x257]=0
DDHB_REG_0257(1).DDHB0[0x258]=0
DDHB_REG_0257(2).DDHB0[0x259]=0
DDHB_REG_0257(3).DDHB0[0x25a]=0
DDHB_REG_0257(4).DDHB0[0x25b]=0
DDHB_REG_0257(5).DDHB0[0x25c]=0
DDHB_REG_0257(6).DDHB0[0x25d]=0
DDHB_REG_0257(7).DDHB0[0x25e]=0
DDHB_REG_0257(0).DDHB1[0x257]=0
DDHB_REG_0257(1).DDHB1[0x258]=0
DDHB_REG_0257(2).DDHB1[0x259]=0
DDHB_REG_0257(3).DDHB1[0x25a]=0
DDHB_REG_0257(4).DDHB1[0x25b]=0
DDHB_REG_0257(5).DDHB1[0x25c]=0
DDHB_REG_0257(6).DDHB1[0x25d]=0
DDHB_REG_0257(7).DDHB1[0x25e]=0
DDHB_REG_0257(0).DDHB2[0x257]=0
DDHB_REG_0257(1).DDHB2[0x258]=0
DDHB_REG_0257(2).DDHB2[0x259]=0
DDHB_REG_0257(3).DDHB2[0x25a]=0
DDHB_REG_0257(4).DDHB2[0x25b]=0
DDHB_REG_0257(5).DDHB2[0x25c]=0
DDHB_REG_0257(6).DDHB2[0x25d]=0
DDHB_REG_0257(7).DDHB2[0x25e]=0
DDHB_REG_0257(0).DDHB3[0x257]=0
DDHB_REG_0257(1).DDHB3[0x258]=0
DDHB_REG_0257(2).DDHB3[0x259]=0
DDHB_REG_0257(3).DDHB3[0x25a]=0
DDHB_REG_0257(4).DDHB3[0x25b]=0
DDHB_REG_0257(5).DDHB3[0x25c]=0
DDHB_REG_0257(6).DDHB3[0x25d]=0
DDHB_REG_0257(7).DDHB3[0x25e]=0
DDHB_REG_0267(0).DDHB0[0x267]=0
DDHB_REG_0267(1).DDHB0[0x268]=0
DDHB_REG_0267(2).DDHB0[0x269]=0
DDHB_REG_0267(3).DDHB0[0x26a]=0
DDHB_REG_0267(4).DDHB0[0x26b]=0
DDHB_REG_0267(5).DDHB0[0x26c]=0
DDHB_REG_0267(6).DDHB0[0x26d]=0
DDHB_REG_0267(7).DDHB0[0x26e]=0
DDHB_REG_0267(0).DDHB1[0x267]=0
DDHB_REG_0267(1).DDHB1[0x268]=0
DDHB_REG_0267(2).DDHB1[0x269]=0
DDHB_REG_0267(3).DDHB1[0x26a]=0
DDHB_REG_0267(4).DDHB1[0x26b]=0
DDHB_REG_0267(5).DDHB1[0x26c]=0
DDHB_REG_0267(6).DDHB1[0x26d]=0
DDHB_REG_0267(7).DDHB1[0x26e]=0
DDHB_REG_0267(0).DDHB2[0x267]=0
DDHB_REG_0267(1).DDHB2[0x268]=0
DDHB_REG_0267(2).DDHB2[0x269]=0
DDHB_REG_0267(3).DDHB2[0x26a]=0
DDHB_REG_0267(4).DDHB2[0x26b]=0
DDHB_REG_0267(5).DDHB2[0x26c]=0
DDHB_REG_0267(6).DDHB2[0x26d]=0
DDHB_REG_0267(7).DDHB2[0x26e]=0
DDHB_REG_0267(0).DDHB3[0x267]=0
DDHB_REG_0267(1).DDHB3[0x268]=0
DDHB_REG_0267(2).DDHB3[0x269]=0
DDHB_REG_0267(3).DDHB3[0x26a]=0
DDHB_REG_0267(4).DDHB3[0x26b]=0
DDHB_REG_0267(5).DDHB3[0x26c]=0
DDHB_REG_0267(6).DDHB3[0x26d]=0
DDHB_REG_0267(7).DDHB3[0x26e]=0
DDHB_REG_0277(0).DDHB0[0x277]=0
DDHB_REG_0277(1).DDHB0[0x278]=0
DDHB_REG_0277(2).DDHB0[0x279]=0
DDHB_REG_0277(3).DDHB0[0x27a]=0
DDHB_REG_0277(4).DDHB0[0x27b]=0
DDHB_REG_0277(5).DDHB0[0x27c]=0
DDHB_REG_0277(6).DDHB0[0x27d]=0
DDHB_REG_0277(7).DDHB0[0x27e]=0
DDHB_REG_0277(0).DDHB1[0x277]=0
DDHB_REG_0277(1).DDHB1[0x278]=0
DDHB_REG_0277(2).DDHB1[0x279]=0
DDHB_REG_0277(3).DDHB1[0x27a]=0
DDHB_REG_0277(4).DDHB1[0x27b]=0
DDHB_REG_0277(5).DDHB1[0x27c]=0
DDHB_REG_0277(6).DDHB1[0x27d]=0
DDHB_REG_0277(7).DDHB1[0x27e]=0
DDHB_REG_0277(0).DDHB2[0x277]=0
DDHB_REG_0277(1).DDHB2[0x278]=0
DDHB_REG_0277(2).DDHB2[0x279]=0
DDHB_REG_0277(3).DDHB2[0x27a]=0
DDHB_REG_0277(4).DDHB2[0x27b]=0
DDHB_REG_0277(5).DDHB2[0x27c]=0
DDHB_REG_0277(6).DDHB2[0x27d]=0
DDHB_REG_0277(7).DDHB2[0x27e]=0
DDHB_REG_0277(0).DDHB3[0x277]=0
DDHB_REG_0277(1).DDHB3[0x278]=0
DDHB_REG_0277(2).DDHB3[0x279]=0
DDHB_REG_0277(3).DDHB3[0x27a]=0
DDHB_REG_0277(4).DDHB3[0x27b]=0
DDHB_REG_0277(5).DDHB3[0x27c]=0
DDHB_REG_0277(6).DDHB3[0x27d]=0
DDHB_REG_0277(7).DDHB3[0x27e]=0
DDHB_REG_0300.DDHB0[0x300]=0x6d2240
DDHB_REG_0300.DDHB1[0x300]=0x80000
DDHB_REG_0300.DDHB2[0x300]=0x240
DDHB_REG_0300.DDHB3[0x300]=0x36240
DDHB_REG_0301.DDHB0[0x301]=0xfac688
DDHB_REG_0301.DDHB1[0x301]=0x88688
DDHB_REG_0301.DDHB2[0x301]=0x8688
DDHB_REG_0301.DDHB3[0x301]=0x2c688
DDHB_REG_0302.DDHB0[0x302]=0x924924
DDHB_REG_0302.DDHB1[0x302]=0x8c9492
DDHB_REG_0302.DDHB2[0x302]=0x112db6
DDHB_REG_0302.DDHB3[0x302]=0x95b000
DDHB_REG_0303.DDHB0[0x303]=0xca3ca3ca3ca3
DDHB_REG_0303.DDHB1[0x303]=0x9e73c0893893
DDHB_REG_0303.DDHB2[0x303]=0x2c505c30c30
DDHB_REG_0303.DDHB3[0x303]=0x9e90273c03c0
DDHB_REG_0305.DDHB0[0x305]=0
DDHB_REG_0305.DDHB1[0x305]=0
DDHB_REG_0305.DDHB2[0x305]=0xf
DDHB_REG_0305.DDHB3[0x305]=0
DDHB_REG_0306.DDHB0[0x306]=0x6db6db
DDHB_REG_0306.DDHB1[0x306]=0x51b000
DDHB_REG_0306.DDHB2[0x306]=0x49b6db
DDHB_REG_0306.DDHB3[0x306]=0x4ad6db
DDHB_REG_0307.DDHB0[0x307]=0xcd
DDHB_REG_0307.DDHB1[0x307]=0x14
DDHB_REG_0307.DDHB2[0x307]=0x14
DDHB_REG_0307.DDHB3[0x307]=0x14
DDHB_REG_0308.DDHB0[0x308]=0xff8fff
DDHB_REG_0308.DDHB1[0x308]=0xfffc27
DDHB_REG_0308.DDHB2[0x308]=0xe3ef3f
DDHB_REG_0308.DDHB3[0x308]=0xff79f8
DDHB_REG_0309.DDHB0[0x309]=0x398a400000
DDHB_REG_0309.DDHB1[0x309]=0x1ff6f59c02f6ad00000000
DDHB_REG_0309.DDHB2[0x309]=0x3981b05ed5a00000001f
DDHB_REG_0309.DDHB3[0x309]=0x1bd7ef6ad26000000398a4
DDHB_REG_0335(0).DDHB0[0x335]=0
DDHB_REG_0335(1).DDHB0[0x336]=0
DDHB_REG_0335(2).DDHB0[0x337]=0
DDHB_REG_0335(3).DDHB0[0x338]=0
DDHB_REG_0335(0).DDHB1[0x335]=0
DDHB_REG_0335(1).DDHB1[0x336]=0
DDHB_REG_0335(2).DDHB1[0x337]=0
DDHB_REG_0335(3).DDHB1[0x338]=0
DDHB_REG_0335(0).DDHB2[0x335]=0
DDHB_REG_0335(1).DDHB2[0x336]=0
DDHB_REG_0335(2).DDHB2[0x337]=0
DDHB_REG_0335(3).DDHB2[0x338]=0
DDHB_REG_0335(0).DDHB3[0x335]=0
DDHB_REG_0335(1).DDHB3[0x336]=0
DDHB_REG_0335(2).DDHB3[0x337]=0
DDHB_REG_0335(3).DDHB3[0x338]=0
DDHB_REG_0355.DDHB0[0x355]=0
DDHB_REG_0355.DDHB1[0x355]=0x200000
DDHB_REG_0355.DDHB2[0x355]=0x500249
DDHB_REG_0355.DDHB3[0x355]=0x8c0000
DDHB_REG_0356.DDHB0[0x356]=0
DDHB_REG_0356.DDHB1[0x356]=0x200000
DDHB_REG_0356.DDHB2[0x356]=0x6c0249
DDHB_REG_0356.DDHB3[0x356]=0x680000
DDHB_REG_0357(0).DDHB0[0x357]=0
DDHB_REG_0357(1).DDHB0[0x358]=0
DDHB_REG_0357(2).DDHB0[0x359]=0
DDHB_REG_0357(3).DDHB0[0x35a]=0
DDHB_REG_0357(4).DDHB0[0x35b]=0
DDHB_REG_0357(5).DDHB0[0x35c]=0
DDHB_REG_0357(6).DDHB0[0x35d]=0
DDHB_REG_0357(7).DDHB0[0x35e]=0
DDHB_REG_0357(0).DDHB1[0x357]=0
DDHB_REG_0357(1).DDHB1[0x358]=0
DDHB_REG_0357(2).DDHB1[0x359]=0
DDHB_REG_0357(3).DDHB1[0x35a]=0
DDHB_REG_0357(4).DDHB1[0x35b]=0
DDHB_REG_0357(5).DDHB1[0x35c]=0
DDHB_REG_0357(6).DDHB1[0x35d]=0
DDHB_REG_0357(7).DDHB1[0x35e]=0
DDHB_REG_0357(0).DDHB2[0x357]=0
DDHB_REG_0357(1).DDHB2[0x358]=0
DDHB_REG_0357(2).DDHB2[0x359]=0
DDHB_REG_0357(3).DDHB2[0x35a]=0
DDHB_REG_0357(4).DDHB2[0x35b]=0
DDHB_REG_0357(5).DDHB2[0x35c]=0
DDHB_REG_0357(6).DDHB2[0x35d]=0
DDHB_REG_0357(7).DDHB2[0x35e]=0
DDHB_REG_0357(0).DDHB3[0x357]=0
DDHB_REG_0357(1).DDHB3[0x358]=0
DDHB_REG_0357(2).DDHB3[0x359]=0
DDHB_REG_0357(3).DDHB3[0x35a]=0
DDHB_REG_0357(4).DDHB3[0x35b]=0
DDHB_REG_0357(5).DDHB3[0x35c]=0
DDHB_REG_0357(6).DDHB3[0x35d]=0
DDHB_REG_0357(7).DDHB3[0x35e]=0
DDHB_REG_0367(0).DDHB0[0x367]=0
DDHB_REG_0367(1).DDHB0[0x368]=0
DDHB_REG_0367(2).DDHB0[0x369]=0
DDHB_REG_0367(3).DDHB0[0x36a]=0
DDHB_REG_0367(4).DDHB0[0x36b]=0
DDHB_REG_0367(5).DDHB0[0x36c]=0
DDHB_REG_0367(6).DDHB0[0x36d]=0
DDHB_REG_0367(7).DDHB0[0x36e]=0
DDHB_REG_0367(0).DDHB1[0x367]=0
DDHB_REG_0367(1).DDHB1[0x368]=0
DDHB_REG_0367(2).DDHB1[0x369]=0
DDHB_REG_0367(3).DDHB1[0x36a]=0
DDHB_REG_0367(4).DDHB1[0x36b]=0
DDHB_REG_0367(5).DDHB1[0x36c]=0
DDHB_REG_0367(6).DDHB1[0x36d]=0
DDHB_REG_0367(7).DDHB1[0x36e]=0
DDHB_REG_0367(0).DDHB2[0x367]=0
DDHB_REG_0367(1).DDHB2[0x368]=0
DDHB_REG_0367(2).DDHB2[0x369]=0
DDHB_REG_0367(3).DDHB2[0x36a]=0
DDHB_REG_0367(4).DDHB2[0x36b]=0
DDHB_REG_0367(5).DDHB2[0x36c]=0
DDHB_REG_0367(6).DDHB2[0x36d]=0
DDHB_REG_0367(7).DDHB2[0x36e]=0
DDHB_REG_0367(0).DDHB3[0x367]=0
DDHB_REG_0367(1).DDHB3[0x368]=0
DDHB_REG_0367(2).DDHB3[0x369]=0
DDHB_REG_0367(3).DDHB3[0x36a]=0
DDHB_REG_0367(4).DDHB3[0x36b]=0
DDHB_REG_0367(5).DDHB3[0x36c]=0
DDHB_REG_0367(6).DDHB3[0x36d]=0
DDHB_REG_0367(7).DDHB3[0x36e]=0
DDHB_REG_0377(0).DDHB0[0x377]=0
DDHB_REG_0377(1).DDHB0[0x378]=0
DDHB_REG_0377(2).DDHB0[0x379]=0
DDHB_REG_0377(3).DDHB0[0x37a]=0
DDHB_REG_0377(4).DDHB0[0x37b]=0
DDHB_REG_0377(5).DDHB0[0x37c]=0
DDHB_REG_0377(6).DDHB0[0x37d]=0
DDHB_REG_0377(7).DDHB0[0x37e]=0
DDHB_REG_0377(0).DDHB1[0x377]=0
DDHB_REG_0377(1).DDHB1[0x378]=0
DDHB_REG_0377(2).DDHB1[0x379]=0
DDHB_REG_0377(3).DDHB1[0x37a]=0
DDHB_REG_0377(4).DDHB1[0x37b]=0
DDHB_REG_0377(5).DDHB1[0x37c]=0
DDHB_REG_0377(6).DDHB1[0x37d]=0
DDHB_REG_0377(7).DDHB1[0x37e]=0
DDHB_REG_0377(0).DDHB2[0x377]=0
DDHB_REG_0377(1).DDHB2[0x378]=0
DDHB_REG_0377(2).DDHB2[0x379]=0
DDHB_REG_0377(3).DDHB2[0x37a]=0
DDHB_REG_0377(4).DDHB2[0x37b]=0
DDHB_REG_0377(5).DDHB2[0x37c]=0
DDHB_REG_0377(6).DDHB2[0x37d]=0
DDHB_REG_0377(7).DDHB2[0x37e]=0
DDHB_REG_0377(0).DDHB3[0x377]=0
DDHB_REG_0377(1).DDHB3[0x378]=0
DDHB_REG_0377(2).DDHB3[0x379]=0
DDHB_REG_0377(3).DDHB3[0x37a]=0
DDHB_REG_0377(4).DDHB3[0x37b]=0
DDHB_REG_0377(5).DDHB3[0x37c]=0
DDHB_REG_0377(6).DDHB3[0x37d]=0
DDHB_REG_0377(7).DDHB3[0x37e]=0
DDHB_REG_0400.DDHB0[0x400]=0x1c0240
DDHB_REG_0400.DDHB1[0x400]=0xf80000
DDHB_REG_0400.DDHB2[0x400]=0
DDHB_REG_0400.DDHB3[0x400]=0x8240
DDHB_REG_0401.DDHB0[0x401]=0x1c8688
DDHB_REG_0401.DDHB1[0x401]=0xf88208
DDHB_REG_0401.DDHB2[0x401]=0xfac688
DDHB_REG_0401.DDHB3[0x401]=0x208688
DDHB_REG_0402.DDHB0[0x402]=0x8ed000
DDHB_REG_0402.DDHB1[0x402]=0x109036
DDHB_REG_0402.DDHB2[0x402]=0x492492
DDHB_REG_0402.DDHB3[0x402]=0x276492
DDHB_REG_0403.DDHB0[0x403]=0x55569a3c03c0
DDHB_REG_0403.DDHB1[0x403]=0x16000000956
DDHB_REG_0403.DDHB2[0x403]=0x893893893893
DDHB_REG_0403.DDHB3[0x403]=0x14592478f78f
DDHB_REG_0405.DDHB0[0x405]=0x30
DDHB_REG_0405.DDHB1[0x405]=0
DDHB_REG_0405.DDHB2[0x405]=0
DDHB_REG_0405.DDHB3[0x405]=0xc0
DDHB_REG_0406.DDHB0[0x406]=0x51b6db
DDHB_REG_0406.DDHB1[0x406]=0x12db5b
DDHB_REG_0406.DDHB2[0x406]=0
DDHB_REG_0406.DDHB3[0x406]=0x6e46db
DDHB_REG_0407.DDHB0[0x407]=0x14
DDHB_REG_0407.DDHB1[0x407]=0x13
DDHB_REG_0407.DDHB2[0x407]=0xcd
DDHB_REG_0407.DDHB3[0x407]=0x34
DDHB_REG_0408.DDHB0[0x408]=0xfe7df8
DDHB_REG_0408.DDHB1[0x408]=0xe3efe2
DDHB_REG_0408.DDHB2[0x408]=0xfffe3f
DDHB_REG_0408.DDHB3[0x408]=0xf3fe37
DDHB_REG_0409.DDHB0[0x409]=0x17b569ff777ace00000000398a4
DDHB_REG_0409.DDHB1[0x409]=0x73000006f59c0017b55ee6b16a
DDHB_REG_0409.DDHB2[0x409]=0
DDHB_REG_0409.DDHB3[0x409]=0x13946000000000000000e6293e0
DDHB_REG_0435(0).DDHB0[0x435]=0
DDHB_REG_0435(1).DDHB0[0x436]=0
DDHB_REG_0435(2).DDHB0[0x437]=0
DDHB_REG_0435(3).DDHB0[0x438]=0
DDHB_REG_0435(0).DDHB1[0x435]=0
DDHB_REG_0435(1).DDHB1[0x436]=0
DDHB_REG_0435(2).DDHB1[0x437]=0
DDHB_REG_0435(3).DDHB1[0x438]=0
DDHB_REG_0435(0).DDHB2[0x435]=0
DDHB_REG_0435(1).DDHB2[0x436]=0
DDHB_REG_0435(2).DDHB2[0x437]=0
DDHB_REG_0435(3).DDHB2[0x438]=0
DDHB_REG_0435(0).DDHB3[0x435]=0
DDHB_REG_0435(1).DDHB3[0x436]=0
DDHB_REG_0435(2).DDHB3[0x437]=0
DDHB_REG_0435(3).DDHB3[0x438]=0
DDHB_REG_0455.DDHB0[0x455]=0x412000
DDHB_REG_0455.DDHB1[0x455]=0
DDHB_REG_0455.DDHB2[0x455]=0
DDHB_REG_0455.DDHB3[0x455]=0x240000
DDHB_REG_0456.DDHB0[0x456]=0x209000
DDHB_REG_0456.DDHB1[0x456]=9
DDHB_REG_0456.DDHB2[0x456]=0
DDHB_REG_0456.DDHB3[0x456]=0x6c0000
DDHB_REG_0457(0).DDHB0[0x457]=0
DDHB_REG_0457(1).DDHB0[0x458]=0
DDHB_REG_0457(2).DDHB0[0x459]=0
DDHB_REG_0457(3).DDHB0[0x45a]=0
DDHB_REG_0457(4).DDHB0[0x45b]=0
DDHB_REG_0457(5).DDHB0[0x45c]=0
DDHB_REG_0457(6).DDHB0[0x45d]=0
DDHB_REG_0457(7).DDHB0[0x45e]=0
DDHB_REG_0457(0).DDHB1[0x457]=0
DDHB_REG_0457(1).DDHB1[0x458]=0
DDHB_REG_0457(2).DDHB1[0x459]=0
DDHB_REG_0457(3).DDHB1[0x45a]=0
DDHB_REG_0457(4).DDHB1[0x45b]=0
DDHB_REG_0457(5).DDHB1[0x45c]=0
DDHB_REG_0457(6).DDHB1[0x45d]=0
DDHB_REG_0457(7).DDHB1[0x45e]=0
DDHB_REG_0457(0).DDHB2[0x457]=0
DDHB_REG_0457(1).DDHB2[0x458]=0
DDHB_REG_0457(2).DDHB2[0x459]=0
DDHB_REG_0457(3).DDHB2[0x45a]=0
DDHB_REG_0457(4).DDHB2[0x45b]=0
DDHB_REG_0457(5).DDHB2[0x45c]=0
DDHB_REG_0457(6).DDHB2[0x45d]=0
DDHB_REG_0457(7).DDHB2[0x45e]=0
DDHB_REG_0457(0).DDHB3[0x457]=0
DDHB_REG_0457(1).DDHB3[0x458]=0
DDHB_REG_0457(2).DDHB3[0x459]=0
DDHB_REG_0457(3).DDHB3[0x45a]=0
DDHB_REG_0457(4).DDHB3[0x45b]=0
DDHB_REG_0457(5).DDHB3[0x45c]=0
DDHB_REG_0457(6).DDHB3[0x45d]=0
DDHB_REG_0457(7).DDHB3[0x45e]=0
DDHB_REG_0467(0).DDHB0[0x467]=0
DDHB_REG_0467(1).DDHB0[0x468]=0
DDHB_REG_0467(2).DDHB0[0x469]=0
DDHB_REG_0467(3).DDHB0[0x46a]=0
DDHB_REG_0467(4).DDHB0[0x46b]=0
DDHB_REG_0467(5).DDHB0[0x46c]=0
DDHB_REG_0467(6).DDHB0[0x46d]=0
DDHB_REG_0467(7).DDHB0[0x46e]=0
DDHB_REG_0467(0).DDHB1[0x467]=0
DDHB_REG_0467(1).DDHB1[0x468]=0
DDHB_REG_0467(2).DDHB1[0x469]=0
DDHB_REG_0467(3).DDHB1[0x46a]=0
DDHB_REG_0467(4).DDHB1[0x46b]=0
DDHB_REG_0467(5).DDHB1[0x46c]=0
DDHB_REG_0467(6).DDHB1[0x46d]=0
DDHB_REG_0467(7).DDHB1[0x46e]=0
DDHB_REG_0467(0).DDHB2[0x467]=0
DDHB_REG_0467(1).DDHB2[0x468]=0
DDHB_REG_0467(2).DDHB2[0x469]=0
DDHB_REG_0467(3).DDHB2[0x46a]=0
DDHB_REG_0467(4).DDHB2[0x46b]=0
DDHB_REG_0467(5).DDHB2[0x46c]=0
DDHB_REG_0467(6).DDHB2[0x46d]=0
DDHB_REG_0467(7).DDHB2[0x46e]=0
DDHB_REG_0467(0).DDHB3[0x467]=0
DDHB_REG_0467(1).DDHB3[0x468]=0
DDHB_REG_0467(2).DDHB3[0x469]=0
DDHB_REG_0467(3).DDHB3[0x46a]=0
DDHB_REG_0467(4).DDHB3[0x46b]=0
DDHB_REG_0467(5).DDHB3[0x46c]=0
DDHB_REG_0467(6).DDHB3[0x46d]=0
DDHB_REG_0467(7).DDHB3[0x46e]=0
DDHB_REG_0477(0).DDHB0[0x477]=0
DDHB_REG_0477(1).DDHB0[0x478]=0
DDHB_REG_0477(2).DDHB0[0x479]=0
DDHB_REG_0477(3).DDHB0[0x47a]=0
DDHB_REG_0477(4).DDHB0[0x47b]=0
DDHB_REG_0477(5).DDHB0[0x47c]=0
DDHB_REG_0477(6).DDHB0[0x47d]=0
DDHB_REG_0477(7).DDHB0[0x47e]=0
DDHB_REG_0477(0).DDHB1[0x477]=0
DDHB_REG_0477(1).DDHB1[0x478]=0
DDHB_REG_0477(2).DDHB1[0x479]=0
DDHB_REG_0477(3).DDHB1[0x47a]=0
DDHB_REG_0477(4).DDHB1[0x47b]=0
DDHB_REG_0477(5).DDHB1[0x47c]=0
DDHB_REG_0477(6).DDHB1[0x47d]=0
DDHB_REG_0477(7).DDHB1[0x47e]=0
DDHB_REG_0477(0).DDHB2[0x477]=0
DDHB_REG_0477(1).DDHB2[0x478]=0
DDHB_REG_0477(2).DDHB2[0x479]=0
DDHB_REG_0477(3).DDHB2[0x47a]=0
DDHB_REG_0477(4).DDHB2[0x47b]=0
DDHB_REG_0477(5).DDHB2[0x47c]=0
DDHB_REG_0477(6).DDHB2[0x47d]=0
DDHB_REG_0477(7).DDHB2[0x47e]=0
DDHB_REG_0477(0).DDHB3[0x477]=0
DDHB_REG_0477(1).DDHB3[0x478]=0
DDHB_REG_0477(2).DDHB3[0x479]=0
DDHB_REG_0477(3).DDHB3[0x47a]=0
DDHB_REG_0477(4).DDHB3[0x47b]=0
DDHB_REG_0477(5).DDHB3[0x47c]=0
DDHB_REG_0477(6).DDHB3[0x47d]=0
DDHB_REG_0477(7).DDHB3[0x47e]=0
DDHB_REG_00A0.DDHB0[0xa0]=0
DDHB_REG_00A0.DDHB1[0xa0]=0
DDHB_REG_00A0.DDHB2[0xa0]=0
DDHB_REG_00A0.DDHB3[0xa0]=0
DDHB_REG_00C2.DDHB0[0xc2]=0x10
DDHB_REG_00C2.DDHB1[0xc2]=0x10
DDHB_REG_00C2.DDHB2[0xc2]=0x10
DDHB_REG_00C2.DDHB3[0xc2]=0x10
DDHB_REG_010C(0).DDHB0[0x10c]=0
DDHB_REG_010C(1).DDHB0[0x10d]=0
DDHB_REG_010C(2).DDHB0[0x10e]=0
DDHB_REG_010C(3).DDHB0[0x10f]=0
DDHB_REG_010C(4).DDHB0[0x110]=0
DDHB_REG_010C(5).DDHB0[0x111]=0
DDHB_REG_010C(6).DDHB0[0x112]=0
DDHB_REG_010C(7).DDHB0[0x113]=0
DDHB_REG_010C(0).DDHB1[0x10c]=0x22222222222222220000000000000000
DDHB_REG_010C(1).DDHB1[0x10d]=0x11111111111111111111111111111111
DDHB_REG_010C(2).DDHB1[0x10e]=0x22222222222222220000000000000000
DDHB_REG_010C(3).DDHB1[0x10f]=0x11111111111111111111111111111111
DDHB_REG_010C(4).DDHB1[0x110]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_010C(5).DDHB1[0x111]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_010C(6).DDHB1[0x112]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_010C(7).DDHB1[0x113]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_010C(0).DDHB2[0x10c]=0
DDHB_REG_010C(1).DDHB2[0x10d]=0
DDHB_REG_010C(2).DDHB2[0x10e]=0
DDHB_REG_010C(3).DDHB2[0x10f]=0
DDHB_REG_010C(4).DDHB2[0x110]=0xe8
DDHB_REG_010C(5).DDHB2[0x111]=0
DDHB_REG_010C(6).DDHB2[0x112]=0
DDHB_REG_010C(7).DDHB2[0x113]=0
DDHB_REG_010C(0).DDHB3[0x10c]=0
DDHB_REG_010C(1).DDHB3[0x10d]=0
DDHB_REG_010C(2).DDHB3[0x10e]=0
DDHB_REG_010C(3).DDHB3[0x10f]=0
DDHB_REG_010C(4).DDHB3[0x110]=0
DDHB_REG_010C(5).DDHB3[0x111]=0
DDHB_REG_010C(6).DDHB3[0x112]=0
DDHB_REG_010C(7).DDHB3[0x113]=0
DDHB_REG_012C(0).DDHB0[0x12c]=0
DDHB_REG_012C(1).DDHB0[0x12d]=0
DDHB_REG_012C(2).DDHB0[0x12e]=0
DDHB_REG_012C(3).DDHB0[0x12f]=0
DDHB_REG_012C(4).DDHB0[0x130]=0
DDHB_REG_012C(5).DDHB0[0x131]=0
DDHB_REG_012C(6).DDHB0[0x132]=0
DDHB_REG_012C(7).DDHB0[0x133]=0
DDHB_REG_012C(0).DDHB1[0x12c]=0
DDHB_REG_012C(1).DDHB1[0x12d]=0
DDHB_REG_012C(2).DDHB1[0x12e]=0
DDHB_REG_012C(3).DDHB1[0x12f]=0
DDHB_REG_012C(4).DDHB1[0x130]=0
DDHB_REG_012C(5).DDHB1[0x131]=0
DDHB_REG_012C(6).DDHB1[0x132]=0
DDHB_REG_012C(7).DDHB1[0x133]=0
DDHB_REG_012C(0).DDHB2[0x12c]=0
DDHB_REG_012C(1).DDHB2[0x12d]=0x50505050
DDHB_REG_012C(2).DDHB2[0x12e]=0
DDHB_REG_012C(3).DDHB2[0x12f]=0x50505050
DDHB_REG_012C(4).DDHB2[0x130]=0
DDHB_REG_012C(5).DDHB2[0x131]=0
DDHB_REG_012C(6).DDHB2[0x132]=0
DDHB_REG_012C(7).DDHB2[0x133]=0
DDHB_REG_012C(0).DDHB3[0x12c]=0
DDHB_REG_012C(1).DDHB3[0x12d]=0xf0f0f0f0
DDHB_REG_012C(2).DDHB3[0x12e]=0
DDHB_REG_012C(3).DDHB3[0x12f]=0xf0f0f0f0
DDHB_REG_012C(4).DDHB3[0x130]=0
DDHB_REG_012C(5).DDHB3[0x131]=0xf0f0f0f0
DDHB_REG_012C(6).DDHB3[0x132]=0
DDHB_REG_012C(7).DDHB3[0x133]=0xf0f0f0f0
DDHB_REG_015E(0).DDHB0[0x15e]=0
DDHB_REG_015E(1).DDHB0[0x15f]=0
DDHB_REG_015E(2).DDHB0[0x160]=0
DDHB_REG_015E(3).DDHB0[0x161]=0
DDHB_REG_015E(4).DDHB0[0x162]=0
DDHB_REG_015E(5).DDHB0[0x163]=0
DDHB_REG_015E(6).DDHB0[0x164]=0
DDHB_REG_015E(7).DDHB0[0x165]=0
DDHB_REG_015E(0).DDHB1[0x15e]=0
DDHB_REG_015E(1).DDHB1[0x15f]=0
DDHB_REG_015E(2).DDHB1[0x160]=0
DDHB_REG_015E(3).DDHB1[0x161]=0
DDHB_REG_015E(4).DDHB1[0x162]=0
DDHB_REG_015E(5).DDHB1[0x163]=0
DDHB_REG_015E(6).DDHB1[0x164]=0
DDHB_REG_015E(7).DDHB1[0x165]=0
DDHB_REG_015E(0).DDHB2[0x15e]=0
DDHB_REG_015E(1).DDHB2[0x15f]=0
DDHB_REG_015E(2).DDHB2[0x160]=0
DDHB_REG_015E(3).DDHB2[0x161]=0
DDHB_REG_015E(4).DDHB2[0x162]=0
DDHB_REG_015E(5).DDHB2[0x163]=0
DDHB_REG_015E(6).DDHB2[0x164]=0
DDHB_REG_015E(7).DDHB2[0x165]=0
DDHB_REG_015E(0).DDHB3[0x15e]=0
DDHB_REG_015E(1).DDHB3[0x15f]=0
DDHB_REG_015E(2).DDHB3[0x160]=0
DDHB_REG_015E(3).DDHB3[0x161]=0
DDHB_REG_015E(4).DDHB3[0x162]=0
DDHB_REG_015E(5).DDHB3[0x163]=0
DDHB_REG_015E(6).DDHB3[0x164]=0
DDHB_REG_015E(7).DDHB3[0x165]=0
DDHB_REG_016E(0).DDHB0[0x16e]=0
DDHB_REG_016E(1).DDHB0[0x16f]=0
DDHB_REG_016E(2).DDHB0[0x170]=0
DDHB_REG_016E(3).DDHB0[0x171]=0
DDHB_REG_016E(4).DDHB0[0x172]=0
DDHB_REG_016E(5).DDHB0[0x173]=0
DDHB_REG_016E(6).DDHB0[0x174]=0
DDHB_REG_016E(7).DDHB0[0x175]=0
DDHB_REG_016E(0).DDHB1[0x16e]=0
DDHB_REG_016E(1).DDHB1[0x16f]=0
DDHB_REG_016E(2).DDHB1[0x170]=0
DDHB_REG_016E(3).DDHB1[0x171]=0
DDHB_REG_016E(4).DDHB1[0x172]=0
DDHB_REG_016E(5).DDHB1[0x173]=0
DDHB_REG_016E(6).DDHB1[0x174]=0
DDHB_REG_016E(7).DDHB1[0x175]=0
DDHB_REG_016E(0).DDHB2[0x16e]=0
DDHB_REG_016E(1).DDHB2[0x16f]=0
DDHB_REG_016E(2).DDHB2[0x170]=0
DDHB_REG_016E(3).DDHB2[0x171]=0
DDHB_REG_016E(4).DDHB2[0x172]=0
DDHB_REG_016E(5).DDHB2[0x173]=0
DDHB_REG_016E(6).DDHB2[0x174]=0
DDHB_REG_016E(7).DDHB2[0x175]=0
DDHB_REG_016E(0).DDHB3[0x16e]=0
DDHB_REG_016E(1).DDHB3[0x16f]=0
DDHB_REG_016E(2).DDHB3[0x170]=0
DDHB_REG_016E(3).DDHB3[0x171]=0
DDHB_REG_016E(4).DDHB3[0x172]=0
DDHB_REG_016E(5).DDHB3[0x173]=0
DDHB_REG_016E(6).DDHB3[0x174]=0
DDHB_REG_016E(7).DDHB3[0x175]=0
DDHB_REG_017E(0).DDHB0[0x17e]=0
DDHB_REG_017E(1).DDHB0[0x17f]=0
DDHB_REG_017E(2).DDHB0[0x180]=0
DDHB_REG_017E(3).DDHB0[0x181]=0
DDHB_REG_017E(4).DDHB0[0x182]=0
DDHB_REG_017E(5).DDHB0[0x183]=0
DDHB_REG_017E(6).DDHB0[0x184]=0
DDHB_REG_017E(7).DDHB0[0x185]=0
DDHB_REG_017E(0).DDHB1[0x17e]=0
DDHB_REG_017E(1).DDHB1[0x17f]=0
DDHB_REG_017E(2).DDHB1[0x180]=0
DDHB_REG_017E(3).DDHB1[0x181]=0
DDHB_REG_017E(4).DDHB1[0x182]=0
DDHB_REG_017E(5).DDHB1[0x183]=0
DDHB_REG_017E(6).DDHB1[0x184]=0
DDHB_REG_017E(7).DDHB1[0x185]=0
DDHB_REG_017E(0).DDHB2[0x17e]=0
DDHB_REG_017E(1).DDHB2[0x17f]=0
DDHB_REG_017E(2).DDHB2[0x180]=0
DDHB_REG_017E(3).DDHB2[0x181]=0
DDHB_REG_017E(4).DDHB2[0x182]=0
DDHB_REG_017E(5).DDHB2[0x183]=0
DDHB_REG_017E(6).DDHB2[0x184]=0
DDHB_REG_017E(7).DDHB2[0x185]=0
DDHB_REG_017E(0).DDHB3[0x17e]=0
DDHB_REG_017E(1).DDHB3[0x17f]=0
DDHB_REG_017E(2).DDHB3[0x180]=0
DDHB_REG_017E(3).DDHB3[0x181]=0
DDHB_REG_017E(4).DDHB3[0x182]=0
DDHB_REG_017E(5).DDHB3[0x183]=0
DDHB_REG_017E(6).DDHB3[0x184]=0
DDHB_REG_017E(7).DDHB3[0x185]=0
DDHB_REG_020D(0).DDHB0[0x20d]=0
DDHB_REG_020D(1).DDHB0[0x20e]=0
DDHB_REG_020D(2).DDHB0[0x20f]=0
DDHB_REG_020D(3).DDHB0[0x210]=0
DDHB_REG_020D(4).DDHB0[0x211]=0
DDHB_REG_020D(5).DDHB0[0x212]=0
DDHB_REG_020D(6).DDHB0[0x213]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_020D(7).DDHB0[0x214]=0x5555555555555555aaaaaaaa00000000
DDHB_REG_020D(0).DDHB1[0x20d]=0
DDHB_REG_020D(1).DDHB1[0x20e]=0
DDHB_REG_020D(2).DDHB1[0x20f]=0
DDHB_REG_020D(3).DDHB1[0x210]=0
DDHB_REG_020D(4).DDHB1[0x211]=0
DDHB_REG_020D(5).DDHB1[0x212]=0x33333333333333332222222222222222
DDHB_REG_020D(6).DDHB1[0x213]=0xffffffffffffffffaaaaaaaa00000000
DDHB_REG_020D(7).DDHB1[0x214]=0x55555555555555550000000000000000
DDHB_REG_020D(0).DDHB2[0x20d]=0
DDHB_REG_020D(1).DDHB2[0x20e]=0
DDHB_REG_020D(2).DDHB2[0x20f]=0
DDHB_REG_020D(3).DDHB2[0x210]=0
DDHB_REG_020D(4).DDHB2[0x211]=0
DDHB_REG_020D(5).DDHB2[0x212]=0
DDHB_REG_020D(6).DDHB2[0x213]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_020D(7).DDHB2[0x214]=0xe8
DDHB_REG_020D(0).DDHB3[0x20d]=0
DDHB_REG_020D(1).DDHB3[0x20e]=0
DDHB_REG_020D(2).DDHB3[0x20f]=0
DDHB_REG_020D(3).DDHB3[0x210]=0
DDHB_REG_020D(4).DDHB3[0x211]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_020D(5).DDHB3[0x212]=0x5555555555555555aaaaaaaa00000000
DDHB_REG_020D(6).DDHB3[0x213]=0xe8
DDHB_REG_020D(7).DDHB3[0x214]=0xffffffffffffffffaaaaaaaa00000000
DDHB_REG_022D(0).DDHB0[0x22d]=0
DDHB_REG_022D(1).DDHB0[0x22e]=0x50505050
DDHB_REG_022D(2).DDHB0[0x22f]=0
DDHB_REG_022D(3).DDHB0[0x230]=0x50505050
DDHB_REG_022D(4).DDHB0[0x231]=0
DDHB_REG_022D(5).DDHB0[0x232]=0
DDHB_REG_022D(6).DDHB0[0x233]=0
DDHB_REG_022D(7).DDHB0[0x234]=0
DDHB_REG_022D(0).DDHB1[0x22d]=0
DDHB_REG_022D(1).DDHB1[0x22e]=0x50505050
DDHB_REG_022D(2).DDHB1[0x22f]=0
DDHB_REG_022D(3).DDHB1[0x230]=0x50505050
DDHB_REG_022D(4).DDHB1[0x231]=0
DDHB_REG_022D(5).DDHB1[0x232]=0
DDHB_REG_022D(6).DDHB1[0x233]=0
DDHB_REG_022D(7).DDHB1[0x234]=0
DDHB_REG_022D(0).DDHB2[0x22d]=0
DDHB_REG_022D(1).DDHB2[0x22e]=0
DDHB_REG_022D(2).DDHB2[0x22f]=0
DDHB_REG_022D(3).DDHB2[0x230]=0
DDHB_REG_022D(4).DDHB2[0x231]=0
DDHB_REG_022D(5).DDHB2[0x232]=0
DDHB_REG_022D(6).DDHB2[0x233]=0
DDHB_REG_022D(7).DDHB2[0x234]=0
DDHB_REG_022D(0).DDHB3[0x22d]=0
DDHB_REG_022D(1).DDHB3[0x22e]=0
DDHB_REG_022D(2).DDHB3[0x22f]=0
DDHB_REG_022D(3).DDHB3[0x230]=0
DDHB_REG_022D(4).DDHB3[0x231]=0
DDHB_REG_022D(5).DDHB3[0x232]=0
DDHB_REG_022D(6).DDHB3[0x233]=0
DDHB_REG_022D(7).DDHB3[0x234]=0
DDHB_REG_025F(0).DDHB0[0x25f]=0
DDHB_REG_025F(1).DDHB0[0x260]=0
DDHB_REG_025F(2).DDHB0[0x261]=0
DDHB_REG_025F(3).DDHB0[0x262]=0
DDHB_REG_025F(4).DDHB0[0x263]=0
DDHB_REG_025F(5).DDHB0[0x264]=0
DDHB_REG_025F(6).DDHB0[0x265]=0
DDHB_REG_025F(7).DDHB0[0x266]=0
DDHB_REG_025F(0).DDHB1[0x25f]=0
DDHB_REG_025F(1).DDHB1[0x260]=0
DDHB_REG_025F(2).DDHB1[0x261]=0
DDHB_REG_025F(3).DDHB1[0x262]=0
DDHB_REG_025F(4).DDHB1[0x263]=0
DDHB_REG_025F(5).DDHB1[0x264]=0
DDHB_REG_025F(6).DDHB1[0x265]=0
DDHB_REG_025F(7).DDHB1[0x266]=0
DDHB_REG_025F(0).DDHB2[0x25f]=0
DDHB_REG_025F(1).DDHB2[0x260]=0
DDHB_REG_025F(2).DDHB2[0x261]=0
DDHB_REG_025F(3).DDHB2[0x262]=0
DDHB_REG_025F(4).DDHB2[0x263]=0
DDHB_REG_025F(5).DDHB2[0x264]=0
DDHB_REG_025F(6).DDHB2[0x265]=0
DDHB_REG_025F(7).DDHB2[0x266]=0
DDHB_REG_025F(0).DDHB3[0x25f]=0
DDHB_REG_025F(1).DDHB3[0x260]=0
DDHB_REG_025F(2).DDHB3[0x261]=0
DDHB_REG_025F(3).DDHB3[0x262]=0
DDHB_REG_025F(4).DDHB3[0x263]=0
DDHB_REG_025F(5).DDHB3[0x264]=0
DDHB_REG_025F(6).DDHB3[0x265]=0
DDHB_REG_025F(7).DDHB3[0x266]=0
DDHB_REG_026F(0).DDHB0[0x26f]=0
DDHB_REG_026F(1).DDHB0[0x270]=0
DDHB_REG_026F(2).DDHB0[0x271]=0
DDHB_REG_026F(3).DDHB0[0x272]=0
DDHB_REG_026F(4).DDHB0[0x273]=0
DDHB_REG_026F(5).DDHB0[0x274]=0
DDHB_REG_026F(6).DDHB0[0x275]=0
DDHB_REG_026F(7).DDHB0[0x276]=0
DDHB_REG_026F(0).DDHB1[0x26f]=0
DDHB_REG_026F(1).DDHB1[0x270]=0
DDHB_REG_026F(2).DDHB1[0x271]=0
DDHB_REG_026F(3).DDHB1[0x272]=0
DDHB_REG_026F(4).DDHB1[0x273]=0
DDHB_REG_026F(5).DDHB1[0x274]=0
DDHB_REG_026F(6).DDHB1[0x275]=0
DDHB_REG_026F(7).DDHB1[0x276]=0
DDHB_REG_026F(0).DDHB2[0x26f]=0
DDHB_REG_026F(1).DDHB2[0x270]=0
DDHB_REG_026F(2).DDHB2[0x271]=0
DDHB_REG_026F(3).DDHB2[0x272]=0
DDHB_REG_026F(4).DDHB2[0x273]=0
DDHB_REG_026F(5).DDHB2[0x274]=0
DDHB_REG_026F(6).DDHB2[0x275]=0
DDHB_REG_026F(7).DDHB2[0x276]=0
DDHB_REG_026F(0).DDHB3[0x26f]=0
DDHB_REG_026F(1).DDHB3[0x270]=0
DDHB_REG_026F(2).DDHB3[0x271]=0
DDHB_REG_026F(3).DDHB3[0x272]=0
DDHB_REG_026F(4).DDHB3[0x273]=0
DDHB_REG_026F(5).DDHB3[0x274]=0
DDHB_REG_026F(6).DDHB3[0x275]=0
DDHB_REG_026F(7).DDHB3[0x276]=0
DDHB_REG_027F(0).DDHB0[0x27f]=0
DDHB_REG_027F(1).DDHB0[0x280]=0
DDHB_REG_027F(2).DDHB0[0x281]=0
DDHB_REG_027F(3).DDHB0[0x282]=0
DDHB_REG_027F(4).DDHB0[0x283]=0
DDHB_REG_027F(5).DDHB0[0x284]=0
DDHB_REG_027F(6).DDHB0[0x285]=0
DDHB_REG_027F(7).DDHB0[0x286]=0
DDHB_REG_027F(0).DDHB1[0x27f]=0
DDHB_REG_027F(1).DDHB1[0x280]=0
DDHB_REG_027F(2).DDHB1[0x281]=0
DDHB_REG_027F(3).DDHB1[0x282]=0
DDHB_REG_027F(4).DDHB1[0x283]=0
DDHB_REG_027F(5).DDHB1[0x284]=0
DDHB_REG_027F(6).DDHB1[0x285]=0
DDHB_REG_027F(7).DDHB1[0x286]=0
DDHB_REG_027F(0).DDHB2[0x27f]=0
DDHB_REG_027F(1).DDHB2[0x280]=0
DDHB_REG_027F(2).DDHB2[0x281]=0
DDHB_REG_027F(3).DDHB2[0x282]=0
DDHB_REG_027F(4).DDHB2[0x283]=0
DDHB_REG_027F(5).DDHB2[0x284]=0
DDHB_REG_027F(6).DDHB2[0x285]=0
DDHB_REG_027F(7).DDHB2[0x286]=0
DDHB_REG_027F(0).DDHB3[0x27f]=0
DDHB_REG_027F(1).DDHB3[0x280]=0
DDHB_REG_027F(2).DDHB3[0x281]=0
DDHB_REG_027F(3).DDHB3[0x282]=0
DDHB_REG_027F(4).DDHB3[0x283]=0
DDHB_REG_027F(5).DDHB3[0x284]=0
DDHB_REG_027F(6).DDHB3[0x285]=0
DDHB_REG_027F(7).DDHB3[0x286]=0
DDHB_REG_030D(0).DDHB0[0x30d]=0x33333333222222220000000000000000
DDHB_REG_030D(1).DDHB0[0x30e]=0x33333333333333333333333344444444
DDHB_REG_030D(2).DDHB0[0x30f]=0x33333333222222220000000000000000
DDHB_REG_030D(3).DDHB0[0x310]=0x33333333333333333333333344444444
DDHB_REG_030D(4).DDHB0[0x311]=0x33333333222222220000000000000000
DDHB_REG_030D(5).DDHB0[0x312]=0x33333333333333333333333344444444
DDHB_REG_030D(6).DDHB0[0x313]=0x33333333222222220000000000000000
DDHB_REG_030D(7).DDHB0[0x314]=0x33333333333333333333333344444444
DDHB_REG_030D(0).DDHB1[0x30d]=0
DDHB_REG_030D(1).DDHB1[0x30e]=0
DDHB_REG_030D(2).DDHB1[0x30f]=0
DDHB_REG_030D(3).DDHB1[0x310]=0
DDHB_REG_030D(4).DDHB1[0x311]=0x33333333222222220000000000000000
DDHB_REG_030D(5).DDHB1[0x312]=0x33333333333333333333333344444444
DDHB_REG_030D(6).DDHB1[0x313]=0
DDHB_REG_030D(7).DDHB1[0x314]=0xffffffff55555555aaaaaaaa00000000
DDHB_REG_030D(0).DDHB2[0x30d]=0x22222222222222220000000000000000
DDHB_REG_030D(1).DDHB2[0x30e]=0x33333333333333331111111111111111
DDHB_REG_030D(2).DDHB2[0x30f]=0x22222222222222220000000000000000
DDHB_REG_030D(3).DDHB2[0x310]=0x33333333333333331111111111111111
DDHB_REG_030D(4).DDHB2[0x311]=0x33333333222222220000000000000000
DDHB_REG_030D(5).DDHB2[0x312]=0x33333333333333333333333344444444
DDHB_REG_030D(6).DDHB2[0x313]=0x55555555555555550000000000000000
DDHB_REG_030D(7).DDHB2[0x314]=0x5555555555555555aaaaaaaa00000000
DDHB_REG_030D(0).DDHB3[0x30d]=0x33333333222222220000000000000000
DDHB_REG_030D(1).DDHB3[0x30e]=0x33333333333333333333333344444444
DDHB_REG_030D(2).DDHB3[0x30f]=0x33333333222222220000000000000000
DDHB_REG_030D(3).DDHB3[0x310]=0x33333333333333333333333344444444
DDHB_REG_030D(4).DDHB3[0x311]=0
DDHB_REG_030D(5).DDHB3[0x312]=0
DDHB_REG_030D(6).DDHB3[0x313]=0xffffffffaaaaaaaa0000000000000000
DDHB_REG_030D(7).DDHB3[0x314]=0x55555555555555550000000000000000
DDHB_REG_032D(0).DDHB0[0x32d]=0
DDHB_REG_032D(1).DDHB0[0x32e]=0
DDHB_REG_032D(2).DDHB0[0x32f]=0
DDHB_REG_032D(3).DDHB0[0x330]=0
DDHB_REG_032D(4).DDHB0[0x331]=0
DDHB_REG_032D(5).DDHB0[0x332]=0
DDHB_REG_032D(6).DDHB0[0x333]=0
DDHB_REG_032D(7).DDHB0[0x334]=0
DDHB_REG_032D(0).DDHB1[0x32d]=0
DDHB_REG_032D(1).DDHB1[0x32e]=0
DDHB_REG_032D(2).DDHB1[0x32f]=0
DDHB_REG_032D(3).DDHB1[0x330]=0
DDHB_REG_032D(4).DDHB1[0x331]=0
DDHB_REG_032D(5).DDHB1[0x332]=0
DDHB_REG_032D(6).DDHB1[0x333]=0
DDHB_REG_032D(7).DDHB1[0x334]=0
DDHB_REG_032D(0).DDHB2[0x32d]=0
DDHB_REG_032D(1).DDHB2[0x32e]=0
DDHB_REG_032D(2).DDHB2[0x32f]=0
DDHB_REG_032D(3).DDHB2[0x330]=0
DDHB_REG_032D(4).DDHB2[0x331]=0
DDHB_REG_032D(5).DDHB2[0x332]=0
DDHB_REG_032D(6).DDHB2[0x333]=0
DDHB_REG_032D(7).DDHB2[0x334]=0
DDHB_REG_032D(0).DDHB3[0x32d]=0
DDHB_REG_032D(1).DDHB3[0x32e]=0
DDHB_REG_032D(2).DDHB3[0x32f]=0
DDHB_REG_032D(3).DDHB3[0x330]=0
DDHB_REG_032D(4).DDHB3[0x331]=0
DDHB_REG_032D(5).DDHB3[0x332]=0xf0f0f0f0
DDHB_REG_032D(6).DDHB3[0x333]=0
DDHB_REG_032D(7).DDHB3[0x334]=0
DDHB_REG_035F(0).DDHB0[0x35f]=0
DDHB_REG_035F(1).DDHB0[0x360]=0
DDHB_REG_035F(2).DDHB0[0x361]=0
DDHB_REG_035F(3).DDHB0[0x362]=0
DDHB_REG_035F(4).DDHB0[0x363]=0
DDHB_REG_035F(5).DDHB0[0x364]=0
DDHB_REG_035F(6).DDHB0[0x365]=0
DDHB_REG_035F(7).DDHB0[0x366]=0
DDHB_REG_035F(0).DDHB1[0x35f]=0
DDHB_REG_035F(1).DDHB1[0x360]=0
DDHB_REG_035F(2).DDHB1[0x361]=0
DDHB_REG_035F(3).DDHB1[0x362]=0
DDHB_REG_035F(4).DDHB1[0x363]=0
DDHB_REG_035F(5).DDHB1[0x364]=0
DDHB_REG_035F(6).DDHB1[0x365]=0
DDHB_REG_035F(7).DDHB1[0x366]=0
DDHB_REG_035F(0).DDHB2[0x35f]=0
DDHB_REG_035F(1).DDHB2[0x360]=0
DDHB_REG_035F(2).DDHB2[0x361]=0
DDHB_REG_035F(3).DDHB2[0x362]=0
DDHB_REG_035F(4).DDHB2[0x363]=0
DDHB_REG_035F(5).DDHB2[0x364]=0
DDHB_REG_035F(6).DDHB2[0x365]=0
DDHB_REG_035F(7).DDHB2[0x366]=0
DDHB_REG_035F(0).DDHB3[0x35f]=0
DDHB_REG_035F(1).DDHB3[0x360]=0
DDHB_REG_035F(2).DDHB3[0x361]=0
DDHB_REG_035F(3).DDHB3[0x362]=0
DDHB_REG_035F(4).DDHB3[0x363]=0
DDHB_REG_035F(5).DDHB3[0x364]=0
DDHB_REG_035F(6).DDHB3[0x365]=0
DDHB_REG_035F(7).DDHB3[0x366]=0
DDHB_REG_036F(0).DDHB0[0x36f]=0
DDHB_REG_036F(1).DDHB0[0x370]=0
DDHB_REG_036F(2).DDHB0[0x371]=0
DDHB_REG_036F(3).DDHB0[0x372]=0
DDHB_REG_036F(4).DDHB0[0x373]=0
DDHB_REG_036F(5).DDHB0[0x374]=0
DDHB_REG_036F(6).DDHB0[0x375]=0
DDHB_REG_036F(7).DDHB0[0x376]=0
DDHB_REG_036F(0).DDHB1[0x36f]=0
DDHB_REG_036F(1).DDHB1[0x370]=0
DDHB_REG_036F(2).DDHB1[0x371]=0
DDHB_REG_036F(3).DDHB1[0x372]=0
DDHB_REG_036F(4).DDHB1[0x373]=0
DDHB_REG_036F(5).DDHB1[0x374]=0
DDHB_REG_036F(6).DDHB1[0x375]=0
DDHB_REG_036F(7).DDHB1[0x376]=0
DDHB_REG_036F(0).DDHB2[0x36f]=0
DDHB_REG_036F(1).DDHB2[0x370]=0
DDHB_REG_036F(2).DDHB2[0x371]=0
DDHB_REG_036F(3).DDHB2[0x372]=0
DDHB_REG_036F(4).DDHB2[0x373]=0
DDHB_REG_036F(5).DDHB2[0x374]=0
DDHB_REG_036F(6).DDHB2[0x375]=0
DDHB_REG_036F(7).DDHB2[0x376]=0
DDHB_REG_036F(0).DDHB3[0x36f]=0
DDHB_REG_036F(1).DDHB3[0x370]=0
DDHB_REG_036F(2).DDHB3[0x371]=0
DDHB_REG_036F(3).DDHB3[0x372]=0
DDHB_REG_036F(4).DDHB3[0x373]=0
DDHB_REG_036F(5).DDHB3[0x374]=0
DDHB_REG_036F(6).DDHB3[0x375]=0
DDHB_REG_036F(7).DDHB3[0x376]=0
DDHB_REG_037F(0).DDHB0[0x37f]=0
DDHB_REG_037F(1).DDHB0[0x380]=0
DDHB_REG_037F(2).DDHB0[0x381]=0
DDHB_REG_037F(3).DDHB0[0x382]=0
DDHB_REG_037F(4).DDHB0[0x383]=0
DDHB_REG_037F(5).DDHB0[0x384]=0
DDHB_REG_037F(6).DDHB0[0x385]=0
DDHB_REG_037F(7).DDHB0[0x386]=0
DDHB_REG_037F(0).DDHB1[0x37f]=0
DDHB_REG_037F(1).DDHB1[0x380]=0
DDHB_REG_037F(2).DDHB1[0x381]=0
DDHB_REG_037F(3).DDHB1[0x382]=0
DDHB_REG_037F(4).DDHB1[0x383]=0
DDHB_REG_037F(5).DDHB1[0x384]=0
DDHB_REG_037F(6).DDHB1[0x385]=0
DDHB_REG_037F(7).DDHB1[0x386]=0
DDHB_REG_037F(0).DDHB2[0x37f]=0
DDHB_REG_037F(1).DDHB2[0x380]=0
DDHB_REG_037F(2).DDHB2[0x381]=0
DDHB_REG_037F(3).DDHB2[0x382]=0
DDHB_REG_037F(4).DDHB2[0x383]=0
DDHB_REG_037F(5).DDHB2[0x384]=0
DDHB_REG_037F(6).DDHB2[0x385]=0
DDHB_REG_037F(7).DDHB2[0x386]=0
DDHB_REG_037F(0).DDHB3[0x37f]=0
DDHB_REG_037F(1).DDHB3[0x380]=0
DDHB_REG_037F(2).DDHB3[0x381]=0
DDHB_REG_037F(3).DDHB3[0x382]=0
DDHB_REG_037F(4).DDHB3[0x383]=0
DDHB_REG_037F(5).DDHB3[0x384]=0
DDHB_REG_037F(6).DDHB3[0x385]=0
DDHB_REG_037F(7).DDHB3[0x386]=0
DDHB_REG_040D(0).DDHB0[0x40d]=0x33333333222222220000000000000000
DDHB_REG_040D(1).DDHB0[0x40e]=0x33333333333333333333333344444444
DDHB_REG_040D(2).DDHB0[0x40f]=0x33333333222222220000000000000000
DDHB_REG_040D(3).DDHB0[0x410]=0x33333333333333333333333344444444
DDHB_REG_040D(4).DDHB0[0x411]=0x22222222222222220000000000000000
DDHB_REG_040D(5).DDHB0[0x412]=0x33333333333333333333333333333333
DDHB_REG_040D(6).DDHB0[0x413]=0
DDHB_REG_040D(7).DDHB0[0x414]=0xffffffffffffffffaaaaaaaa00000000
DDHB_REG_040D(0).DDHB1[0x40d]=0x44332200000000004433220000
DDHB_REG_040D(1).DDHB1[0x40e]=0x44332200000000004433220000
DDHB_REG_040D(2).DDHB1[0x40f]=0
DDHB_REG_040D(3).DDHB1[0x410]=0
DDHB_REG_040D(4).DDHB1[0x411]=0
DDHB_REG_040D(5).DDHB1[0x412]=0
DDHB_REG_040D(6).DDHB1[0x413]=0
DDHB_REG_040D(7).DDHB1[0x414]=0
DDHB_REG_040D(0).DDHB2[0x40d]=0
DDHB_REG_040D(1).DDHB2[0x40e]=0
DDHB_REG_040D(2).DDHB2[0x40f]=0
DDHB_REG_040D(3).DDHB2[0x410]=0
DDHB_REG_040D(4).DDHB2[0x411]=0
DDHB_REG_040D(5).DDHB2[0x412]=0
DDHB_REG_040D(6).DDHB2[0x413]=0
DDHB_REG_040D(7).DDHB2[0x414]=0
DDHB_REG_040D(0).DDHB3[0x40d]=0x33333333222222220000000000000000
DDHB_REG_040D(1).DDHB3[0x40e]=0x33333333333333333333333344444444
DDHB_REG_040D(2).DDHB3[0x40f]=0x33333333222222220000000000000000
DDHB_REG_040D(3).DDHB3[0x410]=0x33333333333333333333333344444444
DDHB_REG_040D(4).DDHB3[0x411]=0
DDHB_REG_040D(5).DDHB3[0x412]=0
DDHB_REG_040D(6).DDHB3[0x413]=0
DDHB_REG_040D(7).DDHB3[0x414]=0x33333333333333332222222222222222
DDHB_REG_042D(0).DDHB0[0x42d]=0
DDHB_REG_042D(1).DDHB0[0x42e]=0
DDHB_REG_042D(2).DDHB0[0x42f]=0
DDHB_REG_042D(3).DDHB0[0x430]=0
DDHB_REG_042D(4).DDHB0[0x431]=0
DDHB_REG_042D(5).DDHB0[0x432]=0
DDHB_REG_042D(6).DDHB0[0x433]=0
DDHB_REG_042D(7).DDHB0[0x434]=0
DDHB_REG_042D(0).DDHB1[0x42d]=0
DDHB_REG_042D(1).DDHB1[0x42e]=0
DDHB_REG_042D(2).DDHB1[0x42f]=0
DDHB_REG_042D(3).DDHB1[0x430]=0x50505050
DDHB_REG_042D(4).DDHB1[0x431]=0
DDHB_REG_042D(5).DDHB1[0x432]=0xc0c0c0c0
DDHB_REG_042D(6).DDHB1[0x433]=0
DDHB_REG_042D(7).DDHB1[0x434]=0
DDHB_REG_042D(0).DDHB2[0x42d]=0
DDHB_REG_042D(1).DDHB2[0x42e]=0
DDHB_REG_042D(2).DDHB2[0x42f]=0
DDHB_REG_042D(3).DDHB2[0x430]=0
DDHB_REG_042D(4).DDHB2[0x431]=0
DDHB_REG_042D(5).DDHB2[0x432]=0
DDHB_REG_042D(6).DDHB2[0x433]=0
DDHB_REG_042D(7).DDHB2[0x434]=0
DDHB_REG_042D(0).DDHB3[0x42d]=0
DDHB_REG_042D(1).DDHB3[0x42e]=0
DDHB_REG_042D(2).DDHB3[0x42f]=0
DDHB_REG_042D(3).DDHB3[0x430]=0
DDHB_REG_042D(4).DDHB3[0x431]=0
DDHB_REG_042D(5).DDHB3[0x432]=0
DDHB_REG_042D(6).DDHB3[0x433]=0
DDHB_REG_042D(7).DDHB3[0x434]=0
DDHB_REG_045F(0).DDHB0[0x45f]=0
DDHB_REG_045F(1).DDHB0[0x460]=0
DDHB_REG_045F(2).DDHB0[0x461]=0
DDHB_REG_045F(3).DDHB0[0x462]=0
DDHB_REG_045F(4).DDHB0[0x463]=0
DDHB_REG_045F(5).DDHB0[0x464]=0
DDHB_REG_045F(6).DDHB0[0x465]=0
DDHB_REG_045F(7).DDHB0[0x466]=0
DDHB_REG_045F(0).DDHB1[0x45f]=0
DDHB_REG_045F(1).DDHB1[0x460]=0
DDHB_REG_045F(2).DDHB1[0x461]=0
DDHB_REG_045F(3).DDHB1[0x462]=0
DDHB_REG_045F(4).DDHB1[0x463]=0
DDHB_REG_045F(5).DDHB1[0x464]=0
DDHB_REG_045F(6).DDHB1[0x465]=0
DDHB_REG_045F(7).DDHB1[0x466]=0
DDHB_REG_045F(0).DDHB2[0x45f]=0
DDHB_REG_045F(1).DDHB2[0x460]=0
DDHB_REG_045F(2).DDHB2[0x461]=0
DDHB_REG_045F(3).DDHB2[0x462]=0
DDHB_REG_045F(4).DDHB2[0x463]=0
DDHB_REG_045F(5).DDHB2[0x464]=0
DDHB_REG_045F(6).DDHB2[0x465]=0
DDHB_REG_045F(7).DDHB2[0x466]=0
DDHB_REG_045F(0).DDHB3[0x45f]=0
DDHB_REG_045F(1).DDHB3[0x460]=0
DDHB_REG_045F(2).DDHB3[0x461]=0
DDHB_REG_045F(3).DDHB3[0x462]=0
DDHB_REG_045F(4).DDHB3[0x463]=0
DDHB_REG_045F(5).DDHB3[0x464]=0
DDHB_REG_045F(6).DDHB3[0x465]=0
DDHB_REG_045F(7).DDHB3[0x466]=0
DDHB_REG_046F(0).DDHB0[0x46f]=0
DDHB_REG_046F(1).DDHB0[0x470]=0
DDHB_REG_046F(2).DDHB0[0x471]=0
DDHB_REG_046F(3).DDHB0[0x472]=0
DDHB_REG_046F(4).DDHB0[0x473]=0
DDHB_REG_046F(5).DDHB0[0x474]=0
DDHB_REG_046F(6).DDHB0[0x475]=0
DDHB_REG_046F(7).DDHB0[0x476]=0
DDHB_REG_046F(0).DDHB1[0x46f]=0
DDHB_REG_046F(1).DDHB1[0x470]=0
DDHB_REG_046F(2).DDHB1[0x471]=0
DDHB_REG_046F(3).DDHB1[0x472]=0
DDHB_REG_046F(4).DDHB1[0x473]=0
DDHB_REG_046F(5).DDHB1[0x474]=0
DDHB_REG_046F(6).DDHB1[0x475]=0
DDHB_REG_046F(7).DDHB1[0x476]=0
DDHB_REG_046F(0).DDHB2[0x46f]=0
DDHB_REG_046F(1).DDHB2[0x470]=0
DDHB_REG_046F(2).DDHB2[0x471]=0
DDHB_REG_046F(3).DDHB2[0x472]=0
DDHB_REG_046F(4).DDHB2[0x473]=0
DDHB_REG_046F(5).DDHB2[0x474]=0
DDHB_REG_046F(6).DDHB2[0x475]=0
DDHB_REG_046F(7).DDHB2[0x476]=0
DDHB_REG_046F(0).DDHB3[0x46f]=0
DDHB_REG_046F(1).DDHB3[0x470]=0
DDHB_REG_046F(2).DDHB3[0x471]=0
DDHB_REG_046F(3).DDHB3[0x472]=0
DDHB_REG_046F(4).DDHB3[0x473]=0
DDHB_REG_046F(5).DDHB3[0x474]=0
DDHB_REG_046F(6).DDHB3[0x475]=0
DDHB_REG_046F(7).DDHB3[0x476]=0
DDHB_REG_047F(0).DDHB0[0x47f]=0
DDHB_REG_047F(1).DDHB0[0x480]=0
DDHB_REG_047F(2).DDHB0[0x481]=0
DDHB_REG_047F(3).DDHB0[0x482]=0
DDHB_REG_047F(4).DDHB0[0x483]=0
DDHB_REG_047F(5).DDHB0[0x484]=0
DDHB_REG_047F(6).DDHB0[0x485]=0
DDHB_REG_047F(7).DDHB0[0x486]=0
DDHB_REG_047F(0).DDHB1[0x47f]=0
DDHB_REG_047F(1).DDHB1[0x480]=0
DDHB_REG_047F(2).DDHB1[0x481]=0
DDHB_REG_047F(3).DDHB1[0x482]=0
DDHB_REG_047F(4).DDHB1[0x483]=0
DDHB_REG_047F(5).DDHB1[0x484]=0
DDHB_REG_047F(6).DDHB1[0x485]=0
DDHB_REG_047F(7).DDHB1[0x486]=0
DDHB_REG_047F(0).DDHB2[0x47f]=0
DDHB_REG_047F(1).DDHB2[0x480]=0
DDHB_REG_047F(2).DDHB2[0x481]=0
DDHB_REG_047F(3).DDHB2[0x482]=0
DDHB_REG_047F(4).DDHB2[0x483]=0
DDHB_REG_047F(5).DDHB2[0x484]=0
DDHB_REG_047F(6).DDHB2[0x485]=0
DDHB_REG_047F(7).DDHB2[0x486]=0
DDHB_REG_047F(0).DDHB3[0x47f]=0
DDHB_REG_047F(1).DDHB3[0x480]=0
DDHB_REG_047F(2).DDHB3[0x481]=0
DDHB_REG_047F(3).DDHB3[0x482]=0
DDHB_REG_047F(4).DDHB3[0x483]=0
DDHB_REG_047F(5).DDHB3[0x484]=0
DDHB_REG_047F(6).DDHB3[0x485]=0
DDHB_REG_047F(7).DDHB3[0x486]=0
DDHB_RESERVED_MIRROR_ADDR.DDHB0[0x85]=0
DDHB_RESERVED_MIRROR_ADDR.DDHB1[0x85]=0
DDHB_RESERVED_MIRROR_ADDR.DDHB2[0x85]=0
DDHB_RESERVED_MIRROR_ADDR.DDHB3[0x85]=0
DDHB_RESERVED_MTCD.DDHB0[0xae]=0x30
DDHB_RESERVED_MTCD.DDHB1[0xae]=0x30
DDHB_RESERVED_MTCD.DDHB2[0xae]=0x30
DDHB_RESERVED_MTCD.DDHB3[0xae]=0x30
DDHB_RESERVED_MTCP.DDHB0[0xad]=0x300000600000000
DDHB_RESERVED_MTCP.DDHB1[0xad]=0x300000600000000
DDHB_RESERVED_MTCP.DDHB2[0xad]=0x300000600000000
DDHB_RESERVED_MTCP.DDHB3[0xad]=0x300000600000000
DDHB_RESERVED_SPARE_0.DDHB0[0x90]=0xffffffff
DDHB_RESERVED_SPARE_0.DDHB1[0x90]=0xffffffff
DDHB_RESERVED_SPARE_0.DDHB2[0x90]=0xffffffff
DDHB_RESERVED_SPARE_0.DDHB3[0x90]=0xffffffff
DDHB_RESERVED_SPARE_1.DDHB0[0x91]=0xffffffff
DDHB_RESERVED_SPARE_1.DDHB1[0x91]=0xffffffff
DDHB_RESERVED_SPARE_1.DDHB2[0x91]=0xffffffff
DDHB_RESERVED_SPARE_1.DDHB3[0x91]=0xffffffff
DDHB_RESERVED_SPARE_2.DDHB0[0x92]=0
DDHB_RESERVED_SPARE_2.DDHB1[0x92]=0
DDHB_RESERVED_SPARE_2.DDHB2[0x92]=0
DDHB_RESERVED_SPARE_2.DDHB3[0x92]=0
DDHB_RESERVED_SPARE_3.DDHB0[0x93]=0
DDHB_RESERVED_SPARE_3.DDHB1[0x93]=0
DDHB_RESERVED_SPARE_3.DDHB2[0x93]=0
DDHB_RESERVED_SPARE_3.DDHB3[0x93]=0
DDHB_SBUS_BROADCAST_ID.DDHB0[0x86]=0x7ff
DDHB_SBUS_BROADCAST_ID.DDHB1[0x86]=0x7ff
DDHB_SBUS_BROADCAST_ID.DDHB2[0x86]=0x7ff
DDHB_SBUS_BROADCAST_ID.DDHB3[0x86]=0x7ff
DDHB_SBUS_LAST_IN_CHAIN.DDHB0[0x87]=0
DDHB_SBUS_LAST_IN_CHAIN.DDHB1[0x87]=0
DDHB_SBUS_LAST_IN_CHAIN.DDHB2[0x87]=0
DDHB_SBUS_LAST_IN_CHAIN.DDHB3[0x87]=0
DDHB_SPECIAL_CLOCK_CONTROLS.DDHB0[0xc1]=2
DDHB_SPECIAL_CLOCK_CONTROLS.DDHB1[0xc1]=2
DDHB_SPECIAL_CLOCK_CONTROLS.DDHB2[0xc1]=2
DDHB_SPECIAL_CLOCK_CONTROLS.DDHB3[0xc1]=2
DDP_AUTO_DOC_NAME_5.DDP0[0x108]=0x10c51800820009001
DDP_BUFF_CRC_ERR_CNT.DDP0[0x115]=0
DDP_BUNDLE_COUNTERS.DDP0[0x12b]=0
DDP_CPU_DELETE_BDB_CONTROL.DDP0[0x111]=0
DDP_CPU_DEL_BDB_CNT.DDP0[0x11c]=0
DDP_CPU_RELEASE_BDB_CONTROL.DDP0[0x110]=0
DDP_CPU_REL_BDB_CNT.DDP0[0x11d]=0
DDP_CPYDAT_CRC_ERR_DEL_BDB_CNT.DDP0[0x11a]=0
DDP_CPYDAT_ECC_ERR_DEL_BDB_CNT.DDP0[0x119]=0
DDP_CPYDAT_PKTSIZE_ERR_DEL_BDB_CNT.DDP0[0x11b]=0
DDP_CRC_ERR_BDB_CAM_FULL_CNT.DDP0[0x11f]=0
DDP_CRC_ERR_BDB_FIFO_FULL_CNT.DDP0[0x11e]=0
DDP_CRC_ERR_DEL_BDB_CNT.DDP0[0x117]=0
DDP_CRC_STORM_CONFIGURATION_REGISTER.DDP0[0x121]=0
DDP_CRC_STORM_DEBUG.DDP0[0x123]=0
DDP_CRC_STORM_MANUAL_RESET.DDP0[0x122]=0
DDP_DDP_GENERAL_CONFIGURATION.DDP0[0x107]=0xb80fa02000000200000000000000
DDP_DDP_STOP_DEQUEUE.DDP0[0x106]=0
DDP_DEBUG_STATUS.DDP0[0x12c]=0
DDP_DELETE_BDB_CONFIGS.DDP0[0x10f]=0x1d
DDP_DELETE_BDB_FIFO_HEAD.DDP0[0x112]=0
DDP_DELETE_BDB_FIFO_STATUS.DDP0[0x113]=0
DDP_ECC_1B_ERR_CNT.DDP0[0x94]=0
DDP_ECC_2B_ERR_CNT.DDP0[0x96]=0
DDP_ECC_ERR_1B_MONITOR_MEM_MASK.DDP0[0x9a]=0x1ff
DDP_ECC_ERR_2B_MONITOR_MEM_MASK.DDP0[0x9c]=0x1ff
DDP_ECC_INTERRUPT_REGISTER.DDP0[0x7]=0
DDP_ECC_INTERRUPT_REGISTER_MASK.DDP0[0x17]=0
DDP_ECC_INTERRUPT_REGISTER_TEST.DDP0[0x1f]=0
DDP_ERR_INITIATE.DDP0[0x124]=0
DDP_EXT_MEM_ERR_INTERRUPT_REGISTER.DDP0[0x100]=0
DDP_EXT_MEM_ERR_INTERRUPT_REGISTER_MASK.DDP0[0x101]=0
DDP_EXT_MEM_ERR_INTERRUPT_REGISTER_TEST.DDP0[0x102]=0
DDP_GTIMER_CONFIGURATION.DDP0[0x89]=0
DDP_GTIMER_CYCLE.DDP0[0x88]=0x3b9aca00
DDP_INTERRUPT_MASK_REGISTER.DDP0[0x10]=0
DDP_INTERRUPT_REGISTER.DDP0[0x0]=0
DDP_INTERRUPT_REGISTER_TEST.DDP0[0x18]=0
DDP_ITE_CONFIGURATIONS.DDP0[0x109]=0x20
DDP_ITE_DEBUG.DDP0[0x10b]=0x80000000000000000000000000000000000000000000000000000000000000
DDP_ITE_DEBUG_FROM_ITPP.DDP0[0x10e]=0
DDP_ITE_DEBUG_TO_ITPP.DDP0[0x10d]=0
DDP_ITE_ERROR_COUNTERS.DDP0[0x10c]=0
DDP_ITE_FIX_CONFIG.DDP0[0x10a]=0
DDP_ITE_INTERRUPT_REGISTER.DDP0[0x103]=0
DDP_ITE_INTERRUPT_REGISTER_MASK.DDP0[0x104]=0
DDP_ITE_INTERRUPT_REGISTER_TEST.DDP0[0x105]=0
DDP_MAXIMUM_AND_MINIMUM_PACKET_SIZE.DDP0[0x120]=0x86f
DDP_MMU_COUNTERS.DDP0[0x12a]=0
DDP_NOT_OUT_READY_COUNTERS.DDP0[0x126]=0x91af3eda91af3eda91af3eda91af3eda91af3eda91af3eda91af3eda91af3eda
DDP_NO_READ_WHEN_READY_COUNTERS.DDP0[0x125]=0
DDP_PACKET_COUNTERS.DDP0[0x128]=0
DDP_PACKET_ERROR_COUNTERS.DDP0[0x129]=0
DDP_PCMI_0.DDP0[0xb0]=0x3b9aca00
DDP_PCMI_1.DDP0[0xb3]=0x3b9aca00
DDP_PCMI_2.DDP0[0xb6]=0x3b9aca00
DDP_PCMI_3.DDP0[0xb9]=0x3b9aca00
DDP_PCMI_4.DDP0[0xbc]=0x3b9aca00
DDP_PCMI_0_S.DDP0[0xb1]=0
DDP_PCMI_0_T.DDP0[0xb2]=0
DDP_PCMI_1_S.DDP0[0xb4]=0
DDP_PCMI_1_T.DDP0[0xb5]=0
DDP_PCMI_2_S.DDP0[0xb7]=0
DDP_PCMI_2_T.DDP0[0xb8]=0
DDP_PCMI_3_S.DDP0[0xba]=0
DDP_PCMI_3_T.DDP0[0xbb]=0
DDP_PCMI_4_S.DDP0[0xbd]=0
DDP_PCMI_4_T.DDP0[0xbe]=0
DDP_PKT_LST_RD_DBUFF.DDP0[0x114]=0
DDP_REG_00C2.DDP0[0xc2]=0x10
DDP_REG_00C5.DDP0[0xc5]=0x786df
DDP_REG_00C6.DDP0[0xc6]=0x53
DDP_REG_00C7.DDP0[0xc7]=3
DDP_RESERVED_MTCD.DDP0[0xae]=0x30
DDP_RESERVED_MTCP.DDP0[0xad]=0x300000600000000
DDP_RESERVED_SPARE_0.DDP0[0x90]=0xffffffff
DDP_RESERVED_SPARE_1.DDP0[0x91]=0xffffffff
DDP_RESERVED_SPARE_2.DDP0[0x92]=0
DDP_RESERVED_SPARE_3.DDP0[0x93]=0
DDP_SBUS_BROADCAST_ID.DDP0[0x86]=0x7ff
DDP_SBUS_LAST_IN_CHAIN.DDP0[0x87]=0
DDP_SPECIAL_CLOCK_CONTROLS.DDP0[0xc1]=2
DDP_TDU_ERR_DEL_BDB_CNT.DDP0[0x118]=0
DDP_TDU_WORDS_ERR_CNT.DDP0[0x116]=0
DDP_TXI_NOT_READY_COUNTERS.DDP0[0x127]=0
DMU_CRU_IHOST_PWR_CONTROL.CMIC0[0x40204]=6
DMU_CRU_IHOST_PWR_CONTROL_STATUS.CMIC0[0x40208]=0
DMU_CRU_IPROC_DEBUG_SEL.CMIC0[0x4020c]=0
DMU_CRU_IPROC_DEBUG_STATUS.CMIC0[0x40210]=0
DMU_CRU_RESET.CMIC0[0x40200]=3
DMU_PCU_CHIP_PLL_LOCK_CONTROL.CMIC0[0x40010]=0
DMU_PCU_CHIP_PLL_LOCK_STATUS.CMIC0[0x4000c]=1
DMU_PCU_CRU_RESET_REASON.CMIC0[0x40014]=0
DMU_PCU_IPROC_CONTROL.CMIC0[0x40000]=0
DMU_PCU_IPROC_RESET_REASON.CMIC0[0x40018]=0
DMU_PCU_IPROC_STRAPS_CAPTURED.CMIC0[0x40028]=0x1800
DMU_PCU_IPROC_STRAPS_SW_OVERRIDE.CMIC0[0x4002c]=0x802
DMU_PCU_OTP_CONFIG_0.CMIC0[0x40048]=0
DMU_PCU_OTP_CONFIG_1.CMIC0[0x4004c]=0
DMU_PCU_OTP_CONFIG_2.CMIC0[0x40050]=0
DMU_PCU_OTP_CONFIG_3.CMIC0[0x40054]=0
DMU_PCU_OTP_CONFIG_4.CMIC0[0x40058]=0
DMU_PCU_OTP_CONFIG_5.CMIC0[0x4005c]=0
DMU_PCU_OTP_CONFIG_6.CMIC0[0x40060]=0
DMU_PCU_OTP_CONFIG_7.CMIC0[0x40064]=0
DMU_PCU_OTP_CONFIG_8.CMIC0[0x40068]=0
DMU_PCU_OTP_CONFIG_9.CMIC0[0x4006c]=0
DMU_PCU_OTP_CONFIG_10.CMIC0[0x40070]=0
DMU_PCU_OTP_CONFIG_11.CMIC0[0x40074]=0
DMU_PCU_OTP_CONFIG_12.CMIC0[0x40078]=0
DMU_PCU_OTP_CONFIG_13.CMIC0[0x4007c]=0
DMU_PCU_OTP_CONFIG_14.CMIC0[0x40080]=0
DMU_PCU_OTP_CONFIG_15.CMIC0[0x40084]=0
DMU_PCU_OTP_CONFIG_16.CMIC0[0x40088]=0
DMU_PCU_OTP_CONFIG_17.CMIC0[0x4008c]=0
DMU_PCU_OTP_CONFIG_18.CMIC0[0x40090]=0
DMU_PCU_OTP_CONFIG_19.CMIC0[0x40094]=0
DMU_PCU_OTP_CONFIG_20.CMIC0[0x40098]=0
DMU_PCU_OTP_CONFIG_21.CMIC0[0x4009c]=0
DMU_PCU_OTP_CONFIG_22.CMIC0[0x400a0]=0
DMU_PCU_OTP_CONFIG_23.CMIC0[0x400a4]=0
DMU_PCU_OTP_CONFIG_24.CMIC0[0x400a8]=0
DMU_PCU_OTP_CONFIG_25.CMIC0[0x400ac]=0
DMU_PCU_OTP_CONFIG_26.CMIC0[0x400b0]=0
DMU_PCU_OTP_CONFIG_27.CMIC0[0x400b4]=0
DMU_PCU_OTP_CONFIG_28.CMIC0[0x400b8]=0
DMU_PCU_OTP_CONFIG_29.CMIC0[0x400bc]=0
DMU_PCU_OTP_CONFIG_30.CMIC0[0x400c0]=0
DMU_PCU_OTP_CONFIG_31.CMIC0[0x400c4]=0
DMU_PCU_OTP_SW_OVERRIDE_0.CMIC0[0x400c8]=0
DMU_PCU_OTP_SW_OVERRIDE_1.CMIC0[0x400cc]=0
DMU_PCU_OTP_SW_OVERRIDE_2.CMIC0[0x400d0]=0
DMU_PCU_OTP_SW_OVERRIDE_3.CMIC0[0x400d4]=0
DMU_PCU_OTP_SW_OVERRIDE_4.CMIC0[0x400d8]=0
DMU_PCU_OTP_SW_OVERRIDE_5.CMIC0[0x400dc]=0
DMU_PCU_OTP_SW_OVERRIDE_6.CMIC0[0x400e0]=0
DMU_PCU_OTP_SW_OVERRIDE_7.CMIC0[0x400e4]=0
DMU_PCU_OTP_SW_OVERRIDE_8.CMIC0[0x400e8]=0
DMU_PCU_OTP_SW_OVERRIDE_9.CMIC0[0x400ec]=0
DMU_PCU_OTP_SW_OVERRIDE_10.CMIC0[0x400f0]=0
DMU_PCU_OTP_SW_OVERRIDE_11.CMIC0[0x400f4]=0
DMU_PCU_OTP_SW_OVERRIDE_12.CMIC0[0x400f8]=0
DMU_PCU_OTP_SW_OVERRIDE_13.CMIC0[0x400fc]=0
DMU_PCU_OTP_SW_OVERRIDE_14.CMIC0[0x40100]=0
DMU_PCU_OTP_SW_OVERRIDE_15.CMIC0[0x40104]=0
DMU_PCU_OTP_SW_OVERRIDE_16.CMIC0[0x40108]=0
DMU_PCU_OTP_SW_OVERRIDE_17.CMIC0[0x4010c]=0
DMU_PCU_OTP_SW_OVERRIDE_18.CMIC0[0x40110]=0
DMU_PCU_OTP_SW_OVERRIDE_19.CMIC0[0x40114]=0
DMU_PCU_OTP_SW_OVERRIDE_20.CMIC0[0x40118]=0
DMU_PCU_OTP_SW_OVERRIDE_21.CMIC0[0x4011c]=0
DMU_PCU_OTP_SW_OVERRIDE_22.CMIC0[0x40120]=0
DMU_PCU_OTP_SW_OVERRIDE_23.CMIC0[0x40124]=0
DMU_PCU_OTP_SW_OVERRIDE_24.CMIC0[0x40128]=0
DMU_PCU_OTP_SW_OVERRIDE_25.CMIC0[0x4012c]=0
DMU_PCU_OTP_SW_OVERRIDE_26.CMIC0[0x40130]=0
DMU_PCU_OTP_SW_OVERRIDE_27.CMIC0[0x40134]=0
DMU_PCU_OTP_SW_OVERRIDE_28.CMIC0[0x40138]=0
DMU_PCU_OTP_SW_OVERRIDE_29.CMIC0[0x4013c]=0
DMU_PCU_OTP_SW_OVERRIDE_30.CMIC0[0x40140]=0
DMU_PCU_OTP_SW_OVERRIDE_31.CMIC0[0x40144]=0
DMU_PCU_OTP_SW_OVERRIDE_EN.CMIC0[0x40034]=0
DMU_PCU_PCIE_SLAVE_RESET_MODE.CMIC0[0x40024]=0
DMU_PCU_POR_CONTROL.CMIC0[0x40044]=0x10
DMU_PCU_SOFT_RESET.CMIC0[0x40008]=0
DMU_PCU_SWITCH_RESET_REASON.CMIC0[0x4001c]=2
DMU_PCU_WATCHDOG_RESET_MODE.CMIC0[0x40020]=0
DPC_DRAM_PHY_CONTROL.DPC0[0x103]=3
DPC_DRAM_PHY_CONTROL.DPC1[0x103]=0x13
DPC_DRAM_PHY_REGISTER_STATUS.DPC0[0x105]=0
DPC_DRAM_PHY_REGISTER_STATUS.DPC1[0x105]=0
DPC_DRAM_PLL_CONFIG.DPC0[0x100]=0x19000000000000000000040000009010000000000300000000000000000023
DPC_DRAM_PLL_CONFIG.DPC1[0x100]=0x19000000000000000000040000009010000000000300000000000000000023
DPC_DRAM_PLL_STATUS.DPC0[0x101]=0x14b5
DPC_DRAM_PLL_STATUS.DPC1[0x101]=0x14b5
DPC_DRAM_RESET_CONTROL.DPC0[0x104]=1
DPC_DRAM_RESET_CONTROL.DPC1[0x104]=1
DPC_ECC_INTERRUPT_REGISTER.DPC0[0x7]=0
DPC_ECC_INTERRUPT_REGISTER.DPC1[0x7]=0
DPC_ECC_INTERRUPT_REGISTER_MASK.DPC0[0x17]=0
DPC_ECC_INTERRUPT_REGISTER_MASK.DPC1[0x17]=0
DPC_ECC_INTERRUPT_REGISTER_TEST.DPC0[0x1f]=0
DPC_ECC_INTERRUPT_REGISTER_TEST.DPC1[0x1f]=0
DPC_ENABLE_DYNAMIC_MEMORY_ACCESS.DPC0[0x84]=1
DPC_ENABLE_DYNAMIC_MEMORY_ACCESS.DPC1[0x84]=1
DPC_INDIRECT_COMMAND.DPC0[0x80]=0xe000000
DPC_INDIRECT_COMMAND.DPC1[0x80]=0xe000000
DPC_INDIRECT_COMMAND_ADDRESS.DPC0[0x81]=0x8000030a
DPC_INDIRECT_COMMAND_ADDRESS.DPC1[0x81]=0x8000030a
DPC_INDIRECT_COMMAND_RD_DATA.DPC0[0x60]=0x9001
DPC_INDIRECT_COMMAND_RD_DATA.DPC1[0x60]=0x9002
DPC_INDIRECT_COMMAND_WR_DATA.DPC0[0x20]=0x8007d0
DPC_INDIRECT_COMMAND_WR_DATA.DPC1[0x20]=0x8007d0
DPC_INDIRECT_FORCE_BUBBLE.DPC0[0x83]=0x20019
DPC_INDIRECT_FORCE_BUBBLE.DPC1[0x83]=0x20019
DPC_INTERRUPT_MASK_REGISTER.DPC0[0x10]=0
DPC_INTERRUPT_MASK_REGISTER.DPC1[0x10]=0
DPC_INTERRUPT_REGISTER.DPC0[0x0]=0
DPC_INTERRUPT_REGISTER.DPC1[0x0]=0
DPC_INTERRUPT_REGISTER_TEST.DPC0[0x18]=0
DPC_INTERRUPT_REGISTER_TEST.DPC1[0x18]=0
DPC_PHY_POR_STATUS.DPC0[0x102]=1
DPC_PHY_POR_STATUS.DPC1[0x102]=1
DPC_REG_0041.DPC0[0x41]=0
DPC_REG_0041.DPC1[0x41]=0
DPC_REG_009A.DPC0[0x9a]=0
DPC_REG_009A.DPC1[0x9a]=0
DPC_REG_009C.DPC0[0x9c]=0
DPC_REG_009C.DPC1[0x9c]=0
DPC_RESERVED_MTCD.DPC0[0xae]=0x30
DPC_RESERVED_MTCD.DPC1[0xae]=0x30
DPC_RESERVED_MTCP.DPC0[0xad]=0x300000600000000
DPC_RESERVED_MTCP.DPC1[0xad]=0x300000600000000
DPC_RESERVED_SPARE_0.DPC0[0x90]=0xffffffff
DPC_RESERVED_SPARE_0.DPC1[0x90]=0xffffffff
DPC_RESERVED_SPARE_1.DPC0[0x91]=0xffffffff
DPC_RESERVED_SPARE_1.DPC1[0x91]=0xffffffff
DPC_RESERVED_SPARE_2.DPC0[0x92]=0
DPC_RESERVED_SPARE_2.DPC1[0x92]=0
DPC_RESERVED_SPARE_3.DPC0[0x93]=0
DPC_RESERVED_SPARE_3.DPC1[0x93]=0
DPC_SBUS_BROADCAST_ID.DPC0[0x86]=0x7ff
DPC_SBUS_BROADCAST_ID.DPC1[0x86]=0x7ff
DPC_SBUS_LAST_IN_CHAIN.DPC0[0x87]=0
DPC_SBUS_LAST_IN_CHAIN.DPC1[0x87]=0
DPC_SPECIAL_CLOCK_CONTROLS.DPC0[0xc1]=2
DPC_SPECIAL_CLOCK_CONTROLS.DPC1[0xc1]=2
DQM_BDB_ALLOCATE_NRDY_CTR.DQM0[0x209]=0
DQM_BDM_RD_ACCESS_DROP_CTR.DQM0[0x206]=0
DQM_BDM_RD_ACCESS_VALID_CTR.DQM0[0x205]=0
DQM_BDM_WR_ACCESS_VALID_CTR.DQM0[0x204]=0
DQM_BD_RD_REQ_NRDY_CTR.DQM0[0x208]=0
DQM_BD_WR_REQ_NRDY_CTR.DQM0[0x207]=0
DQM_BUNDLE_DEQ_CTR.DQM0[0x203]=0
DQM_BUNDLE_ENQ_CTR.DQM0[0x202]=0
DQM_DQM_ENABLERS.DQM0[0x201]=3
DQM_DQM_INIT.DQM0[0x200]=0
DQM_ECC_1B_ERR_CNT.DQM0[0x94]=0
DQM_ECC_2B_ERR_CNT.DQM0[0x96]=0
DQM_ECC_ERR_1B_MONITOR_MEM_MASK.DQM0[0x9a]=0x3f
DQM_ECC_ERR_2B_MONITOR_MEM_MASK.DQM0[0x9c]=0x3f
DQM_ECC_INTERRUPT_REGISTER.DQM0[0x7]=0
DQM_ECC_INTERRUPT_REGISTER_MASK.DQM0[0x17]=0
DQM_ECC_INTERRUPT_REGISTER_TEST.DQM0[0x1f]=0
DQM_ENABLE_DYNAMIC_MEMORY_ACCESS.DQM0[0x84]=0
DQM_GTIMER_CONFIGURATION.DQM0[0x89]=0
DQM_GTIMER_CYCLE.DQM0[0x88]=0x3b9aca00
DQM_INDIRECT_COMMAND.DQM0[0x80]=0xe000002
DQM_INDIRECT_COMMAND_ADDRESS.DQM0[0x81]=0x100
DQM_INDIRECT_COMMAND_RD_DATA.DQM0[0x60]=0x2000000000000040000
DQM_INDIRECT_COMMAND_WR_DATA.DQM0[0x20]=0
DQM_INDIRECT_FORCE_BUBBLE.DQM0[0x83]=0x20019
DQM_INTERRUPT_MASK_REGISTER.DQM0[0x10]=0
DQM_INTERRUPT_REGISTER.DQM0[0x0]=0
DQM_INTERRUPT_REGISTER_TEST.DQM0[0x18]=0
DQM_IQM_BUNDLE_TX_NRDY_CTR.DQM0[0x20a]=0
DQM_LAST_DEQ_CMD.DQM0[0x20c]=0
DQM_LAST_ENQ_CMD.DQM0[0x20b]=0
DQM_REG_0041.DQM0[0x41]=0
DQM_REG_0210.DQM0[0x210]=0x1000000206
DQM_REG_0211.DQM0[0x211]=0
DQM_REG_0212.DQM0[0x212]=0
DQM_REG_0213.DQM0[0x213]=0
DQM_REG_0214.DQM0[0x214]=1
DQM_REG_00C2.DQM0[0xc2]=0x10
DQM_REG_00C5.DQM0[0xc5]=0x786df
DQM_REG_00C7.DQM0[0xc7]=3
DQM_REG_020E.DQM0[0x20e]=0x101000000
DQM_REG_020F.DQM0[0x20f]=0
DQM_RESERVED_MTCD.DQM0[0xae]=0x30
DQM_RESERVED_MTCP.DQM0[0xad]=0x300000600000000
DQM_RESERVED_SPARE_0.DQM0[0x90]=0xffffffff
DQM_RESERVED_SPARE_1.DQM0[0x91]=0xffffffff
DQM_RESERVED_SPARE_2.DQM0[0x92]=0
DQM_RESERVED_SPARE_3.DQM0[0x93]=0
DQM_SBUS_BROADCAST_ID.DQM0[0x86]=0x7ff
DQM_SBUS_LAST_IN_CHAIN.DQM0[0x87]=0
DQM_SPECIAL_CLOCK_CONTROLS.DQM0[0xc1]=2
DQM_TX_FIFO_ERR_INTERRUPT_MASK_REGISTER.DQM0[0x111]=0
DQM_TX_FIFO_ERR_INTERRUPT_REGISTER.DQM0[0x110]=0
DQM_TX_FIFO_ERR_INTERRUPT_REGISTER_TEST.DQM0[0x112]=0
DQM_TX_FIFO_MAX_STATUS.DQM0[0x20d]=0
ECGM_CGM_DB_TH_SP_OR_SHARED.ECGM0[0x159]=0
ECGM_CGM_DEBUG_COUNTERS.ECGM0[0x1cf]=0
ECGM_CGM_DISABLE_DISCARDS_TO_PQP.ECGM0[0x15b]=0
ECGM_CGM_DISABLE_DISCARDS_TO_RQP.ECGM0[0x15a]=0
ECGM_CGM_DP_ELIGIBLE_TO_USE_RESOURCES.ECGM0[0x134]=0xff
ECGM_CGM_DROP_CTR_PKT_OR_DB.ECGM0[0x158]=0
ECGM_CGM_DYN_TH_DEBUG.ECGM0[0x1c5]=0x119b47e08dc91f818f431e8d661acc07481d22150854
ECGM_CGM_INIT_DONE.ECGM0[0x100]=3
ECGM_CGM_MAP_IF_2_TH.ECGM0[0x14a]=0x249249249249249249249249249000000000000000000001249
ECGM_CGM_MAP_REPLICATION_FIFO_TO_TC.ECGM0[0x101]=0xf00f
ECGM_CGM_MC_PD_PER_PORT_DYN_TH_DEBUG.ECGM0[0x1cb]=0
ECGM_CGM_MC_PD_TC_FC_TH.ECGM0[0x142]=0x6d81a585018d2d21324f0cb981a5a
ECGM_CGM_PD_TH_SP_OR_SHARED.ECGM0[0x157]=0
ECGM_CGM_QUEUE_PAIR_DISABLED.ECGM0[0x124]=0
ECGM_CGM_REP_AROUND_INTERRUPT_REGISTER.ECGM0[0x1bf]=0
ECGM_CGM_REP_AROUND_INTERRUPT_REGISTER_MASK.ECGM0[0x1c1]=0
ECGM_CGM_REP_AROUND_INT_REG_TEST.ECGM0[0x1c3]=0
ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_ALPHA_0.ECGM0[0x11e]=0
ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_ALPHA_1.ECGM0[0x120]=0
ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_MAXIMUM_THRESHOLDS.ECGM0[0x110]=0x6c434113c8682000000000000000000000000000020cc9c32dd0d04
ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_MINIMUM_THRESHOLDS.ECGM0[0x117]=0x6c434113c8682000000000000000000000000000020cc9c32dd0d04
ECGM_CONGESTION_MANAGEMENT_GLOBAL_DB_THRESHOLDS.ECGM0[0x105]=0x68234127104e21388
ECGM_CONGESTION_MANAGEMENT_GLOBAL_FLOW_CONTROL_THRESHOLDS.ECGM0[0x13d]=0x2fe97f434b4d2d23f09e223f073008fc11f8
ECGM_CONGESTION_MANAGEMENT_GLOBAL_PD_THRESHOLDS.ECGM0[0x102]=0xe523948fa0157c1388
ECGM_CONGESTION_MANAGEMENT_MULTICAST_FLOW_CONTROL_PER_TC_THREHOSLDS.ECGM0[0x146]=0x6382fe12345fd1e2c8fb2a28bfa
ECGM_CONGESTION_MANAGEMENT_MULTICAST_RESERVED_RESOURCES.ECGM0[0x122]=0x96012c00ec01d8
ECGM_CONGESTION_MANAGEMENT_MULTICAST_RESERVED_RESOURCES_PER_CLASS.ECGM0[0x136]=0x4b012c04b012c000000000000000000000000000004b012c04b012c
ECGM_CONGESTION_MANAGEMENT_PD_SERVICE_POOL_THRESHOLDS.ECGM0[0x108]=0x7721ca45710e52241655ecc9a1ca407721ca45710e52241655ecc9a1ca4
ECGM_CONGESTION_TRACKING_MULTICAST_DBSP_0_MAX_VALUE.ECGM0[0x16a]=0
ECGM_CONGESTION_TRACKING_MULTICAST_DBSP_1_MAX_VALUE.ECGM0[0x16b]=0
ECGM_CONGESTION_TRACKING_MULTICAST_DB_MAX_VALUE.ECGM0[0x166]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(0).ECGM0[0x17c]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(1).ECGM0[0x17d]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(2).ECGM0[0x17e]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(3).ECGM0[0x17f]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(4).ECGM0[0x180]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(5).ECGM0[0x181]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(6).ECGM0[0x182]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(7).ECGM0[0x183]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(8).ECGM0[0x184]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(9).ECGM0[0x185]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(10).ECGM0[0x186]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(11).ECGM0[0x187]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(12).ECGM0[0x188]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(13).ECGM0[0x189]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(14).ECGM0[0x18a]=0
ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE(15).ECGM0[0x18b]=0
ECGM_CONGESTION_TRACKING_MULTICAST_PDSP_0_MAX_VALUE.ECGM0[0x168]=0
ECGM_CONGESTION_TRACKING_MULTICAST_PDSP_1_MAX_VALUE.ECGM0[0x169]=0
ECGM_CONGESTION_TRACKING_MULTICAST_PD_MAX_VALUE.ECGM0[0x163]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(0).ECGM0[0x16c]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(1).ECGM0[0x16d]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(2).ECGM0[0x16e]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(3).ECGM0[0x16f]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(4).ECGM0[0x170]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(5).ECGM0[0x171]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(6).ECGM0[0x172]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(7).ECGM0[0x173]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(8).ECGM0[0x174]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(9).ECGM0[0x175]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(10).ECGM0[0x176]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(11).ECGM0[0x177]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(12).ECGM0[0x178]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(13).ECGM0[0x179]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(14).ECGM0[0x17a]=0
ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE(15).ECGM0[0x17b]=0
ECGM_CONGESTION_TRACKING_TOTAL_DB_MAX_VALUE.ECGM0[0x167]=0x5d
ECGM_CONGESTION_TRACKING_TOTAL_PD_MAX_VALUE.ECGM0[0x164]=0x3f
ECGM_CONGESTION_TRACKING_UNICAST_DB_MAX_VALUE.ECGM0[0x165]=0x5d
ECGM_CONGESTION_TRACKING_UNICAST_PD_MAX_VALUE.ECGM0[0x162]=0x3f
ECGM_ECC_1B_ERR_CNT.ECGM0[0x94]=0
ECGM_ECC_2B_ERR_CNT.ECGM0[0x96]=0
ECGM_ECC_ERR_1B_MONITOR_MEM_MASK.ECGM0[0x9a]=0x3fff
ECGM_ECC_ERR_2B_MONITOR_MEM_MASK.ECGM0[0x9c]=0x3fff
ECGM_ECC_INTERRUPT_REGISTER.ECGM0[0x7]=0
ECGM_ECC_INTERRUPT_REGISTER_MASK.ECGM0[0x17]=0
ECGM_ECC_INTERRUPT_REGISTER_TEST.ECGM0[0x1f]=0
ECGM_EGQ_2_SCH_GLOBAL_FC.ECGM0[0x1dd]=0
ECGM_EGQ_2_SCH_INTERFACE_FC.ECGM0[0x1d8]=0
ECGM_EGQ_2_SCH_INTERFACE_FC_CFG.ECGM0[0x1d7]=1
ECGM_EGQ_2_SCH_PORT_FC.ECGM0[0x1d3]=0
ECGM_EGQ_2_SCH_PORT_FC_CFG.ECGM0[0x1d2]=3
ECGM_ENABLE_DYNAMIC_MEMORY_ACCESS.ECGM0[0x84]=0xfff
ECGM_GTIMER_CONFIGURATION.ECGM0[0x89]=0
ECGM_GTIMER_CYCLE.ECGM0[0x88]=0x3b9aca00
ECGM_INDIRECT_COMMAND.ECGM0[0x80]=0xe000002
ECGM_INDIRECT_COMMAND_ADDRESS.ECGM0[0x81]=0x80020248
ECGM_INDIRECT_COMMAND_RD_DATA.ECGM0[0x60]=0
ECGM_INDIRECT_COMMAND_WR_DATA.ECGM0[0x20]=0x1800000
ECGM_INDIRECT_FORCE_BUBBLE.ECGM0[0x83]=0x20019
ECGM_INTERRUPT_MASK_REGISTER.ECGM0[0x10]=0
ECGM_INTERRUPT_REGISTER.ECGM0[0x0]=4
ECGM_INTERRUPT_REGISTER_TEST.ECGM0[0x18]=0
ECGM_MC_DB_SP_TC_CNT(0).ECGM0[0x1aa]=0
ECGM_MC_DB_SP_TC_CNT(1).ECGM0[0x1ab]=0
ECGM_MC_DB_SP_TC_CNT(2).ECGM0[0x1ac]=0
ECGM_MC_DB_SP_TC_CNT(3).ECGM0[0x1ad]=0
ECGM_MC_DB_SP_TC_CNT(4).ECGM0[0x1ae]=0
ECGM_MC_DB_SP_TC_CNT(5).ECGM0[0x1af]=0
ECGM_MC_DB_SP_TC_CNT(6).ECGM0[0x1b0]=0
ECGM_MC_DB_SP_TC_CNT(7).ECGM0[0x1b1]=0
ECGM_MC_DB_SP_TC_CNT(8).ECGM0[0x1b2]=0
ECGM_MC_DB_SP_TC_CNT(9).ECGM0[0x1b3]=0
ECGM_MC_DB_SP_TC_CNT(10).ECGM0[0x1b4]=0
ECGM_MC_DB_SP_TC_CNT(11).ECGM0[0x1b5]=0
ECGM_MC_DB_SP_TC_CNT(12).ECGM0[0x1b6]=0
ECGM_MC_DB_SP_TC_CNT(13).ECGM0[0x1b7]=0
ECGM_MC_DB_SP_TC_CNT(14).ECGM0[0x1b8]=0
ECGM_MC_DB_SP_TC_CNT(15).ECGM0[0x1b9]=0
ECGM_MC_PD_SP_TC_CNT(0).ECGM0[0x19a]=0
ECGM_MC_PD_SP_TC_CNT(1).ECGM0[0x19b]=0
ECGM_MC_PD_SP_TC_CNT(2).ECGM0[0x19c]=0
ECGM_MC_PD_SP_TC_CNT(3).ECGM0[0x19d]=0
ECGM_MC_PD_SP_TC_CNT(4).ECGM0[0x19e]=0
ECGM_MC_PD_SP_TC_CNT(5).ECGM0[0x19f]=0
ECGM_MC_PD_SP_TC_CNT(6).ECGM0[0x1a0]=0
ECGM_MC_PD_SP_TC_CNT(7).ECGM0[0x1a1]=0
ECGM_MC_PD_SP_TC_CNT(8).ECGM0[0x1a2]=0
ECGM_MC_PD_SP_TC_CNT(9).ECGM0[0x1a3]=0
ECGM_MC_PD_SP_TC_CNT(10).ECGM0[0x1a4]=0
ECGM_MC_PD_SP_TC_CNT(11).ECGM0[0x1a5]=0
ECGM_MC_PD_SP_TC_CNT(12).ECGM0[0x1a6]=0
ECGM_MC_PD_SP_TC_CNT(13).ECGM0[0x1a7]=0
ECGM_MC_PD_SP_TC_CNT(14).ECGM0[0x1a8]=0
ECGM_MC_PD_SP_TC_CNT(15).ECGM0[0x1a9]=0
ECGM_MULTICAST_DATA_BUFFERS_COUNTER.ECGM0[0x190]=0
ECGM_MULTICAST_DATA_BUFFERS_DROP_COUNTER.ECGM0[0x161]=0
ECGM_MULTICAST_REPLICATIONS_PACKET_DESCRIPTORS_COUNTER.ECGM0[0x18d]=0
ECGM_MULTICAST_REPLICATIONS_PACKET_DESCRIPTORS_DROP_COUNTER.ECGM0[0x15d]=0
ECGM_MULTICAST_REPLICATIONS_QUEUE_LENGTH_DROP_COUNTER.ECGM0[0x160]=0
ECGM_PQP_DISCARD_REASONS.ECGM0[0x1bc]=0x639188e08100400040
ECGM_REG_0041.ECGM0[0x41]=0
ECGM_REG_00C2.ECGM0[0xc2]=0x10
ECGM_REG_00C5.ECGM0[0xc5]=0x78000
ECGM_RESERVED_MTCD.ECGM0[0xae]=0x30
ECGM_RESERVED_MTCP.ECGM0[0xad]=0x300000600000000
ECGM_RESERVED_SPARE_0.ECGM0[0x90]=0xffffffff
ECGM_RESERVED_SPARE_1.ECGM0[0x91]=0xffffffff
ECGM_RESERVED_SPARE_2.ECGM0[0x92]=0
ECGM_RESERVED_SPARE_3.ECGM0[0x93]=0
ECGM_RQP_DISCARD_REASONS.ECGM0[0x1ba]=0
ECGM_SBUS_BROADCAST_ID.ECGM0[0x86]=0x7ff
ECGM_SBUS_LAST_IN_CHAIN.ECGM0[0x87]=0
ECGM_SERVICE_POOL_0_MULTICAST_DATA_BUFFERS_COUNTER.ECGM0[0x194]=0
ECGM_SERVICE_POOL_0_MULTICAST_PACKET_DESCRIPTORS_COUNTER.ECGM0[0x192]=0
ECGM_SERVICE_POOL_0_RESERVED_DATA_BUFFERS.ECGM0[0x198]=0x4b0
ECGM_SERVICE_POOL_0_RESERVED_PACKET_DESCRIPTORS.ECGM0[0x196]=0x1d8
ECGM_SERVICE_POOL_1_MULTICAST_DATA_BUFFERS_COUNTER.ECGM0[0x195]=0
ECGM_SERVICE_POOL_1_MULTICAST_PACKET_DESCRIPTORS_COUNTER.ECGM0[0x193]=0
ECGM_SERVICE_POOL_1_RESERVED_DATA_BUFFERS.ECGM0[0x199]=0x4b0
ECGM_SERVICE_POOL_1_RESERVED_PACKET_DESCRIPTORS.ECGM0[0x197]=0x1d8
ECGM_SPECIAL_CLOCK_CONTROLS.ECGM0[0xc1]=2
ECGM_STATISTICS_TRACKING_CONTROL.ECGM0[0x135]=0
ECGM_TOTAL_DATA_BUFFERS_COUNTER.ECGM0[0x191]=0
ECGM_TOTAL_PACKET_DESCRIPTORS_COUNTER.ECGM0[0x18e]=0
ECGM_UNICAST_DATA_BUFFERS_COUNTER.ECGM0[0x18f]=0
ECGM_UNICAST_DATA_BUFFERS_DROP_BY_PQP_COUNTER.ECGM0[0x15f]=0
ECGM_UNICAST_DATA_BUFFERS_DROP_BY_RQP_COUNTER.ECGM0[0x15e]=0
ECGM_UNICAST_PACKET_DESCRIPTORS_COUNTER.ECGM0[0x18c]=0
ECGM_UNICAST_PACKET_DESCRIPTORS_DROP_COUNTER.ECGM0[0x15c]=0x7f
ECI_AVS_TOP_CTRL.ECI0[0x16d]=0
ECI_BLOCKS_POWER_DOWN.ECI0[0x171]=0
ECI_BLOCKS_SBUS_RESET.ECI0[0x173]=0
ECI_BLOCKS_SOFT_INIT.ECI0[0x174]=0
ECI_BLOCKS_SOFT_RESET.ECI0[0x172]=0
ECI_BOND_STATUS.ECI0[0x163]=0x7128483
ECI_BROAD_VIEW_CTRL.ECI0[0x1e8]=0
ECI_BS_PLL_CONFIGURATIONS.ECI0[0x12d]=0x300000000000000000000023c0000000000000000000000000000c000003c000000019000000000000000000000012c00
ECI_BS_PLL_STATUS.ECI0[0x155]=0xa5a01
ECI_CDU_INSTRUMENTATION_CTRL.ECI0[0x1ea]=0
ECI_CGM_INST_CTRL.ECI0[0x1e9]=0
ECI_CORE_FREQUENCY_VALUE.ECI0[0x1f8]=0x24103560
ECI_CORE_PLL_STATUS.ECI0[0x13c]=0xa5a01
ECI_CPU_CHANNEL_CONFIGURATION.ECI0[0x1ef]=2
ECI_CRPS_INSTRUMENTATION_CTRL.ECI0[0x1eb]=0
ECI_CRPS_SELECT_TIME_OF_DAY_SOURCE.ECI0[0x1e3]=1
ECI_DBG_LAST_EVENT_NUM.ECI0[0x1ee]=0
ECI_ECC_1B_ERR_CNT.ECI0[0x94]=0x14e0000
ECI_ECC_2B_ERR_CNT.ECI0[0x96]=0x3ef0000
ECI_ECC_ERR_1B_MONITOR_MEM_MASK.ECI0[0x9a]=3
ECI_ECC_ERR_2B_MONITOR_MEM_MASK.ECI0[0x9c]=3
ECI_ECC_INTERRUPT_REGISTER.ECI0[0x7]=0
ECI_ECC_INTERRUPT_REGISTER_MASK.ECI0[0x17]=0
ECI_ECC_INTERRUPT_REGISTER_TEST.ECI0[0x1f]=0
ECI_ECIC_MDIO_CONFIG.ECI0[0x112]=0
ECI_ECIC_MISC_RESET.ECI0[0x111]=0x18
ECI_ECI_FIFO_CONFIG.ECI0[0x1f9]=0
ECI_ECI_INTERRUPTS.ECI0[0x1f0]=0
ECI_ECI_INTERRUPTS_MASK.ECI0[0x1f1]=0
ECI_ECI_PIR_DEBUG_REGISTER.ECI0[0x1f2]=3
ECI_ECI_REGISTER_0.ECI0[0x188]=0x402000
ECI_ENABLE_DYNAMIC_MEMORY_ACCESS.ECI0[0x84]=0
ECI_EPNI_PKT_WRITTEN.ECI0[0x1f3]=0x36fb333
ECI_FAB_1_PLL_STATUS.ECI0[0x143]=0xa5a01
ECI_FAB_PLL_STATUS.ECI0[0x13d]=0xa5a01
ECI_FAP_GLOBAL_GENERAL_CFG_1.ECI0[0xc3]=1
ECI_FAP_GLOBAL_GENERAL_CFG_2.ECI0[0xc4]=0
ECI_FAP_GLOBAL_GENERAL_CFG_3.ECI0[0xc5]=0x786df
ECI_FAP_GLOBAL_GENERAL_IDB.ECI0[0xc7]=3
ECI_FAP_GLOBAL_PP_1.ECI0[0xe7]=0xf0f0f0
ECI_FAP_GLOBAL_PP_2.ECI0[0xe8]=0x88a88100
ECI_FAP_GLOBAL_PP_3.ECI0[0xe9]=0x9100
ECI_FAP_GLOBAL_PP_4.ECI0[0xea]=0
ECI_FAP_GLOBAL_PP_5.ECI0[0xeb]=0
ECI_FAP_GLOBAL_PP_6.ECI0[0xec]=0
ECI_FAP_GLOBAL_PP_7.ECI0[0xed]=2
ECI_FAP_GLOBAL_PP_8.ECI0[0xee]=0x105557
ECI_FAP_GLOBAL_PP_9.ECI0[0xef]=0
ECI_FAP_GLOBAL_PP_10.ECI0[0xf0]=0
ECI_FAP_GLOBAL_PP_11.ECI0[0xf1]=0
ECI_FAP_GLOBAL_PP_12.ECI0[0xf2]=0
ECI_FAP_GLOBAL_SYS_HEADER_CFG.ECI0[0xc6]=0x53
ECI_FIFO_DMA_SEL.ECI0[0x16f]=0xba9876543210
ECI_FLEXE_PLL_CONFIGURATIONS.ECI0[0x11b]=0x30000000000000000000000000000000000000000000000008002c000003c00000001f0000000000006c00000d8001800
ECI_FMAC_GRACEFUL_POWER_UP_AND_DOWN.ECI0[0x18c]=0
ECI_GLOBAL_MEM_OPTIONS.ECI0[0xc2]=0x10
ECI_GP_CONTROL_0.ECI0[0x18d]=0x6001a2a000000000000000000000000
ECI_GP_CONTROL_1.ECI0[0x191]=0x10000000000000
ECI_GP_CONTROL_2.ECI0[0x195]=0xc1dcd654000000000000000
ECI_GP_CONTROL_3.ECI0[0x199]=0
ECI_GP_CONTROL_4.ECI0[0x19d]=0x50
ECI_GP_CONTROL_5.ECI0[0x1a1]=0x225c10008000808000000
ECI_GP_CONTROL_6.ECI0[0x1a5]=0x13e1bd74c000000225c17d0f3004afe
ECI_GP_CONTROL_7.ECI0[0x1a9]=0x8000000b12b0bbe
ECI_GP_CONTROL_8.ECI0[0x1ad]=0x71111
ECI_GP_CONTROL_9.ECI0[0x1b1]=0
ECI_GP_CONTROL_10.ECI0[0x1b5]=0
ECI_GP_CONTROL_11.ECI0[0x1b9]=0
ECI_GP_STATUS_0.ECI0[0x1bd]=0x62d6d7a00f4b63c4e68156209017d552
ECI_GP_STATUS_1.ECI0[0x1c1]=0xfa22735a646000000000000001ffff0
ECI_GP_STATUS_2.ECI0[0x1c5]=0x80c028085586e4
ECI_GP_STATUS_3.ECI0[0x1c9]=0
ECI_GP_STATUS_4.ECI0[0x1cd]=0x80c02823d10efd
ECI_GP_STATUS_5.ECI0[0x1d1]=0
ECI_GP_STATUS_6.ECI0[0x1d5]=0x2500020001a8000000000000
ECI_GP_STATUS_7.ECI0[0x1d9]=0x2500020001a84a0004000350
ECI_GTIMER_CONFIGURATION.ECI0[0x89]=0
ECI_GTIMER_CYCLE.ECI0[0x88]=0x3b9aca00
ECI_INDIRECT_COMMAND.ECI0[0x80]=0xe000002
ECI_INDIRECT_COMMAND_ADDRESS.ECI0[0x81]=0x1000
ECI_INDIRECT_COMMAND_RD_DATA.ECI0[0x60]=0xe000010008800000000010
ECI_INDIRECT_COMMAND_WR_DATA.ECI0[0x20]=0
ECI_INDIRECT_FORCE_BUBBLE.ECI0[0x83]=0x20019
ECI_INSTRUMENTATION_GENERAL_CTRL.ECI0[0x1ec]=0x40201400
ECI_INTERRUPT_MASK_REGISTER.ECI0[0x10]=0
ECI_INTERRUPT_REGISTER.ECI0[0x0]=0
ECI_INTERRUPT_REGISTER_TEST.ECI0[0x18]=0
ECI_NIF_0_PLL_CONFIGURATIONS.ECI0[0x121]=0
ECI_NIF_0_PLL_STATUS.ECI0[0x149]=0
ECI_NIF_1_PLL_CONFIGURATIONS.ECI0[0x127]=0
ECI_NIF_1_PLL_STATUS.ECI0[0x14f]=0
ECI_NIF_PLL_CONFIGURATIONS.ECI0[0x115]=0x3000000000000000000000000000000000000000000000000800240000041000000027000000000000000000030100e00
ECI_PACKET_SENT.ECI0[0x1f4]=0x36fb333
ECI_PCMI_0.ECI0[0xb0]=0x3b9aca00
ECI_PCMI_1.ECI0[0xb3]=0x3b9aca00
ECI_PCMI_2.ECI0[0xb6]=0x3b9aca00
ECI_PCMI_3.ECI0[0xb9]=0x3b9aca00
ECI_PCMI_4.ECI0[0xbc]=0x3b9aca00
ECI_PCMI_0_S.ECI0[0xb1]=0
ECI_PCMI_0_T.ECI0[0xb2]=0
ECI_PCMI_1_S.ECI0[0xb4]=0
ECI_PCMI_1_T.ECI0[0xb5]=0
ECI_PCMI_2_S.ECI0[0xb7]=0
ECI_PCMI_2_T.ECI0[0xb8]=0
ECI_PCMI_3_S.ECI0[0xba]=0
ECI_PCMI_3_T.ECI0[0xbb]=0
ECI_PCMI_4_S.ECI0[0xbd]=0
ECI_PCMI_4_T.ECI0[0xbe]=0
ECI_PIR_CONFIGURATIONS.ECI0[0x1f5]=7
ECI_POWERUP_CONFIG.ECI0[0x170]=0xa3c0010
ECI_PP_INFO.ECI0[0x1f6]=0
ECI_PRM_PLL_CONTROL_STATUS.ECI0[0x161]=0
ECI_PVT_MON_A_CONTROL_REG.ECI0[0x165]=0x200000000
ECI_PVT_MON_A_THERMAL_DATA.ECI0[0x166]=0x2e82ea
ECI_PVT_MON_B_CONTROL_REG.ECI0[0x167]=0x200000000
ECI_PVT_MON_B_THERMAL_DATA.ECI0[0x168]=0x2f02f4
ECI_PVT_MON_C_CONTROL_REG.ECI0[0x169]=0x200000000
ECI_PVT_MON_C_THERMAL_DATA.ECI0[0x16a]=0x2f02f3
ECI_PVT_MON_D_CONTROL_REG.ECI0[0x16b]=0x200000000
ECI_PVT_MON_D_THERMAL_DATA.ECI0[0x16c]=0x2eb2ef
ECI_REG_0041.ECI0[0x41]=0
ECI_REG_00F3.ECI0[0xf3]=0
ECI_REG_00F4.ECI0[0xf4]=0xc
ECI_REG_00F5.ECI0[0xf5]=0xfac688
ECI_REG_00F6.ECI0[0xf6]=0x7f97f8
ECI_REG_00F7.ECI0[0xf7]=0x7fb7fa
ECI_REG_00F8.ECI0[0xf8]=0x7fd7fc
ECI_REG_00F9.ECI0[0xf9]=0x7ff7fe
ECI_RESERVED_2.ECI0[0x101]=0
ECI_RESERVED_3.ECI0[0x102]=0
ECI_RESERVED_4.ECI0[0x103]=0x12000
ECI_RESERVED_5.ECI0[0x104]=0
ECI_RESERVED_6.ECI0[0x105]=0xffffffff
ECI_RESERVED_7.ECI0[0x106]=0xffffffff
ECI_RESERVED_8.ECI0[0x107]=0xffffffff
ECI_RESERVED_9.ECI0[0x108]=0xffffffff
ECI_RESERVED_10.ECI0[0x109]=0xffffffff
ECI_RESERVED_11.ECI0[0x10a]=0xffffffff
ECI_RESERVED_12.ECI0[0x10b]=0xffffffff
ECI_RESERVED_13.ECI0[0x10c]=0xffffffff
ECI_RESERVED_14.ECI0[0x10d]=0xffffffff
ECI_RESERVED_15.ECI0[0x10e]=0xffffffff
ECI_RESERVED_16.ECI0[0x10f]=0
ECI_RESERVED_17.ECI0[0x110]=0
ECI_RESERVED_19.ECI0[0x139]=0x11dc000000000000006404000000000e070300f0180e0000000000000000000
ECI_RESERVED_20.ECI0[0x13a]=0x100000000011e000000000000000640400000000000000000000050000000000000000000
ECI_RESERVED_21.ECI0[0x162]=0x10189500
ECI_RESERVED_22.ECI0[0x16e]=0x100400000000
ECI_RESERVED_29.ECI0[0x175]=0
ECI_RESERVED_30.ECI0[0x177]=1
ECI_RESERVED_31.ECI0[0x178]=0x848312
ECI_RESERVED_32.ECI0[0x179]=0
ECI_RESERVED_33.ECI0[0x17c]=0x100000000011e000000000000000640400000000000000000000050000000000000000000
ECI_RESERVED_34.ECI0[0x17d]=0x11dc000000000000006404000000000e070300f0180e0000000000000000000
ECI_RESERVED_35.ECI0[0x180]=0
ECI_RESERVED_36.ECI0[0x181]=0
ECI_RESERVED_37.ECI0[0x187]=0x555
ECI_RESERVED_38.ECI0[0x189]=0x4e20
ECI_RESERVED_39.ECI0[0x18a]=0x3abfc
ECI_RESERVED_40.ECI0[0x18b]=1
ECI_RESERVED_43.ECI0[0x1dd]=0
ECI_RESERVED_44.ECI0[0x1de]=0
ECI_RESERVED_45.ECI0[0x1df]=0
ECI_RESERVED_46.ECI0[0x1e0]=0
ECI_RESERVED_47.ECI0[0x1e2]=0
ECI_RESERVED_49.ECI0[0x17a]=7
ECI_RESERVED_50.ECI0[0x17b]=0
ECI_RESERVED_51.ECI0[0x17e]=0x11e0000000000000006404000000000000000000000500000000000000000000700000000000000000000000000000000400000000000000000000000848312
ECI_RESERVED_52.ECI0[0x17f]=0x8000000000000000011dc000000000000006404000000000e070300f0180e00000000000000000000000000000010000
ECI_RESERVED_MTCD.ECI0[0xae]=0x30
ECI_RESERVED_MTCP.ECI0[0xad]=0x300000600000000
ECI_RESERVED_SPARE_0.ECI0[0x90]=0xffffffff
ECI_RESERVED_SPARE_1.ECI0[0x91]=0xffffffff
ECI_RESERVED_SPARE_2.ECI0[0x92]=0
ECI_RESERVED_SPARE_3.ECI0[0x93]=0
ECI_SAM_CONFIGURATIONS.ECI0[0x1e4]=0
ECI_SAM_DBG_TRANSACTION.ECI0[0x1e7]=0
ECI_SAM_ERROR.ECI0[0x1e5]=0
ECI_SAM_RD_DATA.ECI0[0x1e6]=0
ECI_SBUS_BROADCAST_ID.ECI0[0x86]=0x7ff
ECI_SBUS_LAST_IN_CHAIN.ECI0[0x87]=1
ECI_SCRATCH_PAD_0.ECI0[0x182]=0
ECI_SCRATCH_PAD_1.ECI0[0x183]=0
ECI_SELECT_OUTPUT_OF_SYNCHRONOUS_ETHERNET_PADS.ECI0[0x114]=0
ECI_SPECIAL_CLOCK_CONTROLS.ECI0[0xc1]=2
ECI_SW_VERSION.ECI0[0x1e1]=0
ECI_SYNC_E_RSTN.ECI0[0x1f7]=0
ECI_TAP_CONTROL.ECI0[0x164]=0x10
ECI_TAP_CPU_INTERFACE_COMMAND.ECI0[0x184]=0
ECI_TAP_CPU_INTERFACE_DATA_IN.ECI0[0x185]=0x80000000
ECI_TAP_CPU_INTERFACE_DATA_OUT.ECI0[0x186]=0x40000000
ECI_TEST_REGISTER.ECI0[0x176]=0
ECI_TIME_RATIO.ECI0[0x1ed]=0x1403
ECI_TOP_LEVEL_SAMPLING_CFG.ECI0[0x113]=1
ECI_TS_PLL_CONFIGURATIONS.ECI0[0x133]=0x30000000000000000000000000000000000000000000000008000c0000050000000019000000000000005010050200800
ECI_TS_PLL_STATUS.ECI0[0x15b]=0xa5a01
ECI_UC_PLL_STATUS.ECI0[0x13b]=0xa5a01
ECI_VERSION_REGISTER.ECI0[0x100]=0x13884830
EDB_BANK_ELIG_BITMAP.EDB0[0x10b]=0xffffff
EDB_ECC_1B_ERR_CNT.EDB0[0x94]=0
EDB_ECC_2B_ERR_CNT.EDB0[0x96]=0
EDB_ECC_ERR_1B_MONITOR_MEM_MASK.EDB0[0x9a]=0xfffffffffffffffffffffffff
EDB_ECC_ERR_2B_MONITOR_MEM_MASK.EDB0[0x9c]=0xfffffffffffffffffffffffff
EDB_ECC_INTERRUPT_REGISTER.EDB0[0x7]=0
EDB_ECC_INTERRUPT_REGISTER_MASK.EDB0[0x17]=0
EDB_ECC_INTERRUPT_REGISTER_TEST.EDB0[0x1f]=0
EDB_ENABLE_DYNAMIC_MEMORY_ACCESS.EDB0[0x84]=0
EDB_FBC_FREE_CNT(0).EDB0[0x110]=0x8ed6e8f0
EDB_FBC_FREE_CNT(1).EDB0[0x111]=0
EDB_FBC_FREE_CNT(2).EDB0[0x112]=0x7fcb82
EDB_FBC_FREE_CNT(3).EDB0[0x113]=0xa18a1
EDB_FBC_FREE_CNT(4).EDB0[0x114]=0xd9e
EDB_FBC_FREE_CNT(5).EDB0[0x115]=0xcce
EDB_FBC_FREE_CNT(6).EDB0[0x116]=0
EDB_FBC_FREE_CNT(7).EDB0[0x117]=0
EDB_FBC_FREE_CNT(8).EDB0[0x118]=0
EDB_FBC_FREE_CNT(9).EDB0[0x119]=0
EDB_FBM_REG(0).EDB0[0x100]=0x1001fbc00
EDB_FBM_REG(1).EDB0[0x101]=0x1001fbc00
EDB_FBM_REG(2).EDB0[0x102]=0x1001fbc00
EDB_FBM_REG(3).EDB0[0x103]=0x1001fbc00
EDB_FBM_REG(4).EDB0[0x104]=0x1001fbc00
EDB_FBM_REG(5).EDB0[0x105]=0x1001fb400
EDB_FBM_REG(6).EDB0[0x106]=0x1001fb400
EDB_FBM_REG(7).EDB0[0x107]=0x1001fb400
EDB_FBM_REG(8).EDB0[0x108]=0x1001fbc00
EDB_FBM_REG(9).EDB0[0x109]=0x1001fbc00
EDB_FQP_RD_0_REQ_CNT.EDB0[0x10f]=0x8ed6e940
EDB_GTIMER_CONFIGURATION.EDB0[0x89]=0
EDB_GTIMER_CYCLE.EDB0[0x88]=0x3b9aca00
EDB_INDIRECT_COMMAND.EDB0[0x80]=0xe000000
EDB_INDIRECT_COMMAND_ADDRESS.EDB0[0x81]=0
EDB_INDIRECT_COMMAND_RD_DATA.EDB0[0x60]=0x2e3f1f12a1
EDB_INDIRECT_COMMAND_WR_DATA.EDB0[0x20]=0
EDB_INDIRECT_FORCE_BUBBLE.EDB0[0x83]=0x1020019
EDB_INTERRUPT_MASK_REGISTER.EDB0[0x10]=0
EDB_INTERRUPT_REGISTER.EDB0[0x0]=0
EDB_INTERRUPT_REGISTER_TEST.EDB0[0x18]=0
EDB_REG_0041.EDB0[0x41]=0
EDB_REG_00C2.EDB0[0xc2]=0x10
EDB_RESERVED_MTCD.EDB0[0xae]=0x30
EDB_RESERVED_MTCP.EDB0[0xad]=0x300000600000000
EDB_RESERVED_SPARE_0.EDB0[0x90]=0xffffffff
EDB_RESERVED_SPARE_1.EDB0[0x91]=0xffffffff
EDB_RESERVED_SPARE_2.EDB0[0x92]=0
EDB_RESERVED_SPARE_3.EDB0[0x93]=0
EDB_RQP_WR_0_REQ_CNT.EDB0[0x10c]=0x8f60e7b2
EDB_RQP_WR_0_RES_CNT.EDB0[0x10d]=0x8f60e7b9
EDB_RQP_WR_0_RES_ERR_CNT.EDB0[0x10e]=0
EDB_SBUS_BROADCAST_ID.EDB0[0x86]=0x7ff
EDB_SBUS_LAST_IN_CHAIN.EDB0[0x87]=0
EDB_SPECIAL_CLOCK_CONTROLS.EDB0[0xc1]=2
EDB_WBS_CONFIG.EDB0[0x10a]=0x200
EPNI_ALIGNER_CONFIGURATION.EPNI0[0x100]=1
EPNI_ALIGNER_ERROR_STATUS.EPNI0[0x121]=0
EPNI_CRC_HANDLING.EPNI0[0x110]=0
EPNI_DISABLE_EGRESS_INTERFACES.EPNI0[0x101]=0
EPNI_DROPPED_PKT_CONFIGURATION.EPNI0[0x102]=0x1ffffffffffffffffffffffffffffffff80
EPNI_ECC_1B_ERR_CNT.EPNI0[0x94]=0x8000
EPNI_ECC_2B_ERR_CNT.EPNI0[0x96]=0x8000
EPNI_ECC_ERR_1B_MONITOR_MEM_MASK.EPNI0[0x9a]=0x7fff
EPNI_ECC_ERR_2B_MONITOR_MEM_MASK.EPNI0[0x9c]=0x7fff
EPNI_ECC_INTERRUPT_REGISTER.EPNI0[0x7]=0
EPNI_ECC_INTERRUPT_REGISTER_MASK.EPNI0[0x17]=0
EPNI_ECC_INTERRUPT_REGISTER_TEST.EPNI0[0x1f]=0
EPNI_EGQ_IFC_DELAY_CHECK.EPNI0[0x119]=0x500
EPNI_ENABLE_DYNAMIC_MEMORY_ACCESS.EPNI0[0x84]=0
EPNI_EPNI_CNT_CFG.EPNI0[0x11f]=0x71fe00ff800
EPNI_EPNI_DISC_CNT.EPNI0[0x11d]=0
EPNI_EPNI_FIFO_WATERMARKS.EPNI0[0x111]=0x1100
EPNI_EPNI_FRWD_DISC_CNT.EPNI0[0x11e]=0
EPNI_EPNI_IFC_CNT.EPNI0[0x11b]=0xe12645f2
EPNI_EPNI_INIT_STATUS.EPNI0[0x112]=0
EPNI_EPNI_MIRR_CNT.EPNI0[0x11c]=0
EPNI_EPNI_Q_CNT.EPNI0[0x11a]=0xe12645f8
EPNI_ETPP_LAST_INTERRUPT_TM_CMD.EPNI0[0x116]=0
EPNI_ETPP_LAST_TM_CMD.EPNI0[0x113]=0x5401e4117d44049100
EPNI_GTIMER_CONFIGURATION.EPNI0[0x89]=2
EPNI_GTIMER_CYCLE.EPNI0[0x88]=0x23c34600
EPNI_INDIRECT_COMMAND.EPNI0[0x80]=0xe000002
EPNI_INDIRECT_COMMAND_ADDRESS.EPNI0[0x81]=0x100030
EPNI_INDIRECT_COMMAND_RD_DATA.EPNI0[0x60]=7
EPNI_INDIRECT_COMMAND_WR_DATA.EPNI0[0x20]=7
EPNI_INDIRECT_FORCE_BUBBLE.EPNI0[0x83]=0x20019
EPNI_INIT_EPNI_NIF_TXI.EPNI0[0x107]=0
EPNI_INTERRUPT_MASK_REGISTER.EPNI0[0x10]=0
EPNI_INTERRUPT_REGISTER.EPNI0[0x0]=0
EPNI_INTERRUPT_REGISTER_TEST.EPNI0[0x18]=0
EPNI_PCMI_0.EPNI0[0xb0]=0x3b9aca00
EPNI_PCMI_1.EPNI0[0xb3]=0x3b9aca00
EPNI_PCMI_2.EPNI0[0xb6]=0x3b9aca00
EPNI_PCMI_3.EPNI0[0xb9]=0x3b9aca00
EPNI_PCMI_4.EPNI0[0xbc]=0x3b9aca00
EPNI_PCMI_0_S.EPNI0[0xb1]=0
EPNI_PCMI_0_T.EPNI0[0xb2]=0
EPNI_PCMI_1_S.EPNI0[0xb4]=0
EPNI_PCMI_1_T.EPNI0[0xb5]=0
EPNI_PCMI_2_S.EPNI0[0xb7]=0
EPNI_PCMI_2_T.EPNI0[0xb8]=0
EPNI_PCMI_3_S.EPNI0[0xba]=0
EPNI_PCMI_3_T.EPNI0[0xbb]=0
EPNI_PCMI_4_S.EPNI0[0xbd]=0
EPNI_PCMI_4_T.EPNI0[0xbe]=0
EPNI_REG_0041.EPNI0[0x41]=0
EPNI_REG_0098.EPNI0[0x98]=0
EPNI_REG_00A0.EPNI0[0xa0]=0
EPNI_REG_00C2.EPNI0[0xc2]=0x10
EPNI_REG_00C5.EPNI0[0xc5]=0x401
EPNI_RESERVED_MTCD.EPNI0[0xae]=0x30
EPNI_RESERVED_MTCP.EPNI0[0xad]=0x300000600000000
EPNI_RESERVED_SPARE_0.EPNI0[0x90]=0xffffffff
EPNI_RESERVED_SPARE_1.EPNI0[0x91]=0xffffffff
EPNI_RESERVED_SPARE_2.EPNI0[0x92]=0
EPNI_RESERVED_SPARE_3.EPNI0[0x93]=0
EPNI_SBUS_BROADCAST_ID.EPNI0[0x86]=0x7ff
EPNI_SBUS_LAST_IN_CHAIN.EPNI0[0x87]=0
EPNI_SPECIAL_CLOCK_CONTROLS.EPNI0[0xc1]=2
EPNI_SPECIAL_IFS_TXI_IRDY_UNSET.EPNI0[0x122]=0
EPRE_DISABLE_INTERFACES.EPRE0[0x100]=0
EPRE_ECC_1B_ERR_CNT.EPRE0[0x94]=0
EPRE_ECC_2B_ERR_CNT.EPRE0[0x96]=0
EPRE_ECC_ERR_1B_MONITOR_MEM_MASK.EPRE0[0x9a]=0x3fffff
EPRE_ECC_ERR_2B_MONITOR_MEM_MASK.EPRE0[0x9c]=0x3fffff
EPRE_ECC_INTERRUPT_REGISTER.EPRE0[0x7]=0
EPRE_ECC_INTERRUPT_REGISTER_MASK.EPRE0[0x17]=0
EPRE_ECC_INTERRUPT_REGISTER_TEST.EPRE0[0x1f]=0
EPRE_EPRE_FIFO_WATERMARKS.EPRE0[0x107]=0
EPRE_GTIMER_CONFIGURATION.EPRE0[0x89]=0
EPRE_GTIMER_CYCLE.EPRE0[0x88]=0x3b9aca00
EPRE_HP_MIRR_TRAFFIC_SHAPER_CONFIGURATION.EPRE0[0x105]=0x8001ffff
EPRE_IFC_TXI_IRDY_UNSET.EPRE0[0x108]=0
EPRE_INTERRUPT_MASK_REGISTER.EPRE0[0x10]=0
EPRE_INTERRUPT_REGISTER.EPRE0[0x0]=0
EPRE_INTERRUPT_REGISTER_TEST.EPRE0[0x18]=0
EPRE_IRE_RECYCLE_ARBITER_CONFIGURATION.EPRE0[0x102]=0x101
EPRE_MIRR_FIFO_CONFIGURATION.EPRE0[0x101]=0x820
EPRE_RECYLED_TRAFFIC_SHAPER_CONFIGURATION.EPRE0[0x103]=0x8001ffff
EPRE_REG_0098.EPRE0[0x98]=0
EPRE_REG_00A0.EPRE0[0xa0]=0
EPRE_REG_00C2.EPRE0[0xc2]=0x10
EPRE_REG_00C5.EPRE0[0xc5]=0x401
EPRE_RESERVED_MTCD.EPRE0[0xae]=0x30
EPRE_RESERVED_MTCP.EPRE0[0xad]=0x300000600000000
EPRE_RESERVED_SPARE_0.EPRE0[0x90]=0xffffffff
EPRE_RESERVED_SPARE_1.EPRE0[0x91]=0xffffffff
EPRE_RESERVED_SPARE_2.EPRE0[0x92]=0
EPRE_RESERVED_SPARE_3.EPRE0[0x93]=0
EPRE_SBUS_BROADCAST_ID.EPRE0[0x86]=0x7ff
EPRE_SBUS_LAST_IN_CHAIN.EPRE0[0x87]=0
EPRE_SPECIAL_CLOCK_CONTROLS.EPRE0[0xc1]=2
EPS_ACC_MAX_CREDIT.EPS0[0x11f]=0x1000000
EPS_ECC_1B_ERR_CNT.EPS0[0x94]=0
EPS_ECC_2B_ERR_CNT.EPS0[0x96]=0
EPS_ECC_ERR_1B_MONITOR_MEM_MASK.EPS0[0x9a]=0x7ffffff
EPS_ECC_ERR_2B_MONITOR_MEM_MASK.EPS0[0x9c]=0x7ffffff
EPS_ECC_INTERRUPT_REGISTER.EPS0[0x7]=0
EPS_ECC_INTERRUPT_REGISTER_MASK.EPS0[0x17]=0
EPS_ECC_INTERRUPT_REGISTER_TEST.EPS0[0x1f]=0
EPS_EGRESS_CALENDAR_SHAPER_SETTINGS.EPS0[0x115]=0
EPS_EGRESS_SHAPER_ENABLE_SETTINGS.EPS0[0x111]=0x1fe0000184c3d1d03fff
EPS_ENABLE_DYNAMIC_MEMORY_ACCESS.EPS0[0x84]=0
EPS_EPS_CANCEL_CNT.EPS0[0x103]=1
EPS_EPS_CANCEL_STATUS.EPS0[0x102]=0x140a1
EPS_EPS_GENERAL_CFG.EPS0[0x105]=0x440c5e
EPS_EPS_PRIO_PROG_MIS_MATCH_CNT.EPS0[0x104]=0
EPS_EPS_SPR_INIT_STAT.EPS0[0x100]=0
EPS_EPS_WFQ_CNT_NEG_STAT.EPS0[0x101]=0
EPS_GTIMER_CONFIGURATION.EPS0[0x89]=0
EPS_GTIMER_CYCLE.EPS0[0x88]=0x3b9aca00
EPS_HEADER_CMPNS_EN.EPS0[0x10e]=0x1000000000000000
EPS_IFC_IS_CHANNELIZED.EPS0[0x106]=0x19
EPS_IFC_OK_DEQ.EPS0[0x118]=0
EPS_INDIRECT_COMMAND.EPS0[0x80]=0xe000002
EPS_INDIRECT_COMMAND_ADDRESS.EPS0[0x81]=0x210047
EPS_INDIRECT_COMMAND_RD_DATA.EPS0[0x60]=2
EPS_INDIRECT_COMMAND_WR_DATA.EPS0[0x20]=0
EPS_INDIRECT_FORCE_BUBBLE.EPS0[0x83]=0x20019
EPS_INTERRUPT_MASK_REGISTER.EPS0[0x10]=0
EPS_INTERRUPT_REGISTER.EPS0[0x0]=0
EPS_INTERRUPT_REGISTER_TEST.EPS0[0x18]=0
EPS_PORT_MAX_CREDIT_VALUE.EPS0[0x120]=0x270000013800060000000
EPS_PORT_SCH_WFQ_PACKET_SIZE.EPS0[0x10b]=0x400
EPS_PQP_CALENDAR_SETTING.EPS0[0x10d]=0xf
EPS_PS_MODE.EPS0[0x107]=0x5755555
EPS_QPAIR_SPR_DIS_1.EPS0[0x127]=0
EPS_QP_MAX_CREDIT_VALUE.EPS0[0x123]=0x13800040000000000000
EPS_REG_0041.EPS0[0x41]=0
EPS_REG_0098.EPS0[0x98]=0
EPS_REG_00A0.EPS0[0xa0]=0
EPS_REG_00C2.EPS0[0xc2]=0x10
EPS_RESERVED_MTCD.EPS0[0xae]=0x30
EPS_RESERVED_MTCP.EPS0[0xad]=0x300000600000000
EPS_RESERVED_SPARE_0.EPS0[0x90]=0xffffffff
EPS_RESERVED_SPARE_1.EPS0[0x91]=0xffffffff
EPS_RESERVED_SPARE_2.EPS0[0x92]=0
EPS_RESERVED_SPARE_3.EPS0[0x93]=0
EPS_SBUS_BROADCAST_ID.EPS0[0x86]=0x7ff
EPS_SBUS_LAST_IN_CHAIN.EPS0[0x87]=0
EPS_SPECIAL_CLOCK_CONTROLS.EPS0[0xc1]=2
EPS_TCG_MAX_CREDIT_VALUE.EPS0[0x126]=0x4e0001
EPS_TOTAL_EGRESS_SHAPER_SETTINGS.EPS0[0x114]=0x2008000
EPS_UC_MC_WFQ_PACKET_SIZE.EPS0[0x10c]=0x400
ERPP_ACTION_DISABLE.ERPP0[0x5ae]=0
ERPP_ACTION_PROFILE_1.ERPP0[0x580]=0x209241
ERPP_ACTION_PROFILE_2.ERPP0[0x581]=0xa000001
ERPP_CFG_ETHERNET_FWD_CONTEXT.ERPP0[0x58c]=0x400001
ERPP_CFG_EXCLUDE_SOURCE_MAPPED.ERPP0[0x582]=0xffff
ERPP_CFG_FHEI_MODEL.ERPP0[0x588]=0
ERPP_CFG_FILTER_FORWARDING_STRENGTH_1.ERPP0[0x57a]=0xd444440
ERPP_CFG_FILTER_FORWARDING_STRENGTH_2.ERPP0[0x57b]=0x4c40000
ERPP_CFG_FILTER_FORWARDING_STRENGTH_3.ERPP0[0x57c]=0
ERPP_CFG_FILTER_SNOOP_STRENGTH_1.ERPP0[0x57d]=0
ERPP_CFG_FILTER_SNOOP_STRENGTH_2.ERPP0[0x57e]=0
ERPP_CFG_FILTER_SNOOP_STRENGTH_3.ERPP0[0x57f]=0
ERPP_CFG_GLEM_VALID_AND_NOT_FOUND.ERPP0[0x59a]=0
ERPP_CFG_IN_LIF_NULL_VALUE.ERPP0[0x5c2]=0
ERPP_CFG_IPV4_MC_FWD_CONTEXT.ERPP0[0x590]=0x800000008
ERPP_CFG_IPV4_UC_FWD_CONTEXT.ERPP0[0x58e]=0x400000004
ERPP_CFG_IPV6_MC_FWD_CONTEXT.ERPP0[0x594]=0x2000000020
ERPP_CFG_IPV6_UC_FWD_CONTEXT.ERPP0[0x592]=0x1000000010
ERPP_CFG_LEARN_EN_PER_FWD_CONTEXT.ERPP0[0x510]=1
ERPP_CFG_LOCAL_OUTLIF_WIDTH.ERPP0[0x50e]=0x12
ERPP_CFG_MAP_FORWARD_STRENGTH_TO_STRENGTH.ERPP0[0x558]=0x76543210
ERPP_CFG_OPP_LEARNING_DISABLE(0).ERPP0[0x532]=0
ERPP_CFG_OPP_LEARNING_DISABLE(1).ERPP0[0x533]=0
ERPP_CFG_OPP_LEARNING_DISABLE(2).ERPP0[0x534]=0
ERPP_CFG_OPP_LEARNING_DISABLE(3).ERPP0[0x535]=0
ERPP_CFG_OTM_LEARNING_DISABLE(0).ERPP0[0x512]=0
ERPP_CFG_OTM_LEARNING_DISABLE(1).ERPP0[0x513]=0
ERPP_CFG_OTM_LEARNING_DISABLE(2).ERPP0[0x514]=0
ERPP_CFG_OTM_LEARNING_DISABLE(3).ERPP0[0x515]=0
ERPP_CFG_OUTLIF_PROFILE_WIDTH.ERPP0[0x50f]=1
ERPP_CFG_OUTRIF_MAX_VALUE.ERPP0[0x50b]=0x1000
ERPP_CFG_PROTOCOL_IS_TCP.ERPP0[0x50d]=0x100
ERPP_CFG_PROTOCOL_IS_UDP.ERPP0[0x50c]=0x200
ERPP_CFG_RIF_IN_STACK.ERPP0[0x50a]=0
ERPP_CFG_SPLIT_HORIZON_FILTER.ERPP0[0x58a]=0
ERPP_CFG_TDM_MAP_QUEUE_TO_TDM(0).ERPP0[0x55a]=0
ERPP_CFG_TDM_MAP_QUEUE_TO_TDM(1).ERPP0[0x55b]=0
ERPP_CFG_TDM_MAP_QUEUE_TO_TDM(2).ERPP0[0x55c]=0
ERPP_CFG_TDM_MAP_QUEUE_TO_TDM(3).ERPP0[0x55d]=0
ERPP_COLLECTOR_VIS_EN.ERPP0[0x25c]=1
ERPP_COUNTER.ERPP0[0x5a1]=0x37
ERPP_DBG_LAST_FES.ERPP0[0x5b4]=0x581
ERPP_DBG_LAST_FES_NUM.ERPP0[0x5b8]=0
ERPP_DEVICE_CFG_BTR.ERPP0[0x59b]=0
ERPP_DEVICE_CFG_JR_COMPATIBILITY_APP_DB_INDEX.ERPP0[0x5ac]=0
ERPP_DEVICE_CFG_PARSER_ENABLERS.ERPP0[0x219]=0x1e
ERPP_DEVICE_CFG_POP_SIZE_IN_BYTES.ERPP0[0x598]=4
ERPP_DEVICE_CFG_REMARK_PROFILE.ERPP0[0x599]=0
ERPP_DUMMY_REGISTER.ERPP0[0x40e]=0
ERPP_ECC_1B_ERR_CNT.ERPP0[0x94]=0
ERPP_ECC_2B_ERR_CNT.ERPP0[0x96]=0
ERPP_ECC_ERR_1B_MONITOR_MEM_MASK.ERPP0[0x9a]=0x7fffffffff
ERPP_ECC_ERR_2B_MONITOR_MEM_MASK.ERPP0[0x9c]=0x7fffffffff
ERPP_ECC_INTERRUPT_REGISTER.ERPP0[0x7]=0
ERPP_ECC_INTERRUPT_REGISTER_MASK.ERPP0[0x17]=0
ERPP_ECC_INTERRUPT_REGISTER_TEST.ERPP0[0x1f]=0
ERPP_ENABLE_DYNAMIC_MEMORY_ACCESS.ERPP0[0x84]=0x3f
ERPP_EPMFCS_TCAM_ECC_FIX_EN.ERPP0[0x1001]=0
ERPP_EPMFCS_TCAM_PROTECTION_ERROR.ERPP0[0x1003]=0
ERPP_EPMFCS_TCAM_PROTECTION_MACHINE_CONFIGURATION.ERPP0[0x1000]=0xff
ERPP_EPMFCS_TCAM_RESET_BLOCK.ERPP0[0x1002]=0
ERPP_ERPP_DISCARDS_INTERRUPT_REGISTER_MASK.ERPP0[0x503]=0
ERPP_ERPP_DISCARDS_INTERRUPT_REGISTER_MASK_2.ERPP0[0x504]=0
ERPP_ERPP_DISCARD_INTERRUPT_REGISTER.ERPP0[0x500]=0x20
ERPP_ERPP_DISCARD_INTERRUPT_REGISTER_2.ERPP0[0x501]=0x9e00080000
ERPP_ERPP_DISCARD_INT_REG_2_TEST.ERPP0[0x507]=0
ERPP_ERPP_DISCARD_INT_REG_TEST.ERPP0[0x506]=0
ERPP_ERPP_SAMPLE_VALIDS.ERPP0[0xf000]=0x1ffcd
ERPP_FHEI_MPLS_COMMAND.ERPP0[0x59c]=0x10
ERPP_FIFO_ALMOST_FULL_THRESHOLD.ERPP0[0x59e]=0x8a0040800
ERPP_FWD_CONTEXT_IS_PP.ERPP0[0x596]=0x8020003c040725fd
ERPP_FWD_LAYER_ADDITIONAL_INFO_TO_IP_MC_ELIGIBLE_MAPPING.ERPP0[0x201]=0xcccc
ERPP_GLOBAL_CONFIG.ERPP0[0x509]=1
ERPP_GTIMER_CONFIGURATION.ERPP0[0x89]=0
ERPP_GTIMER_CYCLE.ERPP0[0x88]=0x3b9aca00
ERPP_INDIRECT_COMMAND.ERPP0[0x80]=0x3fff0000
ERPP_INDIRECT_COMMAND_ADDRESS.ERPP0[0x81]=0x82f30000
ERPP_INDIRECT_COMMAND_RD_DATA.ERPP0[0x60]=0
ERPP_INDIRECT_COMMAND_WIDE_MEM.ERPP0[0x41]=0
ERPP_INDIRECT_COMMAND_WR_DATA.ERPP0[0x20]=0
ERPP_INDIRECT_FORCE_BUBBLE.ERPP0[0x83]=0x20019
ERPP_INDIRECT_WR_MASK.ERPP0[0x40]=0xff
ERPP_INGRESS_TRAPPED_BY_FHEI.ERPP0[0x5a2]=0x20
ERPP_INTERRUPT_MASK_REGISTER.ERPP0[0x10]=0
ERPP_INTERRUPT_REGISTER.ERPP0[0x0]=0
ERPP_INTERRUPT_REGISTER_TEST.ERPP0[0x18]=0
ERPP_INVALID_OTM.ERPP0[0x587]=0x3ff
ERPP_JERICHO_COMPATIBLE_REGISTERS.ERPP0[0x202]=0xfd400
ERPP_LAG_FILTER_ENABLE.ERPP0[0x585]=0
ERPP_LAG_GROUP_MODE.ERPP0[0x586]=1
ERPP_LEARN_CMD_DESTINATION_OFFSET.ERPP0[0x5a9]=0
ERPP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_ENTRY_FORMAT_INDEX.ERPP0[0x5a8]=0
ERPP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUE.ERPP0[0x5a5]=0
ERPP_LEARN_CMD_EEI_OFFSET.ERPP0[0x5ab]=0xf
ERPP_LEARN_CMD_FEC_OFFSET.ERPP0[0x5ad]=0
ERPP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_ENTRY_FORMAT_INDEX.ERPP0[0x5a7]=0
ERPP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUE.ERPP0[0x5a3]=0
ERPP_LEARN_CMD_OUT_LIF_OFFSET.ERPP0[0x5aa]=0x15
ERPP_NUM_ENTRIES_NETWORK_HEADERS_FIFO.ERPP0[0x216]=0x6c000
ERPP_NUM_ENTRIES_PMF_INITIAL_ACTIONS_FIFO.ERPP0[0x557]=0x2d0000
ERPP_NUM_ENTRIES_PP_DSP_FOR_VISIBILITY_AND_IS_TDM_FIFO.ERPP0[0x217]=0x68000
ERPP_NUM_ENTRIES_PRP_PER_PORT_INFO_FIFO.ERPP0[0x552]=0x1f0000
ERPP_NUM_ENTRIES_PRP_SAVE_NETWORK_HEADER_FIFO.ERPP0[0x555]=0x10000
ERPP_NUM_ENTRIES_PRP_WAIT_FOR_GLEM_FIFO.ERPP0[0x553]=0x230000
ERPP_NUM_ENTRIES_PRP_WAIT_FOR_NETWORK_HEADER_FIFO.ERPP0[0x554]=0x1000
ERPP_NUM_ENTRIES_SYSTEM_HEADERS_CONTAINER_FIFO.ERPP0[0x218]=0x24000
ERPP_NUM_ENTRIES_TM_DATA_BYPASS_FIFO.ERPP0[0x556]=0x4500000
ERPP_NUM_ENTRIES_TM_FIELDS_FIFO.ERPP0[0x215]=0x250000
ERPP_PARITY_ERR_CNT.ERPP0[0x98]=0
ERPP_PARSER_FIFO_ALMOST_FULL_THRESHOLD.ERPP0[0x214]=0
ERPP_PAR_ERR_MEM_MASK.ERPP0[0xa0]=0x7f
ERPP_PCMI_0.ERPP0[0xb0]=0x3b9aca00
ERPP_PCMI_1.ERPP0[0xb3]=0x3b9aca00
ERPP_PCMI_2.ERPP0[0xb6]=0x3b9aca00
ERPP_PCMI_3.ERPP0[0xb9]=0x3b9aca00
ERPP_PCMI_4.ERPP0[0xbc]=0x3b9aca00
ERPP_PCMI_0_S.ERPP0[0xb1]=0
ERPP_PCMI_0_T.ERPP0[0xb2]=0
ERPP_PCMI_1_S.ERPP0[0xb4]=0
ERPP_PCMI_1_T.ERPP0[0xb5]=0
ERPP_PCMI_2_S.ERPP0[0xb7]=0
ERPP_PCMI_2_T.ERPP0[0xb8]=0
ERPP_PCMI_3_S.ERPP0[0xba]=0
ERPP_PCMI_3_T.ERPP0[0xbb]=0
ERPP_PCMI_4_S.ERPP0[0xbd]=0
ERPP_PCMI_4_T.ERPP0[0xbe]=0
ERPP_PES_DEBUG_SELECT.ERPP0[0x40d]=0
ERPP_PES_PRSE_CONFIG(0).ERPP0[0x405]=0x10
ERPP_PES_PRSE_CONFIG(1).ERPP0[0x406]=0x11
ERPP_PES_PRSE_CONFIG(2).ERPP0[0x407]=0x12
ERPP_PES_PRSE_CONFIG(3).ERPP0[0x408]=0x13
ERPP_PES_PRSE_CONFIG(4).ERPP0[0x409]=0x14
ERPP_PES_PRSE_CONFIG(5).ERPP0[0x40a]=0x15
ERPP_PES_PRSE_CONFIG(6).ERPP0[0x40b]=0x16
ERPP_PES_PRSE_CONFIG(7).ERPP0[0x40c]=0x17
ERPP_PMF_DEFAULT_ACTIONS.ERPP0[0x5af]=0
ERPP_PMF_PROGRAM_OUTLIF_PROFILE_MAP.ERPP0[0x5c0]=0x800000010
ERPP_PMF_PRTOCOL_IS_L_4.ERPP0[0x5b3]=0x300
ERPP_PORT_VISIBILITY_EN(0).ERPP0[0x21a]=0
ERPP_PORT_VISIBILITY_EN(1).ERPP0[0x21b]=0
ERPP_PORT_VISIBILITY_EN(2).ERPP0[0x21c]=0
ERPP_PORT_VISIBILITY_EN(3).ERPP0[0x21d]=0
ERPP_PORT_VISIBILITY_FORCE(0).ERPP0[0x23a]=0x1010004000000000000000000000000000000000050e40000001fffffffff
ERPP_PORT_VISIBILITY_FORCE(1).ERPP0[0x23b]=0
ERPP_PORT_VISIBILITY_FORCE(2).ERPP0[0x23c]=0
ERPP_PORT_VISIBILITY_FORCE(3).ERPP0[0x23d]=0
ERPP_PPH_BASE_FIELDS_CG_2.ERPP0[0x20c]=0x3530813081b16231239084b01000456035a05010706030d02100112
ERPP_PP_CONFIG.ERPP0[0x559]=3
ERPP_PSG_DEBUG_SELECT.ERPP0[0x413]=0
ERPP_PSG_PRSE_CONFIG(0).ERPP0[0x40f]=0x10
ERPP_PSG_PRSE_CONFIG(1).ERPP0[0x410]=0x11
ERPP_PSG_PRSE_CONFIG(2).ERPP0[0x411]=0x12
ERPP_PSG_PRSE_CONFIG(3).ERPP0[0x412]=0x13
ERPP_REG_0602.ERPP0[0x602]=0
ERPP_REG_1004.ERPP0[0x1004]=0
ERPP_REG_1007.ERPP0[0x1007]=0xc000000000
ERPP_REG_1009.ERPP0[0x1009]=0
ERPP_REG_00C2.ERPP0[0xc2]=0x10
ERPP_REG_00C5.ERPP0[0xc5]=0x2d1
ERPP_REG_00C6.ERPP0[0xc6]=0x13
ERPP_REG_00E8.ERPP0[0xe8]=0x88a88100
ERPP_REG_00E9.ERPP0[0xe9]=0x9100
ERPP_REG_00EB.ERPP0[0xeb]=0
ERPP_REG_00EE.ERPP0[0xee]=0x5557
ERPP_REG_00F0.ERPP0[0xf0]=0
ERPP_REG_00F1.ERPP0[0xf1]=0
ERPP_REG_00F2.ERPP0[0xf2]=0
ERPP_REG_059D.ERPP0[0x59d]=1
ERPP_RESERVED_MTCD.ERPP0[0xae]=0x30
ERPP_RESERVED_MTCP.ERPP0[0xad]=0x300000600000000
ERPP_RESERVED_SPARE_0.ERPP0[0x90]=0xffffffff
ERPP_RESERVED_SPARE_1.ERPP0[0x91]=0xffffffff
ERPP_RESERVED_SPARE_2.ERPP0[0x92]=0
ERPP_RESERVED_SPARE_3.ERPP0[0x93]=0
ERPP_SBUS_BROADCAST_ID.ERPP0[0x86]=0x7ff
ERPP_SBUS_LAST_IN_CHAIN.ERPP0[0x87]=0
ERPP_SER_ACTION_RESOLUTION.ERPP0[0x5a0]=9
ERPP_SPECIAL_CLOCK_CONTROLS.ERPP0[0xc1]=2
ERPP_STAT_VISIBILITY.ERPP0[0x25a]=0
ERPP_SYSTEM_HEADERS_CG_1.ERPP0[0x203]=0x201220804a7241480c500213b500cd30134400000000001a0036900c6318c631b4018011
ERPP_TDM_GENERAL_CONFIGURATION.ERPP0[0x589]=0
ERPP_TM_SPARE_BITS.ERPP0[0x5b9]=0
ERPP_TTL_SCOPE.ERPP0[0x583]=0x100
ERPP_UTILITY_REGS.ERPP0[0x200]=8
ERPP_VMV_SHIFT_VALUE_MAP.ERPP0[0x5ba]=0x2db6d00000002db6d00000002db6d00000002db6d02d
ERPP_XBR_CONFIG(0).ERPP0[0x400]=0
ERPP_XBR_CONFIG(1).ERPP0[0x401]=0
ERPP_XBR_CONFIG(2).ERPP0[0x402]=0
ERPP_XBR_CONFIG(3).ERPP0[0x403]=0
ERPP_XBR_CONFIG(4).ERPP0[0x404]=0
ESB_ECC_1B_ERR_CNT.ESB0[0x94]=0
ESB_ECC_2B_ERR_CNT.ESB0[0x96]=0
ESB_ECC_ERR_1B_MONITOR_MEM_MASK.ESB0[0x9a]=0x7ffffff
ESB_ECC_ERR_2B_MONITOR_MEM_MASK.ESB0[0x9c]=0x7ffffff
ESB_ECC_INTERRUPT_REGISTER.ESB0[0x7]=0
ESB_ECC_INTERRUPT_REGISTER_MASK.ESB0[0x17]=0
ESB_ECC_INTERRUPT_REGISTER_TEST.ESB0[0x1f]=0
ESB_ENABLE_DYNAMIC_MEMORY_ACCESS.ESB0[0x84]=1
ESB_ESB_ADD_QUEUE.ESB0[0x118]=0x726
ESB_ESB_BURST_WATERMARK_CONFIG.ESB0[0x11a]=0x9a
ESB_ESB_BYTE_WATERMARK.ESB0[0x11b]=0x1219
ESB_ESB_CALENDER_SETTING.ESB0[0x117]=0
ESB_ESB_CNT_CFG.ESB0[0x12c]=0x1fe00
ESB_ESB_INIT.ESB0[0x115]=1
ESB_ESB_ORDY.ESB0[0x11c]=0
ESB_ESB_Q_CNT.ESB0[0x12b]=0xe12649c0
ESB_ESB_REMOVE_QUEUE.ESB0[0x119]=0x134
ESB_ESB_SBC_UNDER_FLOW_STATUS.ESB0[0x126]=0
ESB_ESB_SCH_CFG.ESB0[0x116]=2
ESB_ESB_TXI_NOT_READY.ESB0[0x121]=0x201ffffffffffffffffffffffffffffffffffff
ESB_FLEXE_COUNTERS_CONFIG.ESB0[0x135]=0
ESB_FLEXE_DEBUG.ESB0[0x12d]=0x21e00000002
ESB_FLEXE_INCOMING_COUNTERS.ESB0[0x12f]=0
ESB_FLEXE_OUTGOING_COUNTERS.ESB0[0x133]=0
ESB_FPC_0_CONFIG.ESB0[0x100]=0xffc9a
ESB_FPC_0_DELETE.ESB0[0x101]=0
ESB_FPC_0_DELETE_STAT.ESB0[0x104]=0
ESB_FPC_0_FREE_ERROR_STAT.ESB0[0x102]=0
ESB_FPC_0_STAT.ESB0[0x103]=0xf7a8
ESB_FPC_1_CONFIG.ESB0[0x105]=0xffc9a
ESB_FPC_1_DELETE.ESB0[0x106]=0
ESB_FPC_1_DELETE_STAT.ESB0[0x109]=0
ESB_FPC_1_FREE_ERROR_STAT.ESB0[0x107]=0
ESB_FPC_1_STAT.ESB0[0x108]=0xe76c
ESB_FPC_2_CONFIG.ESB0[0x10a]=0xffc9a
ESB_FPC_2_DELETE.ESB0[0x10b]=0
ESB_FPC_2_DELETE_STAT.ESB0[0x10e]=0
ESB_FPC_2_FREE_ERROR_STAT.ESB0[0x10c]=0
ESB_FPC_2_STAT.ESB0[0x10d]=0xe7a8
ESB_FPC_3_CONFIG.ESB0[0x10f]=0xffc9a
ESB_FPC_3_DELETE.ESB0[0x110]=0
ESB_FPC_3_DELETE_STAT.ESB0[0x113]=0
ESB_FPC_3_FREE_ERROR_STAT.ESB0[0x111]=0
ESB_FPC_3_STAT.ESB0[0x112]=0x107ac
ESB_GTIMER_CONFIGURATION.ESB0[0x89]=0
ESB_GTIMER_CYCLE.ESB0[0x88]=0x3b9aca00
ESB_INDIRECT_COMMAND.ESB0[0x80]=0xe000002
ESB_INDIRECT_COMMAND_ADDRESS.ESB0[0x81]=0x1d0100
ESB_INDIRECT_COMMAND_RD_DATA.ESB0[0x60]=0xff
ESB_INDIRECT_COMMAND_WR_DATA.ESB0[0x20]=0xff
ESB_INDIRECT_FORCE_BUBBLE.ESB0[0x83]=0x20019
ESB_INIT_DONE_STATUS.ESB0[0x114]=0
ESB_INTERRUPT_MASK_REGISTER.ESB0[0x10]=0
ESB_INTERRUPT_REGISTER.ESB0[0x0]=0
ESB_INTERRUPT_REGISTER_TEST.ESB0[0x18]=0
ESB_REG_0041.ESB0[0x41]=0
ESB_REG_0098.ESB0[0x98]=0
ESB_REG_00A0.ESB0[0xa0]=0
ESB_REG_00C2.ESB0[0xc2]=0x10
ESB_RESERVED_MTCD.ESB0[0xae]=0x30
ESB_RESERVED_MTCP.ESB0[0xad]=0x300000600000000
ESB_RESERVED_SPARE_0.ESB0[0x90]=0xffffffff
ESB_RESERVED_SPARE_1.ESB0[0x91]=0xffffffff
ESB_RESERVED_SPARE_2.ESB0[0x92]=0
ESB_RESERVED_SPARE_3.ESB0[0x93]=0
ESB_SBUS_BROADCAST_ID.ESB0[0x86]=0x7ff
ESB_SBUS_LAST_IN_CHAIN.ESB0[0x87]=0
ESB_SPECIAL_CLOCK_CONTROLS.ESB0[0xc1]=2
ETPPA_APP_INJECTTION.ETPPA0[0x1050]=0
ETPPA_BYPASS_FIFO_ALMOST_FULL_THRESHOLD.ETPPA0[0x106]=0
ETPPA_BYPASS_STAMP_FTMH_ENABLE.ETPPA0[0x107]=0
ETPPA_CFG_ACCEPTABLE_FRAME_TYPE_PER_FWD_CODE.ETPPA0[0x910]=1
ETPPA_CFG_EEDB_ENABLED.ETPPA0[0x936]=1
ETPPA_CFG_EEI_ISID_TYPE.ETPPA0[0x93f]=0
ETPPA_CFG_FHEI_MODEL.ETPPA0[0x909]=0
ETPPA_CFG_FHEI_MPLS_POP_TYPE.ETPPA0[0x939]=0x30
ETPPA_CFG_FHEI_MPLS_SWAP_REMARK_MAP.ETPPA0[0x93a]=0x7060504030201000000
ETPPA_CFG_FHEI_MPLS_SWAP_TYPE.ETPPA0[0x93e]=0x1d
ETPPA_CFG_FHEI_QOS_MODEL_MAP.ETPPA0[0x937]=0x208
ETPPA_CFG_FHEI_TTL_MODEL_MAP.ETPPA0[0x938]=0xc
ETPPA_CFG_FORWARDING_ACTION_STRENGTH_1.ETPPA0[0x90d]=0
ETPPA_CFG_FWD_CODE_TO_ACTION_PROFILE.ETPPA0[0x92f]=0
ETPPA_CFG_INGRESS_NWK_QOS_TYPE.ETPPA0[0x92b]=0
ETPPA_CFG_INLIF_SELECTED.ETPPA0[0x91c]=0x33
ETPPA_CFG_IN_LIF_NULL_VALUE.ETPPA0[0x956]=0
ETPPA_CFG_LAYER_PROTOCOL_IPV4.ETPPA0[0x10d]=4
ETPPA_CFG_LAYER_PROTOCOL_IPV6.ETPPA0[0x10e]=8
ETPPA_CFG_LAYER_PROTOCOL_MPLS.ETPPA0[0x10c]=0x10
ETPPA_CFG_MAP_FORWARD_STRENGTH_TO_STRENGTH.ETPPA0[0x935]=0x76543210
ETPPA_CFG_MAP_FWD_LAYER_PROTOCOL.ETPPA0[0x920]=0x4688
ETPPA_CFG_MAP_FWD_LAYER_TYPE.ETPPA0[0x91d]=0x3440
ETPPA_CFG_MAP_SNIFF_TO_MIRROR_ACTION.ETPPA0[0x90c]=0x68f
ETPPA_CFG_MAP_SNIFF_TO_SNOOP_ACTION.ETPPA0[0x90a]=0x68f
ETPPA_CFG_MAP_SNIFF_TO_SNOOP_STRENGTH.ETPPA0[0x90b]=0x688
ETPPA_CFG_OUTLIF_SELECTED.ETPPA0[0x91a]=0xfe00000be02bd5
ETPPA_CFG_REMARK_PROTOCOL_PROFILE.ETPPA0[0x923]=0
ETPPA_CFG_RIF_IN_STACK.ETPPA0[0x903]=0x1e
ETPPA_CFG_RIF_MAX_VALUE.ETPPA0[0x904]=0x1000
ETPPA_CFG_SNOOP_ACTION_STRENGTH_1.ETPPA0[0x90e]=0
ETPPA_CFG_TC_2_NWK_QOS_MAPPING.ETPPA0[0x929]=0x706050403020100
ETPPA_CFG_TRAP_ACTION_PROFILE_1.ETPPA0[0x90f]=0
ETPPA_COLLECTOR_VIS_EN.ETPPA0[0x3ac]=1
ETPPA_COS_PROFILE_TABLE.ETPPA0[0x912]=0
ETPPA_DEVICE_CFG_PARSER_ENABLERS.ETPPA0[0x369]=0x1e
ETPPA_DEVICE_CFG_POP_SIZE_IN_BYTES.ETPPA0[0x905]=4
ETPPA_DEVICE_CFG_REMARK_PROFILE.ETPPA0[0x908]=0
ETPPA_DUMMY_REGISTER.ETPPA0[0x450]=0
ETPPA_ECC_1B_ERR_CNT.ETPPA0[0x94]=0
ETPPA_ECC_2B_ERR_CNT.ETPPA0[0x96]=0
ETPPA_ECC_ERR_1B_MONITOR_MEM_MASK.ETPPA0[0x9a]=0x1fffff
ETPPA_ECC_ERR_2B_MONITOR_MEM_MASK.ETPPA0[0x9c]=0x1fffff
ETPPA_ECC_INTERRUPT_REGISTER.ETPPA0[0x7]=0
ETPPA_ECC_INTERRUPT_REGISTER_MASK.ETPPA0[0x17]=0
ETPPA_ECC_INTERRUPT_REGISTER_TEST.ETPPA0[0x1f]=0
ETPPA_ENABLE_DYNAMIC_MEMORY_ACCESS.ETPPA0[0x84]=1
ETPPA_ETHERNET_FWD_CODE.ETPPA0[0x10a]=0x400001
ETPPA_ETPPA_INT_REG.ETPPA0[0x100]=0x38100
ETPPA_ETPPA_INT_REG_MASK.ETPPA0[0x101]=0
ETPPA_ETPPA_INT_REG_TEST.ETPPA0[0x102]=0
ETPPA_ETPPA_SAMPLE_VALIDS.ETPPA0[0xf000]=0x3f
ETPPA_ETPP_LATENCY_SETTINGS.ETPPA0[0x103]=0x488
ETPPA_ETPP_PRP_INT_REG.ETPPA0[0x900]=0
ETPPA_ETPP_PRP_INT_REG_MASK.ETPPA0[0x901]=0
ETPPA_ETPP_PRP_INT_REG_TEST.ETPPA0[0x902]=0
ETPPA_FHEI_MPLS_COMMAND.ETPPA0[0x907]=0x10
ETPPA_FIFO_ALMOST_FULL_THRESHOLD.ETPPA0[0x942]=0
ETPPA_FWD_LAYER_ADDITIONAL_INFO_TO_IP_MC_ELIGIBLE_MAPPING.ETPPA0[0x351]=0xcccc
ETPPA_GTIMER_CONFIGURATION.ETPPA0[0x89]=0
ETPPA_GTIMER_CYCLE.ETPPA0[0x88]=0x3b9aca00
ETPPA_INDIRECT_COMMAND.ETPPA0[0x80]=0x3fff0000
ETPPA_INDIRECT_COMMAND_ADDRESS.ETPPA0[0x81]=0x8f000005
ETPPA_INDIRECT_COMMAND_RD_DATA.ETPPA0[0x60]=0x14d400100200044630e0ea626ac467ef03000008003002230007fa00020000000000002cc81bb33fdede26794a6d19810000050800452004fe000340003711cd
ETPPA_INDIRECT_COMMAND_WIDE_MEM.ETPPA0[0x41]=0
ETPPA_INDIRECT_COMMAND_WR_DATA.ETPPA0[0x20]=0
ETPPA_INDIRECT_FORCE_BUBBLE.ETPPA0[0x83]=0x20019
ETPPA_INGRESS_TRAPPED_BY_FHEI.ETPPA0[0x945]=0x20
ETPPA_INITIAL_NWK_QOS_SELECT.ETPPA0[0x946]=0x555055505550fff
ETPPA_INITIAL_NWK_QOS_SELECT_PLUS_1.ETPPA0[0x94e]=0xfff0fff0fff0fff
ETPPA_INTERRUPT_MASK_REGISTER.ETPPA0[0x10]=0
ETPPA_INTERRUPT_REGISTER.ETPPA0[0x0]=0
ETPPA_INTERRUPT_REGISTER_TEST.ETPPA0[0x18]=0
ETPPA_JERICHO_COMPATIBLE_REGISTERS.ETPPA0[0x352]=0xfd400
ETPPA_NUM_ENTRIES_BYPASS_FIFO.ETPPA0[0x104]=0x15000000
ETPPA_NUM_ENTRIES_NETWORK_HEADERS_FIFO.ETPPA0[0x366]=0x58000
ETPPA_NUM_ENTRIES_PP_DSP_FOR_VISIBILITY_AND_IS_TDM_FIFO.ETPPA0[0x367]=0x54000
ETPPA_NUM_ENTRIES_PRP_NETWORK_HEADER_FIFO.ETPPA0[0x941]=0xc40000
ETPPA_NUM_ENTRIES_PRP_SYSTEM_HEADER_FIFO.ETPPA0[0x940]=0xd40000
ETPPA_NUM_ENTRIES_SYSTEM_HEADERS_CONTAINER_FIFO.ETPPA0[0x368]=0x38000
ETPPA_NUM_ENTRIES_TM_FIELDS_FIFO.ETPPA0[0x365]=0x1e0000
ETPPA_OUTRIF_MAX_VALUE.ETPPA0[0x108]=0x1000
ETPPA_PARITY_ERR_CNT.ETPPA0[0x98]=0
ETPPA_PARSER_FIFO_ALMOST_FULL_THRESHOLD.ETPPA0[0x364]=0
ETPPA_PAR_ERR_MEM_MASK.ETPPA0[0xa0]=0xff
ETPPA_PCMI_0.ETPPA0[0xb0]=0x3b9aca00
ETPPA_PCMI_1.ETPPA0[0xb3]=0x3b9aca00
ETPPA_PCMI_2.ETPPA0[0xb6]=0x3b9aca00
ETPPA_PCMI_3.ETPPA0[0xb9]=0x3b9aca00
ETPPA_PCMI_4.ETPPA0[0xbc]=0x3b9aca00
ETPPA_PCMI_0_S.ETPPA0[0xb1]=0
ETPPA_PCMI_0_T.ETPPA0[0xb2]=0
ETPPA_PCMI_1_S.ETPPA0[0xb4]=0
ETPPA_PCMI_1_T.ETPPA0[0xb5]=0
ETPPA_PCMI_2_S.ETPPA0[0xb7]=0
ETPPA_PCMI_2_T.ETPPA0[0xb8]=0
ETPPA_PCMI_3_S.ETPPA0[0xba]=0
ETPPA_PCMI_3_T.ETPPA0[0xbb]=0
ETPPA_PCMI_4_S.ETPPA0[0xbd]=0
ETPPA_PCMI_4_T.ETPPA0[0xbe]=0
ETPPA_PES_DEBUG_SELECT.ETPPA0[0x40d]=0
ETPPA_PES_PRSE_CONFIG(0).ETPPA0[0x405]=0x10
ETPPA_PES_PRSE_CONFIG(1).ETPPA0[0x406]=0x11
ETPPA_PES_PRSE_CONFIG(2).ETPPA0[0x407]=0x12
ETPPA_PES_PRSE_CONFIG(3).ETPPA0[0x408]=0x13
ETPPA_PES_PRSE_CONFIG(4).ETPPA0[0x409]=0x14
ETPPA_PES_PRSE_CONFIG(5).ETPPA0[0x40a]=0x15
ETPPA_PES_PRSE_CONFIG(6).ETPPA0[0x40b]=0x16
ETPPA_PES_PRSE_CONFIG(7).ETPPA0[0x40c]=0x17
ETPPA_PMF_ACR_ACTION_DISABLE.ETPPA0[0x943]=0
ETPPA_PORT_VISIBILITY_EN(0).ETPPA0[0x36a]=0
ETPPA_PORT_VISIBILITY_EN(1).ETPPA0[0x36b]=0
ETPPA_PORT_VISIBILITY_EN(2).ETPPA0[0x36c]=0
ETPPA_PORT_VISIBILITY_EN(3).ETPPA0[0x36d]=0
ETPPA_PORT_VISIBILITY_FORCE(0).ETPPA0[0x38a]=0x1010004000000000000000000000000000000000050e40000001fffffffff
ETPPA_PORT_VISIBILITY_FORCE(1).ETPPA0[0x38b]=0
ETPPA_PORT_VISIBILITY_FORCE(2).ETPPA0[0x38c]=0
ETPPA_PORT_VISIBILITY_FORCE(3).ETPPA0[0x38d]=0
ETPPA_PPH_BASE_FIELDS_CG_2.ETPPA0[0x35c]=0x3530813081b16231239084b01000456035a05010706030d02100112
ETPPA_PRP_CONTEXT_ENABLERS.ETPPA0[0x906]=0x1ffff
ETPPA_PSG_DEBUG_SELECT.ETPPA0[0x455]=0
ETPPA_PSG_PRSE_CONFIG(0).ETPPA0[0x451]=0x10
ETPPA_PSG_PRSE_CONFIG(1).ETPPA0[0x452]=0x11
ETPPA_PSG_PRSE_CONFIG(2).ETPPA0[0x453]=0x12
ETPPA_PSG_PRSE_CONFIG(3).ETPPA0[0x454]=0x13
ETPPA_REG_0340.ETPPA0[0x340]=0x1921100
ETPPA_REG_0341.ETPPA0[0x341]=0xdd8c80100315619000000101080a99f2bf5c8c95a5b08ec9c51977b7e1366144838ed97b0ae1c1270362d4c24d9c42c61a696f2621cacb20d4ce2a29e700000000000000000000000000000000000000
ETPPA_REG_1051.ETPPA0[0x1051]=0x1004
ETPPA_REG_00C2.ETPPA0[0xc2]=0x10
ETPPA_REG_00C5.ETPPA0[0xc5]=0x2d6
ETPPA_REG_00C6.ETPPA0[0xc6]=0x53
ETPPA_REG_00E8.ETPPA0[0xe8]=0x88a88100
ETPPA_REG_00E9.ETPPA0[0xe9]=0x9100
ETPPA_REG_00EB.ETPPA0[0xeb]=0
ETPPA_REG_00EE.ETPPA0[0xee]=0x105557
ETPPA_REG_00F0.ETPPA0[0xf0]=0
ETPPA_REG_00F1.ETPPA0[0xf1]=0
ETPPA_REG_00F2.ETPPA0[0xf2]=0
ETPPA_RESERVED_MTCD.ETPPA0[0xae]=0x30
ETPPA_RESERVED_MTCP.ETPPA0[0xad]=0x300000600000000
ETPPA_RESERVED_SPARE_0.ETPPA0[0x90]=0xffffffff
ETPPA_RESERVED_SPARE_1.ETPPA0[0x91]=0xffffffff
ETPPA_RESERVED_SPARE_2.ETPPA0[0x92]=0
ETPPA_RESERVED_SPARE_3.ETPPA0[0x93]=0
ETPPA_SBUS_BROADCAST_ID.ETPPA0[0x86]=0x7ff
ETPPA_SBUS_LAST_IN_CHAIN.ETPPA0[0x87]=0
ETPPA_SPECIAL_CLOCK_CONTROLS.ETPPA0[0xc1]=2
ETPPA_STAT_VISIBILITY.ETPPA0[0x3aa]=0
ETPPA_SYSTEM_HEADERS_CG_1.ETPPA0[0x353]=0x201220804a7241480c500213b500cd30134400000000001a0036900c6318c631b4018011
ETPPA_TDM_GENERAL_CONFIGURATION.ETPPA0[0x109]=0
ETPPA_UTILITY_REGS.ETPPA0[0x350]=9
ETPPA_XBR_CONFIG(0).ETPPA0[0x400]=0
ETPPA_XBR_CONFIG(1).ETPPA0[0x401]=0
ETPPA_XBR_CONFIG(2).ETPPA0[0x402]=0
ETPPA_XBR_CONFIG(3).ETPPA0[0x403]=0
ETPPA_XBR_CONFIG(4).ETPPA0[0x404]=0
ETPPA_XOR_INIT_DONE.ETPPA0[0x10f]=1
ETPPB_BTC_DEFAULT_VALUES.ETPPB0[0x443]=0
ETPPB_BTC_INT_REG.ETPPB0[0x440]=8
ETPPB_BTC_INT_REG_MASK.ETPPB0[0x441]=0
ETPPB_BTC_INT_REG_TEST.ETPPB0[0x442]=0
ETPPB_CFG_CW_PREVENT_MAP.ETPPB0[0x1d3]=0
ETPPB_CFG_EXTERNAL_STATISTICS_CORE_ID.ETPPB0[0x14a]=0
ETPPB_CFG_EXTERNAL_STATISTICS_IDENTIFIER.ETPPB0[0x149]=0
ETPPB_CFG_EXTERNAL_STATISTICS_OPCODE_SIZE.ETPPB0[0x141]=0
ETPPB_CFG_FHEI_TYPE_CPU_TRAP.ETPPB0[0x108]=5
ETPPB_CFG_FORWARD_CODE_IPV4_OR_IPV6.ETPPB0[0x1d6]=0x3000000030
ETPPB_CFG_GENERAL_PACKET_SIZE_COMPENSATION.ETPPB0[0x1de]=2
ETPPB_CFG_IEEE_1588_MAC_ENABLE(0).ETPPB0[0x14b]=0x1ffffffffe
ETPPB_CFG_IEEE_1588_MAC_ENABLE(1).ETPPB0[0x14c]=0
ETPPB_CFG_IEEE_1588_MAC_ENABLE(2).ETPPB0[0x14d]=0
ETPPB_CFG_IEEE_1588_MAC_ENABLE(3).ETPPB0[0x14e]=0
ETPPB_CFG_IEEE_1588_RECORD_TS.ETPPB0[0x18e]=4
ETPPB_CFG_IEEE_1588_TS_OFFSET_FIX.ETPPB0[0x16c]=0
ETPPB_CFG_IEEE_1588_TX_STAMP_CF.ETPPB0[0x16d]=2
ETPPB_CFG_IEEE_OSTS_PER_PORT_EN(0).ETPPB0[0x16e]=0
ETPPB_CFG_IEEE_OSTS_PER_PORT_EN(1).ETPPB0[0x16f]=0
ETPPB_CFG_IEEE_OSTS_PER_PORT_EN(2).ETPPB0[0x170]=0
ETPPB_CFG_IEEE_OSTS_PER_PORT_EN(3).ETPPB0[0x171]=0
ETPPB_CFG_INIT_PROBABILITY_VALUE.ETPPB0[0x1dc]=0xffffffffffffffff
ETPPB_CFG_MAP_REMARK_PROFILE_QOS_DP.ETPPB0[0x1be]=0xffbbcdeb38bdab49ca307b9ac5a928398a418820
ETPPB_CFG_MAP_REMARK_PROFILE_QOS_VAR.ETPPB0[0x1b9]=0xffbbcdeb38bdab49ca307b9ac5a928398a418820
ETPPB_CFG_MEMBERSHIP_PER_FWD_CODE.ETPPB0[0x196]=1
ETPPB_CFG_MEMBERSHIP_PER_PORT_EN(0).ETPPB0[0x198]=0
ETPPB_CFG_MEMBERSHIP_PER_PORT_EN(1).ETPPB0[0x199]=0
ETPPB_CFG_MEMBERSHIP_PER_PORT_EN(2).ETPPB0[0x19a]=0
ETPPB_CFG_MEMBERSHIP_PER_PORT_EN(3).ETPPB0[0x19b]=0
ETPPB_CFG_MEMBERSHIP_TRAP_PARAMS.ETPPB0[0x195]=0x84
ETPPB_CFG_MIRROR_ACTION_NULL_PROFILE.ETPPB0[0x123]=7
ETPPB_CFG_MPLS_CONTROL_WORD.ETPPB0[0x1d4]=0
ETPPB_CFG_OAM_TYPE.ETPPB0[0x10a]=0x40002
ETPPB_CFG_OVERRIDE_PIPE_QOS_VALUES.ETPPB0[0x1c5]=0
ETPPB_CFG_PIPE_MAPPED_TTL_VARIABLE_MAP.ETPPB0[0x1c8]=0xff000000000000000000000000000000000000000000000000000000000000
ETPPB_CFG_STAT_METADATA_CURRENT_PROTOCOL_TYPE.ETPPB0[0x1d0]=0
ETPPB_CFG_STP_STATE_PER_FWD_CODE.ETPPB0[0x193]=1
ETPPB_CFG_STP_TRAP_PARAMS.ETPPB0[0x192]=0x8d
ETPPB_CFG_TRAP_BYTES_TO_ADD.ETPPB0[0x10b]=0x114997948e8
ETPPB_CFG_TRAP_DP_EXTERNAL_SHIFT.ETPPB0[0x140]=0
ETPPB_CFG_TRAP_DP_INTERNAL_SHIFT.ETPPB0[0x13a]=0x18
ETPPB_CFG_TRAP_DROP_EXTERNAL_SHIFT.ETPPB0[0x13c]=0
ETPPB_CFG_TRAP_DROP_INTERNAL_SHIFT.ETPPB0[0x136]=0x18
ETPPB_CFG_TRAP_ECN_EXTERNAL_SHIFT.ETPPB0[0x13e]=0
ETPPB_CFG_TRAP_ECN_INTERNAL_SHIFT.ETPPB0[0x138]=0x18
ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_METADATA_SHIFT.ETPPB0[0x143]=0
ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_0_SHIFT.ETPPB0[0x145]=0
ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_1_SHIFT.ETPPB0[0x146]=0
ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_2_SHIFT.ETPPB0[0x147]=0
ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_3_SHIFT.ETPPB0[0x148]=0
ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OPCODE_SHIFT.ETPPB0[0x142]=0
ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_PACKET_SIZE_SHIFT.ETPPB0[0x144]=0
ETPPB_CFG_TRAP_MC_EXTERNAL_SHIFT.ETPPB0[0x13b]=0
ETPPB_CFG_TRAP_MC_INTERNAL_SHIFT.ETPPB0[0x135]=0x18
ETPPB_CFG_TRAP_OBJ_0_SHIFT.ETPPB0[0x12b]=0x18
ETPPB_CFG_TRAP_OBJ_1_SHIFT.ETPPB0[0x12c]=0x18
ETPPB_CFG_TRAP_OBJ_2_SHIFT.ETPPB0[0x12d]=0x18
ETPPB_CFG_TRAP_OBJ_3_SHIFT.ETPPB0[0x12e]=0x18
ETPPB_CFG_TRAP_OBJ_4_SHIFT.ETPPB0[0x12f]=0x18
ETPPB_CFG_TRAP_OBJ_5_SHIFT.ETPPB0[0x130]=0x18
ETPPB_CFG_TRAP_OBJ_6_SHIFT.ETPPB0[0x131]=0
ETPPB_CFG_TRAP_OBJ_7_SHIFT.ETPPB0[0x132]=0
ETPPB_CFG_TRAP_OBJ_8_SHIFT.ETPPB0[0x133]=0
ETPPB_CFG_TRAP_OBJ_9_SHIFT.ETPPB0[0x134]=0
ETPPB_CFG_TRAP_PORT_EXTERNAL_SHIFT.ETPPB0[0x13d]=0
ETPPB_CFG_TRAP_PORT_INTERNAL_SHIFT.ETPPB0[0x137]=0x18
ETPPB_CFG_TRAP_TC_EXTERNAL_SHIFT.ETPPB0[0x13f]=0
ETPPB_CFG_TRAP_TC_INTERNAL_SHIFT.ETPPB0[0x139]=0x18
ETPPB_CFG_TS_UDP_ENCAP.ETPPB0[0x16b]=0
ETPPB_CFG_TTL_MODEL_PIPE_MAP.ETPPB0[0x1d5]=0xa
ETPPB_CFG_VID.ETPPB0[0x18f]=0
ETPPB_DEVICE_CFG_PORT_MTU_EN.ETPPB0[0x1b8]=1
ETPPB_DEVICE_CFG_TRAP_FUNCTIONS_ENABLE.ETPPB0[0x1c3]=3
ETPPB_ECC_1B_ERR_CNT.ETPPB0[0x94]=0
ETPPB_ECC_2B_ERR_CNT.ETPPB0[0x96]=0
ETPPB_ECC_ERR_1B_MONITOR_MEM_MASK.ETPPB0[0x9a]=0x1ffffffffffff
ETPPB_ECC_ERR_2B_MONITOR_MEM_MASK.ETPPB0[0x9c]=0x1ffffffffffff
ETPPB_ECC_INTERRUPT_REGISTER.ETPPB0[0x7]=0
ETPPB_ECC_INTERRUPT_REGISTER_MASK.ETPPB0[0x17]=0
ETPPB_ECC_INTERRUPT_REGISTER_TEST.ETPPB0[0x1f]=0
ETPPB_ENABLE_DYNAMIC_MEMORY_ACCESS.ETPPB0[0x84]=1
ETPPB_ENC_1_CONTEXT_STATUS.ETPPB0[0x452]=0x3200000
ETPPB_ENC_2_CONTEXT_STATUS.ETPPB0[0x453]=0x2200000
ETPPB_ENC_3_CONTEXT_STATUS.ETPPB0[0x454]=0x2600000
ETPPB_ENC_4_CONTEXT_STATUS.ETPPB0[0x455]=0x580000
ETPPB_ENC_5_CONTEXT_STATUS.ETPPB0[0x456]=0x600000
ETPPB_ENC_DEVICE_CONFIGS.ETPPB0[0x1c4]=0
ETPPB_ETPPB_INT_REG.ETPPB0[0x100]=1
ETPPB_ETPPB_INT_REG_MASK.ETPPB0[0x101]=0
ETPPB_ETPPB_INT_REG_TEST.ETPPB0[0x102]=0
ETPPB_ETPPB_SAMPLE_VALIDS.ETPPB0[0xf000]=0xff
ETPPB_FIFO_ALMOST_FULL_THRESHOLD.ETPPB0[0x104]=0
ETPPB_FWD_CONTEXT_STATUS.ETPPB0[0x451]=0x3600000
ETPPB_GTIMER_CONFIGURATION.ETPPB0[0x89]=0
ETPPB_GTIMER_CYCLE.ETPPB0[0x88]=0x3b9aca00
ETPPB_INDIRECT_COMMAND.ETPPB0[0x80]=0x3fff0000
ETPPB_INDIRECT_COMMAND_ADDRESS.ETPPB0[0x81]=0x8007000c
ETPPB_INDIRECT_COMMAND_RD_DATA.ETPPB0[0x60]=0x1f60000000
ETPPB_INDIRECT_COMMAND_WIDE_MEM.ETPPB0[0x41]=0
ETPPB_INDIRECT_COMMAND_WR_DATA.ETPPB0[0x20]=0
ETPPB_INDIRECT_FORCE_BUBBLE.ETPPB0[0x83]=0x20019
ETPPB_INTERRUPT_MASK_REGISTER.ETPPB0[0x10]=0
ETPPB_INTERRUPT_REGISTER.ETPPB0[0x0]=0
ETPPB_INTERRUPT_REGISTER_TEST.ETPPB0[0x18]=0
ETPPB_MAP_STS_TO_INTERFACE.ETPPB0[0x125]=0x100f
ETPPB_MAP_STS_TO_TYPE.ETPPB0[0x129]=0
ETPPB_MIRROR_ACTION_TABLE.ETPPB0[0x118]=0
ETPPB_NETWORK_OFFSET.ETPPB0[0x109]=0
ETPPB_NUM_ENTRIES_ENCAPSULATION_2_DATA_FIFO.ETPPB0[0x1d8]=0x600
ETPPB_NUM_ENTRIES_ENCAPSULATION_3_DATA_FIFO.ETPPB0[0x1d9]=0x600
ETPPB_NUM_ENTRIES_ENCAPSULATION_4_DATA_FIFO.ETPPB0[0x1da]=0x600
ETPPB_NUM_ENTRIES_ENCAPSULATION_5_DATA_FIFO.ETPPB0[0x1db]=0x600
ETPPB_NUM_ENTRIES_TRAP_BYPASS_FIFO.ETPPB0[0x107]=0xc80000
ETPPB_NUM_ENTRIES_TRAP_ORIGINAL_FTMH_FIFO.ETPPB0[0x105]=0x10c00000
ETPPB_PARITY_ERR_CNT.ETPPB0[0x98]=0
ETPPB_PAR_ERR_MEM_MASK.ETPPB0[0xa0]=0x3ffff
ETPPB_PCMI_0.ETPPB0[0xb0]=0x3b9aca00
ETPPB_PCMI_1.ETPPB0[0xb3]=0x3b9aca00
ETPPB_PCMI_2.ETPPB0[0xb6]=0x3b9aca00
ETPPB_PCMI_3.ETPPB0[0xb9]=0x3b9aca00
ETPPB_PCMI_4.ETPPB0[0xbc]=0x3b9aca00
ETPPB_PCMI_0_S.ETPPB0[0xb1]=0
ETPPB_PCMI_0_T.ETPPB0[0xb2]=0
ETPPB_PCMI_1_S.ETPPB0[0xb4]=0
ETPPB_PCMI_1_T.ETPPB0[0xb5]=0
ETPPB_PCMI_2_S.ETPPB0[0xb7]=0
ETPPB_PCMI_2_T.ETPPB0[0xb8]=0
ETPPB_PCMI_3_S.ETPPB0[0xba]=0
ETPPB_PCMI_3_T.ETPPB0[0xbb]=0
ETPPB_PCMI_4_S.ETPPB0[0xbd]=0
ETPPB_PCMI_4_T.ETPPB0[0xbe]=0
ETPPB_QOS_MODEL_MAPPING_TABLE.ETPPB0[0x1c6]=0x400702dbd
ETPPB_RCY_CMD_MAP.ETPPB0[0x124]=0
ETPPB_REG_0103.ETPPB0[0x103]=0x1ff
ETPPB_REG_0300.ETPPB0[0x300]=0
ETPPB_REG_0301.ETPPB0[0x301]=0x200800000000520000002001dc0016000000000000000012880e4d0005937600000000e000000000000000e10000604000000000000000000000000000000000000000000000000000000000000000
ETPPB_REG_0315.ETPPB0[0x315]=1
ETPPB_REG_0320.ETPPB0[0x320]=0x9a1000
ETPPB_REG_0321.ETPPB0[0x321]=0x200800000000520000002001dc0016000000000000000012880e4d000593f740000000e000000000000000e10000604000000000000000000000000000000000000000000000000000000000000000
ETPPB_REG_0335.ETPPB0[0x335]=0
ETPPB_REG_0340.ETPPB0[0x340]=0
ETPPB_REG_0341.ETPPB0[0x341]=0x100400000000460000002001ac0014000000000000000012dc1bbd0005a16300000000e000000000000000e10000504000000000000000000000000000000000000000000000000000000000000000
ETPPB_REG_0355.ETPPB0[0x355]=1
ETPPB_REG_0360.ETPPB0[0x360]=0x1a21200
ETPPB_REG_0361.ETPPB0[0x361]=0x800000000000000000000000a100005000000000000000008000000000000000000000000000000000000e8800b442480000000000000000000000000000000000000000030300000000000000100080
ETPPB_REG_0520.ETPPB0[0x520]=0x1ba1100
ETPPB_REG_0521.ETPPB0[0x521]=0x200800000000460000002001ac0016000000000000000012600c690005a28840000000e000000000000000e10000604000000000000000000000000000000000000000000000000000000000000000
ETPPB_REG_0535.ETPPB0[0x535]=0
ETPPB_REG_00C2.ETPPB0[0xc2]=0x10
ETPPB_REG_00C5.ETPPB0[0xc5]=0x2d6
ETPPB_REG_00C6.ETPPB0[0xc6]=0x53
ETPPB_REG_00E8.ETPPB0[0xe8]=0x88a88100
ETPPB_REG_00E9.ETPPB0[0xe9]=0x9100
ETPPB_REG_00EB.ETPPB0[0xeb]=0
ETPPB_REG_00EE.ETPPB0[0xee]=0x105557
ETPPB_REG_00F0.ETPPB0[0xf0]=0
ETPPB_REG_00F1.ETPPB0[0xf1]=0
ETPPB_REG_00F2.ETPPB0[0xf2]=0
ETPPB_RESERVED_MTCD.ETPPB0[0xae]=0x30
ETPPB_RESERVED_MTCP.ETPPB0[0xad]=0x300000600000000
ETPPB_RESERVED_SPARE_0.ETPPB0[0x90]=0xffffffff
ETPPB_RESERVED_SPARE_1.ETPPB0[0x91]=0xffffffff
ETPPB_RESERVED_SPARE_2.ETPPB0[0x92]=0
ETPPB_RESERVED_SPARE_3.ETPPB0[0x93]=0
ETPPB_SBUS_BROADCAST_ID.ETPPB0[0x86]=0x7ff
ETPPB_SBUS_LAST_IN_CHAIN.ETPPB0[0x87]=0
ETPPB_SNOOP_ACTION_TABLE.ETPPB0[0x10d]=0x83ffffffff000000000014ffffffffc47fffffffe0000000000
ETPPB_SPECIAL_CLOCK_CONTROLS.ETPPB0[0xc1]=2
ETPPB_TERM_CONTEXT_STATUS.ETPPB0[0x450]=0x3800000
ETPPB_TRAP_ADDITIONAL_DATA_STATUS.ETPPB0[0x458]=0x1c0000
ETPPB_TRAP_CONTEXT_STATUS.ETPPB0[0x457]=0x10000
ETPPC_CFG_CW_PREVENT_MAP.ETPPC0[0x138]=0
ETPPC_CFG_DEFAULT_INVALID_ETPS.ETPPC0[0x819]=0
ETPPC_CFG_DONT_COUNT.ETPPC0[0x850]=7
ETPPC_CFG_DONT_METER.ETPPC0[0x851]=7
ETPPC_CFG_DP_METER_CMD.ETPPC0[0x8b3]=0
ETPPC_CFG_DROP_CNI_VALID_PER_SYSTEM_HEADER_FLOW_PROFILE.ETPPC0[0x8c7]=0
ETPPC_CFG_EES_TYPE_VALID_FOR_VSD.ETPPC0[0x817]=0x7e
ETPPC_CFG_ENTRY_IS_EM_BUSTER.ETPPC0[0x80c]=0x80200000d50
ETPPC_CFG_ESEM_1_SHIFT_VAL.ETPPC0[0x811]=0x24924949249b
ETPPC_CFG_ESEM_2_SHIFT_VAL.ETPPC0[0x813]=0x24924949249b
ETPPC_CFG_ESEM_3_SHIFT_VAL.ETPPC0[0x815]=0x492492492492
ETPPC_CFG_FINAL_DP_TRAP.ETPPC0[0x860]=0
ETPPC_CFG_FLOW_ID_EXIST.ETPPC0[0x80e]=0
ETPPC_CFG_FORWARD_CODE_IPV4_OR_IPV6.ETPPC0[0x13b]=0x3000000030
ETPPC_CFG_FWD_EGRESS_DO_NOT_TTL_DECREMENT.ETPPC0[0x700]=0xf0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
ETPPC_CFG_GENERAL_PACKET_SIZE_COMPENSATION.ETPPC0[0x13e]=2
ETPPC_CFG_IEEE_1588_RX_STAMP.ETPPC0[0x8ba]=2
ETPPC_CFG_INVALID_OAM_LIF.ETPPC0[0x85e]=0xffff
ETPPC_CFG_IS_TTL_MODEL_INHERIT_PHP.ETPPC0[0x8c1]=5
ETPPC_CFG_KEEP_ING_ECID(0).ETPPC0[0x720]=0
ETPPC_CFG_KEEP_ING_ECID(1).ETPPC0[0x721]=0
ETPPC_CFG_KEEP_ING_ECID(2).ETPPC0[0x722]=0
ETPPC_CFG_KEEP_ING_ECID(3).ETPPC0[0x723]=0
ETPPC_CFG_LATENCY_MEASUREMENT_CQ.ETPPC0[0x8c9]=5
ETPPC_CFG_LATENCY_MEASUREMENT_DE.ETPPC0[0x8cb]=0xf
ETPPC_CFG_LATENCY_MEASUREMENT_LQ.ETPPC0[0x8c8]=0xa
ETPPC_CFG_LATENCY_MEASUREMENT_TYP.ETPPC0[0x8ca]=0xf
ETPPC_CFG_LATENCY_TRAP_PARAMS.ETPPC0[0x8bb]=0x3c00
ETPPC_CFG_LAYER_PROTOCOL_IPV4.ETPPC0[0x112]=4
ETPPC_CFG_LAYER_PROTOCOL_IPV6.ETPPC0[0x113]=8
ETPPC_CFG_LAYER_PROTOCOL_MPLS.ETPPC0[0x111]=0x10
ETPPC_CFG_LAYER_PROTOCOL_OAM.ETPPC0[0x114]=0x4000
ETPPC_CFG_MAINTAIN_AVERAGE.ETPPC0[0x8c5]=0x3c
ETPPC_CFG_MAP_FIRST_NIBBLE.ETPPC0[0x8bc]=0xffffdcff
ETPPC_CFG_MAP_FWD_LAYER_PROTOCOL.ETPPC0[0x116]=0x4688
ETPPC_CFG_MAP_FWD_PLUS_1_EXPLICIT_REMARK_PROFILE.ETPPC0[0x8bf]=0x2182
ETPPC_CFG_MAP_FWD_PLUS_1_PROTOCOL.ETPPC0[0x8c2]=0xffffffffffffff4f
ETPPC_CFG_MAP_FWD_PLUS_1_REMARK_PROFILE.ETPPC0[0x8c0]=0x50505050
ETPPC_CFG_MAP_OUTLIF_PROFILE_TO_L_2_CP_PROFILE.ETPPC0[0x712]=0
ETPPC_CFG_MAP_REMARK_PROFILE_QOS_DP.ETPPC0[0x124]=0xffbbcdeb38bdab49ca307b9ac5a928398a418820
ETPPC_CFG_MAP_REMARK_PROFILE_QOS_VAR.ETPPC0[0x11f]=0xffbbcdeb38bdab49ca307b9ac5a928398a418820
ETPPC_CFG_MAP_STACK_ACTION_PROFILE_IDX.ETPPC0[0x84b]=0x842
ETPPC_CFG_METERING_TRAP_PARAMS.ETPPC0[0x85f]=0
ETPPC_CFG_METER_OFFSET_MAP.ETPPC0[0x8ad]=0
ETPPC_CFG_MPLS_CONTROL_WORD.ETPPC0[0x139]=0
ETPPC_CFG_OAM_PORT_PROFILE(0).ETPPC0[0x888]=0x600000000000002000000001
ETPPC_CFG_OAM_PORT_PROFILE(1).ETPPC0[0x889]=0
ETPPC_CFG_OAM_PORT_PROFILE(2).ETPPC0[0x88a]=0
ETPPC_CFG_OAM_PORT_PROFILE(3).ETPPC0[0x88b]=0
ETPPC_CFG_OAM_TRAP_LIF_PROFILE_MAP.ETPPC0[0x857]=0
ETPPC_CFG_OTM_STATISTICS_OBJECT_COMMAND.ETPPC0[0x881]=0
ETPPC_CFG_OTM_STATISTICS_PER_OTM_EN(0).ETPPC0[0x861]=0
ETPPC_CFG_OTM_STATISTICS_PER_OTM_EN(1).ETPPC0[0x862]=0
ETPPC_CFG_OTM_STATISTICS_PER_OTM_EN(2).ETPPC0[0x863]=0
ETPPC_CFG_OTM_STATISTICS_PER_OTM_EN(3).ETPPC0[0x864]=0
ETPPC_CFG_OVERRIDE_PIPE_QOS_VALUES.ETPPC0[0x12a]=0
ETPPC_CFG_PEM_ESEM_DEFAULT_RESULT_PROFILE.ETPPC0[0x810]=0xcc
ETPPC_CFG_PHANTOM_QUEUES_ENABLE.ETPPC0[0x8c4]=1
ETPPC_CFG_PIPE_MAPPED_TTL_VARIABLE_MAP.ETPPC0[0x12d]=0xff000000000000000000000000000000000000000000000000000000000000
ETPPC_CFG_PRIORITY_MAP_OAM_LIF_PROFILE.ETPPC0[0x853]=0
ETPPC_CFG_PROTECTION_DB_TRAP_PARAMS.ETPPC0[0x84c]=0x8d
ETPPC_CFG_QOS_MODEL_IS_PIPE.ETPPC0[0x115]=0x7e
ETPPC_CFG_REMARK_PROTOCOL_PROFILE.ETPPC0[0x119]=0
ETPPC_CFG_SPLIT_HORIZON_FILTER.ETPPC0[0x824]=0x200
ETPPC_CFG_SPLIT_HORIZON_PER_FWD_CODE.ETPPC0[0x826]=1
ETPPC_CFG_SPLIT_HORIZON_PER_OUTLIF_PROFILE.ETPPC0[0x828]=0xffffffffffffffff
ETPPC_CFG_SPLIT_HORIZON_PER_OUT_PP_PORT(0).ETPPC0[0x82a]=0xfffffffff80000000000007dffffffffe
ETPPC_CFG_SPLIT_HORIZON_PER_OUT_PP_PORT(1).ETPPC0[0x82b]=0
ETPPC_CFG_SPLIT_HORIZON_PER_OUT_PP_PORT(2).ETPPC0[0x82c]=0
ETPPC_CFG_SPLIT_HORIZON_PER_OUT_PP_PORT(3).ETPPC0[0x82d]=0
ETPPC_CFG_SPLIT_HORIZON_TRAP_PARAMS.ETPPC0[0x84a]=0x8d
ETPPC_CFG_STACK_MIRROR_ACTION_PROFILE.ETPPC0[0x84f]=7
ETPPC_CFG_STACK_TRAP_1_TRAP_PARAMS.ETPPC0[0x84d]=0
ETPPC_CFG_STACK_TRAP_2_TRAP_PARAMS.ETPPC0[0x84e]=0
ETPPC_CFG_STATISTICS_VALID_PER_SYSTEM_HEADER_FLOW_PROFILE.ETPPC0[0x8c6]=0
ETPPC_CFG_STAT_METADATA_CURRENT_PROTOCOL_TYPE.ETPPC0[0x135]=0
ETPPC_CFG_STAT_OBJ_CMD_TO_IS_METER.ETPPC0[0x8a9]=0
ETPPC_CFG_STAT_OBJ_CMD_TO_METER_IF.ETPPC0[0x8a8]=0
ETPPC_CFG_STAT_OBJ_CMD_TO_METER_QOS_PROFILE.ETPPC0[0x8aa]=0
ETPPC_CFG_SWITCH_ID.ETPPC0[0x8b9]=0
ETPPC_CFG_TAIL_EDITING_BITMAP.ETPPC0[0x8b4]=0x3fe00
ETPPC_CFG_TAIL_EDITING_SIZE.ETPPC0[0x8b7]=0x380
ETPPC_CFG_TERMINATION_FWD_CODE_EN.ETPPC0[0x80a]=0x8020003c0e472eff
ETPPC_CFG_TTL_MODEL_PIPE_MAP.ETPPC0[0x13a]=0xa
ETPPC_DEVICE_CFG_TS_UDP_ENCAP.ETPPC0[0x80f]=0
ETPPC_ECC_1B_ERR_CNT.ETPPC0[0x94]=0
ETPPC_ECC_2B_ERR_CNT.ETPPC0[0x96]=0
ETPPC_ECC_ERR_1B_MONITOR_MEM_MASK.ETPPC0[0x9a]=0xffffffff
ETPPC_ECC_ERR_2B_MONITOR_MEM_MASK.ETPPC0[0x9c]=0xffffffff
ETPPC_ECC_INTERRUPT_REGISTER.ETPPC0[0x7]=0
ETPPC_ECC_INTERRUPT_REGISTER_MASK.ETPPC0[0x17]=0
ETPPC_ECC_INTERRUPT_REGISTER_TEST.ETPPC0[0x1f]=0
ETPPC_ENABLE_DYNAMIC_MEMORY_ACCESS.ETPPC0[0x84]=1
ETPPC_ENC_DEVICE_CONFIGS.ETPPC0[0x129]=0
ETPPC_ETHERNET_FWD_CODE.ETPPC0[0x10f]=0x400001
ETPPC_ETPPC_INT_REG.ETPPC0[0x100]=0
ETPPC_ETPPC_INT_REG_MASK.ETPPC0[0x101]=0
ETPPC_ETPPC_INT_REG_TEST.ETPPC0[0x102]=0
ETPPC_ETPPC_SAMPLE_VALIDS.ETPPC0[0xf000]=0x3ff
ETPPC_ETPP_TERM_INT_REG.ETPPC0[0x800]=0
ETPPC_ETPP_TERM_INT_REG_MASK.ETPPC0[0x801]=0
ETPPC_ETPP_TERM_INT_REG_TEST.ETPPC0[0x802]=0
ETPPC_ETPS_ENTRY_IS_AC.ETPPC0[0x71e]=0
ETPPC_GTIMER_CONFIGURATION.ETPPC0[0x89]=0
ETPPC_GTIMER_CYCLE.ETPPC0[0x88]=0x3b9aca00
ETPPC_INDIRECT_COMMAND.ETPPC0[0x80]=0x3fff0000
ETPPC_INDIRECT_COMMAND_ADDRESS.ETPPC0[0x81]=0x82630040
ETPPC_INDIRECT_COMMAND_RD_DATA.ETPPC0[0x60]=9
ETPPC_INDIRECT_COMMAND_WIDE_MEM.ETPPC0[0x41]=0
ETPPC_INDIRECT_COMMAND_WR_DATA.ETPPC0[0x20]=0
ETPPC_INDIRECT_FORCE_BUBBLE.ETPPC0[0x83]=0x20019
ETPPC_INTERRUPT_MASK_REGISTER.ETPPC0[0x10]=0
ETPPC_INTERRUPT_REGISTER.ETPPC0[0x0]=0
ETPPC_INTERRUPT_REGISTER_TEST.ETPPC0[0x18]=0
ETPPC_IPV4_MC_FWD_CODE.ETPPC0[0x109]=0x800000008
ETPPC_IPV4_UC_FWD_CODE.ETPPC0[0x105]=0x400000004
ETPPC_IPV6_MC_FWD_CODE.ETPPC0[0x10b]=0x2000000020
ETPPC_IPV6_UC_FWD_CODE.ETPPC0[0x107]=0x1000000010
ETPPC_JERICHO_COMPATIBLE_REGISTERS.ETPPC0[0x104]=0
ETPPC_MAP_FWD_QOS_REMARK_OR_KEEP.ETPPC0[0x746]=8
ETPPC_MAP_STRENGTH_TO_OAM_INJECTION.ETPPC0[0x852]=0x80
ETPPC_MEF_L_2_CP_TRANSPARANT_BITMAP.ETPPC0[0x716]=0
ETPPC_MPLS_FWD_CODE.ETPPC0[0x10d]=0x4000000
ETPPC_NUM_ENTRIES_BIER_BIT_MASK_FIFO.ETPPC0[0x710]=0x4200000
ETPPC_NUM_ENTRIES_ENCAPSULATION_1_DATA_FIFO.ETPPC0[0x13d]=0x600
ETPPC_NUM_ENTRIES_ESEM_1_RESULT_FIFO.ETPPC0[0x805]=0x400
ETPPC_NUM_ENTRIES_ESEM_2_RESULT_FIFO.ETPPC0[0x806]=0
ETPPC_NUM_ENTRIES_EXEM_RESULT_FIFO.ETPPC0[0x807]=0
ETPPC_NUM_ENTRIES_FWD_BYPASS_FIFO.ETPPC0[0x711]=0x1c00
ETPPC_NUM_ENTRIES_OEM_RESULT_FIFO.ETPPC0[0x809]=0x400
ETPPC_NUM_ENTRIES_TERM_PIPE_FIFO_1.ETPPC0[0x804]=0x1e0000
ETPPC_NUM_ENTRIES_TERM_PIPE_FIFO_2.ETPPC0[0x803]=0x2a0000
ETPPC_NUM_ENTRIES_VSD_RESULT_FIFO.ETPPC0[0x808]=0x1400
ETPPC_OAM_COUNTER_IN_RANGE_CFG_0.ETPPC0[0x1104]=0
ETPPC_OAM_COUNTER_IN_RANGE_CFG_1.ETPPC0[0x1105]=0
ETPPC_OAM_COUNTER_IN_RANGE_CFG_2.ETPPC0[0x1106]=0
ETPPC_OAM_COUNTER_NOT_IN_RANGE_CFG_0.ETPPC0[0x1107]=0x400000
ETPPC_OAM_COUNTER_NOT_IN_RANGE_CFG_1.ETPPC0[0x1108]=0x400000
ETPPC_OAM_COUNTER_NOT_IN_RANGE_CFG_2.ETPPC0[0x1109]=0x400000
ETPPC_OAM_COUNTER_RANGE.ETPPC0[0x1102]=0xfffff00000
ETPPC_OAM_DEFAULT_ACC_MEP_PROFILES.ETPPC0[0x1112]=0
ETPPC_OAM_DEFAULT_COUNTERS.ETPPC0[0x110d]=0
ETPPC_OAM_DEFAULT_INTERFACE.ETPPC0[0x1113]=0
ETPPC_OAM_DEFAULT_MP_TYPE_VECTOR.ETPPC0[0x1110]=0
ETPPC_OAM_LIF_DB_ACCESS_PROFILE_EN_0.ETPPC0[0x110a]=0
ETPPC_OAM_LIF_DB_ACCESS_PROFILE_EN_1.ETPPC0[0x110b]=0
ETPPC_OAM_LIF_DB_ACCESS_PROFILE_EN_2.ETPPC0[0x110c]=0
ETPPC_OAM_LM_COUNTER_READ_IDX_SEL_MEM.ETPPC0[0x1115]=0x555500aaaa0000000000000000280000555500aaaa00
ETPPC_OAM_PACKET_INJECTED_BITMAP.ETPPC0[0x1114]=0x80
ETPPC_OAM_PRIORITY_MAP.ETPPC0[0x85b]=0xfac688
ETPPC_OAM_PROCESS_MAP.ETPPC0[0x882]=0x40030000008e4452146000
ETPPC_OAM_VMV_SHIFT_VALUE_MAP.ETPPC0[0x111d]=0x492492492492492492492492000000000000492492492492
ETPPC_OUTLIF_ORIENTATION_MAPPING.ETPPC0[0x81e]=8
ETPPC_PARITY_ERR_CNT.ETPPC0[0x98]=0
ETPPC_PAR_ERR_MEM_MASK.ETPPC0[0xa0]=0x7f
ETPPC_PCMI_0.ETPPC0[0xb0]=0x3b9aca00
ETPPC_PCMI_1.ETPPC0[0xb3]=0x3b9aca00
ETPPC_PCMI_2.ETPPC0[0xb6]=0x3b9aca00
ETPPC_PCMI_3.ETPPC0[0xb9]=0x3b9aca00
ETPPC_PCMI_4.ETPPC0[0xbc]=0x3b9aca00
ETPPC_PCMI_0_S.ETPPC0[0xb1]=0
ETPPC_PCMI_0_T.ETPPC0[0xb2]=0
ETPPC_PCMI_1_S.ETPPC0[0xb4]=0
ETPPC_PCMI_1_T.ETPPC0[0xb5]=0
ETPPC_PCMI_2_S.ETPPC0[0xb7]=0
ETPPC_PCMI_2_T.ETPPC0[0xb8]=0
ETPPC_PCMI_3_S.ETPPC0[0xba]=0
ETPPC_PCMI_3_T.ETPPC0[0xbb]=0
ETPPC_PCMI_4_S.ETPPC0[0xbd]=0
ETPPC_PCMI_4_T.ETPPC0[0xbe]=0
ETPPC_PHP_MAP_FWD_CODE.ETPPC0[0x8bd]=0xfff143fff102
ETPPC_QOS_MODEL_MAPPING_TABLE.ETPPC0[0x12b]=0x400702dbd
ETPPC_REG_0300.ETPPC0[0x300]=0x1fe1100
ETPPC_REG_0301.ETPPC0[0x301]=0x200800000000520000002001dc0016000000000000000012880e4d0005c296c0000000e000000000000000e10000604000000000000000000000000000000000000000000000000000000000000000
ETPPC_REG_0315.ETPPC0[0x315]=1
ETPPC_REG_0320.ETPPC0[0x320]=0x1521000
ETPPC_REG_0321.ETPPC0[0x321]=0x5751b0100be9f60000000101080a4c158422a41d0c4a0101050a72635cdb7267af4c3fc100000000000000000049396245a88734379d1300000000000000000000000000000000000000000000000000
ETPPC_REG_0330.ETPPC0[0x330]=0x17661200
ETPPC_REG_0331.ETPPC0[0x331]=0x4000000002001000ffff0200070001fa
ETPPC_REG_0335.ETPPC0[0x335]=1
ETPPC_REG_0345.ETPPC0[0x345]=1
ETPPC_REG_00C2.ETPPC0[0xc2]=0x10
ETPPC_REG_00C5.ETPPC0[0xc5]=0x2d6
ETPPC_REG_00C6.ETPPC0[0xc6]=0x53
ETPPC_REG_00E8.ETPPC0[0xe8]=0x88a88100
ETPPC_REG_00E9.ETPPC0[0xe9]=0x9100
ETPPC_REG_00EB.ETPPC0[0xeb]=0
ETPPC_REG_00EE.ETPPC0[0xee]=0x105557
ETPPC_REG_00F0.ETPPC0[0xf0]=0
ETPPC_REG_00F1.ETPPC0[0xf1]=0
ETPPC_REG_00F2.ETPPC0[0xf2]=0
ETPPC_RESERVED_MTCD.ETPPC0[0xae]=0x30
ETPPC_RESERVED_MTCP.ETPPC0[0xad]=0x300000600000000
ETPPC_RESERVED_SPARE_0.ETPPC0[0x90]=0xffffffff
ETPPC_RESERVED_SPARE_1.ETPPC0[0x91]=0xffffffff
ETPPC_RESERVED_SPARE_2.ETPPC0[0x92]=0
ETPPC_RESERVED_SPARE_3.ETPPC0[0x93]=0
ETPPC_SBUS_BROADCAST_ID.ETPPC0[0x86]=0x7ff
ETPPC_SBUS_LAST_IN_CHAIN.ETPPC0[0x87]=0
ETPPC_SPECIAL_CLOCK_CONTROLS.ETPPC0[0xc1]=2
ETPPC_STATISTICS_FWD_CODE_TO_PROTOCOL_TYPE.ETPPC0[0x740]=0
ETPPC_XOR_INIT_DONE.ETPPC0[0x103]=0xf
EVNT_ECC_1B_ERR_CNT.EVNT0[0x94]=0
EVNT_ECC_2B_ERR_CNT.EVNT0[0x96]=0
EVNT_ECC_ERR_1B_MONITOR_MEM_MASK.EVNT0[0x9a]=0x7ffffffffff
EVNT_ECC_ERR_2B_MONITOR_MEM_MASK.EVNT0[0x9c]=0x7ffffffffff
EVNT_ECC_INTERRUPT_REGISTER.EVNT0[0x7]=0
EVNT_ECC_INTERRUPT_REGISTER_MASK.EVNT0[0x17]=0
EVNT_ECC_INTERRUPT_REGISTER_TEST.EVNT0[0x1f]=0
EVNT_ENABLE_DYNAMIC_MEMORY_ACCESS.EVNT0[0x84]=1
EVNT_EVENTOR_INTERRUPT_MASK_REGISTER.EVNT0[0x101]=0
EVNT_EVENTOR_INTERRUPT_REGISTER.EVNT0[0x100]=0
EVNT_EVENTOR_INTERRUPT_REGISTER_TEST.EVNT0[0x102]=0
EVNT_EVENTOR_INT_BIT_TRIGGER.EVNT0[0x103]=0
EVNT_EVPCK_HEADER_STACK(0).EVNT0[0x156]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(1).EVNT0[0x157]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(2).EVNT0[0x158]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(3).EVNT0[0x159]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(4).EVNT0[0x15a]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(5).EVNT0[0x15b]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(6).EVNT0[0x15c]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(7).EVNT0[0x15d]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(8).EVNT0[0x15e]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(9).EVNT0[0x15f]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(10).EVNT0[0x160]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(11).EVNT0[0x161]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(12).EVNT0[0x162]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(13).EVNT0[0x163]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(14).EVNT0[0x164]=0x1000000000000
EVNT_EVPCK_HEADER_STACK(15).EVNT0[0x165]=0x1000000000000
EVNT_EVPCK_HEADER_STACK_SIZE(0).EVNT0[0x167]=0
EVNT_EVPCK_HEADER_STACK_SIZE(1).EVNT0[0x168]=0
EVNT_EVPCK_HEADER_STACK_SIZE(2).EVNT0[0x169]=0
EVNT_EVPCK_HEADER_STACK_SIZE(3).EVNT0[0x16a]=0
EVNT_EVPCK_HEADER_STACK_SIZE(4).EVNT0[0x16b]=0
EVNT_EVPCK_HEADER_STACK_SIZE(5).EVNT0[0x16c]=0
EVNT_EVPCK_HEADER_STACK_SIZE(6).EVNT0[0x16d]=0
EVNT_EVPCK_HEADER_STACK_SIZE(7).EVNT0[0x16e]=0
EVNT_EVPCK_HEADER_STACK_SIZE(8).EVNT0[0x16f]=0
EVNT_EVPCK_HEADER_STACK_SIZE(9).EVNT0[0x170]=0
EVNT_EVPCK_HEADER_STACK_SIZE(10).EVNT0[0x171]=0
EVNT_EVPCK_HEADER_STACK_SIZE(11).EVNT0[0x172]=0
EVNT_EVPCK_HEADER_STACK_SIZE(12).EVNT0[0x173]=0
EVNT_EVPCK_HEADER_STACK_SIZE(13).EVNT0[0x174]=0
EVNT_EVPCK_HEADER_STACK_SIZE(14).EVNT0[0x175]=0
EVNT_EVPCK_HEADER_STACK_SIZE(15).EVNT0[0x176]=0
EVNT_EVPCK_HEADER_TIMESTAMP_SEL.EVNT0[0x166]=0
EVNT_EXT_BLOCKS_SELECTOR_CFG.EVNT0[0x105]=0x128398a418820
EVNT_GTIMER_CONFIGURATION.EVNT0[0x89]=0
EVNT_GTIMER_CYCLE.EVNT0[0x88]=0x3b9aca00
EVNT_INDIRECT_COMMAND.EVNT0[0x80]=0xe000002
EVNT_INDIRECT_COMMAND_ADDRESS.EVNT0[0x81]=0xca0100
EVNT_INDIRECT_COMMAND_RD_DATA.EVNT0[0x60]=0x39983828129d087fffffffdf
EVNT_INDIRECT_COMMAND_WR_DATA.EVNT0[0x20]=0
EVNT_INDIRECT_FORCE_BUBBLE.EVNT0[0x83]=0x20019
EVNT_INTERNAL_HOST_EVENT_TRIGGER.EVNT0[0x11f]=0
EVNT_INTERNAL_TOD_EVENT_VALUE(0).EVNT0[0x11a]=0
EVNT_INTERNAL_TOD_EVENT_VALUE(1).EVNT0[0x11b]=0
EVNT_INTERNAL_TOD_EVENT_VALUE(2).EVNT0[0x11c]=0
EVNT_INTERNAL_TOD_EVENT_VALUE(3).EVNT0[0x11d]=0
EVNT_INTERNAL_TOD_EVENT_VALUE(4).EVNT0[0x11e]=0
EVNT_INTERRUPT_MASK_REGISTER.EVNT0[0x10]=0
EVNT_INTERRUPT_REGISTER.EVNT0[0x0]=0
EVNT_INTERRUPT_REGISTER_TEST.EVNT0[0x18]=0
EVNT_MACT_EVENTOR_DMA_SEL.EVNT0[0x2ea]=0
EVNT_MAIN_MEM_BANK_TYPE(0).EVNT0[0x2e2]=1
EVNT_MAIN_MEM_BANK_TYPE(1).EVNT0[0x2e3]=1
EVNT_MAIN_MEM_BANK_TYPE(2).EVNT0[0x2e4]=1
EVNT_MAIN_MEM_BANK_TYPE(3).EVNT0[0x2e5]=1
EVNT_MAIN_MEM_BANK_TYPE(4).EVNT0[0x2e6]=1
EVNT_MAIN_MEM_BANK_TYPE(5).EVNT0[0x2e7]=1
EVNT_MAIN_MEM_BANK_TYPE(6).EVNT0[0x2e8]=1
EVNT_MAIN_MEM_BANK_TYPE(7).EVNT0[0x2e9]=1
EVNT_MAIN_MEM_RX_PTRS(0).EVNT0[0x2a2]=0
EVNT_MAIN_MEM_RX_PTRS(1).EVNT0[0x2a3]=0
EVNT_MAIN_MEM_RX_PTRS(2).EVNT0[0x2a4]=0
EVNT_MAIN_MEM_RX_PTRS(3).EVNT0[0x2a5]=0
EVNT_MAIN_MEM_RX_PTRS(4).EVNT0[0x2a6]=0
EVNT_MAIN_MEM_RX_PTRS(5).EVNT0[0x2a7]=0
EVNT_MAIN_MEM_RX_PTRS(6).EVNT0[0x2a8]=0
EVNT_MAIN_MEM_RX_PTRS(7).EVNT0[0x2a9]=0
EVNT_MAIN_MEM_RX_PTRS(8).EVNT0[0x2aa]=0
EVNT_MAIN_MEM_RX_PTRS(9).EVNT0[0x2ab]=0
EVNT_MAIN_MEM_RX_PTRS(10).EVNT0[0x2ac]=0
EVNT_MAIN_MEM_RX_PTRS(11).EVNT0[0x2ad]=0
EVNT_MAIN_MEM_RX_PTRS(12).EVNT0[0x2ae]=0
EVNT_MAIN_MEM_RX_PTRS(13).EVNT0[0x2af]=0
EVNT_MAIN_MEM_RX_PTRS(14).EVNT0[0x2b0]=0
EVNT_MAIN_MEM_RX_PTRS(15).EVNT0[0x2b1]=0
EVNT_MAIN_MEM_RX_PTRS(16).EVNT0[0x2b2]=0
EVNT_MAIN_MEM_RX_PTRS(17).EVNT0[0x2b3]=0
EVNT_MAIN_MEM_RX_PTRS(18).EVNT0[0x2b4]=0
EVNT_MAIN_MEM_RX_PTRS(19).EVNT0[0x2b5]=0
EVNT_MAIN_MEM_RX_PTRS(20).EVNT0[0x2b6]=0
EVNT_MAIN_MEM_RX_PTRS(21).EVNT0[0x2b7]=0
EVNT_MAIN_MEM_RX_PTRS(22).EVNT0[0x2b8]=0
EVNT_MAIN_MEM_RX_PTRS(23).EVNT0[0x2b9]=0
EVNT_MAIN_MEM_RX_PTRS(24).EVNT0[0x2ba]=0
EVNT_MAIN_MEM_RX_PTRS(25).EVNT0[0x2bb]=0
EVNT_MAIN_MEM_RX_PTRS(26).EVNT0[0x2bc]=0
EVNT_MAIN_MEM_RX_PTRS(27).EVNT0[0x2bd]=0
EVNT_MAIN_MEM_RX_PTRS(28).EVNT0[0x2be]=0
EVNT_MAIN_MEM_RX_PTRS(29).EVNT0[0x2bf]=0
EVNT_MAIN_MEM_RX_PTRS(30).EVNT0[0x2c0]=0
EVNT_MAIN_MEM_RX_PTRS(31).EVNT0[0x2c1]=0
EVNT_MAIN_MEM_TX_PTRS(0).EVNT0[0x2c2]=0
EVNT_MAIN_MEM_TX_PTRS(1).EVNT0[0x2c3]=0
EVNT_MAIN_MEM_TX_PTRS(2).EVNT0[0x2c4]=0
EVNT_MAIN_MEM_TX_PTRS(3).EVNT0[0x2c5]=0
EVNT_MAIN_MEM_TX_PTRS(4).EVNT0[0x2c6]=0
EVNT_MAIN_MEM_TX_PTRS(5).EVNT0[0x2c7]=0
EVNT_MAIN_MEM_TX_PTRS(6).EVNT0[0x2c8]=0
EVNT_MAIN_MEM_TX_PTRS(7).EVNT0[0x2c9]=0
EVNT_MAIN_MEM_TX_PTRS(8).EVNT0[0x2ca]=0
EVNT_MAIN_MEM_TX_PTRS(9).EVNT0[0x2cb]=0
EVNT_MAIN_MEM_TX_PTRS(10).EVNT0[0x2cc]=0
EVNT_MAIN_MEM_TX_PTRS(11).EVNT0[0x2cd]=0
EVNT_MAIN_MEM_TX_PTRS(12).EVNT0[0x2ce]=0
EVNT_MAIN_MEM_TX_PTRS(13).EVNT0[0x2cf]=0
EVNT_MAIN_MEM_TX_PTRS(14).EVNT0[0x2d0]=0
EVNT_MAIN_MEM_TX_PTRS(15).EVNT0[0x2d1]=0
EVNT_MAIN_MEM_TX_PTRS(16).EVNT0[0x2d2]=0
EVNT_MAIN_MEM_TX_PTRS(17).EVNT0[0x2d3]=0
EVNT_MAIN_MEM_TX_PTRS(18).EVNT0[0x2d4]=0
EVNT_MAIN_MEM_TX_PTRS(19).EVNT0[0x2d5]=0
EVNT_MAIN_MEM_TX_PTRS(20).EVNT0[0x2d6]=0
EVNT_MAIN_MEM_TX_PTRS(21).EVNT0[0x2d7]=0
EVNT_MAIN_MEM_TX_PTRS(22).EVNT0[0x2d8]=0
EVNT_MAIN_MEM_TX_PTRS(23).EVNT0[0x2d9]=0
EVNT_MAIN_MEM_TX_PTRS(24).EVNT0[0x2da]=0
EVNT_MAIN_MEM_TX_PTRS(25).EVNT0[0x2db]=0
EVNT_MAIN_MEM_TX_PTRS(26).EVNT0[0x2dc]=0
EVNT_MAIN_MEM_TX_PTRS(27).EVNT0[0x2dd]=0
EVNT_MAIN_MEM_TX_PTRS(28).EVNT0[0x2de]=0
EVNT_MAIN_MEM_TX_PTRS(29).EVNT0[0x2df]=0
EVNT_MAIN_MEM_TX_PTRS(30).EVNT0[0x2e0]=0
EVNT_MAIN_MEM_TX_PTRS(31).EVNT0[0x2e1]=0
EVNT_PIPE_SELECTOR.EVNT0[0x104]=0
EVNT_REG_0041.EVNT0[0x41]=0
EVNT_REG_0098.EVNT0[0x98]=0
EVNT_REG_00A0.EVNT0[0xa0]=0
EVNT_REG_00C2.EVNT0[0xc2]=0x10
EVNT_REG_00C5.EVNT0[0xc5]=0x78006
EVNT_RESERVED_MTCD.EVNT0[0xae]=0x30
EVNT_RESERVED_MTCP.EVNT0[0xad]=0x300000600000000
EVNT_RESERVED_SPARE_0.EVNT0[0x90]=0xffffffff
EVNT_RESERVED_SPARE_1.EVNT0[0x91]=0xffffffff
EVNT_RESERVED_SPARE_2.EVNT0[0x92]=0
EVNT_RESERVED_SPARE_3.EVNT0[0x93]=0
EVNT_RX_CMIC_FLEX_CMD.EVNT0[0x121]=0xffffffff0000000000000000
EVNT_RX_EVPCK_HEADER_STACK_SIZE.EVNT0[0x177]=0x10
EVNT_RX_HANDLER_CMIC_STMS_STATE.EVNT0[0x114]=0
EVNT_RX_MAIN_BUFFER_TH.EVNT0[0x29f]=0xc86432190c86432190c86432190c86432190
EVNT_RX_MAIN_BUFFER_TIMEOUT.EVNT0[0x2a1]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
EVNT_RX_SEQ_CHECK.EVNT0[0x178]=0
EVNT_RX_TO_TX_BUFFER.EVNT0[0x17a]=0
EVNT_SBUS_BROADCAST_ID.EVNT0[0x86]=0x7ff
EVNT_SBUS_LAST_IN_CHAIN.EVNT0[0x87]=0
EVNT_SHARED_CMIC_ENG_POOL.EVNT0[0x117]=0
EVNT_SPECIAL_CLOCK_CONTROLS.EVNT0[0xc1]=2
EVNT_TRANSMIT_ERR_HEADER_STACK(0).EVNT0[0x143]=0
EVNT_TRANSMIT_ERR_HEADER_STACK(1).EVNT0[0x144]=0
EVNT_TRANSMIT_ERR_HEADER_STACK_SIZE.EVNT0[0x145]=0
EVNT_TRANSMIT_HEADER_STACK(0).EVNT0[0x123]=0
EVNT_TRANSMIT_HEADER_STACK(1).EVNT0[0x124]=0
EVNT_TRANSMIT_HEADER_STACK(2).EVNT0[0x125]=0
EVNT_TRANSMIT_HEADER_STACK(3).EVNT0[0x126]=0
EVNT_TRANSMIT_HEADER_STACK(4).EVNT0[0x127]=0
EVNT_TRANSMIT_HEADER_STACK(5).EVNT0[0x128]=0
EVNT_TRANSMIT_HEADER_STACK(6).EVNT0[0x129]=0
EVNT_TRANSMIT_HEADER_STACK(7).EVNT0[0x12a]=0
EVNT_TRANSMIT_HEADER_STACK(8).EVNT0[0x12b]=0
EVNT_TRANSMIT_HEADER_STACK(9).EVNT0[0x12c]=0
EVNT_TRANSMIT_HEADER_STACK(10).EVNT0[0x12d]=0
EVNT_TRANSMIT_HEADER_STACK(11).EVNT0[0x12e]=0
EVNT_TRANSMIT_HEADER_STACK(12).EVNT0[0x12f]=0
EVNT_TRANSMIT_HEADER_STACK(13).EVNT0[0x130]=0
EVNT_TRANSMIT_HEADER_STACK(14).EVNT0[0x131]=0
EVNT_TRANSMIT_HEADER_STACK(15).EVNT0[0x132]=0
EVNT_TRANSMIT_HEADER_STACK(16).EVNT0[0x133]=0
EVNT_TRANSMIT_HEADER_STACK(17).EVNT0[0x134]=0
EVNT_TRANSMIT_HEADER_STACK(18).EVNT0[0x135]=0
EVNT_TRANSMIT_HEADER_STACK(19).EVNT0[0x136]=0
EVNT_TRANSMIT_HEADER_STACK(20).EVNT0[0x137]=0
EVNT_TRANSMIT_HEADER_STACK(21).EVNT0[0x138]=0
EVNT_TRANSMIT_HEADER_STACK(22).EVNT0[0x139]=0
EVNT_TRANSMIT_HEADER_STACK(23).EVNT0[0x13a]=0
EVNT_TRANSMIT_HEADER_STACK(24).EVNT0[0x13b]=0
EVNT_TRANSMIT_HEADER_STACK(25).EVNT0[0x13c]=0
EVNT_TRANSMIT_HEADER_STACK(26).EVNT0[0x13d]=0
EVNT_TRANSMIT_HEADER_STACK(27).EVNT0[0x13e]=0
EVNT_TRANSMIT_HEADER_STACK(28).EVNT0[0x13f]=0
EVNT_TRANSMIT_HEADER_STACK(29).EVNT0[0x140]=0
EVNT_TRANSMIT_HEADER_STACK(30).EVNT0[0x141]=0
EVNT_TRANSMIT_HEADER_STACK(31).EVNT0[0x142]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(0).EVNT0[0x146]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(1).EVNT0[0x147]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(2).EVNT0[0x148]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(3).EVNT0[0x149]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(4).EVNT0[0x14a]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(5).EVNT0[0x14b]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(6).EVNT0[0x14c]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(7).EVNT0[0x14d]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(8).EVNT0[0x14e]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(9).EVNT0[0x14f]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(10).EVNT0[0x150]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(11).EVNT0[0x151]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(12).EVNT0[0x152]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(13).EVNT0[0x153]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(14).EVNT0[0x154]=0
EVNT_TRANSMIT_HEADER_STACK_SIZE(15).EVNT0[0x155]=0
EVNT_TX_1588_TOD_SAMP.EVNT0[0x118]=0xfa227cc944c8
EVNT_TX_1588_TOD_SAMP_SRC_SEL.EVNT0[0x119]=0
EVNT_TX_CMIC_FLEX_CMD.EVNT0[0x120]=0xffffffff0000000000000000
EVNT_TX_CONTEXT_IS_FIFO_DMA.EVNT0[0x179]=0
EVNT_TX_ENG_CLEAR_BUFFER_MEM_ERR.EVNT0[0x10a]=0
EVNT_TX_ENG_CONTEXT_PRIORITY_RR_VEC.EVNT0[0x116]=0xff
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(0).EVNT0[0x18b]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(1).EVNT0[0x18c]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(2).EVNT0[0x18d]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(3).EVNT0[0x18e]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(4).EVNT0[0x18f]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(5).EVNT0[0x190]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(6).EVNT0[0x191]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(7).EVNT0[0x192]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(8).EVNT0[0x193]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(9).EVNT0[0x194]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(10).EVNT0[0x195]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(11).EVNT0[0x196]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(12).EVNT0[0x197]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(13).EVNT0[0x198]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(14).EVNT0[0x199]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE(15).EVNT0[0x19a]=0x640
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(0).EVNT0[0x17b]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(1).EVNT0[0x17c]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(2).EVNT0[0x17d]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(3).EVNT0[0x17e]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(4).EVNT0[0x17f]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(5).EVNT0[0x180]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(6).EVNT0[0x181]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(7).EVNT0[0x182]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(8).EVNT0[0x183]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(9).EVNT0[0x184]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(10).EVNT0[0x185]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(11).EVNT0[0x186]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(12).EVNT0[0x187]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(13).EVNT0[0x188]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(14).EVNT0[0x189]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE(15).EVNT0[0x18a]=0
EVNT_TX_ENG_CONTEXT_QUEUE_TYPE.EVNT0[0x122]=0xffff
EVNT_TX_ENG_DUMMY_PATTERN.EVNT0[0x29c]=0xffffffff
EVNT_TX_ENG_ERR_CONFIG.EVNT0[0x29d]=0
EVNT_TX_ENG_EVENTS_CNT(0).EVNT0[0x19b]=0
EVNT_TX_ENG_EVENTS_CNT(1).EVNT0[0x19c]=0
EVNT_TX_ENG_EVENTS_CNT(2).EVNT0[0x19d]=0
EVNT_TX_ENG_EVENTS_CNT(3).EVNT0[0x19e]=0
EVNT_TX_ENG_EVENTS_CNT(4).EVNT0[0x19f]=0
EVNT_TX_ENG_EVENTS_CNT(5).EVNT0[0x1a0]=0
EVNT_TX_ENG_EVENTS_CNT(6).EVNT0[0x1a1]=0
EVNT_TX_ENG_EVENTS_CNT(7).EVNT0[0x1a2]=0
EVNT_TX_ENG_EVENTS_CNT(8).EVNT0[0x1a3]=0
EVNT_TX_ENG_EVENTS_CNT(9).EVNT0[0x1a4]=0
EVNT_TX_ENG_EVENTS_CNT(10).EVNT0[0x1a5]=0
EVNT_TX_ENG_EVENTS_CNT(11).EVNT0[0x1a6]=0
EVNT_TX_ENG_EVENTS_CNT(12).EVNT0[0x1a7]=0
EVNT_TX_ENG_EVENTS_CNT(13).EVNT0[0x1a8]=0
EVNT_TX_ENG_EVENTS_CNT(14).EVNT0[0x1a9]=0
EVNT_TX_ENG_EVENTS_CNT(15).EVNT0[0x1aa]=0
EVNT_TX_ENG_EVENTS_CNT(16).EVNT0[0x1ab]=0
EVNT_TX_ENG_EVENTS_CNT(17).EVNT0[0x1ac]=0
EVNT_TX_ENG_EVENTS_CNT(18).EVNT0[0x1ad]=0
EVNT_TX_ENG_EVENTS_CNT(19).EVNT0[0x1ae]=0
EVNT_TX_ENG_EVENTS_CNT(20).EVNT0[0x1af]=0
EVNT_TX_ENG_EVENTS_CNT(21).EVNT0[0x1b0]=0
EVNT_TX_ENG_EVENTS_CNT(22).EVNT0[0x1b1]=0
EVNT_TX_ENG_EVENTS_CNT(23).EVNT0[0x1b2]=0
EVNT_TX_ENG_EVENTS_CNT(24).EVNT0[0x1b3]=0
EVNT_TX_ENG_EVENTS_CNT(25).EVNT0[0x1b4]=0
EVNT_TX_ENG_EVENTS_CNT(26).EVNT0[0x1b5]=0
EVNT_TX_ENG_EVENTS_CNT(27).EVNT0[0x1b6]=0
EVNT_TX_ENG_EVENTS_CNT(28).EVNT0[0x1b7]=0
EVNT_TX_ENG_EVENTS_CNT(29).EVNT0[0x1b8]=0
EVNT_TX_ENG_EVENTS_CNT(30).EVNT0[0x1b9]=0
EVNT_TX_ENG_EVENTS_CNT(31).EVNT0[0x1ba]=0
EVNT_TX_ENG_EVENTS_CNT(32).EVNT0[0x1bb]=0
EVNT_TX_ENG_EVENTS_CNT(33).EVNT0[0x1bc]=0
EVNT_TX_ENG_EVENTS_CNT(34).EVNT0[0x1bd]=0
EVNT_TX_ENG_EVENTS_CNT(35).EVNT0[0x1be]=0
EVNT_TX_ENG_EVENTS_CNT(36).EVNT0[0x1bf]=0
EVNT_TX_ENG_EVENTS_CNT(37).EVNT0[0x1c0]=0
EVNT_TX_ENG_EVENTS_CNT(38).EVNT0[0x1c1]=0
EVNT_TX_ENG_EVENTS_CNT(39).EVNT0[0x1c2]=0
EVNT_TX_ENG_EVENTS_CNT(40).EVNT0[0x1c3]=0
EVNT_TX_ENG_EVENTS_CNT(41).EVNT0[0x1c4]=0
EVNT_TX_ENG_EVENTS_CNT(42).EVNT0[0x1c5]=0
EVNT_TX_ENG_EVENTS_CNT(43).EVNT0[0x1c6]=0
EVNT_TX_ENG_EVENTS_CNT(44).EVNT0[0x1c7]=0
EVNT_TX_ENG_EVENTS_CNT(45).EVNT0[0x1c8]=0
EVNT_TX_ENG_EVENTS_CNT(46).EVNT0[0x1c9]=0
EVNT_TX_ENG_EVENTS_CNT(47).EVNT0[0x1ca]=0
EVNT_TX_ENG_EVENTS_CNT(48).EVNT0[0x1cb]=0
EVNT_TX_ENG_EVENTS_CNT(49).EVNT0[0x1cc]=0
EVNT_TX_ENG_EVENTS_CNT(50).EVNT0[0x1cd]=0
EVNT_TX_ENG_EVENTS_CNT(51).EVNT0[0x1ce]=0
EVNT_TX_ENG_EVENTS_CNT(52).EVNT0[0x1cf]=0
EVNT_TX_ENG_EVENTS_CNT(53).EVNT0[0x1d0]=0
EVNT_TX_ENG_EVENTS_CNT(54).EVNT0[0x1d1]=0
EVNT_TX_ENG_EVENTS_CNT(55).EVNT0[0x1d2]=0
EVNT_TX_ENG_EVENTS_CNT(56).EVNT0[0x1d3]=0
EVNT_TX_ENG_EVENTS_CNT(57).EVNT0[0x1d4]=0
EVNT_TX_ENG_EVENTS_CNT(58).EVNT0[0x1d5]=0
EVNT_TX_ENG_EVENTS_CNT(59).EVNT0[0x1d6]=0
EVNT_TX_ENG_EVENTS_CNT(60).EVNT0[0x1d7]=0
EVNT_TX_ENG_EVENTS_CNT(61).EVNT0[0x1d8]=0
EVNT_TX_ENG_EVENTS_CNT(62).EVNT0[0x1d9]=0
EVNT_TX_ENG_EVENTS_CNT(63).EVNT0[0x1da]=0
EVNT_TX_ENG_EVENTS_CNT(64).EVNT0[0x1db]=0
EVNT_TX_ENG_EVENTS_CNT(65).EVNT0[0x1dc]=0
EVNT_TX_ENG_EVENTS_CNT(66).EVNT0[0x1dd]=0
EVNT_TX_ENG_EVENTS_CNT(67).EVNT0[0x1de]=0
EVNT_TX_ENG_EVENTS_CNT(68).EVNT0[0x1df]=0
EVNT_TX_ENG_EVENTS_CNT(69).EVNT0[0x1e0]=0
EVNT_TX_ENG_EVENTS_CNT(70).EVNT0[0x1e1]=0
EVNT_TX_ENG_EVENTS_CNT(71).EVNT0[0x1e2]=0
EVNT_TX_ENG_EVENTS_CNT(72).EVNT0[0x1e3]=0
EVNT_TX_ENG_EVENTS_CNT(73).EVNT0[0x1e4]=0
EVNT_TX_ENG_EVENTS_CNT(74).EVNT0[0x1e5]=0
EVNT_TX_ENG_EVENTS_CNT(75).EVNT0[0x1e6]=0
EVNT_TX_ENG_EVENTS_CNT(76).EVNT0[0x1e7]=0
EVNT_TX_ENG_EVENTS_CNT(77).EVNT0[0x1e8]=0
EVNT_TX_ENG_EVENTS_CNT(78).EVNT0[0x1e9]=0
EVNT_TX_ENG_EVENTS_CNT(79).EVNT0[0x1ea]=0
EVNT_TX_ENG_EVENTS_CNT(80).EVNT0[0x1eb]=0
EVNT_TX_ENG_EVENTS_CNT(81).EVNT0[0x1ec]=0
EVNT_TX_ENG_EVENTS_CNT(82).EVNT0[0x1ed]=0
EVNT_TX_ENG_EVENTS_CNT(83).EVNT0[0x1ee]=0
EVNT_TX_ENG_EVENTS_CNT(84).EVNT0[0x1ef]=0
EVNT_TX_ENG_EVENTS_CNT(85).EVNT0[0x1f0]=0
EVNT_TX_ENG_EVENTS_CNT(86).EVNT0[0x1f1]=0
EVNT_TX_ENG_EVENTS_CNT(87).EVNT0[0x1f2]=0
EVNT_TX_ENG_EVENTS_CNT(88).EVNT0[0x1f3]=0
EVNT_TX_ENG_EVENTS_CNT(89).EVNT0[0x1f4]=0
EVNT_TX_ENG_EVENTS_CNT(90).EVNT0[0x1f5]=0
EVNT_TX_ENG_EVENTS_CNT(91).EVNT0[0x1f6]=0
EVNT_TX_ENG_EVENTS_CNT(92).EVNT0[0x1f7]=0
EVNT_TX_ENG_EVENTS_CNT(93).EVNT0[0x1f8]=0
EVNT_TX_ENG_EVENTS_CNT(94).EVNT0[0x1f9]=0
EVNT_TX_ENG_EVENTS_CNT(95).EVNT0[0x1fa]=0
EVNT_TX_ENG_EVENTS_CNT(96).EVNT0[0x1fb]=0
EVNT_TX_ENG_EVENTS_CNT(97).EVNT0[0x1fc]=0
EVNT_TX_ENG_EVENTS_CNT(98).EVNT0[0x1fd]=0
EVNT_TX_ENG_EVENTS_CNT(99).EVNT0[0x1fe]=0
EVNT_TX_ENG_EVENTS_CNT(100).EVNT0[0x1ff]=0
EVNT_TX_ENG_EVENTS_CNT(101).EVNT0[0x200]=0
EVNT_TX_ENG_EVENTS_CNT(102).EVNT0[0x201]=0
EVNT_TX_ENG_EVENTS_CNT(103).EVNT0[0x202]=0
EVNT_TX_ENG_EVENTS_CNT(104).EVNT0[0x203]=0
EVNT_TX_ENG_EVENTS_CNT(105).EVNT0[0x204]=0
EVNT_TX_ENG_EVENTS_CNT(106).EVNT0[0x205]=0
EVNT_TX_ENG_EVENTS_CNT(107).EVNT0[0x206]=0
EVNT_TX_ENG_EVENTS_CNT(108).EVNT0[0x207]=0
EVNT_TX_ENG_EVENTS_CNT(109).EVNT0[0x208]=0
EVNT_TX_ENG_EVENTS_CNT(110).EVNT0[0x209]=0
EVNT_TX_ENG_EVENTS_CNT(111).EVNT0[0x20a]=0
EVNT_TX_ENG_EVENTS_CNT(112).EVNT0[0x20b]=0
EVNT_TX_ENG_EVENTS_CNT(113).EVNT0[0x20c]=0
EVNT_TX_ENG_EVENTS_CNT(114).EVNT0[0x20d]=0
EVNT_TX_ENG_EVENTS_CNT(115).EVNT0[0x20e]=0
EVNT_TX_ENG_EVENTS_CNT(116).EVNT0[0x20f]=0
EVNT_TX_ENG_EVENTS_CNT(117).EVNT0[0x210]=0
EVNT_TX_ENG_EVENTS_CNT(118).EVNT0[0x211]=0
EVNT_TX_ENG_EVENTS_CNT(119).EVNT0[0x212]=0
EVNT_TX_ENG_EVENTS_CNT(120).EVNT0[0x213]=0
EVNT_TX_ENG_EVENTS_CNT(121).EVNT0[0x214]=0
EVNT_TX_ENG_EVENTS_CNT(122).EVNT0[0x215]=0
EVNT_TX_ENG_EVENTS_CNT(123).EVNT0[0x216]=0
EVNT_TX_ENG_EVENTS_CNT(124).EVNT0[0x217]=0
EVNT_TX_ENG_EVENTS_CNT(125).EVNT0[0x218]=0
EVNT_TX_ENG_EVENTS_CNT(126).EVNT0[0x219]=0
EVNT_TX_ENG_EVENTS_CNT(127).EVNT0[0x21a]=0
EVNT_TX_ENG_EVENTS_CNT(128).EVNT0[0x21b]=0
EVNT_TX_ENG_EVENTS_CNT(129).EVNT0[0x21c]=0
EVNT_TX_ENG_EVENTS_CNT(130).EVNT0[0x21d]=0
EVNT_TX_ENG_EVENTS_CNT(131).EVNT0[0x21e]=0
EVNT_TX_ENG_EVENTS_CNT(132).EVNT0[0x21f]=0
EVNT_TX_ENG_EVENTS_CNT(133).EVNT0[0x220]=0
EVNT_TX_ENG_EVENTS_CNT(134).EVNT0[0x221]=0
EVNT_TX_ENG_EVENTS_CNT(135).EVNT0[0x222]=0
EVNT_TX_ENG_EVENTS_CNT(136).EVNT0[0x223]=0
EVNT_TX_ENG_EVENTS_CNT(137).EVNT0[0x224]=0
EVNT_TX_ENG_EVENTS_CNT(138).EVNT0[0x225]=0
EVNT_TX_ENG_EVENTS_CNT(139).EVNT0[0x226]=0
EVNT_TX_ENG_EVENTS_CNT(140).EVNT0[0x227]=0
EVNT_TX_ENG_EVENTS_CNT(141).EVNT0[0x228]=0
EVNT_TX_ENG_EVENTS_CNT(142).EVNT0[0x229]=0
EVNT_TX_ENG_EVENTS_CNT(143).EVNT0[0x22a]=0
EVNT_TX_ENG_EVENTS_CNT(144).EVNT0[0x22b]=0
EVNT_TX_ENG_EVENTS_CNT(145).EVNT0[0x22c]=0
EVNT_TX_ENG_EVENTS_CNT(146).EVNT0[0x22d]=0
EVNT_TX_ENG_EVENTS_CNT(147).EVNT0[0x22e]=0
EVNT_TX_ENG_EVENTS_CNT(148).EVNT0[0x22f]=0
EVNT_TX_ENG_EVENTS_CNT(149).EVNT0[0x230]=0
EVNT_TX_ENG_EVENTS_CNT(150).EVNT0[0x231]=0
EVNT_TX_ENG_EVENTS_CNT(151).EVNT0[0x232]=0
EVNT_TX_ENG_EVENTS_CNT(152).EVNT0[0x233]=0
EVNT_TX_ENG_EVENTS_CNT(153).EVNT0[0x234]=0
EVNT_TX_ENG_EVENTS_CNT(154).EVNT0[0x235]=0
EVNT_TX_ENG_EVENTS_CNT(155).EVNT0[0x236]=0
EVNT_TX_ENG_EVENTS_CNT(156).EVNT0[0x237]=0
EVNT_TX_ENG_EVENTS_CNT(157).EVNT0[0x238]=0
EVNT_TX_ENG_EVENTS_CNT(158).EVNT0[0x239]=0
EVNT_TX_ENG_EVENTS_CNT(159).EVNT0[0x23a]=0
EVNT_TX_ENG_EVENTS_CNT(160).EVNT0[0x23b]=0
EVNT_TX_ENG_EVENTS_CNT(161).EVNT0[0x23c]=0
EVNT_TX_ENG_EVENTS_CNT(162).EVNT0[0x23d]=0
EVNT_TX_ENG_EVENTS_CNT(163).EVNT0[0x23e]=0
EVNT_TX_ENG_EVENTS_CNT(164).EVNT0[0x23f]=0
EVNT_TX_ENG_EVENTS_CNT(165).EVNT0[0x240]=0
EVNT_TX_ENG_EVENTS_CNT(166).EVNT0[0x241]=0
EVNT_TX_ENG_EVENTS_CNT(167).EVNT0[0x242]=0
EVNT_TX_ENG_EVENTS_CNT(168).EVNT0[0x243]=0
EVNT_TX_ENG_EVENTS_CNT(169).EVNT0[0x244]=0
EVNT_TX_ENG_EVENTS_CNT(170).EVNT0[0x245]=0
EVNT_TX_ENG_EVENTS_CNT(171).EVNT0[0x246]=0
EVNT_TX_ENG_EVENTS_CNT(172).EVNT0[0x247]=0
EVNT_TX_ENG_EVENTS_CNT(173).EVNT0[0x248]=0
EVNT_TX_ENG_EVENTS_CNT(174).EVNT0[0x249]=0
EVNT_TX_ENG_EVENTS_CNT(175).EVNT0[0x24a]=0
EVNT_TX_ENG_EVENTS_CNT(176).EVNT0[0x24b]=0
EVNT_TX_ENG_EVENTS_CNT(177).EVNT0[0x24c]=0
EVNT_TX_ENG_EVENTS_CNT(178).EVNT0[0x24d]=0
EVNT_TX_ENG_EVENTS_CNT(179).EVNT0[0x24e]=0
EVNT_TX_ENG_EVENTS_CNT(180).EVNT0[0x24f]=0
EVNT_TX_ENG_EVENTS_CNT(181).EVNT0[0x250]=0
EVNT_TX_ENG_EVENTS_CNT(182).EVNT0[0x251]=0
EVNT_TX_ENG_EVENTS_CNT(183).EVNT0[0x252]=0
EVNT_TX_ENG_EVENTS_CNT(184).EVNT0[0x253]=0
EVNT_TX_ENG_EVENTS_CNT(185).EVNT0[0x254]=0
EVNT_TX_ENG_EVENTS_CNT(186).EVNT0[0x255]=0
EVNT_TX_ENG_EVENTS_CNT(187).EVNT0[0x256]=0
EVNT_TX_ENG_EVENTS_CNT(188).EVNT0[0x257]=0
EVNT_TX_ENG_EVENTS_CNT(189).EVNT0[0x258]=0
EVNT_TX_ENG_EVENTS_CNT(190).EVNT0[0x259]=0
EVNT_TX_ENG_EVENTS_CNT(191).EVNT0[0x25a]=0
EVNT_TX_ENG_EVENTS_CNT(192).EVNT0[0x25b]=0
EVNT_TX_ENG_EVENTS_CNT(193).EVNT0[0x25c]=0
EVNT_TX_ENG_EVENTS_CNT(194).EVNT0[0x25d]=0
EVNT_TX_ENG_EVENTS_CNT(195).EVNT0[0x25e]=0
EVNT_TX_ENG_EVENTS_CNT(196).EVNT0[0x25f]=0
EVNT_TX_ENG_EVENTS_CNT(197).EVNT0[0x260]=0
EVNT_TX_ENG_EVENTS_CNT(198).EVNT0[0x261]=0
EVNT_TX_ENG_EVENTS_CNT(199).EVNT0[0x262]=0
EVNT_TX_ENG_EVENTS_CNT(200).EVNT0[0x263]=0
EVNT_TX_ENG_EVENTS_CNT(201).EVNT0[0x264]=0
EVNT_TX_ENG_EVENTS_CNT(202).EVNT0[0x265]=0
EVNT_TX_ENG_EVENTS_CNT(203).EVNT0[0x266]=0
EVNT_TX_ENG_EVENTS_CNT(204).EVNT0[0x267]=0
EVNT_TX_ENG_EVENTS_CNT(205).EVNT0[0x268]=0
EVNT_TX_ENG_EVENTS_CNT(206).EVNT0[0x269]=0
EVNT_TX_ENG_EVENTS_CNT(207).EVNT0[0x26a]=0
EVNT_TX_ENG_EVENTS_CNT(208).EVNT0[0x26b]=0
EVNT_TX_ENG_EVENTS_CNT(209).EVNT0[0x26c]=0
EVNT_TX_ENG_EVENTS_CNT(210).EVNT0[0x26d]=0
EVNT_TX_ENG_EVENTS_CNT(211).EVNT0[0x26e]=0
EVNT_TX_ENG_EVENTS_CNT(212).EVNT0[0x26f]=0
EVNT_TX_ENG_EVENTS_CNT(213).EVNT0[0x270]=0
EVNT_TX_ENG_EVENTS_CNT(214).EVNT0[0x271]=0
EVNT_TX_ENG_EVENTS_CNT(215).EVNT0[0x272]=0
EVNT_TX_ENG_EVENTS_CNT(216).EVNT0[0x273]=0
EVNT_TX_ENG_EVENTS_CNT(217).EVNT0[0x274]=0
EVNT_TX_ENG_EVENTS_CNT(218).EVNT0[0x275]=0
EVNT_TX_ENG_EVENTS_CNT(219).EVNT0[0x276]=0
EVNT_TX_ENG_EVENTS_CNT(220).EVNT0[0x277]=0
EVNT_TX_ENG_EVENTS_CNT(221).EVNT0[0x278]=0
EVNT_TX_ENG_EVENTS_CNT(222).EVNT0[0x279]=0
EVNT_TX_ENG_EVENTS_CNT(223).EVNT0[0x27a]=0
EVNT_TX_ENG_EVENTS_CNT(224).EVNT0[0x27b]=0
EVNT_TX_ENG_EVENTS_CNT(225).EVNT0[0x27c]=0
EVNT_TX_ENG_EVENTS_CNT(226).EVNT0[0x27d]=0
EVNT_TX_ENG_EVENTS_CNT(227).EVNT0[0x27e]=0
EVNT_TX_ENG_EVENTS_CNT(228).EVNT0[0x27f]=0
EVNT_TX_ENG_EVENTS_CNT(229).EVNT0[0x280]=0
EVNT_TX_ENG_EVENTS_CNT(230).EVNT0[0x281]=0
EVNT_TX_ENG_EVENTS_CNT(231).EVNT0[0x282]=0
EVNT_TX_ENG_EVENTS_CNT(232).EVNT0[0x283]=0
EVNT_TX_ENG_EVENTS_CNT(233).EVNT0[0x284]=0
EVNT_TX_ENG_EVENTS_CNT(234).EVNT0[0x285]=0
EVNT_TX_ENG_EVENTS_CNT(235).EVNT0[0x286]=0
EVNT_TX_ENG_EVENTS_CNT(236).EVNT0[0x287]=0
EVNT_TX_ENG_EVENTS_CNT(237).EVNT0[0x288]=0
EVNT_TX_ENG_EVENTS_CNT(238).EVNT0[0x289]=0
EVNT_TX_ENG_EVENTS_CNT(239).EVNT0[0x28a]=0
EVNT_TX_ENG_EVENTS_CNT(240).EVNT0[0x28b]=0
EVNT_TX_ENG_EVENTS_CNT(241).EVNT0[0x28c]=0
EVNT_TX_ENG_EVENTS_CNT(242).EVNT0[0x28d]=0
EVNT_TX_ENG_EVENTS_CNT(243).EVNT0[0x28e]=0
EVNT_TX_ENG_EVENTS_CNT(244).EVNT0[0x28f]=0
EVNT_TX_ENG_EVENTS_CNT(245).EVNT0[0x290]=0
EVNT_TX_ENG_EVENTS_CNT(246).EVNT0[0x291]=0
EVNT_TX_ENG_EVENTS_CNT(247).EVNT0[0x292]=0
EVNT_TX_ENG_EVENTS_CNT(248).EVNT0[0x293]=0
EVNT_TX_ENG_EVENTS_CNT(249).EVNT0[0x294]=0
EVNT_TX_ENG_EVENTS_CNT(250).EVNT0[0x295]=0
EVNT_TX_ENG_EVENTS_CNT(251).EVNT0[0x296]=0
EVNT_TX_ENG_EVENTS_CNT(252).EVNT0[0x297]=0
EVNT_TX_ENG_EVENTS_CNT(253).EVNT0[0x298]=0
EVNT_TX_ENG_EVENTS_CNT(254).EVNT0[0x299]=0
EVNT_TX_ENG_EVENTS_CNT(255).EVNT0[0x29a]=0
EVNT_TX_ENG_EVPCK_PADDING_ENABLE.EVNT0[0x29b]=0
EVNT_TX_HANDLER_ACCEPT_UNDONE_NEW_EVENT_REQS.EVNT0[0x106]=0
EVNT_TX_HANDLER_CLEAR_CMIC_DONE_STM_ERR.EVNT0[0x109]=0
EVNT_TX_HANDLER_CMIC_STMS_STATE.EVNT0[0x10b]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(0).EVNT0[0x10c]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(1).EVNT0[0x10d]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(2).EVNT0[0x10e]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(3).EVNT0[0x10f]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(4).EVNT0[0x110]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(5).EVNT0[0x111]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(6).EVNT0[0x112]=0
EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE(7).EVNT0[0x113]=0
EVNT_TX_HANDLER_EXT_PRIORITY_RR_VEC.EVNT0[0x115]=0x1f
EVNT_TX_HANDLER_ONETIME_EVENT_EN.EVNT0[0x108]=0
EVNT_TX_HANDLER_REQ_EN.EVNT0[0x107]=0xfc00
EVNT_TX_MAIN_BUFFER_TH.EVNT0[0x29e]=0xc86432190c86432190c86432190c86432190
EVNT_TX_MAIN_BUFFER_TIMEOUT.EVNT0[0x2a0]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
FEU_BIST_ERROR_GENERATOR.FEU0[0x1828]=0
FEU_BIST_EVENTS_GENERATOR.FEU0[0x1825]=0x1000000000000000000000000
FEU_BIST_EVENTS_STATUS.FEU0[0x1826]=0x100000000
FEU_CONTROL_FRAME_CONFIG.FEU0[0x390]=0
FEU_ECC_1B_ERR_CNT.FEU0[0x94]=0
FEU_ECC_2B_ERR_CNT.FEU0[0x96]=0
FEU_ECC_ERR_1B_MONITOR_MEM_MASK.FEU0[0x9a]=0xffffff
FEU_ECC_ERR_2B_MONITOR_MEM_MASK.FEU0[0x9c]=0xffffff
FEU_ECC_INTERRUPT_REGISTER.FEU0[0x7]=0
FEU_ECC_INTERRUPT_REGISTER_MASK.FEU0[0x17]=0
FEU_ECC_INTERRUPT_REGISTER_TEST.FEU0[0x1f]=0
FEU_EGQ_CRDT_CONFIG.FEU0[0xb5b]=0
FEU_ENABLE_DYNAMIC_MEMORY_ACCESS.FEU0[0x84]=0xf
FEU_ETH_TX_GEN_LLFC_CNT.FEU0[0x17f3]=0
FEU_ETH_TX_LLFC_STOP_TX_CNT.FEU0[0x17f2]=0
FEU_FCF_RMC_ASSIGNMENT(0).FEU0[0x181c]=0
FEU_FCF_RMC_ASSIGNMENT(1).FEU0[0x181d]=0
FEU_FCF_RMC_ASSIGNMENT(2).FEU0[0x181e]=0
FEU_FCF_RMC_ASSIGNMENT(3).FEU0[0x181f]=0
FEU_FCF_RMC_ASSIGNMENT(4).FEU0[0x1820]=0
FEU_FCF_RMC_ASSIGNMENT(5).FEU0[0x1821]=0
FEU_FCF_RMC_ASSIGNMENT(6).FEU0[0x1822]=0
FEU_FCF_RMC_ASSIGNMENT(7).FEU0[0x1823]=0
FEU_FC_2_CFC_CONTROL.FEU0[0x1824]=0
FEU_FC_BIST.FEU0[0x1827]=0
FEU_FC_CHOOSE_PORT_FOR_ETH_TX.FEU0[0x17f1]=0
FEU_FC_CHOOSE_PORT_FOR_PFC.FEU0[0x17ef]=0
FEU_FC_GEN_SAFC_REFRESH_TIMER(0).FEU0[0x17da]=0x1000000
FEU_FC_GEN_SAFC_REFRESH_TIMER(1).FEU0[0x17db]=0x1000000
FEU_FC_GEN_SAFC_REFRESH_TIMER(2).FEU0[0x17dc]=0x1000000
FEU_FC_GEN_SAFC_REFRESH_TIMER(3).FEU0[0x17dd]=0x1000000
FEU_FC_GEN_SAFC_REFRESH_TIMER(4).FEU0[0x17de]=0x1000000
FEU_FC_GEN_SAFC_REFRESH_TIMER(5).FEU0[0x17df]=0x1000000
FEU_FC_GEN_SAFC_REFRESH_TIMER(6).FEU0[0x17e0]=0x1000000
FEU_FC_GEN_SAFC_REFRESH_TIMER(7).FEU0[0x17e1]=0x1000000
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(0).FEU0[0x17f4]=0
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(1).FEU0[0x17f5]=0
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(2).FEU0[0x17f6]=0
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(3).FEU0[0x17f7]=0
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(4).FEU0[0x17f8]=0
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(5).FEU0[0x17f9]=0
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(6).FEU0[0x17fa]=0
FEU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT(7).FEU0[0x17fb]=0
FEU_FC_LLFC_STOP_TX_FORCE.FEU0[0x17c8]=0
FEU_FC_LLFC_STOP_TX_FROM_CFC_MASK.FEU0[0x17cc]=0
FEU_FC_MASK_FC_WHEN_LINK_FAIL.FEU0[0x17d8]=0xff
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(0).FEU0[0x180c]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(1).FEU0[0x180d]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(2).FEU0[0x180e]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(3).FEU0[0x180f]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(4).FEU0[0x1810]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(5).FEU0[0x1811]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(6).FEU0[0x1812]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(7).FEU0[0x1813]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(8).FEU0[0x1814]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(9).FEU0[0x1815]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(10).FEU0[0x1816]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(11).FEU0[0x1817]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(12).FEU0[0x1818]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(13).FEU0[0x1819]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(14).FEU0[0x181a]=0
FEU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC(15).FEU0[0x181b]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(0).FEU0[0x17fc]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(1).FEU0[0x17fd]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(2).FEU0[0x17fe]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(3).FEU0[0x17ff]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(4).FEU0[0x1800]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(5).FEU0[0x1801]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(6).FEU0[0x1802]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(7).FEU0[0x1803]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(8).FEU0[0x1804]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(9).FEU0[0x1805]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(10).FEU0[0x1806]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(11).FEU0[0x1807]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(12).FEU0[0x1808]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(13).FEU0[0x1809]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(14).FEU0[0x180a]=0
FEU_FC_MASK_PFC_PRIO_OF_RMC(15).FEU0[0x180b]=0
FEU_FC_PFC_CFG.FEU0[0x17c6]=0x25
FEU_FC_PFC_DEBUG_INDICATIONS.FEU0[0x17f0]=0
FEU_FC_PFC_RX_BITMAP_MAP_FORCE_EN.FEU0[0x17d1]=0xff
FEU_FC_PFC_RX_BITMAP_TYPE_A.FEU0[0x17cf]=0xff008040201008040201
FEU_FC_PFC_RX_BITMAP_TYPE_B.FEU0[0x17d0]=0xff008040201008040201
FEU_FC_PFC_RX_BITMAP_TYPE_PER_PORT.FEU0[0x17d2]=0
FEU_FC_PFC_TX_BITMAP_TYPE_A.FEU0[0x17d3]=0xfff8040201008040201
FEU_FC_PFC_TX_BITMAP_TYPE_B.FEU0[0x17d4]=0xfff8040201008040201
FEU_FC_PFC_TX_BITMAP_TYPE_C.FEU0[0x17d5]=0xfff8040201008040201
FEU_FC_PFC_TX_BITMAP_TYPE_D.FEU0[0x17d6]=0xfff8040201008040201
FEU_FC_PFC_TX_BITMAP_TYPE_PER_PORT.FEU0[0x17d7]=0
FEU_FC_RESET.FEU0[0x17c5]=1
FEU_FC_RX_GEN_LLFC_FROM_QMLF.FEU0[0x17e2]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(0).FEU0[0x17e3]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(1).FEU0[0x17e4]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(2).FEU0[0x17e5]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(3).FEU0[0x17e6]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(4).FEU0[0x17e7]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(5).FEU0[0x17e8]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(6).FEU0[0x17e9]=0
FEU_FC_RX_GEN_PFC_FROM_QMLF_PORT(7).FEU0[0x17ea]=0
FEU_FC_TX_GEN_LLFC_FORCE.FEU0[0x17c7]=0
FEU_FC_TX_GEN_LLFC_FROM_CFC.FEU0[0x17eb]=0
FEU_FC_TX_GEN_LLFC_FROM_CFC_MASK.FEU0[0x17ca]=0
FEU_FC_TX_GEN_LLFC_FROM_CFC_OCB_MASK.FEU0[0x17cb]=0
FEU_FC_TX_GEN_LLFC_FROM_CFC_PD_MASK.FEU0[0x17cd]=0
FEU_FC_TX_GEN_LLFC_TO_PM.FEU0[0x17ec]=0
FEU_FC_TX_GEN_PFC_FORCE.FEU0[0x17c9]=0
FEU_FC_TX_GEN_PFC_FORCE_MASK.FEU0[0x17ce]=0
FEU_FC_TX_LLFC_STOP_TX_FROM_CFC.FEU0[0x17ed]=0
FEU_FC_TX_LLFC_STOP_TX_TO_PM.FEU0[0x17ee]=0
FEU_FC_TX_LOW_PASS_FILTER.FEU0[0x17d9]=0x10100
FEU_FEC_BYPASS_INDICATION_ENABLE(0).FEU0[0x1ac4]=0
FEU_FEC_BYPASS_INDICATION_ENABLE(1).FEU0[0x1ac5]=0
FEU_FEC_BYPASS_INDICATION_ENABLE(2).FEU0[0x1ac6]=0
FEU_FEC_BYPASS_INDICATION_ENABLE(3).FEU0[0x1ac7]=0
FEU_FEC_DECODER_ALIGN_STATUS(0).FEU0[0x1ac8]=0
FEU_FEC_DECODER_ALIGN_STATUS(1).FEU0[0x1ac9]=0
FEU_FEC_DECODER_ALIGN_STATUS(2).FEU0[0x1aca]=0
FEU_FEC_DECODER_ALIGN_STATUS(3).FEU0[0x1acb]=0
FEU_FEC_DECODER_AMPS_LOCK_STATUS(0).FEU0[0x1acc]=0
FEU_FEC_DECODER_AMPS_LOCK_STATUS(1).FEU0[0x1acd]=0
FEU_FEC_DECODER_AMPS_LOCK_STATUS(2).FEU0[0x1ace]=0
FEU_FEC_DECODER_AMPS_LOCK_STATUS(3).FEU0[0x1acf]=0
FEU_FEC_DECODER_DESKEW_FAIL_STATUS(0).FEU0[0x1ad0]=0
FEU_FEC_DECODER_DESKEW_FAIL_STATUS(1).FEU0[0x1ad1]=0
FEU_FEC_DECODER_DESKEW_FAIL_STATUS(2).FEU0[0x1ad2]=0
FEU_FEC_DECODER_DESKEW_FAIL_STATUS(3).FEU0[0x1ad3]=0
FEU_FEC_DECODER_LANE_MAPPING(0).FEU0[0x1ad4]=0
FEU_FEC_DECODER_LANE_MAPPING(1).FEU0[0x1ad5]=0
FEU_FEC_DECODER_LANE_MAPPING(2).FEU0[0x1ad6]=0
FEU_FEC_DECODER_LANE_MAPPING(3).FEU0[0x1ad7]=0
FEU_FEC_DECODER_RX_SERDES_VALID_CFG.FEU0[0x1af6]=1
FEU_FIFO_WRITE_POINTER_QMLF_SELECT.FEU0[0x15da]=0
FEU_FIFO_WRITE_POINTER_RESULT.FEU0[0x15db]=0
FEU_FLUSH_OR_STOP_RX_FIFO.FEU0[0x1abe]=0
FEU_FLUSH_SOP_WITH_ERR_CONFIG(0).FEU0[0xa88]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(1).FEU0[0xa89]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(2).FEU0[0xa8a]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(3).FEU0[0xa8b]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(4).FEU0[0xa8c]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(5).FEU0[0xa8d]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(6).FEU0[0xa8e]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(7).FEU0[0xa8f]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(8).FEU0[0xa90]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(9).FEU0[0xa91]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(10).FEU0[0xa92]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(11).FEU0[0xa93]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(12).FEU0[0xa94]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(13).FEU0[0xa95]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(14).FEU0[0xa96]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(15).FEU0[0xa97]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(16).FEU0[0xa98]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(17).FEU0[0xa99]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(18).FEU0[0xa9a]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(19).FEU0[0xa9b]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(20).FEU0[0xa9c]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(21).FEU0[0xa9d]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(22).FEU0[0xa9e]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(23).FEU0[0xa9f]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(24).FEU0[0xaa0]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(25).FEU0[0xaa1]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(26).FEU0[0xaa2]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(27).FEU0[0xaa3]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(28).FEU0[0xaa4]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(29).FEU0[0xaa5]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(30).FEU0[0xaa6]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(31).FEU0[0xaa7]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(32).FEU0[0xaa8]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(33).FEU0[0xaa9]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(34).FEU0[0xaaa]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(35).FEU0[0xaab]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(36).FEU0[0xaac]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(37).FEU0[0xaad]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(38).FEU0[0xaae]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(39).FEU0[0xaaf]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(40).FEU0[0xab0]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(41).FEU0[0xab1]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(42).FEU0[0xab2]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(43).FEU0[0xab3]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(44).FEU0[0xab4]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(45).FEU0[0xab5]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(46).FEU0[0xab6]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(47).FEU0[0xab7]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(48).FEU0[0xab8]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(49).FEU0[0xab9]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(50).FEU0[0xaba]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(51).FEU0[0xabb]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(52).FEU0[0xabc]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(53).FEU0[0xabd]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(54).FEU0[0xabe]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(55).FEU0[0xabf]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(56).FEU0[0xac0]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(57).FEU0[0xac1]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(58).FEU0[0xac2]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(59).FEU0[0xac3]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(60).FEU0[0xac4]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(61).FEU0[0xac5]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(62).FEU0[0xac6]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(63).FEU0[0xac7]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(64).FEU0[0xac8]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(65).FEU0[0xac9]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(66).FEU0[0xaca]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(67).FEU0[0xacb]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(68).FEU0[0xacc]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(69).FEU0[0xacd]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(70).FEU0[0xace]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(71).FEU0[0xacf]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(72).FEU0[0xad0]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(73).FEU0[0xad1]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(74).FEU0[0xad2]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(75).FEU0[0xad3]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(76).FEU0[0xad4]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(77).FEU0[0xad5]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(78).FEU0[0xad6]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(79).FEU0[0xad7]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(80).FEU0[0xad8]=3
FEU_FLUSH_SOP_WITH_ERR_CONFIG(81).FEU0[0xad9]=3
FEU_GSDEBUGREG.FEU0[0x1a3a]=0
FEU_GTIMER_CONFIGURATION.FEU0[0x89]=0
FEU_GTIMER_CYCLE.FEU0[0x88]=0x3b9aca00
FEU_INDIRECT_COMMAND.FEU0[0x80]=0xe000002
FEU_INDIRECT_COMMAND_ADDRESS.FEU0[0x81]=0xddd2
FEU_INDIRECT_COMMAND_RD_DATA.FEU0[0x60]=0x1859ef2edec028da808af0f210049f1eefb2e6610cc3a9dc99e047e073ff2c35a3227eddb78
FEU_INDIRECT_COMMAND_WR_DATA.FEU0[0x20]=0
FEU_INDIRECT_FORCE_BUBBLE.FEU0[0x83]=0x20019
FEU_INPUT_STAGE_CONFIG.FEU0[0x1af8]=1
FEU_INSTRUMENTATION_CLEAR_MEMORY.FEU0[0x1835]=0
FEU_INSTRUMENTATION_CONFIG.FEU0[0x1829]=0xf
FEU_INSTRUMENTATION_DEBUG_1.FEU0[0x182b]=0
FEU_INSTRUMENTATION_DEBUG_2.FEU0[0x182d]=0
FEU_INSTRUMENTATION_DEBUG_WRAP_AROUND.FEU0[0x1831]=0
FEU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.FEU0[0x15d9]=0
FEU_INSTRUMENTATION_INTERVALS_COUNTER.FEU0[0x1837]=0
FEU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN.FEU0[0x1833]=0xf
FEU_INSTRUMENTATION_OVERRIDE_MODE.FEU0[0x182f]=1
FEU_INSTRUMENTATION_RESET_LOW.FEU0[0x1839]=0
FEU_INTERRUPT_MASK_REGISTER.FEU0[0x10]=0
FEU_INTERRUPT_REGISTER.FEU0[0x0]=0
FEU_INTERRUPT_REGISTER_TEST.FEU0[0x18]=0
FEU_LAST_ADDR_ACCESS_CONFIG.FEU0[0x1ee6]=0
FEU_LAST_RECEIVED_FROM_EGQ_CONFIG.FEU0[0x112e]=0
FEU_LAST_RECEIVED_FROM_EGQ_CONTROLS.FEU0[0x112d]=0x2f2267be
FEU_LAST_RECEIVED_FROM_EGQ_DATA.FEU0[0x112f]=0xb38eb7a0be8522c2ddf13b33c6ef7de81f787a5895fbc69ca45c49bbf5a33739bb8cf5ffd66dfabeebdda90f76fd352e785d77bffae9ec66b5bcf4d65b06975f
FEU_LAST_RECEIVED_FROM_IRE_CONFIG.FEU0[0x1131]=0
FEU_LAST_RECEIVED_FROM_IRE_CONTROLS.FEU0[0x1130]=0x1ceedd6
FEU_LAST_RECEIVED_FROM_IRE_DATA.FEU0[0x1132]=0xdec3efee5b7efdef6e14f27a39ffbf7ffffffd7de6a6adc795e0f583d68467dcfd8871e62bbfd55e9d4ff3dd2bf9fdd34a5ea8e586996159629e8ecff6ebbb17
FEU_LAST_RECEIVED_FROM_PARSER_CONFIG.FEU0[0x112c]=0
FEU_LAST_RECEIVED_FROM_PARSER_PER_PORT.FEU0[0x112b]=0xbf8c7cff5dede7f98b72fffe130dbf6f7a1797f3e97ebd2fe3d9dfc7777ffddebbd753a736eff1cdfff5ae74bfdafdff06a8fd4d83b28f7cbd677736fda9ffb0c
FEU_LAST_RECEIVED_FROM_PM_CONFIG.FEU0[0x113c]=0
FEU_LAST_RECEIVED_FROM_PM_CONTROLS.FEU0[0x113d]=0xff7ffafcbee3fe
FEU_LAST_RECEIVED_FROM_PM_DATA.FEU0[0x113e]=0x7bffbd7fee6bdbdedf58fd3fca4271a3049aefd5a808c7b760cdf1b35556c98c1f5b6cae49c06d00a6d2dfbbbfdebffbef6fbf7bbbffeffdfffffffff7fedfff
FEU_LAST_SENT_TO_ILU_CONFIG.FEU0[0x1138]=0
FEU_LAST_SENT_TO_ILU_CONTROLS.FEU0[0x1136]=0x1cfbfa
FEU_LAST_SENT_TO_ILU_DATA.FEU0[0x1137]=0xc234596de7bc75ca4e959ca6a3635a604587fbffa99363d73279b4603f29ce172b39cbac1eeb9d5a4a1a19c6e3bd0c7f969b231d714fcffcd36c79eb3f4ef6bd
FEU_LAST_SENT_TO_IRE_OR_ESB_CONFIG.FEU0[0x1135]=0
FEU_LAST_SENT_TO_IRE_OR_ESB_CONTROLS.FEU0[0x1133]=0x145956a3dae37f52
FEU_LAST_SENT_TO_IRE_OR_ESB_DATA.FEU0[0x1134]=0x18deebbd63da3a941ae7a4b93114a3f0176fc3fbc5017c935239edc80231fd40c9880ab27c8c8a3a53ea3fdfbc3ffd5e963186a22fcc3d64530797c960fa1dbb
FEU_LAST_SENT_TO_PM_CONFIG.FEU0[0x113b]=0
FEU_LAST_SENT_TO_PM_CONTROLS.FEU0[0x1139]=0x1bbf9effe
FEU_LAST_SENT_TO_PM_DATA.FEU0[0x113a]=0xbf7bfffbfefffffefffff7fffff6fef7ffdbffff7ff68fcfff7feffffb76ed6ffdeefffffffffddbf7ff7d9cf9fefffffef7bb73ffe2fffff9deffefffeffffe
FEU_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER.FEU0[0x101]=0
FEU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER.FEU0[0x100]=0
FEU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST.FEU0[0x102]=0
FEU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER.FEU0[0x104]=0
FEU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER.FEU0[0x103]=0
FEU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST.FEU0[0x105]=0
FEU_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS.FEU0[0x15dc]=0
FEU_OUTPUT_STAGE_CALENDAR(0).FEU0[0x1eeb]=0
FEU_OUTPUT_STAGE_CALENDAR(1).FEU0[0x1eec]=0
FEU_OUTPUT_STAGE_CALENDAR(2).FEU0[0x1eed]=0
FEU_OUTPUT_STAGE_CALENDAR(3).FEU0[0x1eee]=0
FEU_OUTPUT_STAGE_CALENDAR(4).FEU0[0x1eef]=0
FEU_OUTPUT_STAGE_CALENDAR(5).FEU0[0x1ef0]=0
FEU_OUTPUT_STAGE_CALENDAR(6).FEU0[0x1ef1]=0
FEU_OUTPUT_STAGE_CALENDAR(7).FEU0[0x1ef2]=0
FEU_OUTPUT_STAGE_CALENDAR(8).FEU0[0x1ef3]=0
FEU_OUTPUT_STAGE_CALENDAR(9).FEU0[0x1ef4]=0
FEU_OUTPUT_STAGE_CALENDAR(10).FEU0[0x1ef5]=0
FEU_OUTPUT_STAGE_CALENDAR(11).FEU0[0x1ef6]=0
FEU_OUTPUT_STAGE_CALENDAR(12).FEU0[0x1ef7]=0
FEU_OUTPUT_STAGE_CALENDAR(13).FEU0[0x1ef8]=0
FEU_OUTPUT_STAGE_CALENDAR(14).FEU0[0x1ef9]=0
FEU_OUTPUT_STAGE_CALENDAR(15).FEU0[0x1efa]=0
FEU_OUTPUT_STAGE_CALENDAR(16).FEU0[0x1efb]=0
FEU_OUTPUT_STAGE_CALENDAR(17).FEU0[0x1efc]=0
FEU_OUTPUT_STAGE_CALENDAR(18).FEU0[0x1efd]=0
FEU_OUTPUT_STAGE_CALENDAR(19).FEU0[0x1efe]=0
FEU_OUTPUT_STAGE_CALENDAR(20).FEU0[0x1eff]=0
FEU_OUTPUT_STAGE_CALENDAR(21).FEU0[0x1f00]=0
FEU_OUTPUT_STAGE_CALENDAR(22).FEU0[0x1f01]=0
FEU_OUTPUT_STAGE_CALENDAR(23).FEU0[0x1f02]=0
FEU_OUTPUT_STAGE_CALENDAR(24).FEU0[0x1f03]=0
FEU_OUTPUT_STAGE_CALENDAR(25).FEU0[0x1f04]=0
FEU_OUTPUT_STAGE_CALENDAR(26).FEU0[0x1f05]=0
FEU_OUTPUT_STAGE_CALENDAR(27).FEU0[0x1f06]=0
FEU_OUTPUT_STAGE_CALENDAR(28).FEU0[0x1f07]=0
FEU_OUTPUT_STAGE_CALENDAR(29).FEU0[0x1f08]=0
FEU_OUTPUT_STAGE_CALENDAR(30).FEU0[0x1f09]=0
FEU_OUTPUT_STAGE_CALENDAR(31).FEU0[0x1f0a]=0
FEU_OUTPUT_STAGE_CALENDAR(32).FEU0[0x1f0b]=0
FEU_OUTPUT_STAGE_CALENDAR(33).FEU0[0x1f0c]=0
FEU_OUTPUT_STAGE_CALENDAR(34).FEU0[0x1f0d]=0
FEU_OUTPUT_STAGE_CALENDAR(35).FEU0[0x1f0e]=0
FEU_OUTPUT_STAGE_CALENDAR(36).FEU0[0x1f0f]=0
FEU_OUTPUT_STAGE_CALENDAR(37).FEU0[0x1f10]=0
FEU_OUTPUT_STAGE_CALENDAR(38).FEU0[0x1f11]=0
FEU_OUTPUT_STAGE_CALENDAR(39).FEU0[0x1f12]=0
FEU_OUTPUT_STAGE_CALENDAR(40).FEU0[0x1f13]=0
FEU_OUTPUT_STAGE_CALENDAR(41).FEU0[0x1f14]=0
FEU_OUTPUT_STAGE_CALENDAR(42).FEU0[0x1f15]=0
FEU_OUTPUT_STAGE_CALENDAR(43).FEU0[0x1f16]=0
FEU_OUTPUT_STAGE_CALENDAR(44).FEU0[0x1f17]=0
FEU_OUTPUT_STAGE_CALENDAR(45).FEU0[0x1f18]=0
FEU_OUTPUT_STAGE_CALENDAR(46).FEU0[0x1f19]=0
FEU_OUTPUT_STAGE_CALENDAR(47).FEU0[0x1f1a]=0
FEU_OUTPUT_STAGE_CALENDAR(48).FEU0[0x1f1b]=0
FEU_OUTPUT_STAGE_CALENDAR(49).FEU0[0x1f1c]=0
FEU_OUTPUT_STAGE_CALENDAR(50).FEU0[0x1f1d]=0
FEU_OUTPUT_STAGE_CALENDAR(51).FEU0[0x1f1e]=0
FEU_OUTPUT_STAGE_CALENDAR(52).FEU0[0x1f1f]=0
FEU_OUTPUT_STAGE_CALENDAR(53).FEU0[0x1f20]=0
FEU_OUTPUT_STAGE_CALENDAR(54).FEU0[0x1f21]=0
FEU_OUTPUT_STAGE_CALENDAR(55).FEU0[0x1f22]=0
FEU_OUTPUT_STAGE_CALENDAR(56).FEU0[0x1f23]=0
FEU_OUTPUT_STAGE_CALENDAR(57).FEU0[0x1f24]=0
FEU_OUTPUT_STAGE_CALENDAR(58).FEU0[0x1f25]=0
FEU_OUTPUT_STAGE_CALENDAR(59).FEU0[0x1f26]=0
FEU_OUTPUT_STAGE_CALENDAR(60).FEU0[0x1f27]=0
FEU_OUTPUT_STAGE_CALENDAR(61).FEU0[0x1f28]=0
FEU_OUTPUT_STAGE_CALENDAR(62).FEU0[0x1f29]=0
FEU_OUTPUT_STAGE_CALENDAR(63).FEU0[0x1f2a]=0
FEU_OUTPUT_STAGE_CALENDAR(64).FEU0[0x1f2b]=0
FEU_OUTPUT_STAGE_CALENDAR(65).FEU0[0x1f2c]=0
FEU_OUTPUT_STAGE_CALENDAR(66).FEU0[0x1f2d]=0
FEU_OUTPUT_STAGE_CALENDAR(67).FEU0[0x1f2e]=0
FEU_OUTPUT_STAGE_CALENDAR(68).FEU0[0x1f2f]=0
FEU_OUTPUT_STAGE_CALENDAR(69).FEU0[0x1f30]=0
FEU_OUTPUT_STAGE_CALENDAR(70).FEU0[0x1f31]=0
FEU_OUTPUT_STAGE_CALENDAR(71).FEU0[0x1f32]=0
FEU_OUTPUT_STAGE_CALENDAR(72).FEU0[0x1f33]=0
FEU_OUTPUT_STAGE_CALENDAR(73).FEU0[0x1f34]=0
FEU_OUTPUT_STAGE_CALENDAR(74).FEU0[0x1f35]=0
FEU_OUTPUT_STAGE_CALENDAR(75).FEU0[0x1f36]=0
FEU_OUTPUT_STAGE_CALENDAR(76).FEU0[0x1f37]=0
FEU_OUTPUT_STAGE_CALENDAR(77).FEU0[0x1f38]=0
FEU_OUTPUT_STAGE_CALENDAR(78).FEU0[0x1f39]=0
FEU_OUTPUT_STAGE_CALENDAR(79).FEU0[0x1f3a]=0
FEU_OUTPUT_STAGE_CALENDAR(80).FEU0[0x1f3b]=0
FEU_OUTPUT_STAGE_CALENDAR(81).FEU0[0x1f3c]=0
FEU_OUTPUT_STAGE_CALENDAR_SAMPLE.FEU0[0x1f3d]=1
FEU_PARITY_ERR_CNT.FEU0[0x98]=0
FEU_PAR_ERR_MEM_MASK.FEU0[0xa0]=0xfff
FEU_PCMI_0.FEU0[0xb0]=0x3b9aca00
FEU_PCMI_1.FEU0[0xb3]=0x3b9aca00
FEU_PCMI_2.FEU0[0xb6]=0x3b9aca00
FEU_PCMI_3.FEU0[0xb9]=0x3b9aca00
FEU_PCMI_4.FEU0[0xbc]=0x3b9aca00
FEU_PCMI_0_S.FEU0[0xb1]=0
FEU_PCMI_0_T.FEU0[0xb2]=0
FEU_PCMI_1_S.FEU0[0xb4]=0
FEU_PCMI_1_T.FEU0[0xb5]=0
FEU_PCMI_2_S.FEU0[0xb7]=0
FEU_PCMI_2_T.FEU0[0xb8]=0
FEU_PCMI_3_S.FEU0[0xba]=0
FEU_PCMI_3_T.FEU0[0xbb]=0
FEU_PCMI_4_S.FEU0[0xbd]=0
FEU_PCMI_4_T.FEU0[0xbe]=0
FEU_PORT_MAP_TO_RMC(0).FEU0[0x1af9]=0xffffffffff
FEU_PORT_MAP_TO_RMC(1).FEU0[0x1afa]=0xffffffffff
FEU_PORT_MAP_TO_RMC(2).FEU0[0x1afb]=0xffffffffff
FEU_PORT_MAP_TO_RMC(3).FEU0[0x1afc]=0xffffffffff
FEU_PORT_MAP_TO_RMC(4).FEU0[0x1afd]=0xffffffffff
FEU_PORT_MAP_TO_RMC(5).FEU0[0x1afe]=0xffffffffff
FEU_PORT_MAP_TO_RMC(6).FEU0[0x1aff]=0xffffffffff
FEU_PORT_MAP_TO_RMC(7).FEU0[0x1b00]=0xffffffffff
FEU_PORT_MAP_TO_RMC(8).FEU0[0x1b01]=0xffffffffff
FEU_PORT_MAP_TO_RMC(9).FEU0[0x1b02]=0xffffffffff
FEU_PORT_MAP_TO_RMC(10).FEU0[0x1b03]=0xffffffffff
FEU_PORT_MAP_TO_RMC(11).FEU0[0x1b04]=0xffffffffff
FEU_PORT_MAP_TO_RMC(12).FEU0[0x1b05]=0xffffffffff
FEU_PORT_MAP_TO_RMC(13).FEU0[0x1b06]=0xffffffffff
FEU_PORT_MAP_TO_RMC(14).FEU0[0x1b07]=0xffffffffff
FEU_PORT_MAP_TO_RMC(15).FEU0[0x1b08]=0xffffffffff
FEU_PORT_MAP_TO_RMC(16).FEU0[0x1b09]=0xffffffffff
FEU_PORT_MAP_TO_RMC(17).FEU0[0x1b0a]=0xffffffffff
FEU_PORT_MAP_TO_RMC(18).FEU0[0x1b0b]=0xffffffffff
FEU_PORT_MAP_TO_RMC(19).FEU0[0x1b0c]=0xffffffffff
FEU_PORT_MAP_TO_RMC(20).FEU0[0x1b0d]=0xffffffffff
FEU_PORT_MAP_TO_RMC(21).FEU0[0x1b0e]=0xffffffffff
FEU_PORT_MAP_TO_RMC(22).FEU0[0x1b0f]=0xffffffffff
FEU_PORT_MAP_TO_RMC(23).FEU0[0x1b10]=0xffffffffff
FEU_PORT_MAP_TO_RMC(24).FEU0[0x1b11]=0xffffffffff
FEU_PORT_MAP_TO_RMC(25).FEU0[0x1b12]=0xffffffffff
FEU_PORT_MAP_TO_RMC(26).FEU0[0x1b13]=0xffffffffff
FEU_PORT_MAP_TO_RMC(27).FEU0[0x1b14]=0xffffffffff
FEU_PORT_MAP_TO_RMC(28).FEU0[0x1b15]=0xffffffffff
FEU_PORT_MAP_TO_RMC(29).FEU0[0x1b16]=0xffffffffff
FEU_PORT_MAP_TO_RMC(30).FEU0[0x1b17]=0xffffffffff
FEU_PORT_MAP_TO_RMC(31).FEU0[0x1b18]=0xffffffffff
FEU_PORT_MAP_TO_RMC(32).FEU0[0x1b19]=0xffffffffff
FEU_PORT_MAP_TO_RMC(33).FEU0[0x1b1a]=0xffffffffff
FEU_PORT_MAP_TO_RMC(34).FEU0[0x1b1b]=0xffffffffff
FEU_PORT_MAP_TO_RMC(35).FEU0[0x1b1c]=0xffffffffff
FEU_PORT_MAP_TO_RMC(36).FEU0[0x1b1d]=0xffffffffff
FEU_PORT_MAP_TO_RMC(37).FEU0[0x1b1e]=0xffffffffff
FEU_PORT_MAP_TO_RMC(38).FEU0[0x1b1f]=0xffffffffff
FEU_PORT_MAP_TO_RMC(39).FEU0[0x1b20]=0xffffffffff
FEU_PORT_MAP_TO_RMC(40).FEU0[0x1b21]=0xffffffffff
FEU_PORT_MAP_TO_RMC(41).FEU0[0x1b22]=0xffffffffff
FEU_PORT_MAP_TO_RMC(42).FEU0[0x1b23]=0xffffffffff
FEU_PORT_MAP_TO_RMC(43).FEU0[0x1b24]=0xffffffffff
FEU_PORT_MAP_TO_RMC(44).FEU0[0x1b25]=0xffffffffff
FEU_PORT_MAP_TO_RMC(45).FEU0[0x1b26]=0xffffffffff
FEU_PORT_MAP_TO_RMC(46).FEU0[0x1b27]=0xffffffffff
FEU_PORT_MAP_TO_RMC(47).FEU0[0x1b28]=0xffffffffff
FEU_PORT_MAP_TO_RMC(48).FEU0[0x1b29]=0xffffffffff
FEU_PORT_MAP_TO_RMC(49).FEU0[0x1b2a]=0xffffffffff
FEU_PORT_MAP_TO_RMC(50).FEU0[0x1b2b]=0xffffffffff
FEU_PORT_MAP_TO_RMC(51).FEU0[0x1b2c]=0xffffffffff
FEU_PORT_MAP_TO_RMC(52).FEU0[0x1b2d]=0xffffffffff
FEU_PORT_MAP_TO_RMC(53).FEU0[0x1b2e]=0xffffffffff
FEU_PORT_MAP_TO_RMC(54).FEU0[0x1b2f]=0xffffffffff
FEU_PORT_MAP_TO_RMC(55).FEU0[0x1b30]=0xffffffffff
FEU_PORT_MAP_TO_RMC(56).FEU0[0x1b31]=0xffffffffff
FEU_PORT_MAP_TO_RMC(57).FEU0[0x1b32]=0xffffffffff
FEU_PORT_MAP_TO_RMC(58).FEU0[0x1b33]=0xffffffffff
FEU_PORT_MAP_TO_RMC(59).FEU0[0x1b34]=0xffffffffff
FEU_PORT_MAP_TO_RMC(60).FEU0[0x1b35]=0xffffffffff
FEU_PORT_MAP_TO_RMC(61).FEU0[0x1b36]=0xffffffffff
FEU_PORT_MAP_TO_RMC(62).FEU0[0x1b37]=0xffffffffff
FEU_PORT_MAP_TO_RMC(63).FEU0[0x1b38]=0xffffffffff
FEU_PORT_MAP_TO_RMC(64).FEU0[0x1b39]=0xffffffffff
FEU_PORT_MAP_TO_RMC(65).FEU0[0x1b3a]=0xffffffffff
FEU_PORT_MAP_TO_RMC(66).FEU0[0x1b3b]=0xffffffffff
FEU_PORT_MAP_TO_RMC(67).FEU0[0x1b3c]=0xffffffffff
FEU_PORT_MAP_TO_RMC(68).FEU0[0x1b3d]=0xffffffffff
FEU_PORT_MAP_TO_RMC(69).FEU0[0x1b3e]=0xffffffffff
FEU_PORT_MAP_TO_RMC(70).FEU0[0x1b3f]=0xffffffffff
FEU_PORT_MAP_TO_RMC(71).FEU0[0x1b40]=0xffffffffff
FEU_PORT_MAP_TO_RMC(72).FEU0[0x1b41]=0xffffffffff
FEU_PORT_MAP_TO_RMC(73).FEU0[0x1b42]=0xffffffffff
FEU_PORT_MAP_TO_RMC(74).FEU0[0x1b43]=0xffffffffff
FEU_PORT_MAP_TO_RMC(75).FEU0[0x1b44]=0xffffffffff
FEU_PORT_MAP_TO_RMC(76).FEU0[0x1b45]=0xffffffffff
FEU_PORT_MAP_TO_RMC(77).FEU0[0x1b46]=0xffffffffff
FEU_PORT_MAP_TO_RMC(78).FEU0[0x1b47]=0xffffffffff
FEU_PORT_MAP_TO_RMC(79).FEU0[0x1b48]=0xffffffffff
FEU_PORT_MAP_TO_RMC(80).FEU0[0x1b49]=0xffffffffff
FEU_PORT_MAP_TO_RMC(81).FEU0[0x1b4a]=0xffffffffff
FEU_PRD_BYPASS.FEU0[0x218]=0
FEU_PRD_CONFIG.FEU0[0x112]=3
FEU_PRD_EN.FEU0[0x117]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(0).FEU0[0x198]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(1).FEU0[0x199]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(2).FEU0[0x19a]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(3).FEU0[0x19b]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(4).FEU0[0x19c]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(5).FEU0[0x19d]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(6).FEU0[0x19e]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(7).FEU0[0x19f]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(8).FEU0[0x1a0]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(9).FEU0[0x1a1]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(10).FEU0[0x1a2]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(11).FEU0[0x1a3]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(12).FEU0[0x1a4]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(13).FEU0[0x1a5]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(14).FEU0[0x1a6]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(15).FEU0[0x1a7]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(16).FEU0[0x1a8]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(17).FEU0[0x1a9]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(18).FEU0[0x1aa]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(19).FEU0[0x1ab]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(20).FEU0[0x1ac]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(21).FEU0[0x1ad]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(22).FEU0[0x1ae]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(23).FEU0[0x1af]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(24).FEU0[0x1b0]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(25).FEU0[0x1b1]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(26).FEU0[0x1b2]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(27).FEU0[0x1b3]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(28).FEU0[0x1b4]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(29).FEU0[0x1b5]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(30).FEU0[0x1b6]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(31).FEU0[0x1b7]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(32).FEU0[0x1b8]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(33).FEU0[0x1b9]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(34).FEU0[0x1ba]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(35).FEU0[0x1bb]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(36).FEU0[0x1bc]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(37).FEU0[0x1bd]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(38).FEU0[0x1be]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(39).FEU0[0x1bf]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(40).FEU0[0x1c0]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(41).FEU0[0x1c1]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(42).FEU0[0x1c2]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(43).FEU0[0x1c3]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(44).FEU0[0x1c4]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(45).FEU0[0x1c5]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(46).FEU0[0x1c6]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(47).FEU0[0x1c7]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(48).FEU0[0x1c8]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(49).FEU0[0x1c9]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(50).FEU0[0x1ca]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(51).FEU0[0x1cb]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(52).FEU0[0x1cc]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(53).FEU0[0x1cd]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(54).FEU0[0x1ce]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(55).FEU0[0x1cf]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(56).FEU0[0x1d0]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(57).FEU0[0x1d1]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(58).FEU0[0x1d2]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(59).FEU0[0x1d3]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(60).FEU0[0x1d4]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(61).FEU0[0x1d5]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(62).FEU0[0x1d6]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(63).FEU0[0x1d7]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(64).FEU0[0x1d8]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(65).FEU0[0x1d9]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(66).FEU0[0x1da]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(67).FEU0[0x1db]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(68).FEU0[0x1dc]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(69).FEU0[0x1dd]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(70).FEU0[0x1de]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(71).FEU0[0x1df]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(72).FEU0[0x1e0]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(73).FEU0[0x1e1]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(74).FEU0[0x1e2]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(75).FEU0[0x1e3]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(76).FEU0[0x1e4]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(77).FEU0[0x1e5]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(78).FEU0[0x1e6]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(79).FEU0[0x1e7]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(80).FEU0[0x1e8]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(81).FEU0[0x1e9]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(82).FEU0[0x1ea]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(83).FEU0[0x1eb]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(84).FEU0[0x1ec]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(85).FEU0[0x1ed]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(86).FEU0[0x1ee]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(87).FEU0[0x1ef]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(88).FEU0[0x1f0]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(89).FEU0[0x1f1]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(90).FEU0[0x1f2]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(91).FEU0[0x1f3]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(92).FEU0[0x1f4]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(93).FEU0[0x1f5]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(94).FEU0[0x1f6]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(95).FEU0[0x1f7]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(96).FEU0[0x1f8]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(97).FEU0[0x1f9]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(98).FEU0[0x1fa]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(99).FEU0[0x1fb]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(100).FEU0[0x1fc]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(101).FEU0[0x1fd]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(102).FEU0[0x1fe]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(103).FEU0[0x1ff]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(104).FEU0[0x200]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(105).FEU0[0x201]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(106).FEU0[0x202]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(107).FEU0[0x203]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(108).FEU0[0x204]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(109).FEU0[0x205]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(110).FEU0[0x206]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(111).FEU0[0x207]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(112).FEU0[0x208]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(113).FEU0[0x209]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(114).FEU0[0x20a]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(115).FEU0[0x20b]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(116).FEU0[0x20c]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(117).FEU0[0x20d]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(118).FEU0[0x20e]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(119).FEU0[0x20f]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(120).FEU0[0x210]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(121).FEU0[0x211]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(122).FEU0[0x212]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(123).FEU0[0x213]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(124).FEU0[0x214]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(125).FEU0[0x215]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(126).FEU0[0x216]=0
FEU_PRD_ERR_PKT_DROP_CNT_RMC(127).FEU0[0x217]=0
FEU_PRD_OVERRIDES_1.FEU0[0x219]=0
FEU_PRD_OVERRIDES_2(0).FEU0[0x21a]=0
FEU_PRD_OVERRIDES_2(1).FEU0[0x21b]=0
FEU_PRD_OVERRIDES_2(2).FEU0[0x21c]=0
FEU_PRD_OVERRIDES_2(3).FEU0[0x21d]=0
FEU_PRD_OVERRIDES_2(4).FEU0[0x21e]=0
FEU_PRD_OVERRIDES_2(5).FEU0[0x21f]=0
FEU_PRD_OVERRIDES_2(6).FEU0[0x220]=0
FEU_PRD_OVERRIDES_2(7).FEU0[0x221]=0
FEU_PRD_OVERRIDES_2(8).FEU0[0x222]=0
FEU_PRD_OVERRIDES_2(9).FEU0[0x223]=0
FEU_PRD_OVERRIDES_2(10).FEU0[0x224]=0
FEU_PRD_OVERRIDES_2(11).FEU0[0x225]=0
FEU_PRD_OVERRIDES_2(12).FEU0[0x226]=0
FEU_PRD_OVERRIDES_2(13).FEU0[0x227]=0
FEU_PRD_OVERRIDES_2(14).FEU0[0x228]=0
FEU_PRD_OVERRIDES_2(15).FEU0[0x229]=0
FEU_PRD_OVERRIDES_2(16).FEU0[0x22a]=0
FEU_PRD_OVERRIDES_2(17).FEU0[0x22b]=0
FEU_PRD_OVERRIDES_2(18).FEU0[0x22c]=0
FEU_PRD_OVERRIDES_2(19).FEU0[0x22d]=0
FEU_PRD_OVERRIDES_2(20).FEU0[0x22e]=0
FEU_PRD_OVERRIDES_2(21).FEU0[0x22f]=0
FEU_PRD_OVERRIDES_2(22).FEU0[0x230]=0
FEU_PRD_OVERRIDES_2(23).FEU0[0x231]=0
FEU_PRD_OVERRIDES_2(24).FEU0[0x232]=0
FEU_PRD_OVERRIDES_2(25).FEU0[0x233]=0
FEU_PRD_OVERRIDES_2(26).FEU0[0x234]=0
FEU_PRD_OVERRIDES_2(27).FEU0[0x235]=0
FEU_PRD_OVERRIDES_2(28).FEU0[0x236]=0
FEU_PRD_OVERRIDES_2(29).FEU0[0x237]=0
FEU_PRD_OVERRIDES_2(30).FEU0[0x238]=0
FEU_PRD_OVERRIDES_2(31).FEU0[0x239]=0
FEU_PRD_OVERRIDES_2(32).FEU0[0x23a]=0
FEU_PRD_OVERRIDES_2(33).FEU0[0x23b]=0
FEU_PRD_OVERRIDES_2(34).FEU0[0x23c]=0
FEU_PRD_OVERRIDES_2(35).FEU0[0x23d]=0
FEU_PRD_OVERRIDES_2(36).FEU0[0x23e]=0
FEU_PRD_OVERRIDES_2(37).FEU0[0x23f]=0
FEU_PRD_OVERRIDES_2(38).FEU0[0x240]=0
FEU_PRD_OVERRIDES_2(39).FEU0[0x241]=0
FEU_PRD_OVERRIDES_2(40).FEU0[0x242]=0
FEU_PRD_OVERRIDES_2(41).FEU0[0x243]=0
FEU_PRD_OVERRIDES_2(42).FEU0[0x244]=0
FEU_PRD_OVERRIDES_2(43).FEU0[0x245]=0
FEU_PRD_OVERRIDES_2(44).FEU0[0x246]=0
FEU_PRD_OVERRIDES_2(45).FEU0[0x247]=0
FEU_PRD_OVERRIDES_2(46).FEU0[0x248]=0
FEU_PRD_OVERRIDES_2(47).FEU0[0x249]=0
FEU_PRD_OVERRIDES_2(48).FEU0[0x24a]=0
FEU_PRD_OVERRIDES_2(49).FEU0[0x24b]=0
FEU_PRD_OVERRIDES_2(50).FEU0[0x24c]=0
FEU_PRD_OVERRIDES_2(51).FEU0[0x24d]=0
FEU_PRD_OVERRIDES_2(52).FEU0[0x24e]=0
FEU_PRD_OVERRIDES_2(53).FEU0[0x24f]=0
FEU_PRD_OVERRIDES_2(54).FEU0[0x250]=0
FEU_PRD_OVERRIDES_2(55).FEU0[0x251]=0
FEU_PRD_OVERRIDES_2(56).FEU0[0x252]=0
FEU_PRD_OVERRIDES_2(57).FEU0[0x253]=0
FEU_PRD_OVERRIDES_2(58).FEU0[0x254]=0
FEU_PRD_OVERRIDES_2(59).FEU0[0x255]=0
FEU_PRD_OVERRIDES_2(60).FEU0[0x256]=0
FEU_PRD_OVERRIDES_2(61).FEU0[0x257]=0
FEU_PRD_OVERRIDES_2(62).FEU0[0x258]=0
FEU_PRD_OVERRIDES_2(63).FEU0[0x259]=0
FEU_PRD_OVERRIDES_2(64).FEU0[0x25a]=0
FEU_PRD_OVERRIDES_2(65).FEU0[0x25b]=0
FEU_PRD_OVERRIDES_2(66).FEU0[0x25c]=0
FEU_PRD_OVERRIDES_2(67).FEU0[0x25d]=0
FEU_PRD_OVERRIDES_2(68).FEU0[0x25e]=0
FEU_PRD_OVERRIDES_2(69).FEU0[0x25f]=0
FEU_PRD_OVERRIDES_2(70).FEU0[0x260]=0
FEU_PRD_OVERRIDES_2(71).FEU0[0x261]=0
FEU_PRD_OVERRIDES_2(72).FEU0[0x262]=0
FEU_PRD_OVERRIDES_2(73).FEU0[0x263]=0
FEU_PRD_OVERRIDES_2(74).FEU0[0x264]=0
FEU_PRD_OVERRIDES_2(75).FEU0[0x265]=0
FEU_PRD_OVERRIDES_2(76).FEU0[0x266]=0
FEU_PRD_OVERRIDES_2(77).FEU0[0x267]=0
FEU_PRD_OVERRIDES_2(78).FEU0[0x268]=0
FEU_PRD_OVERRIDES_2(79).FEU0[0x269]=0
FEU_PRD_OVERRIDES_2(80).FEU0[0x26a]=0
FEU_PRD_OVERRIDES_2(81).FEU0[0x26b]=0
FEU_PRD_OVERRIDES_3(0).FEU0[0x26c]=0
FEU_PRD_OVERRIDES_3(1).FEU0[0x26d]=0
FEU_PRD_OVERRIDES_3(2).FEU0[0x26e]=0
FEU_PRD_OVERRIDES_3(3).FEU0[0x26f]=0
FEU_PRD_OVERRIDES_3(4).FEU0[0x270]=0
FEU_PRD_OVERRIDES_3(5).FEU0[0x271]=0
FEU_PRD_OVERRIDES_3(6).FEU0[0x272]=0
FEU_PRD_OVERRIDES_3(7).FEU0[0x273]=0
FEU_PRD_OVERRIDES_3(8).FEU0[0x274]=0
FEU_PRD_OVERRIDES_3(9).FEU0[0x275]=0
FEU_PRD_OVERRIDES_3(10).FEU0[0x276]=0
FEU_PRD_OVERRIDES_3(11).FEU0[0x277]=0
FEU_PRD_OVERRIDES_3(12).FEU0[0x278]=0
FEU_PRD_OVERRIDES_3(13).FEU0[0x279]=0
FEU_PRD_OVERRIDES_3(14).FEU0[0x27a]=0
FEU_PRD_OVERRIDES_3(15).FEU0[0x27b]=0
FEU_PRD_OVERRIDES_3(16).FEU0[0x27c]=0
FEU_PRD_OVERRIDES_3(17).FEU0[0x27d]=0
FEU_PRD_OVERRIDES_3(18).FEU0[0x27e]=0
FEU_PRD_OVERRIDES_3(19).FEU0[0x27f]=0
FEU_PRD_OVERRIDES_3(20).FEU0[0x280]=0
FEU_PRD_OVERRIDES_3(21).FEU0[0x281]=0
FEU_PRD_OVERRIDES_3(22).FEU0[0x282]=0
FEU_PRD_OVERRIDES_3(23).FEU0[0x283]=0
FEU_PRD_OVERRIDES_3(24).FEU0[0x284]=0
FEU_PRD_OVERRIDES_3(25).FEU0[0x285]=0
FEU_PRD_OVERRIDES_3(26).FEU0[0x286]=0
FEU_PRD_OVERRIDES_3(27).FEU0[0x287]=0
FEU_PRD_OVERRIDES_3(28).FEU0[0x288]=0
FEU_PRD_OVERRIDES_3(29).FEU0[0x289]=0
FEU_PRD_OVERRIDES_3(30).FEU0[0x28a]=0
FEU_PRD_OVERRIDES_3(31).FEU0[0x28b]=0
FEU_PRD_OVERRIDES_3(32).FEU0[0x28c]=0
FEU_PRD_OVERRIDES_3(33).FEU0[0x28d]=0
FEU_PRD_OVERRIDES_3(34).FEU0[0x28e]=0
FEU_PRD_OVERRIDES_3(35).FEU0[0x28f]=0
FEU_PRD_OVERRIDES_3(36).FEU0[0x290]=0
FEU_PRD_OVERRIDES_3(37).FEU0[0x291]=0
FEU_PRD_OVERRIDES_3(38).FEU0[0x292]=0
FEU_PRD_OVERRIDES_3(39).FEU0[0x293]=0
FEU_PRD_OVERRIDES_3(40).FEU0[0x294]=0
FEU_PRD_OVERRIDES_3(41).FEU0[0x295]=0
FEU_PRD_OVERRIDES_3(42).FEU0[0x296]=0
FEU_PRD_OVERRIDES_3(43).FEU0[0x297]=0
FEU_PRD_OVERRIDES_3(44).FEU0[0x298]=0
FEU_PRD_OVERRIDES_3(45).FEU0[0x299]=0
FEU_PRD_OVERRIDES_3(46).FEU0[0x29a]=0
FEU_PRD_OVERRIDES_3(47).FEU0[0x29b]=0
FEU_PRD_OVERRIDES_3(48).FEU0[0x29c]=0
FEU_PRD_OVERRIDES_3(49).FEU0[0x29d]=0
FEU_PRD_OVERRIDES_3(50).FEU0[0x29e]=0
FEU_PRD_OVERRIDES_3(51).FEU0[0x29f]=0
FEU_PRD_OVERRIDES_3(52).FEU0[0x2a0]=0
FEU_PRD_OVERRIDES_3(53).FEU0[0x2a1]=0
FEU_PRD_OVERRIDES_3(54).FEU0[0x2a2]=0
FEU_PRD_OVERRIDES_3(55).FEU0[0x2a3]=0
FEU_PRD_OVERRIDES_3(56).FEU0[0x2a4]=0
FEU_PRD_OVERRIDES_3(57).FEU0[0x2a5]=0
FEU_PRD_OVERRIDES_3(58).FEU0[0x2a6]=0
FEU_PRD_OVERRIDES_3(59).FEU0[0x2a7]=0
FEU_PRD_OVERRIDES_3(60).FEU0[0x2a8]=0
FEU_PRD_OVERRIDES_3(61).FEU0[0x2a9]=0
FEU_PRD_OVERRIDES_3(62).FEU0[0x2aa]=0
FEU_PRD_OVERRIDES_3(63).FEU0[0x2ab]=0
FEU_PRD_OVERRIDES_3(64).FEU0[0x2ac]=0
FEU_PRD_OVERRIDES_3(65).FEU0[0x2ad]=0
FEU_PRD_OVERRIDES_3(66).FEU0[0x2ae]=0
FEU_PRD_OVERRIDES_3(67).FEU0[0x2af]=0
FEU_PRD_OVERRIDES_3(68).FEU0[0x2b0]=0
FEU_PRD_OVERRIDES_3(69).FEU0[0x2b1]=0
FEU_PRD_OVERRIDES_3(70).FEU0[0x2b2]=0
FEU_PRD_OVERRIDES_3(71).FEU0[0x2b3]=0
FEU_PRD_OVERRIDES_3(72).FEU0[0x2b4]=0
FEU_PRD_OVERRIDES_3(73).FEU0[0x2b5]=0
FEU_PRD_OVERRIDES_3(74).FEU0[0x2b6]=0
FEU_PRD_OVERRIDES_3(75).FEU0[0x2b7]=0
FEU_PRD_OVERRIDES_3(76).FEU0[0x2b8]=0
FEU_PRD_OVERRIDES_3(77).FEU0[0x2b9]=0
FEU_PRD_OVERRIDES_3(78).FEU0[0x2ba]=0
FEU_PRD_OVERRIDES_3(79).FEU0[0x2bb]=0
FEU_PRD_OVERRIDES_3(80).FEU0[0x2bc]=0
FEU_PRD_OVERRIDES_3(81).FEU0[0x2bd]=0
FEU_PRD_PKT_DROP_CNT_RMC(0).FEU0[0x118]=0
FEU_PRD_PKT_DROP_CNT_RMC(1).FEU0[0x119]=0
FEU_PRD_PKT_DROP_CNT_RMC(2).FEU0[0x11a]=0
FEU_PRD_PKT_DROP_CNT_RMC(3).FEU0[0x11b]=0
FEU_PRD_PKT_DROP_CNT_RMC(4).FEU0[0x11c]=0
FEU_PRD_PKT_DROP_CNT_RMC(5).FEU0[0x11d]=0
FEU_PRD_PKT_DROP_CNT_RMC(6).FEU0[0x11e]=0
FEU_PRD_PKT_DROP_CNT_RMC(7).FEU0[0x11f]=0
FEU_PRD_PKT_DROP_CNT_RMC(8).FEU0[0x120]=0
FEU_PRD_PKT_DROP_CNT_RMC(9).FEU0[0x121]=0
FEU_PRD_PKT_DROP_CNT_RMC(10).FEU0[0x122]=0
FEU_PRD_PKT_DROP_CNT_RMC(11).FEU0[0x123]=0
FEU_PRD_PKT_DROP_CNT_RMC(12).FEU0[0x124]=0
FEU_PRD_PKT_DROP_CNT_RMC(13).FEU0[0x125]=0
FEU_PRD_PKT_DROP_CNT_RMC(14).FEU0[0x126]=0
FEU_PRD_PKT_DROP_CNT_RMC(15).FEU0[0x127]=0
FEU_PRD_PKT_DROP_CNT_RMC(16).FEU0[0x128]=0
FEU_PRD_PKT_DROP_CNT_RMC(17).FEU0[0x129]=0
FEU_PRD_PKT_DROP_CNT_RMC(18).FEU0[0x12a]=0
FEU_PRD_PKT_DROP_CNT_RMC(19).FEU0[0x12b]=0
FEU_PRD_PKT_DROP_CNT_RMC(20).FEU0[0x12c]=0
FEU_PRD_PKT_DROP_CNT_RMC(21).FEU0[0x12d]=0
FEU_PRD_PKT_DROP_CNT_RMC(22).FEU0[0x12e]=0
FEU_PRD_PKT_DROP_CNT_RMC(23).FEU0[0x12f]=0
FEU_PRD_PKT_DROP_CNT_RMC(24).FEU0[0x130]=0
FEU_PRD_PKT_DROP_CNT_RMC(25).FEU0[0x131]=0
FEU_PRD_PKT_DROP_CNT_RMC(26).FEU0[0x132]=0
FEU_PRD_PKT_DROP_CNT_RMC(27).FEU0[0x133]=0
FEU_PRD_PKT_DROP_CNT_RMC(28).FEU0[0x134]=0
FEU_PRD_PKT_DROP_CNT_RMC(29).FEU0[0x135]=0
FEU_PRD_PKT_DROP_CNT_RMC(30).FEU0[0x136]=0
FEU_PRD_PKT_DROP_CNT_RMC(31).FEU0[0x137]=0
FEU_PRD_PKT_DROP_CNT_RMC(32).FEU0[0x138]=0
FEU_PRD_PKT_DROP_CNT_RMC(33).FEU0[0x139]=0
FEU_PRD_PKT_DROP_CNT_RMC(34).FEU0[0x13a]=0
FEU_PRD_PKT_DROP_CNT_RMC(35).FEU0[0x13b]=0
FEU_PRD_PKT_DROP_CNT_RMC(36).FEU0[0x13c]=0
FEU_PRD_PKT_DROP_CNT_RMC(37).FEU0[0x13d]=0
FEU_PRD_PKT_DROP_CNT_RMC(38).FEU0[0x13e]=0
FEU_PRD_PKT_DROP_CNT_RMC(39).FEU0[0x13f]=0
FEU_PRD_PKT_DROP_CNT_RMC(40).FEU0[0x140]=0
FEU_PRD_PKT_DROP_CNT_RMC(41).FEU0[0x141]=0
FEU_PRD_PKT_DROP_CNT_RMC(42).FEU0[0x142]=0
FEU_PRD_PKT_DROP_CNT_RMC(43).FEU0[0x143]=0
FEU_PRD_PKT_DROP_CNT_RMC(44).FEU0[0x144]=0
FEU_PRD_PKT_DROP_CNT_RMC(45).FEU0[0x145]=0
FEU_PRD_PKT_DROP_CNT_RMC(46).FEU0[0x146]=0
FEU_PRD_PKT_DROP_CNT_RMC(47).FEU0[0x147]=0
FEU_PRD_PKT_DROP_CNT_RMC(48).FEU0[0x148]=0
FEU_PRD_PKT_DROP_CNT_RMC(49).FEU0[0x149]=0
FEU_PRD_PKT_DROP_CNT_RMC(50).FEU0[0x14a]=0
FEU_PRD_PKT_DROP_CNT_RMC(51).FEU0[0x14b]=0
FEU_PRD_PKT_DROP_CNT_RMC(52).FEU0[0x14c]=0
FEU_PRD_PKT_DROP_CNT_RMC(53).FEU0[0x14d]=0
FEU_PRD_PKT_DROP_CNT_RMC(54).FEU0[0x14e]=0
FEU_PRD_PKT_DROP_CNT_RMC(55).FEU0[0x14f]=0
FEU_PRD_PKT_DROP_CNT_RMC(56).FEU0[0x150]=0
FEU_PRD_PKT_DROP_CNT_RMC(57).FEU0[0x151]=0
FEU_PRD_PKT_DROP_CNT_RMC(58).FEU0[0x152]=0
FEU_PRD_PKT_DROP_CNT_RMC(59).FEU0[0x153]=0
FEU_PRD_PKT_DROP_CNT_RMC(60).FEU0[0x154]=0
FEU_PRD_PKT_DROP_CNT_RMC(61).FEU0[0x155]=0
FEU_PRD_PKT_DROP_CNT_RMC(62).FEU0[0x156]=0
FEU_PRD_PKT_DROP_CNT_RMC(63).FEU0[0x157]=0
FEU_PRD_PKT_DROP_CNT_RMC(64).FEU0[0x158]=0
FEU_PRD_PKT_DROP_CNT_RMC(65).FEU0[0x159]=0
FEU_PRD_PKT_DROP_CNT_RMC(66).FEU0[0x15a]=0
FEU_PRD_PKT_DROP_CNT_RMC(67).FEU0[0x15b]=0
FEU_PRD_PKT_DROP_CNT_RMC(68).FEU0[0x15c]=0
FEU_PRD_PKT_DROP_CNT_RMC(69).FEU0[0x15d]=0
FEU_PRD_PKT_DROP_CNT_RMC(70).FEU0[0x15e]=0
FEU_PRD_PKT_DROP_CNT_RMC(71).FEU0[0x15f]=0
FEU_PRD_PKT_DROP_CNT_RMC(72).FEU0[0x160]=0
FEU_PRD_PKT_DROP_CNT_RMC(73).FEU0[0x161]=0
FEU_PRD_PKT_DROP_CNT_RMC(74).FEU0[0x162]=0
FEU_PRD_PKT_DROP_CNT_RMC(75).FEU0[0x163]=0
FEU_PRD_PKT_DROP_CNT_RMC(76).FEU0[0x164]=0
FEU_PRD_PKT_DROP_CNT_RMC(77).FEU0[0x165]=0
FEU_PRD_PKT_DROP_CNT_RMC(78).FEU0[0x166]=0
FEU_PRD_PKT_DROP_CNT_RMC(79).FEU0[0x167]=0
FEU_PRD_PKT_DROP_CNT_RMC(80).FEU0[0x168]=0
FEU_PRD_PKT_DROP_CNT_RMC(81).FEU0[0x169]=0
FEU_PRD_PKT_DROP_CNT_RMC(82).FEU0[0x16a]=0
FEU_PRD_PKT_DROP_CNT_RMC(83).FEU0[0x16b]=0
FEU_PRD_PKT_DROP_CNT_RMC(84).FEU0[0x16c]=0
FEU_PRD_PKT_DROP_CNT_RMC(85).FEU0[0x16d]=0
FEU_PRD_PKT_DROP_CNT_RMC(86).FEU0[0x16e]=0
FEU_PRD_PKT_DROP_CNT_RMC(87).FEU0[0x16f]=0
FEU_PRD_PKT_DROP_CNT_RMC(88).FEU0[0x170]=0
FEU_PRD_PKT_DROP_CNT_RMC(89).FEU0[0x171]=0
FEU_PRD_PKT_DROP_CNT_RMC(90).FEU0[0x172]=0
FEU_PRD_PKT_DROP_CNT_RMC(91).FEU0[0x173]=0
FEU_PRD_PKT_DROP_CNT_RMC(92).FEU0[0x174]=0
FEU_PRD_PKT_DROP_CNT_RMC(93).FEU0[0x175]=0
FEU_PRD_PKT_DROP_CNT_RMC(94).FEU0[0x176]=0
FEU_PRD_PKT_DROP_CNT_RMC(95).FEU0[0x177]=0
FEU_PRD_PKT_DROP_CNT_RMC(96).FEU0[0x178]=0
FEU_PRD_PKT_DROP_CNT_RMC(97).FEU0[0x179]=0
FEU_PRD_PKT_DROP_CNT_RMC(98).FEU0[0x17a]=0
FEU_PRD_PKT_DROP_CNT_RMC(99).FEU0[0x17b]=0
FEU_PRD_PKT_DROP_CNT_RMC(100).FEU0[0x17c]=0
FEU_PRD_PKT_DROP_CNT_RMC(101).FEU0[0x17d]=0
FEU_PRD_PKT_DROP_CNT_RMC(102).FEU0[0x17e]=0
FEU_PRD_PKT_DROP_CNT_RMC(103).FEU0[0x17f]=0
FEU_PRD_PKT_DROP_CNT_RMC(104).FEU0[0x180]=0
FEU_PRD_PKT_DROP_CNT_RMC(105).FEU0[0x181]=0
FEU_PRD_PKT_DROP_CNT_RMC(106).FEU0[0x182]=0
FEU_PRD_PKT_DROP_CNT_RMC(107).FEU0[0x183]=0
FEU_PRD_PKT_DROP_CNT_RMC(108).FEU0[0x184]=0
FEU_PRD_PKT_DROP_CNT_RMC(109).FEU0[0x185]=0
FEU_PRD_PKT_DROP_CNT_RMC(110).FEU0[0x186]=0
FEU_PRD_PKT_DROP_CNT_RMC(111).FEU0[0x187]=0
FEU_PRD_PKT_DROP_CNT_RMC(112).FEU0[0x188]=0
FEU_PRD_PKT_DROP_CNT_RMC(113).FEU0[0x189]=0
FEU_PRD_PKT_DROP_CNT_RMC(114).FEU0[0x18a]=0
FEU_PRD_PKT_DROP_CNT_RMC(115).FEU0[0x18b]=0
FEU_PRD_PKT_DROP_CNT_RMC(116).FEU0[0x18c]=0
FEU_PRD_PKT_DROP_CNT_RMC(117).FEU0[0x18d]=0
FEU_PRD_PKT_DROP_CNT_RMC(118).FEU0[0x18e]=0
FEU_PRD_PKT_DROP_CNT_RMC(119).FEU0[0x18f]=0
FEU_PRD_PKT_DROP_CNT_RMC(120).FEU0[0x190]=0
FEU_PRD_PKT_DROP_CNT_RMC(121).FEU0[0x191]=0
FEU_PRD_PKT_DROP_CNT_RMC(122).FEU0[0x192]=0
FEU_PRD_PKT_DROP_CNT_RMC(123).FEU0[0x193]=0
FEU_PRD_PKT_DROP_CNT_RMC(124).FEU0[0x194]=0
FEU_PRD_PKT_DROP_CNT_RMC(125).FEU0[0x195]=0
FEU_PRD_PKT_DROP_CNT_RMC(126).FEU0[0x196]=0
FEU_PRD_PKT_DROP_CNT_RMC(127).FEU0[0x197]=0
FEU_PRD_PROFILE_CFG(0).FEU0[0x2be]=0
FEU_PRD_PROFILE_CFG(1).FEU0[0x2bf]=0
FEU_PRD_PROFILE_CFG(2).FEU0[0x2c0]=0
FEU_PRD_PROFILE_CFG(3).FEU0[0x2c1]=0
FEU_PRD_PROFILE_CFG(4).FEU0[0x2c2]=0
FEU_PRD_PROFILE_CFG(5).FEU0[0x2c3]=0
FEU_PRD_PROFILE_CFG(6).FEU0[0x2c4]=0
FEU_PRD_PROFILE_CFG(7).FEU0[0x2c5]=0
FEU_PRD_PROFILE_CFG(8).FEU0[0x2c6]=0
FEU_PRD_PROFILE_CFG(9).FEU0[0x2c7]=0
FEU_PRD_PROFILE_CFG(10).FEU0[0x2c8]=0
FEU_PRD_PROFILE_CFG(11).FEU0[0x2c9]=0
FEU_PRD_PROFILE_CFG(12).FEU0[0x2ca]=0
FEU_PRD_PROFILE_CFG(13).FEU0[0x2cb]=0
FEU_PRD_PROFILE_CFG(14).FEU0[0x2cc]=0
FEU_PRD_PROFILE_CFG(15).FEU0[0x2cd]=0
FEU_PRD_PROFILE_CFG(16).FEU0[0x2ce]=0
FEU_PRD_PROFILE_CFG(17).FEU0[0x2cf]=0
FEU_PRD_PROFILE_CFG(18).FEU0[0x2d0]=0
FEU_PRD_PROFILE_CFG(19).FEU0[0x2d1]=0
FEU_PRD_PROFILE_CFG(20).FEU0[0x2d2]=0
FEU_PRD_PROFILE_CFG(21).FEU0[0x2d3]=0
FEU_PRD_PROFILE_CFG(22).FEU0[0x2d4]=0
FEU_PRD_PROFILE_CFG(23).FEU0[0x2d5]=0
FEU_PRD_PROFILE_CFG(24).FEU0[0x2d6]=0
FEU_PRD_PROFILE_CFG(25).FEU0[0x2d7]=0
FEU_PRD_PROFILE_CFG(26).FEU0[0x2d8]=0
FEU_PRD_PROFILE_CFG(27).FEU0[0x2d9]=0
FEU_PRD_PROFILE_CFG(28).FEU0[0x2da]=0
FEU_PRD_PROFILE_CFG(29).FEU0[0x2db]=0
FEU_PRD_PROFILE_CFG(30).FEU0[0x2dc]=0
FEU_PRD_PROFILE_CFG(31).FEU0[0x2dd]=0
FEU_PRD_PROFILE_CFG(32).FEU0[0x2de]=0
FEU_PRD_PROFILE_CFG(33).FEU0[0x2df]=0
FEU_PRD_PROFILE_CFG(34).FEU0[0x2e0]=0
FEU_PRD_PROFILE_CFG(35).FEU0[0x2e1]=0
FEU_PRD_PROFILE_CFG(36).FEU0[0x2e2]=0
FEU_PRD_PROFILE_CFG(37).FEU0[0x2e3]=0
FEU_PRD_PROFILE_CFG(38).FEU0[0x2e4]=0
FEU_PRD_PROFILE_CFG(39).FEU0[0x2e5]=0
FEU_PRD_PROFILE_CFG(40).FEU0[0x2e6]=0
FEU_PRD_PROFILE_CFG(41).FEU0[0x2e7]=0
FEU_PRD_PROFILE_CFG(42).FEU0[0x2e8]=0
FEU_PRD_PROFILE_CFG(43).FEU0[0x2e9]=0
FEU_PRD_PROFILE_CFG(44).FEU0[0x2ea]=0
FEU_PRD_PROFILE_CFG(45).FEU0[0x2eb]=0
FEU_PRD_PROFILE_CFG(46).FEU0[0x2ec]=0
FEU_PRD_PROFILE_CFG(47).FEU0[0x2ed]=0
FEU_PRD_PROFILE_CFG(48).FEU0[0x2ee]=0
FEU_PRD_PROFILE_CFG(49).FEU0[0x2ef]=0
FEU_PRD_PROFILE_CFG(50).FEU0[0x2f0]=0
FEU_PRD_PROFILE_CFG(51).FEU0[0x2f1]=0
FEU_PRD_PROFILE_CFG(52).FEU0[0x2f2]=0
FEU_PRD_PROFILE_CFG(53).FEU0[0x2f3]=0
FEU_PRD_PROFILE_CFG(54).FEU0[0x2f4]=0
FEU_PRD_PROFILE_CFG(55).FEU0[0x2f5]=0
FEU_PRD_PROFILE_CFG(56).FEU0[0x2f6]=0
FEU_PRD_PROFILE_CFG(57).FEU0[0x2f7]=0
FEU_PRD_PROFILE_CFG(58).FEU0[0x2f8]=0
FEU_PRD_PROFILE_CFG(59).FEU0[0x2f9]=0
FEU_PRD_PROFILE_CFG(60).FEU0[0x2fa]=0
FEU_PRD_PROFILE_CFG(61).FEU0[0x2fb]=0
FEU_PRD_PROFILE_CFG(62).FEU0[0x2fc]=0
FEU_PRD_PROFILE_CFG(63).FEU0[0x2fd]=0
FEU_PRD_PROFILE_CFG(64).FEU0[0x2fe]=0
FEU_PRD_PROFILE_CFG(65).FEU0[0x2ff]=0
FEU_PRD_PROFILE_CFG(66).FEU0[0x300]=0
FEU_PRD_PROFILE_CFG(67).FEU0[0x301]=0
FEU_PRD_PROFILE_CFG(68).FEU0[0x302]=0
FEU_PRD_PROFILE_CFG(69).FEU0[0x303]=0
FEU_PRD_PROFILE_CFG(70).FEU0[0x304]=0
FEU_PRD_PROFILE_CFG(71).FEU0[0x305]=0
FEU_PRD_PROFILE_CFG(72).FEU0[0x306]=0
FEU_PRD_PROFILE_CFG(73).FEU0[0x307]=0
FEU_PRD_PROFILE_CFG(74).FEU0[0x308]=0
FEU_PRD_PROFILE_CFG(75).FEU0[0x309]=0
FEU_PRD_PROFILE_CFG(76).FEU0[0x30a]=0
FEU_PRD_PROFILE_CFG(77).FEU0[0x30b]=0
FEU_PRD_PROFILE_CFG(78).FEU0[0x30c]=0
FEU_PRD_PROFILE_CFG(79).FEU0[0x30d]=0
FEU_PRD_PROFILE_CFG(80).FEU0[0x30e]=0
FEU_PRD_PROFILE_CFG(81).FEU0[0x30f]=0
FEU_REG_0041.FEU0[0x41]=0
FEU_REG_00C2.FEU0[0xc2]=0x10
FEU_REG_00C4.FEU0[0xc4]=0
FEU_RESERVED_MTCD.FEU0[0xae]=0x30
FEU_RESERVED_MTCP.FEU0[0xad]=0x300000600000000
FEU_RESERVED_SPARE_0.FEU0[0x90]=0xffffffff
FEU_RESERVED_SPARE_1.FEU0[0x91]=0xffffffff
FEU_RESERVED_SPARE_2.FEU0[0x92]=0
FEU_RESERVED_SPARE_3.FEU0[0x93]=0
FEU_RUNT_PKT_CONFIG.FEU0[0x463]=3
FEU_RX_CLIENT_TO_PRD_PORT_MAP(0).FEU0[0x411]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(1).FEU0[0x412]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(2).FEU0[0x413]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(3).FEU0[0x414]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(4).FEU0[0x415]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(5).FEU0[0x416]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(6).FEU0[0x417]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(7).FEU0[0x418]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(8).FEU0[0x419]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(9).FEU0[0x41a]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(10).FEU0[0x41b]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(11).FEU0[0x41c]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(12).FEU0[0x41d]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(13).FEU0[0x41e]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(14).FEU0[0x41f]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(15).FEU0[0x420]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(16).FEU0[0x421]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(17).FEU0[0x422]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(18).FEU0[0x423]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(19).FEU0[0x424]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(20).FEU0[0x425]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(21).FEU0[0x426]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(22).FEU0[0x427]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(23).FEU0[0x428]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(24).FEU0[0x429]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(25).FEU0[0x42a]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(26).FEU0[0x42b]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(27).FEU0[0x42c]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(28).FEU0[0x42d]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(29).FEU0[0x42e]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(30).FEU0[0x42f]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(31).FEU0[0x430]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(32).FEU0[0x431]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(33).FEU0[0x432]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(34).FEU0[0x433]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(35).FEU0[0x434]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(36).FEU0[0x435]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(37).FEU0[0x436]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(38).FEU0[0x437]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(39).FEU0[0x438]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(40).FEU0[0x439]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(41).FEU0[0x43a]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(42).FEU0[0x43b]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(43).FEU0[0x43c]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(44).FEU0[0x43d]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(45).FEU0[0x43e]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(46).FEU0[0x43f]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(47).FEU0[0x440]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(48).FEU0[0x441]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(49).FEU0[0x442]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(50).FEU0[0x443]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(51).FEU0[0x444]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(52).FEU0[0x445]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(53).FEU0[0x446]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(54).FEU0[0x447]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(55).FEU0[0x448]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(56).FEU0[0x449]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(57).FEU0[0x44a]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(58).FEU0[0x44b]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(59).FEU0[0x44c]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(60).FEU0[0x44d]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(61).FEU0[0x44e]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(62).FEU0[0x44f]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(63).FEU0[0x450]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(64).FEU0[0x451]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(65).FEU0[0x452]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(66).FEU0[0x453]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(67).FEU0[0x454]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(68).FEU0[0x455]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(69).FEU0[0x456]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(70).FEU0[0x457]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(71).FEU0[0x458]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(72).FEU0[0x459]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(73).FEU0[0x45a]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(74).FEU0[0x45b]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(75).FEU0[0x45c]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(76).FEU0[0x45d]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(77).FEU0[0x45e]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(78).FEU0[0x45f]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(79).FEU0[0x460]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(80).FEU0[0x461]=0
FEU_RX_CLIENT_TO_PRD_PORT_MAP(81).FEU0[0x462]=0
FEU_RX_FEC_DECODER_CORRECTED_BIT_CNT(0).FEU0[0x1af0]=0
FEU_RX_FEC_DECODER_CORRECTED_BIT_CNT(1).FEU0[0x1af1]=0
FEU_RX_FEC_DECODER_CORRECTED_BIT_CNT(2).FEU0[0x1af2]=0
FEU_RX_FEC_DECODER_CORRECTED_BIT_CNT(3).FEU0[0x1af3]=0
FEU_RX_FEC_DECODER_CORRECTED_BIT_CNT(4).FEU0[0x1af4]=0
FEU_RX_FEC_DECODER_CORRECTED_BIT_CNT(5).FEU0[0x1af5]=0
FEU_RX_FEC_DECODER_CORRECTED_CODE_WORD_CNT(0).FEU0[0x1ae8]=0
FEU_RX_FEC_DECODER_CORRECTED_CODE_WORD_CNT(1).FEU0[0x1ae9]=0
FEU_RX_FEC_DECODER_CORRECTED_CODE_WORD_CNT(2).FEU0[0x1aea]=0
FEU_RX_FEC_DECODER_CORRECTED_CODE_WORD_CNT(3).FEU0[0x1aeb]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_0(0).FEU0[0x1ad8]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_0(1).FEU0[0x1ad9]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_0(2).FEU0[0x1ada]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_0(3).FEU0[0x1adb]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_1(0).FEU0[0x1adc]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_1(1).FEU0[0x1add]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_1(2).FEU0[0x1ade]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_1(3).FEU0[0x1adf]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_2(0).FEU0[0x1ae0]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_2(1).FEU0[0x1ae1]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_2(2).FEU0[0x1ae2]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_2(3).FEU0[0x1ae3]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_3(0).FEU0[0x1ae4]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_3(1).FEU0[0x1ae5]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_3(2).FEU0[0x1ae6]=0
FEU_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_3(3).FEU0[0x1ae7]=0
FEU_RX_FEC_DECODER_UNCORRECTED_CODE_WORD_CNT(0).FEU0[0x1aec]=0
FEU_RX_FEC_DECODER_UNCORRECTED_CODE_WORD_CNT(1).FEU0[0x1aed]=0
FEU_RX_FEC_DECODER_UNCORRECTED_CODE_WORD_CNT(2).FEU0[0x1aee]=0
FEU_RX_FEC_DECODER_UNCORRECTED_CODE_WORD_CNT(3).FEU0[0x1aef]=0
FEU_RX_FIFOS_SRSTN.FEU0[0x107]=0
FEU_RX_FIRST_MEM_UNIT(0).FEU0[0x1e14]=0
FEU_RX_FIRST_MEM_UNIT(1).FEU0[0x1e15]=0
FEU_RX_FIRST_MEM_UNIT(2).FEU0[0x1e16]=0
FEU_RX_FIRST_MEM_UNIT(3).FEU0[0x1e17]=0
FEU_RX_FIRST_MEM_UNIT(4).FEU0[0x1e18]=0
FEU_RX_FIRST_MEM_UNIT(5).FEU0[0x1e19]=0
FEU_RX_FIRST_MEM_UNIT(6).FEU0[0x1e1a]=0
FEU_RX_FIRST_MEM_UNIT(7).FEU0[0x1e1b]=0
FEU_RX_FIRST_MEM_UNIT(8).FEU0[0x1e1c]=0
FEU_RX_FIRST_MEM_UNIT(9).FEU0[0x1e1d]=0
FEU_RX_FIRST_MEM_UNIT(10).FEU0[0x1e1e]=0
FEU_RX_FIRST_MEM_UNIT(11).FEU0[0x1e1f]=0
FEU_RX_FIRST_MEM_UNIT(12).FEU0[0x1e20]=0
FEU_RX_FIRST_MEM_UNIT(13).FEU0[0x1e21]=0
FEU_RX_FIRST_MEM_UNIT(14).FEU0[0x1e22]=0
FEU_RX_FIRST_MEM_UNIT(15).FEU0[0x1e23]=0
FEU_RX_FIRST_MEM_UNIT(16).FEU0[0x1e24]=0
FEU_RX_FIRST_MEM_UNIT(17).FEU0[0x1e25]=0
FEU_RX_FIRST_MEM_UNIT(18).FEU0[0x1e26]=0
FEU_RX_FIRST_MEM_UNIT(19).FEU0[0x1e27]=0
FEU_RX_FIRST_MEM_UNIT(20).FEU0[0x1e28]=0
FEU_RX_FIRST_MEM_UNIT(21).FEU0[0x1e29]=0
FEU_RX_FIRST_MEM_UNIT(22).FEU0[0x1e2a]=0
FEU_RX_FIRST_MEM_UNIT(23).FEU0[0x1e2b]=0
FEU_RX_FIRST_MEM_UNIT(24).FEU0[0x1e2c]=0
FEU_RX_FIRST_MEM_UNIT(25).FEU0[0x1e2d]=0
FEU_RX_FIRST_MEM_UNIT(26).FEU0[0x1e2e]=0
FEU_RX_FIRST_MEM_UNIT(27).FEU0[0x1e2f]=0
FEU_RX_FIRST_MEM_UNIT(28).FEU0[0x1e30]=0
FEU_RX_FIRST_MEM_UNIT(29).FEU0[0x1e31]=0
FEU_RX_FIRST_MEM_UNIT(30).FEU0[0x1e32]=0
FEU_RX_FIRST_MEM_UNIT(31).FEU0[0x1e33]=0
FEU_RX_FIRST_MEM_UNIT(32).FEU0[0x1e34]=0
FEU_RX_FIRST_MEM_UNIT(33).FEU0[0x1e35]=0
FEU_RX_FIRST_MEM_UNIT(34).FEU0[0x1e36]=0
FEU_RX_FIRST_MEM_UNIT(35).FEU0[0x1e37]=0
FEU_RX_FIRST_MEM_UNIT(36).FEU0[0x1e38]=0
FEU_RX_FIRST_MEM_UNIT(37).FEU0[0x1e39]=0
FEU_RX_FIRST_MEM_UNIT(38).FEU0[0x1e3a]=0
FEU_RX_FIRST_MEM_UNIT(39).FEU0[0x1e3b]=0
FEU_RX_FIRST_MEM_UNIT(40).FEU0[0x1e3c]=0
FEU_RX_FIRST_MEM_UNIT(41).FEU0[0x1e3d]=0
FEU_RX_FIRST_MEM_UNIT(42).FEU0[0x1e3e]=0
FEU_RX_FIRST_MEM_UNIT(43).FEU0[0x1e3f]=0
FEU_RX_FIRST_MEM_UNIT(44).FEU0[0x1e40]=0
FEU_RX_FIRST_MEM_UNIT(45).FEU0[0x1e41]=0
FEU_RX_FIRST_MEM_UNIT(46).FEU0[0x1e42]=0
FEU_RX_FIRST_MEM_UNIT(47).FEU0[0x1e43]=0
FEU_RX_FIRST_MEM_UNIT(48).FEU0[0x1e44]=0
FEU_RX_FIRST_MEM_UNIT(49).FEU0[0x1e45]=0
FEU_RX_FIRST_MEM_UNIT(50).FEU0[0x1e46]=0
FEU_RX_FIRST_MEM_UNIT(51).FEU0[0x1e47]=0
FEU_RX_FIRST_MEM_UNIT(52).FEU0[0x1e48]=0
FEU_RX_FIRST_MEM_UNIT(53).FEU0[0x1e49]=0
FEU_RX_FIRST_MEM_UNIT(54).FEU0[0x1e4a]=0
FEU_RX_FIRST_MEM_UNIT(55).FEU0[0x1e4b]=0
FEU_RX_FIRST_MEM_UNIT(56).FEU0[0x1e4c]=0
FEU_RX_FIRST_MEM_UNIT(57).FEU0[0x1e4d]=0
FEU_RX_FIRST_MEM_UNIT(58).FEU0[0x1e4e]=0
FEU_RX_FIRST_MEM_UNIT(59).FEU0[0x1e4f]=0
FEU_RX_FIRST_MEM_UNIT(60).FEU0[0x1e50]=0
FEU_RX_FIRST_MEM_UNIT(61).FEU0[0x1e51]=0
FEU_RX_FIRST_MEM_UNIT(62).FEU0[0x1e52]=0
FEU_RX_FIRST_MEM_UNIT(63).FEU0[0x1e53]=0
FEU_RX_FIRST_MEM_UNIT(64).FEU0[0x1e54]=0
FEU_RX_FIRST_MEM_UNIT(65).FEU0[0x1e55]=0
FEU_RX_FIRST_MEM_UNIT(66).FEU0[0x1e56]=0
FEU_RX_FIRST_MEM_UNIT(67).FEU0[0x1e57]=0
FEU_RX_FIRST_MEM_UNIT(68).FEU0[0x1e58]=0
FEU_RX_FIRST_MEM_UNIT(69).FEU0[0x1e59]=0
FEU_RX_FIRST_MEM_UNIT(70).FEU0[0x1e5a]=0
FEU_RX_FIRST_MEM_UNIT(71).FEU0[0x1e5b]=0
FEU_RX_FIRST_MEM_UNIT(72).FEU0[0x1e5c]=0
FEU_RX_FIRST_MEM_UNIT(73).FEU0[0x1e5d]=0
FEU_RX_FIRST_MEM_UNIT(74).FEU0[0x1e5e]=0
FEU_RX_FIRST_MEM_UNIT(75).FEU0[0x1e5f]=0
FEU_RX_FIRST_MEM_UNIT(76).FEU0[0x1e60]=0
FEU_RX_FIRST_MEM_UNIT(77).FEU0[0x1e61]=0
FEU_RX_FIRST_MEM_UNIT(78).FEU0[0x1e62]=0
FEU_RX_FIRST_MEM_UNIT(79).FEU0[0x1e63]=0
FEU_RX_FIRST_MEM_UNIT(80).FEU0[0x1e64]=0
FEU_RX_FIRST_MEM_UNIT(81).FEU0[0x1e65]=0
FEU_RX_FIRST_MEM_UNIT(82).FEU0[0x1e66]=0
FEU_RX_FIRST_MEM_UNIT(83).FEU0[0x1e67]=0
FEU_RX_FIRST_MEM_UNIT(84).FEU0[0x1e68]=0
FEU_RX_FIRST_MEM_UNIT(85).FEU0[0x1e69]=0
FEU_RX_FIRST_MEM_UNIT(86).FEU0[0x1e6a]=0
FEU_RX_FIRST_MEM_UNIT(87).FEU0[0x1e6b]=0
FEU_RX_FIRST_MEM_UNIT(88).FEU0[0x1e6c]=0
FEU_RX_FIRST_MEM_UNIT(89).FEU0[0x1e6d]=0
FEU_RX_FIRST_MEM_UNIT(90).FEU0[0x1e6e]=0
FEU_RX_FIRST_MEM_UNIT(91).FEU0[0x1e6f]=0
FEU_RX_FIRST_MEM_UNIT(92).FEU0[0x1e70]=0
FEU_RX_FIRST_MEM_UNIT(93).FEU0[0x1e71]=0
FEU_RX_FIRST_MEM_UNIT(94).FEU0[0x1e72]=0
FEU_RX_FIRST_MEM_UNIT(95).FEU0[0x1e73]=0
FEU_RX_FIRST_MEM_UNIT(96).FEU0[0x1e74]=0
FEU_RX_FIRST_MEM_UNIT(97).FEU0[0x1e75]=0
FEU_RX_FIRST_MEM_UNIT(98).FEU0[0x1e76]=0
FEU_RX_FIRST_MEM_UNIT(99).FEU0[0x1e77]=0
FEU_RX_FIRST_MEM_UNIT(100).FEU0[0x1e78]=0
FEU_RX_FIRST_MEM_UNIT(101).FEU0[0x1e79]=0
FEU_RX_FIRST_MEM_UNIT(102).FEU0[0x1e7a]=0
FEU_RX_FIRST_MEM_UNIT(103).FEU0[0x1e7b]=0
FEU_RX_FIRST_MEM_UNIT(104).FEU0[0x1e7c]=0
FEU_RX_FIRST_MEM_UNIT(105).FEU0[0x1e7d]=0
FEU_RX_FIRST_MEM_UNIT(106).FEU0[0x1e7e]=0
FEU_RX_FIRST_MEM_UNIT(107).FEU0[0x1e7f]=0
FEU_RX_FIRST_MEM_UNIT(108).FEU0[0x1e80]=0
FEU_RX_FIRST_MEM_UNIT(109).FEU0[0x1e81]=0
FEU_RX_FIRST_MEM_UNIT(110).FEU0[0x1e82]=0
FEU_RX_FIRST_MEM_UNIT(111).FEU0[0x1e83]=0
FEU_RX_FIRST_MEM_UNIT(112).FEU0[0x1e84]=0
FEU_RX_FIRST_MEM_UNIT(113).FEU0[0x1e85]=0
FEU_RX_FIRST_MEM_UNIT(114).FEU0[0x1e86]=0
FEU_RX_FIRST_MEM_UNIT(115).FEU0[0x1e87]=0
FEU_RX_FIRST_MEM_UNIT(116).FEU0[0x1e88]=0
FEU_RX_FIRST_MEM_UNIT(117).FEU0[0x1e89]=0
FEU_RX_FIRST_MEM_UNIT(118).FEU0[0x1e8a]=0
FEU_RX_FIRST_MEM_UNIT(119).FEU0[0x1e8b]=0
FEU_RX_FIRST_MEM_UNIT(120).FEU0[0x1e8c]=0
FEU_RX_FIRST_MEM_UNIT(121).FEU0[0x1e8d]=0
FEU_RX_FIRST_MEM_UNIT(122).FEU0[0x1e8e]=0
FEU_RX_FIRST_MEM_UNIT(123).FEU0[0x1e8f]=0
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FEU_RX_FIRST_MEM_UNIT(126).FEU0[0x1e92]=0
FEU_RX_FIRST_MEM_UNIT(127).FEU0[0x1e93]=0
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FEU_RX_MLF_LEVEL(21).FEU0[0x7b2]=0
FEU_RX_MLF_LEVEL(22).FEU0[0x7b4]=0
FEU_RX_MLF_LEVEL(23).FEU0[0x7b6]=0
FEU_RX_MLF_LEVEL(24).FEU0[0x7b8]=0
FEU_RX_MLF_LEVEL(25).FEU0[0x7ba]=0
FEU_RX_MLF_LEVEL(26).FEU0[0x7bc]=0
FEU_RX_MLF_LEVEL(27).FEU0[0x7be]=0
FEU_RX_MLF_LEVEL(28).FEU0[0x7c0]=0
FEU_RX_MLF_LEVEL(29).FEU0[0x7c2]=0
FEU_RX_MLF_LEVEL(30).FEU0[0x7c4]=0
FEU_RX_MLF_LEVEL(31).FEU0[0x7c6]=0
FEU_RX_MLF_LEVEL(32).FEU0[0x7c8]=0
FEU_RX_MLF_LEVEL(33).FEU0[0x7ca]=0
FEU_RX_MLF_LEVEL(34).FEU0[0x7cc]=0
FEU_RX_MLF_LEVEL(35).FEU0[0x7ce]=0
FEU_RX_MLF_LEVEL(36).FEU0[0x7d0]=0
FEU_RX_MLF_LEVEL(37).FEU0[0x7d2]=0
FEU_RX_MLF_LEVEL(38).FEU0[0x7d4]=0
FEU_RX_MLF_LEVEL(39).FEU0[0x7d6]=0
FEU_RX_MLF_LEVEL(40).FEU0[0x7d8]=0
FEU_RX_MLF_LEVEL(41).FEU0[0x7da]=0
FEU_RX_MLF_LEVEL(42).FEU0[0x7dc]=0
FEU_RX_MLF_LEVEL(43).FEU0[0x7de]=0
FEU_RX_MLF_LEVEL(44).FEU0[0x7e0]=0
FEU_RX_MLF_LEVEL(45).FEU0[0x7e2]=0
FEU_RX_MLF_LEVEL(46).FEU0[0x7e4]=0
FEU_RX_MLF_LEVEL(47).FEU0[0x7e6]=0
FEU_RX_MLF_LEVEL(48).FEU0[0x7e8]=0
FEU_RX_MLF_LEVEL(49).FEU0[0x7ea]=0
FEU_RX_MLF_LEVEL(50).FEU0[0x7ec]=0
FEU_RX_MLF_LEVEL(51).FEU0[0x7ee]=0
FEU_RX_MLF_LEVEL(52).FEU0[0x7f0]=0
FEU_RX_MLF_LEVEL(53).FEU0[0x7f2]=0
FEU_RX_MLF_LEVEL(54).FEU0[0x7f4]=0
FEU_RX_MLF_LEVEL(55).FEU0[0x7f6]=0
FEU_RX_MLF_LEVEL(56).FEU0[0x7f8]=0
FEU_RX_MLF_LEVEL(57).FEU0[0x7fa]=0
FEU_RX_MLF_LEVEL(58).FEU0[0x7fc]=0
FEU_RX_MLF_LEVEL(59).FEU0[0x7fe]=0
FEU_RX_MLF_LEVEL(60).FEU0[0x800]=0
FEU_RX_MLF_LEVEL(61).FEU0[0x802]=0
FEU_RX_MLF_LEVEL(62).FEU0[0x804]=0
FEU_RX_MLF_LEVEL(63).FEU0[0x806]=0
FEU_RX_MLF_LEVEL(64).FEU0[0x808]=0
FEU_RX_MLF_LEVEL(65).FEU0[0x80a]=0
FEU_RX_MLF_LEVEL(66).FEU0[0x80c]=0
FEU_RX_MLF_LEVEL(67).FEU0[0x80e]=0
FEU_RX_MLF_LEVEL(68).FEU0[0x810]=0
FEU_RX_MLF_LEVEL(69).FEU0[0x812]=0
FEU_RX_MLF_LEVEL(70).FEU0[0x814]=0
FEU_RX_MLF_LEVEL(71).FEU0[0x816]=0
FEU_RX_MLF_LEVEL(72).FEU0[0x818]=0
FEU_RX_MLF_LEVEL(73).FEU0[0x81a]=0
FEU_RX_MLF_LEVEL(74).FEU0[0x81c]=0
FEU_RX_MLF_LEVEL(75).FEU0[0x81e]=0
FEU_RX_MLF_LEVEL(76).FEU0[0x820]=0
FEU_RX_MLF_LEVEL(77).FEU0[0x822]=0
FEU_RX_MLF_LEVEL(78).FEU0[0x824]=0
FEU_RX_MLF_LEVEL(79).FEU0[0x826]=0
FEU_RX_MLF_LEVEL(80).FEU0[0x828]=0
FEU_RX_MLF_LEVEL(81).FEU0[0x82a]=0
FEU_RX_MLF_LEVEL(82).FEU0[0x82c]=0
FEU_RX_MLF_LEVEL(83).FEU0[0x82e]=0
FEU_RX_MLF_LEVEL(84).FEU0[0x830]=0
FEU_RX_MLF_LEVEL(85).FEU0[0x832]=0
FEU_RX_MLF_LEVEL(86).FEU0[0x834]=0
FEU_RX_MLF_LEVEL(87).FEU0[0x836]=0
FEU_RX_MLF_LEVEL(88).FEU0[0x838]=0
FEU_RX_MLF_LEVEL(89).FEU0[0x83a]=0
FEU_RX_MLF_LEVEL(90).FEU0[0x83c]=0
FEU_RX_MLF_LEVEL(91).FEU0[0x83e]=0
FEU_RX_MLF_LEVEL(92).FEU0[0x840]=0
FEU_RX_MLF_LEVEL(93).FEU0[0x842]=0
FEU_RX_MLF_LEVEL(94).FEU0[0x844]=0
FEU_RX_MLF_LEVEL(95).FEU0[0x846]=0
FEU_RX_MLF_LEVEL(96).FEU0[0x848]=0
FEU_RX_MLF_LEVEL(97).FEU0[0x84a]=0
FEU_RX_MLF_LEVEL(98).FEU0[0x84c]=0
FEU_RX_MLF_LEVEL(99).FEU0[0x84e]=0
FEU_RX_MLF_LEVEL(100).FEU0[0x850]=0
FEU_RX_MLF_LEVEL(101).FEU0[0x852]=0
FEU_RX_MLF_LEVEL(102).FEU0[0x854]=0
FEU_RX_MLF_LEVEL(103).FEU0[0x856]=0
FEU_RX_MLF_LEVEL(104).FEU0[0x858]=0
FEU_RX_MLF_LEVEL(105).FEU0[0x85a]=0
FEU_RX_MLF_LEVEL(106).FEU0[0x85c]=0
FEU_RX_MLF_LEVEL(107).FEU0[0x85e]=0
FEU_RX_MLF_LEVEL(108).FEU0[0x860]=0
FEU_RX_MLF_LEVEL(109).FEU0[0x862]=0
FEU_RX_MLF_LEVEL(110).FEU0[0x864]=0
FEU_RX_MLF_LEVEL(111).FEU0[0x866]=0
FEU_RX_MLF_LEVEL(112).FEU0[0x868]=0
FEU_RX_MLF_LEVEL(113).FEU0[0x86a]=0
FEU_RX_MLF_LEVEL(114).FEU0[0x86c]=0
FEU_RX_MLF_LEVEL(115).FEU0[0x86e]=0
FEU_RX_MLF_LEVEL(116).FEU0[0x870]=0
FEU_RX_MLF_LEVEL(117).FEU0[0x872]=0
FEU_RX_MLF_LEVEL(118).FEU0[0x874]=0
FEU_RX_MLF_LEVEL(119).FEU0[0x876]=0
FEU_RX_MLF_LEVEL(120).FEU0[0x878]=0
FEU_RX_MLF_LEVEL(121).FEU0[0x87a]=0
FEU_RX_MLF_LEVEL(122).FEU0[0x87c]=0
FEU_RX_MLF_LEVEL(123).FEU0[0x87e]=0
FEU_RX_MLF_LEVEL(124).FEU0[0x880]=0
FEU_RX_MLF_LEVEL(125).FEU0[0x882]=0
FEU_RX_MLF_LEVEL(126).FEU0[0x884]=0
FEU_RX_MLF_LEVEL(127).FEU0[0x886]=0
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(0).FEU0[0x588]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(1).FEU0[0x589]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(2).FEU0[0x58a]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(3).FEU0[0x58b]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(4).FEU0[0x58c]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(5).FEU0[0x58d]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(6).FEU0[0x58e]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(7).FEU0[0x58f]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(8).FEU0[0x590]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(9).FEU0[0x591]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(10).FEU0[0x592]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(11).FEU0[0x593]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(12).FEU0[0x594]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(13).FEU0[0x595]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(14).FEU0[0x596]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(15).FEU0[0x597]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(16).FEU0[0x598]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(17).FEU0[0x599]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(18).FEU0[0x59a]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(19).FEU0[0x59b]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(20).FEU0[0x59c]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(21).FEU0[0x59d]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(22).FEU0[0x59e]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(23).FEU0[0x59f]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(24).FEU0[0x5a0]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(25).FEU0[0x5a1]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(26).FEU0[0x5a2]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(27).FEU0[0x5a3]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(28).FEU0[0x5a4]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(29).FEU0[0x5a5]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(30).FEU0[0x5a6]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(31).FEU0[0x5a7]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(32).FEU0[0x5a8]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(33).FEU0[0x5a9]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(34).FEU0[0x5aa]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(35).FEU0[0x5ab]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(36).FEU0[0x5ac]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(37).FEU0[0x5ad]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(38).FEU0[0x5ae]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(39).FEU0[0x5af]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(40).FEU0[0x5b0]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(41).FEU0[0x5b1]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(42).FEU0[0x5b2]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(43).FEU0[0x5b3]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(44).FEU0[0x5b4]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(45).FEU0[0x5b5]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(46).FEU0[0x5b6]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(47).FEU0[0x5b7]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(48).FEU0[0x5b8]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(49).FEU0[0x5b9]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(50).FEU0[0x5ba]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(51).FEU0[0x5bb]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(52).FEU0[0x5bc]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(53).FEU0[0x5bd]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(54).FEU0[0x5be]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(55).FEU0[0x5bf]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(56).FEU0[0x5c0]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(57).FEU0[0x5c1]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(58).FEU0[0x5c2]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(59).FEU0[0x5c3]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(60).FEU0[0x5c4]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(61).FEU0[0x5c5]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(62).FEU0[0x5c6]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(63).FEU0[0x5c7]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(64).FEU0[0x5c8]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(65).FEU0[0x5c9]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(66).FEU0[0x5ca]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(67).FEU0[0x5cb]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(68).FEU0[0x5cc]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(69).FEU0[0x5cd]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(70).FEU0[0x5ce]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(71).FEU0[0x5cf]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(72).FEU0[0x5d0]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(73).FEU0[0x5d1]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(74).FEU0[0x5d2]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(75).FEU0[0x5d3]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(76).FEU0[0x5d4]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(77).FEU0[0x5d5]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(78).FEU0[0x5d6]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(79).FEU0[0x5d7]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(80).FEU0[0x5d8]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(81).FEU0[0x5d9]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(82).FEU0[0x5da]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(83).FEU0[0x5db]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(84).FEU0[0x5dc]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(85).FEU0[0x5dd]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(86).FEU0[0x5de]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(87).FEU0[0x5df]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(88).FEU0[0x5e0]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(89).FEU0[0x5e1]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(90).FEU0[0x5e2]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(91).FEU0[0x5e3]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(92).FEU0[0x5e4]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(93).FEU0[0x5e5]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(94).FEU0[0x5e6]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(95).FEU0[0x5e7]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(96).FEU0[0x5e8]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(97).FEU0[0x5e9]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(98).FEU0[0x5ea]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(99).FEU0[0x5eb]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(100).FEU0[0x5ec]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(101).FEU0[0x5ed]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(102).FEU0[0x5ee]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(103).FEU0[0x5ef]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(104).FEU0[0x5f0]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(105).FEU0[0x5f1]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(106).FEU0[0x5f2]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(107).FEU0[0x5f3]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(108).FEU0[0x5f4]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(109).FEU0[0x5f5]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(110).FEU0[0x5f6]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(111).FEU0[0x5f7]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(112).FEU0[0x5f8]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(113).FEU0[0x5f9]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(114).FEU0[0x5fa]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(115).FEU0[0x5fb]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(116).FEU0[0x5fc]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(117).FEU0[0x5fd]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(118).FEU0[0x5fe]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(119).FEU0[0x5ff]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(120).FEU0[0x600]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(121).FEU0[0x601]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(122).FEU0[0x602]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(123).FEU0[0x603]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(124).FEU0[0x604]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(125).FEU0[0x605]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(126).FEU0[0x606]=0xfc0200
FEU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC(127).FEU0[0x607]=0xfc0200
FEU_RX_MLF_MAX_OCCUPANCY(0).FEU0[0x888]=0
FEU_RX_MLF_MAX_OCCUPANCY(1).FEU0[0x88a]=0
FEU_RX_MLF_MAX_OCCUPANCY(2).FEU0[0x88c]=0
FEU_RX_MLF_MAX_OCCUPANCY(3).FEU0[0x88e]=0
FEU_RX_MLF_MAX_OCCUPANCY(4).FEU0[0x890]=0
FEU_RX_MLF_MAX_OCCUPANCY(5).FEU0[0x892]=0
FEU_RX_MLF_MAX_OCCUPANCY(6).FEU0[0x894]=0
FEU_RX_MLF_MAX_OCCUPANCY(7).FEU0[0x896]=0
FEU_RX_MLF_MAX_OCCUPANCY(8).FEU0[0x898]=0
FEU_RX_MLF_MAX_OCCUPANCY(9).FEU0[0x89a]=0
FEU_RX_MLF_MAX_OCCUPANCY(10).FEU0[0x89c]=0
FEU_RX_MLF_MAX_OCCUPANCY(11).FEU0[0x89e]=0
FEU_RX_MLF_MAX_OCCUPANCY(12).FEU0[0x8a0]=0
FEU_RX_MLF_MAX_OCCUPANCY(13).FEU0[0x8a2]=0
FEU_RX_MLF_MAX_OCCUPANCY(14).FEU0[0x8a4]=0
FEU_RX_MLF_MAX_OCCUPANCY(15).FEU0[0x8a6]=0
FEU_RX_MLF_MAX_OCCUPANCY(16).FEU0[0x8a8]=0
FEU_RX_MLF_MAX_OCCUPANCY(17).FEU0[0x8aa]=0
FEU_RX_MLF_MAX_OCCUPANCY(18).FEU0[0x8ac]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(96).FEU0[0x12a0]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(99).FEU0[0x12a3]=0
FEU_RX_PKT_PRD_DROP_COUNTER(100).FEU0[0x12a4]=0
FEU_RX_PKT_PRD_DROP_COUNTER(101).FEU0[0x12a5]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(104).FEU0[0x12a8]=0
FEU_RX_PKT_PRD_DROP_COUNTER(105).FEU0[0x12a9]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(107).FEU0[0x12ab]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(113).FEU0[0x12b1]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(115).FEU0[0x12b3]=0
FEU_RX_PKT_PRD_DROP_COUNTER(116).FEU0[0x12b4]=0
FEU_RX_PKT_PRD_DROP_COUNTER(117).FEU0[0x12b5]=0
FEU_RX_PKT_PRD_DROP_COUNTER(118).FEU0[0x12b6]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(120).FEU0[0x12b8]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(125).FEU0[0x12bd]=0
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FEU_RX_PKT_PRD_DROP_COUNTER(127).FEU0[0x12bf]=0
FEU_RX_PORT_MAP_IS_INVALID(0).FEU0[0x15dd]=0
FEU_RX_PORT_MAP_IS_INVALID(1).FEU0[0x15de]=0
FEU_RX_PORT_MAP_IS_INVALID(2).FEU0[0x15df]=0
FEU_RX_PORT_MAP_IS_INVALID(3).FEU0[0x15e0]=0
FEU_RX_PORT_MAP_IS_INVALID(4).FEU0[0x15e1]=0
FEU_RX_PORT_MAP_IS_INVALID(5).FEU0[0x15e2]=0
FEU_RX_PORT_MAP_IS_INVALID(6).FEU0[0x15e3]=0
FEU_RX_PORT_MAP_IS_INVALID(7).FEU0[0x15e4]=0
FEU_RX_PORT_MAP_IS_INVALID(8).FEU0[0x15e5]=0
FEU_RX_PORT_MAP_IS_INVALID(9).FEU0[0x15e6]=0
FEU_RX_PORT_MAP_IS_INVALID(10).FEU0[0x15e7]=0
FEU_RX_PORT_MAP_IS_INVALID(11).FEU0[0x15e8]=0
FEU_RX_PORT_MAP_IS_INVALID(12).FEU0[0x15e9]=0
FEU_RX_PORT_MAP_IS_INVALID(13).FEU0[0x15ea]=0
FEU_RX_PORT_MAP_IS_INVALID(14).FEU0[0x15eb]=0
FEU_RX_PORT_MAP_IS_INVALID(15).FEU0[0x15ec]=0
FEU_RX_PORT_MAP_IS_INVALID(16).FEU0[0x15ed]=0
FEU_RX_PORT_MAP_IS_INVALID(17).FEU0[0x15ee]=0
FEU_RX_PORT_MAP_IS_INVALID(18).FEU0[0x15ef]=0
FEU_RX_PORT_MAP_IS_INVALID(19).FEU0[0x15f0]=0
FEU_RX_PORT_MAP_IS_INVALID(20).FEU0[0x15f1]=0
FEU_RX_PORT_MAP_IS_INVALID(21).FEU0[0x15f2]=0
FEU_RX_PORT_MAP_IS_INVALID(22).FEU0[0x15f3]=0
FEU_RX_PORT_MAP_IS_INVALID(23).FEU0[0x15f4]=0
FEU_RX_PORT_MAP_IS_INVALID(24).FEU0[0x15f5]=0
FEU_RX_PORT_MAP_IS_INVALID(25).FEU0[0x15f6]=0
FEU_RX_PORT_MAP_IS_INVALID(26).FEU0[0x15f7]=0
FEU_RX_PORT_MAP_IS_INVALID(27).FEU0[0x15f8]=0
FEU_RX_PORT_MAP_IS_INVALID(28).FEU0[0x15f9]=0
FEU_RX_PORT_MAP_IS_INVALID(29).FEU0[0x15fa]=0
FEU_RX_PORT_MAP_IS_INVALID(30).FEU0[0x15fb]=0
FEU_RX_PORT_MAP_IS_INVALID(31).FEU0[0x15fc]=0
FEU_RX_PORT_MAP_IS_INVALID(32).FEU0[0x15fd]=0
FEU_RX_PORT_MAP_IS_INVALID(33).FEU0[0x15fe]=0
FEU_RX_PORT_MAP_IS_INVALID(34).FEU0[0x15ff]=0
FEU_RX_PORT_MAP_IS_INVALID(35).FEU0[0x1600]=0
FEU_RX_PORT_MAP_IS_INVALID(36).FEU0[0x1601]=0
FEU_RX_PORT_MAP_IS_INVALID(37).FEU0[0x1602]=0
FEU_RX_PORT_MAP_IS_INVALID(38).FEU0[0x1603]=0
FEU_RX_PORT_MAP_IS_INVALID(39).FEU0[0x1604]=0
FEU_RX_PORT_MAP_IS_INVALID(40).FEU0[0x1605]=0
FEU_RX_PORT_MAP_IS_INVALID(41).FEU0[0x1606]=0
FEU_RX_PORT_MAP_IS_INVALID(42).FEU0[0x1607]=0
FEU_RX_PORT_MAP_IS_INVALID(43).FEU0[0x1608]=0
FEU_RX_PORT_MAP_IS_INVALID(44).FEU0[0x1609]=0
FEU_RX_PORT_MAP_IS_INVALID(45).FEU0[0x160a]=0
FEU_RX_PORT_MAP_IS_INVALID(46).FEU0[0x160b]=0
FEU_RX_PORT_MAP_IS_INVALID(47).FEU0[0x160c]=0
FEU_RX_PORT_MAP_IS_INVALID(48).FEU0[0x160d]=0
FEU_RX_PORT_MAP_IS_INVALID(49).FEU0[0x160e]=0
FEU_RX_PORT_MAP_IS_INVALID(50).FEU0[0x160f]=0
FEU_RX_PORT_MAP_IS_INVALID(51).FEU0[0x1610]=0
FEU_RX_PORT_MAP_IS_INVALID(52).FEU0[0x1611]=0
FEU_RX_PORT_MAP_IS_INVALID(53).FEU0[0x1612]=0
FEU_RX_PORT_MAP_IS_INVALID(54).FEU0[0x1613]=0
FEU_RX_PORT_MAP_IS_INVALID(55).FEU0[0x1614]=0
FEU_RX_PORT_MAP_IS_INVALID(56).FEU0[0x1615]=0
FEU_RX_PORT_MAP_IS_INVALID(57).FEU0[0x1616]=0
FEU_RX_PORT_MAP_IS_INVALID(58).FEU0[0x1617]=0
FEU_RX_PORT_MAP_IS_INVALID(59).FEU0[0x1618]=0
FEU_RX_PORT_MAP_IS_INVALID(60).FEU0[0x1619]=0
FEU_RX_PORT_MAP_IS_INVALID(61).FEU0[0x161a]=0
FEU_RX_PORT_MAP_IS_INVALID(62).FEU0[0x161b]=0
FEU_RX_PORT_MAP_IS_INVALID(63).FEU0[0x161c]=0
FEU_RX_PORT_MAP_IS_INVALID(64).FEU0[0x161d]=0
FEU_RX_PORT_MAP_IS_INVALID(65).FEU0[0x161e]=0
FEU_RX_PORT_MAP_IS_INVALID(66).FEU0[0x161f]=0
FEU_RX_PORT_MAP_IS_INVALID(67).FEU0[0x1620]=0
FEU_RX_PORT_MAP_IS_INVALID(68).FEU0[0x1621]=0
FEU_RX_PORT_MAP_IS_INVALID(69).FEU0[0x1622]=0
FEU_RX_PORT_MAP_IS_INVALID(70).FEU0[0x1623]=0
FEU_RX_PORT_MAP_IS_INVALID(71).FEU0[0x1624]=0
FEU_RX_PORT_MAP_IS_INVALID(72).FEU0[0x1625]=0
FEU_RX_PORT_MAP_IS_INVALID(73).FEU0[0x1626]=0
FEU_RX_PORT_MAP_IS_INVALID(74).FEU0[0x1627]=0
FEU_RX_PORT_MAP_IS_INVALID(75).FEU0[0x1628]=0
FEU_RX_PORT_MAP_IS_INVALID(76).FEU0[0x1629]=0
FEU_RX_PORT_MAP_IS_INVALID(77).FEU0[0x162a]=0
FEU_RX_PORT_MAP_IS_INVALID(78).FEU0[0x162b]=0
FEU_RX_PORT_MAP_IS_INVALID(79).FEU0[0x162c]=0
FEU_RX_PORT_MAP_IS_INVALID(80).FEU0[0x162d]=0
FEU_RX_PORT_MAP_IS_INVALID(81).FEU0[0x162e]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(0).FEU0[0x162f]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(1).FEU0[0x1630]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(2).FEU0[0x1631]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(3).FEU0[0x1632]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(4).FEU0[0x1633]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(5).FEU0[0x1634]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(6).FEU0[0x1635]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(7).FEU0[0x1636]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(8).FEU0[0x1637]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(9).FEU0[0x1638]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(10).FEU0[0x1639]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(11).FEU0[0x163a]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(12).FEU0[0x163b]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(13).FEU0[0x163c]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(14).FEU0[0x163d]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(15).FEU0[0x163e]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(16).FEU0[0x163f]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(17).FEU0[0x1640]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(18).FEU0[0x1641]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(19).FEU0[0x1642]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(20).FEU0[0x1643]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(21).FEU0[0x1644]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(22).FEU0[0x1645]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(23).FEU0[0x1646]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(24).FEU0[0x1647]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(25).FEU0[0x1648]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(26).FEU0[0x1649]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(27).FEU0[0x164a]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(28).FEU0[0x164b]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(29).FEU0[0x164c]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(30).FEU0[0x164d]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(31).FEU0[0x164e]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(32).FEU0[0x164f]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(33).FEU0[0x1650]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(34).FEU0[0x1651]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(35).FEU0[0x1652]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(36).FEU0[0x1653]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(37).FEU0[0x1654]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(38).FEU0[0x1655]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(39).FEU0[0x1656]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(40).FEU0[0x1657]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(41).FEU0[0x1658]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(42).FEU0[0x1659]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(43).FEU0[0x165a]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(44).FEU0[0x165b]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(45).FEU0[0x165c]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(46).FEU0[0x165d]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(47).FEU0[0x165e]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(48).FEU0[0x165f]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(49).FEU0[0x1660]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(50).FEU0[0x1661]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(51).FEU0[0x1662]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(52).FEU0[0x1663]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(53).FEU0[0x1664]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(54).FEU0[0x1665]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(55).FEU0[0x1666]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(56).FEU0[0x1667]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(57).FEU0[0x1668]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(58).FEU0[0x1669]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(59).FEU0[0x166a]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(60).FEU0[0x166b]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(61).FEU0[0x166c]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(62).FEU0[0x166d]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(63).FEU0[0x166e]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(64).FEU0[0x166f]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(65).FEU0[0x1670]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(66).FEU0[0x1671]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(67).FEU0[0x1672]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(68).FEU0[0x1673]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(69).FEU0[0x1674]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(70).FEU0[0x1675]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(71).FEU0[0x1676]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(72).FEU0[0x1677]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(73).FEU0[0x1678]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(74).FEU0[0x1679]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(75).FEU0[0x167a]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(76).FEU0[0x167b]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(77).FEU0[0x167c]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(78).FEU0[0x167d]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(79).FEU0[0x167e]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(80).FEU0[0x167f]=0
FEU_RX_PORT_MAP_IS_INVALID_PARAM(81).FEU0[0x1680]=0
FEU_RX_PORT_MAP_MASK_PARSER_TDM.FEU0[0x16d3]=6
FEU_RX_RMCDEFINTION(0).FEU0[0x1bcb]=0
FEU_RX_RMCDEFINTION(1).FEU0[0x1bcc]=0
FEU_RX_RMCDEFINTION(2).FEU0[0x1bcd]=0
FEU_RX_RMCDEFINTION(3).FEU0[0x1bce]=0
FEU_RX_RMCDEFINTION(4).FEU0[0x1bcf]=0
FEU_RX_RMCDEFINTION(5).FEU0[0x1bd0]=0
FEU_RX_RMCDEFINTION(6).FEU0[0x1bd1]=0
FEU_RX_RMCDEFINTION(7).FEU0[0x1bd2]=0
FEU_RX_RMCDEFINTION(8).FEU0[0x1bd3]=0
FEU_RX_RMCDEFINTION(9).FEU0[0x1bd4]=0
FEU_RX_RMCDEFINTION(10).FEU0[0x1bd5]=0
FEU_RX_RMCDEFINTION(11).FEU0[0x1bd6]=0
FEU_RX_RMCDEFINTION(12).FEU0[0x1bd7]=0
FEU_RX_RMCDEFINTION(13).FEU0[0x1bd8]=0
FEU_RX_RMCDEFINTION(14).FEU0[0x1bd9]=0
FEU_RX_RMCDEFINTION(15).FEU0[0x1bda]=0
FEU_RX_RMCDEFINTION(16).FEU0[0x1bdb]=0
FEU_RX_RMCDEFINTION(17).FEU0[0x1bdc]=0
FEU_RX_RMCDEFINTION(18).FEU0[0x1bdd]=0
FEU_RX_RMCDEFINTION(19).FEU0[0x1bde]=0
FEU_RX_RMCDEFINTION(20).FEU0[0x1bdf]=0
FEU_RX_RMCDEFINTION(21).FEU0[0x1be0]=0
FEU_RX_RMCDEFINTION(22).FEU0[0x1be1]=0
FEU_RX_RMCDEFINTION(23).FEU0[0x1be2]=0
FEU_RX_RMCDEFINTION(24).FEU0[0x1be3]=0
FEU_RX_RMCDEFINTION(25).FEU0[0x1be4]=0
FEU_RX_RMCDEFINTION(26).FEU0[0x1be5]=0
FEU_RX_RMCDEFINTION(27).FEU0[0x1be6]=0
FEU_RX_RMCDEFINTION(28).FEU0[0x1be7]=0
FEU_RX_RMCDEFINTION(29).FEU0[0x1be8]=0
FEU_RX_RMCDEFINTION(30).FEU0[0x1be9]=0
FEU_RX_RMCDEFINTION(31).FEU0[0x1bea]=0
FEU_RX_RMCDEFINTION(32).FEU0[0x1beb]=0
FEU_RX_RMCDEFINTION(33).FEU0[0x1bec]=0
FEU_RX_RMCDEFINTION(34).FEU0[0x1bed]=0
FEU_RX_RMCDEFINTION(35).FEU0[0x1bee]=0
FEU_RX_RMCDEFINTION(36).FEU0[0x1bef]=0
FEU_RX_RMCDEFINTION(37).FEU0[0x1bf0]=0
FEU_RX_RMCDEFINTION(38).FEU0[0x1bf1]=0
FEU_RX_RMCDEFINTION(39).FEU0[0x1bf2]=0
FEU_RX_RMCDEFINTION(40).FEU0[0x1bf3]=0
FEU_RX_RMCDEFINTION(41).FEU0[0x1bf4]=0
FEU_RX_RMCDEFINTION(42).FEU0[0x1bf5]=0
FEU_RX_RMCDEFINTION(43).FEU0[0x1bf6]=0
FEU_RX_RMCDEFINTION(44).FEU0[0x1bf7]=0
FEU_RX_RMCDEFINTION(45).FEU0[0x1bf8]=0
FEU_RX_RMCDEFINTION(46).FEU0[0x1bf9]=0
FEU_RX_RMCDEFINTION(47).FEU0[0x1bfa]=0
FEU_RX_RMCDEFINTION(48).FEU0[0x1bfb]=0
FEU_RX_RMCDEFINTION(49).FEU0[0x1bfc]=0
FEU_RX_RMCDEFINTION(50).FEU0[0x1bfd]=0
FEU_RX_RMCDEFINTION(51).FEU0[0x1bfe]=0
FEU_RX_RMCDEFINTION(52).FEU0[0x1bff]=0
FEU_RX_RMCDEFINTION(53).FEU0[0x1c00]=0
FEU_RX_RMCDEFINTION(54).FEU0[0x1c01]=0
FEU_RX_RMCDEFINTION(55).FEU0[0x1c02]=0
FEU_RX_RMCDEFINTION(56).FEU0[0x1c03]=0
FEU_RX_RMCDEFINTION(57).FEU0[0x1c04]=0
FEU_RX_RMCDEFINTION(58).FEU0[0x1c05]=0
FEU_RX_RMCDEFINTION(59).FEU0[0x1c06]=0
FEU_RX_RMCDEFINTION(60).FEU0[0x1c07]=0
FEU_RX_RMCDEFINTION(61).FEU0[0x1c08]=0
FEU_RX_RMCDEFINTION(62).FEU0[0x1c09]=0
FEU_RX_RMCDEFINTION(63).FEU0[0x1c0a]=0
FEU_RX_RMCDEFINTION(64).FEU0[0x1c0b]=0
FEU_RX_RMCDEFINTION(65).FEU0[0x1c0c]=0
FEU_RX_RMCDEFINTION(66).FEU0[0x1c0d]=0
FEU_RX_RMCDEFINTION(67).FEU0[0x1c0e]=0
FEU_RX_RMCDEFINTION(68).FEU0[0x1c0f]=0
FEU_RX_RMCDEFINTION(69).FEU0[0x1c10]=0
FEU_RX_RMCDEFINTION(70).FEU0[0x1c11]=0
FEU_RX_RMCDEFINTION(71).FEU0[0x1c12]=0
FEU_RX_RMCDEFINTION(72).FEU0[0x1c13]=0
FEU_RX_RMCDEFINTION(73).FEU0[0x1c14]=0
FEU_RX_RMCDEFINTION(74).FEU0[0x1c15]=0
FEU_RX_RMCDEFINTION(75).FEU0[0x1c16]=0
FEU_RX_RMCDEFINTION(76).FEU0[0x1c17]=0
FEU_RX_RMCDEFINTION(77).FEU0[0x1c18]=0
FEU_RX_RMCDEFINTION(78).FEU0[0x1c19]=0
FEU_RX_RMCDEFINTION(79).FEU0[0x1c1a]=0
FEU_RX_RMCDEFINTION(80).FEU0[0x1c1b]=0
FEU_RX_RMCDEFINTION(81).FEU0[0x1c1c]=0
FEU_RX_RMCDEFINTION(82).FEU0[0x1c1d]=0
FEU_RX_RMCDEFINTION(83).FEU0[0x1c1e]=0
FEU_RX_RMCDEFINTION(84).FEU0[0x1c1f]=0
FEU_RX_RMCDEFINTION(85).FEU0[0x1c20]=0
FEU_RX_RMCDEFINTION(86).FEU0[0x1c21]=0
FEU_RX_RMCDEFINTION(87).FEU0[0x1c22]=0
FEU_RX_RMCDEFINTION(88).FEU0[0x1c23]=0
FEU_RX_RMCDEFINTION(89).FEU0[0x1c24]=0
FEU_RX_RMCDEFINTION(90).FEU0[0x1c25]=0
FEU_RX_RMCDEFINTION(91).FEU0[0x1c26]=0
FEU_RX_RMCDEFINTION(92).FEU0[0x1c27]=0
FEU_RX_RMCDEFINTION(93).FEU0[0x1c28]=0
FEU_RX_RMCDEFINTION(94).FEU0[0x1c29]=0
FEU_RX_RMCDEFINTION(95).FEU0[0x1c2a]=0
FEU_RX_RMCDEFINTION(96).FEU0[0x1c2b]=0
FEU_RX_RMCDEFINTION(97).FEU0[0x1c2c]=0
FEU_RX_RMCDEFINTION(98).FEU0[0x1c2d]=0
FEU_RX_RMCDEFINTION(99).FEU0[0x1c2e]=0
FEU_RX_RMCDEFINTION(100).FEU0[0x1c2f]=0
FEU_RX_RMCDEFINTION(101).FEU0[0x1c30]=0
FEU_RX_RMCDEFINTION(102).FEU0[0x1c31]=0
FEU_RX_RMCDEFINTION(103).FEU0[0x1c32]=0
FEU_RX_RMCDEFINTION(104).FEU0[0x1c33]=0
FEU_RX_RMCDEFINTION(105).FEU0[0x1c34]=0
FEU_RX_RMCDEFINTION(106).FEU0[0x1c35]=0
FEU_RX_RMCDEFINTION(107).FEU0[0x1c36]=0
FEU_RX_RMCDEFINTION(108).FEU0[0x1c37]=0
FEU_RX_RMCDEFINTION(109).FEU0[0x1c38]=0
FEU_RX_RMCDEFINTION(110).FEU0[0x1c39]=0
FEU_RX_RMCDEFINTION(111).FEU0[0x1c3a]=0
FEU_RX_RMCDEFINTION(112).FEU0[0x1c3b]=0
FEU_RX_RMCDEFINTION(113).FEU0[0x1c3c]=0
FEU_RX_RMCDEFINTION(114).FEU0[0x1c3d]=0
FEU_RX_RMCDEFINTION(115).FEU0[0x1c3e]=0
FEU_RX_RMCDEFINTION(116).FEU0[0x1c3f]=0
FEU_RX_RMCDEFINTION(117).FEU0[0x1c40]=0
FEU_RX_RMCDEFINTION(118).FEU0[0x1c41]=0
FEU_RX_RMCDEFINTION(119).FEU0[0x1c42]=0
FEU_RX_RMCDEFINTION(120).FEU0[0x1c43]=0
FEU_RX_RMCDEFINTION(121).FEU0[0x1c44]=0
FEU_RX_RMCDEFINTION(122).FEU0[0x1c45]=0
FEU_RX_RMCDEFINTION(123).FEU0[0x1c46]=0
FEU_RX_RMCDEFINTION(124).FEU0[0x1c47]=0
FEU_RX_RMCDEFINTION(125).FEU0[0x1c48]=0
FEU_RX_RMCDEFINTION(126).FEU0[0x1c49]=0
FEU_RX_RMCDEFINTION(127).FEU0[0x1c4a]=0
FEU_RX_RMC_L_1_CFG_2(0).FEU0[0x16d4]=0x3f
FEU_RX_RMC_L_1_CFG_2(1).FEU0[0x16d5]=0x3f
FEU_RX_RMC_L_1_CFG_2(2).FEU0[0x16d6]=0x3f
FEU_RX_RMC_L_1_CFG_2(3).FEU0[0x16d7]=0x3f
FEU_RX_RMC_L_1_CFG_2(4).FEU0[0x16d8]=0x3f
FEU_RX_RMC_L_1_CFG_2(5).FEU0[0x16d9]=0x3f
FEU_RX_RMC_L_1_CFG_2(6).FEU0[0x16da]=0x3f
FEU_RX_RMC_L_1_CFG_2(7).FEU0[0x16db]=0x3f
FEU_RX_RMC_L_1_CFG_2(8).FEU0[0x16dc]=0x3f
FEU_RX_RMC_L_1_CFG_2(9).FEU0[0x16dd]=0x3f
FEU_RX_RMC_L_1_CFG_2(10).FEU0[0x16de]=0x3f
FEU_RX_RMC_L_1_CFG_2(11).FEU0[0x16df]=0x3f
FEU_RX_RMC_L_1_CFG_2(12).FEU0[0x16e0]=0x3f
FEU_RX_RMC_L_1_CFG_2(13).FEU0[0x16e1]=0x3f
FEU_RX_RMC_L_1_CFG_2(14).FEU0[0x16e2]=0x3f
FEU_RX_RMC_L_1_CFG_2(15).FEU0[0x16e3]=0x3f
FEU_RX_RMC_L_1_CFG_2(16).FEU0[0x16e4]=0x3f
FEU_RX_RMC_L_1_CFG_2(17).FEU0[0x16e5]=0x3f
FEU_RX_RMC_L_1_CFG_2(18).FEU0[0x16e6]=0x3f
FEU_RX_RMC_L_1_CFG_2(19).FEU0[0x16e7]=0x3f
FEU_RX_RMC_L_1_CFG_2(20).FEU0[0x16e8]=0x3f
FEU_RX_RMC_L_1_CFG_2(21).FEU0[0x16e9]=0x3f
FEU_RX_RMC_L_1_CFG_2(22).FEU0[0x16ea]=0x3f
FEU_RX_RMC_L_1_CFG_2(23).FEU0[0x16eb]=0x3f
FEU_RX_RMC_L_1_CFG_2(24).FEU0[0x16ec]=0x3f
FEU_RX_RMC_L_1_CFG_2(25).FEU0[0x16ed]=0x3f
FEU_RX_RMC_L_1_CFG_2(26).FEU0[0x16ee]=0x3f
FEU_RX_RMC_L_1_CFG_2(27).FEU0[0x16ef]=0x3f
FEU_RX_RMC_L_1_CFG_2(28).FEU0[0x16f0]=0x3f
FEU_RX_RMC_L_1_CFG_2(29).FEU0[0x16f1]=0x3f
FEU_RX_RMC_L_1_CFG_2(30).FEU0[0x16f2]=0x3f
FEU_RX_RMC_L_1_CFG_2(31).FEU0[0x16f3]=0x3f
FEU_RX_RMC_L_1_CFG_2(32).FEU0[0x16f4]=0x3f
FEU_RX_RMC_L_1_CFG_2(33).FEU0[0x16f5]=0x3f
FEU_RX_RMC_L_1_CFG_2(34).FEU0[0x16f6]=0x3f
FEU_RX_RMC_L_1_CFG_2(35).FEU0[0x16f7]=0x3f
FEU_RX_RMC_L_1_CFG_2(36).FEU0[0x16f8]=0x3f
FEU_RX_RMC_L_1_CFG_2(37).FEU0[0x16f9]=0x3f
FEU_RX_RMC_L_1_CFG_2(38).FEU0[0x16fa]=0x3f
FEU_RX_RMC_L_1_CFG_2(39).FEU0[0x16fb]=0x3f
FEU_RX_RMC_L_1_CFG_2(40).FEU0[0x16fc]=0x3f
FEU_RX_RMC_L_1_CFG_2(41).FEU0[0x16fd]=0x3f
FEU_RX_RMC_L_1_CFG_2(42).FEU0[0x16fe]=0x3f
FEU_RX_RMC_L_1_CFG_2(43).FEU0[0x16ff]=0x3f
FEU_RX_RMC_L_1_CFG_2(44).FEU0[0x1700]=0x3f
FEU_RX_RMC_L_1_CFG_2(45).FEU0[0x1701]=0x3f
FEU_RX_RMC_L_1_CFG_2(46).FEU0[0x1702]=0x3f
FEU_RX_RMC_L_1_CFG_2(47).FEU0[0x1703]=0x3f
FEU_RX_RMC_L_1_CFG_2(48).FEU0[0x1704]=0x3f
FEU_RX_RMC_L_1_CFG_2(49).FEU0[0x1705]=0x3f
FEU_RX_RMC_L_1_CFG_2(50).FEU0[0x1706]=0x3f
FEU_RX_RMC_L_1_CFG_2(51).FEU0[0x1707]=0x3f
FEU_RX_RMC_L_1_CFG_2(52).FEU0[0x1708]=0x3f
FEU_RX_RMC_L_1_CFG_2(53).FEU0[0x1709]=0x3f
FEU_RX_RMC_L_1_CFG_2(54).FEU0[0x170a]=0x3f
FEU_RX_RMC_L_1_CFG_2(55).FEU0[0x170b]=0x3f
FEU_RX_RMC_L_1_CFG_2(56).FEU0[0x170c]=0x3f
FEU_RX_RMC_L_1_CFG_2(57).FEU0[0x170d]=0x3f
FEU_RX_RMC_L_1_CFG_2(58).FEU0[0x170e]=0x3f
FEU_RX_RMC_L_1_CFG_2(59).FEU0[0x170f]=0x3f
FEU_RX_RMC_L_1_CFG_2(60).FEU0[0x1710]=0x3f
FEU_RX_RMC_L_1_CFG_2(61).FEU0[0x1711]=0x3f
FEU_RX_RMC_L_1_CFG_2(62).FEU0[0x1712]=0x3f
FEU_RX_RMC_L_1_CFG_2(63).FEU0[0x1713]=0x3f
FEU_RX_RMC_L_1_CFG_2(64).FEU0[0x1714]=0x3f
FEU_RX_RMC_L_1_CFG_2(65).FEU0[0x1715]=0x3f
FEU_RX_RMC_L_1_CFG_2(66).FEU0[0x1716]=0x3f
FEU_RX_RMC_L_1_CFG_2(67).FEU0[0x1717]=0x3f
FEU_RX_RMC_L_1_CFG_2(68).FEU0[0x1718]=0x3f
FEU_RX_RMC_L_1_CFG_2(69).FEU0[0x1719]=0x3f
FEU_RX_RMC_L_1_CFG_2(70).FEU0[0x171a]=0x3f
FEU_RX_RMC_L_1_CFG_2(71).FEU0[0x171b]=0x3f
FEU_RX_RMC_L_1_CFG_2(72).FEU0[0x171c]=0x3f
FEU_RX_RMC_L_1_CFG_2(73).FEU0[0x171d]=0x3f
FEU_RX_RMC_L_1_CFG_2(74).FEU0[0x171e]=0x3f
FEU_RX_RMC_L_1_CFG_2(75).FEU0[0x171f]=0x3f
FEU_RX_RMC_L_1_CFG_2(76).FEU0[0x1720]=0x3f
FEU_RX_RMC_L_1_CFG_2(77).FEU0[0x1721]=0x3f
FEU_RX_RMC_L_1_CFG_2(78).FEU0[0x1722]=0x3f
FEU_RX_RMC_L_1_CFG_2(79).FEU0[0x1723]=0x3f
FEU_RX_RMC_L_1_CFG_2(80).FEU0[0x1724]=0x3f
FEU_RX_RMC_L_1_CFG_2(81).FEU0[0x1725]=0x3f
FEU_RX_RMC_L_1_CFG_3(0).FEU0[0x1726]=0x7f
FEU_RX_RMC_L_1_CFG_3(1).FEU0[0x1727]=0x7f
FEU_RX_RMC_L_1_CFG_3(2).FEU0[0x1728]=0x7f
FEU_RX_RMC_L_1_CFG_3(3).FEU0[0x1729]=0x7f
FEU_RX_RMC_L_1_CFG_3(4).FEU0[0x172a]=0x7f
FEU_RX_RMC_L_1_CFG_3(5).FEU0[0x172b]=0x7f
FEU_RX_RMC_L_1_CFG_3(6).FEU0[0x172c]=0x7f
FEU_RX_RMC_L_1_CFG_3(7).FEU0[0x172d]=0x7f
FEU_RX_RMC_L_1_CFG_3(8).FEU0[0x172e]=0x7f
FEU_RX_RMC_L_1_CFG_3(9).FEU0[0x172f]=0x7f
FEU_RX_RMC_L_1_CFG_3(10).FEU0[0x1730]=0x7f
FEU_RX_RMC_L_1_CFG_3(11).FEU0[0x1731]=0x7f
FEU_RX_RMC_L_1_CFG_3(12).FEU0[0x1732]=0x7f
FEU_RX_RMC_L_1_CFG_3(13).FEU0[0x1733]=0x7f
FEU_RX_RMC_L_1_CFG_3(14).FEU0[0x1734]=0x7f
FEU_RX_RMC_L_1_CFG_3(15).FEU0[0x1735]=0x7f
FEU_RX_RMC_L_1_CFG_3(16).FEU0[0x1736]=0x7f
FEU_RX_RMC_L_1_CFG_3(17).FEU0[0x1737]=0x7f
FEU_RX_RMC_L_1_CFG_3(18).FEU0[0x1738]=0x7f
FEU_RX_RMC_L_1_CFG_3(19).FEU0[0x1739]=0x7f
FEU_RX_RMC_L_1_CFG_3(20).FEU0[0x173a]=0x7f
FEU_RX_RMC_L_1_CFG_3(21).FEU0[0x173b]=0x7f
FEU_RX_RMC_L_1_CFG_3(22).FEU0[0x173c]=0x7f
FEU_RX_RMC_L_1_CFG_3(23).FEU0[0x173d]=0x7f
FEU_RX_RMC_L_1_CFG_3(24).FEU0[0x173e]=0x7f
FEU_RX_RMC_L_1_CFG_3(25).FEU0[0x173f]=0x7f
FEU_RX_RMC_L_1_CFG_3(26).FEU0[0x1740]=0x7f
FEU_RX_RMC_L_1_CFG_3(27).FEU0[0x1741]=0x7f
FEU_RX_RMC_L_1_CFG_3(28).FEU0[0x1742]=0x7f
FEU_RX_RMC_L_1_CFG_3(29).FEU0[0x1743]=0x7f
FEU_RX_RMC_L_1_CFG_3(30).FEU0[0x1744]=0x7f
FEU_RX_RMC_L_1_CFG_3(31).FEU0[0x1745]=0x7f
FEU_RX_RMC_L_1_CFG_3(32).FEU0[0x1746]=0x7f
FEU_RX_RMC_L_1_CFG_3(33).FEU0[0x1747]=0x7f
FEU_RX_RMC_L_1_CFG_3(34).FEU0[0x1748]=0x7f
FEU_RX_RMC_L_1_CFG_3(35).FEU0[0x1749]=0x7f
FEU_RX_RMC_L_1_CFG_3(36).FEU0[0x174a]=0x7f
FEU_RX_RMC_L_1_CFG_3(37).FEU0[0x174b]=0x7f
FEU_RX_RMC_L_1_CFG_3(38).FEU0[0x174c]=0x7f
FEU_RX_RMC_L_1_CFG_3(39).FEU0[0x174d]=0x7f
FEU_RX_RMC_L_1_CFG_3(40).FEU0[0x174e]=0x7f
FEU_RX_RMC_L_1_CFG_3(41).FEU0[0x174f]=0x7f
FEU_RX_RMC_L_1_CFG_3(42).FEU0[0x1750]=0x7f
FEU_RX_RMC_L_1_CFG_3(43).FEU0[0x1751]=0x7f
FEU_RX_RMC_L_1_CFG_3(44).FEU0[0x1752]=0x7f
FEU_RX_RMC_L_1_CFG_3(45).FEU0[0x1753]=0x7f
FEU_RX_RMC_L_1_CFG_3(46).FEU0[0x1754]=0x7f
FEU_RX_RMC_L_1_CFG_3(47).FEU0[0x1755]=0x7f
FEU_RX_RMC_L_1_CFG_3(48).FEU0[0x1756]=0x7f
FEU_RX_RMC_L_1_CFG_3(49).FEU0[0x1757]=0x7f
FEU_RX_RMC_L_1_CFG_3(50).FEU0[0x1758]=0x7f
FEU_RX_RMC_L_1_CFG_3(51).FEU0[0x1759]=0x7f
FEU_RX_RMC_L_1_CFG_4(0).FEU0[0x175a]=0
FEU_RX_RMC_L_1_CFG_4(1).FEU0[0x175b]=0
FEU_RX_RMC_L_1_CFG_4(2).FEU0[0x175c]=0
FEU_RX_RMC_L_1_CFG_4(3).FEU0[0x175d]=0
FEU_RX_RMC_L_1_CFG_4(4).FEU0[0x175e]=0
FEU_RX_RMC_L_1_CFG_4(5).FEU0[0x175f]=0
FEU_RX_RMC_L_1_CFG_4(6).FEU0[0x1760]=0
FEU_RX_RMC_L_1_CFG_4(7).FEU0[0x1761]=0
FEU_RX_RMC_L_1_CFG_4(8).FEU0[0x1762]=0
FEU_RX_RMC_L_1_CFG_4(9).FEU0[0x1763]=0
FEU_RX_RMC_L_1_CFG_4(10).FEU0[0x1764]=0
FEU_RX_RMC_L_1_CFG_4(11).FEU0[0x1765]=0
FEU_RX_RMC_L_1_CFG_4(12).FEU0[0x1766]=0
FEU_RX_RMC_L_1_CFG_4(13).FEU0[0x1767]=0
FEU_RX_RMC_L_1_CFG_4(14).FEU0[0x1768]=0
FEU_RX_RMC_L_1_CFG_4(15).FEU0[0x1769]=0
FEU_RX_RMC_L_1_CFG_4(16).FEU0[0x176a]=0
FEU_RX_RMC_L_1_CFG_4(17).FEU0[0x176b]=0
FEU_RX_RMC_L_1_CFG_4(18).FEU0[0x176c]=0
FEU_RX_RMC_L_1_CFG_4(19).FEU0[0x176d]=0
FEU_RX_RMC_L_1_CFG_4(20).FEU0[0x176e]=0
FEU_RX_RMC_L_1_CFG_4(21).FEU0[0x176f]=0
FEU_RX_RMC_L_1_CFG_4(22).FEU0[0x1770]=0
FEU_RX_RMC_L_1_CFG_4(23).FEU0[0x1771]=0
FEU_RX_RMC_L_1_CFG_4(24).FEU0[0x1772]=0
FEU_RX_RMC_L_1_CFG_4(25).FEU0[0x1773]=0
FEU_RX_RMC_L_1_CFG_4(26).FEU0[0x1774]=0
FEU_RX_RMC_L_1_CFG_4(27).FEU0[0x1775]=0
FEU_RX_RMC_L_1_CFG_4(28).FEU0[0x1776]=0
FEU_RX_RMC_L_1_CFG_4(29).FEU0[0x1777]=0
FEU_RX_RMC_L_1_CFG_4(30).FEU0[0x1778]=0
FEU_RX_RMC_L_1_CFG_4(31).FEU0[0x1779]=0
FEU_RX_RMC_L_1_CFG_4(32).FEU0[0x177a]=0
FEU_RX_RMC_L_1_CFG_4(33).FEU0[0x177b]=0
FEU_RX_RMC_L_1_CFG_4(34).FEU0[0x177c]=0
FEU_RX_RMC_L_1_CFG_4(35).FEU0[0x177d]=0
FEU_RX_RMC_L_1_CFG_4(36).FEU0[0x177e]=0
FEU_RX_RMC_L_1_CFG_4(37).FEU0[0x177f]=0
FEU_RX_RMC_L_1_CFG_4(38).FEU0[0x1780]=0
FEU_RX_RMC_L_1_CFG_4(39).FEU0[0x1781]=0
FEU_RX_RMC_L_1_CFG_4(40).FEU0[0x1782]=0
FEU_RX_RMC_L_1_CFG_4(41).FEU0[0x1783]=0
FEU_RX_RMC_L_1_CFG_4(42).FEU0[0x1784]=0
FEU_RX_RMC_L_1_CFG_4(43).FEU0[0x1785]=0
FEU_RX_RMC_L_1_CFG_4(44).FEU0[0x1786]=0
FEU_RX_RMC_L_1_CFG_4(45).FEU0[0x1787]=0
FEU_RX_RMC_L_1_CFG_4(46).FEU0[0x1788]=0
FEU_RX_RMC_L_1_CFG_4(47).FEU0[0x1789]=0
FEU_RX_RMC_L_1_CFG_4(48).FEU0[0x178a]=0
FEU_RX_RMC_L_1_CFG_4(49).FEU0[0x178b]=0
FEU_RX_RMC_L_1_CFG_4(50).FEU0[0x178c]=0
FEU_RX_RMC_L_1_CFG_4(51).FEU0[0x178d]=0
FEU_RX_RMC_L_1_CFG_5.FEU0[0x178e]=0
FEU_RX_RMC_L_1_CFG_6.FEU0[0x178f]=0
FEU_RX_RMC_L_1_CFG_7.FEU0[0x1790]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(0).FEU0[0x1681]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(1).FEU0[0x1682]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(2).FEU0[0x1683]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(3).FEU0[0x1684]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(4).FEU0[0x1685]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(5).FEU0[0x1686]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(6).FEU0[0x1687]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(7).FEU0[0x1688]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(8).FEU0[0x1689]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(9).FEU0[0x168a]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(10).FEU0[0x168b]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(11).FEU0[0x168c]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(12).FEU0[0x168d]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(13).FEU0[0x168e]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(14).FEU0[0x168f]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(15).FEU0[0x1690]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(16).FEU0[0x1691]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(17).FEU0[0x1692]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(18).FEU0[0x1693]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(19).FEU0[0x1694]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(20).FEU0[0x1695]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(21).FEU0[0x1696]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(22).FEU0[0x1697]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(23).FEU0[0x1698]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(24).FEU0[0x1699]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(25).FEU0[0x169a]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(26).FEU0[0x169b]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(27).FEU0[0x169c]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(28).FEU0[0x169d]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(29).FEU0[0x169e]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(30).FEU0[0x169f]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(31).FEU0[0x16a0]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(32).FEU0[0x16a1]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(33).FEU0[0x16a2]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(34).FEU0[0x16a3]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(35).FEU0[0x16a4]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(36).FEU0[0x16a5]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(37).FEU0[0x16a6]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(38).FEU0[0x16a7]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(39).FEU0[0x16a8]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(40).FEU0[0x16a9]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(41).FEU0[0x16aa]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(42).FEU0[0x16ab]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(43).FEU0[0x16ac]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(44).FEU0[0x16ad]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(45).FEU0[0x16ae]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(46).FEU0[0x16af]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(47).FEU0[0x16b0]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(48).FEU0[0x16b1]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(49).FEU0[0x16b2]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(50).FEU0[0x16b3]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(51).FEU0[0x16b4]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(52).FEU0[0x16b5]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(53).FEU0[0x16b6]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(54).FEU0[0x16b7]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(55).FEU0[0x16b8]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(56).FEU0[0x16b9]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(57).FEU0[0x16ba]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(58).FEU0[0x16bb]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(59).FEU0[0x16bc]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(60).FEU0[0x16bd]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(61).FEU0[0x16be]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(62).FEU0[0x16bf]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(63).FEU0[0x16c0]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(64).FEU0[0x16c1]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(65).FEU0[0x16c2]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(66).FEU0[0x16c3]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(67).FEU0[0x16c4]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(68).FEU0[0x16c5]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(69).FEU0[0x16c6]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(70).FEU0[0x16c7]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(71).FEU0[0x16c8]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(72).FEU0[0x16c9]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(73).FEU0[0x16ca]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(74).FEU0[0x16cb]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(75).FEU0[0x16cc]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(76).FEU0[0x16cd]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(77).FEU0[0x16ce]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(78).FEU0[0x16cf]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(79).FEU0[0x16d0]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(80).FEU0[0x16d1]=0
FEU_RX_RMC_MAP_TO_PORT_IS_INVALID(81).FEU0[0x16d2]=0
FEU_RX_RMC_OVF.FEU0[0xfdf]=0
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(0).FEU0[0x988]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(1).FEU0[0x98a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(2).FEU0[0x98c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(3).FEU0[0x98e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(4).FEU0[0x990]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(5).FEU0[0x992]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(6).FEU0[0x994]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(7).FEU0[0x996]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(8).FEU0[0x998]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(9).FEU0[0x99a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(10).FEU0[0x99c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(11).FEU0[0x99e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(12).FEU0[0x9a0]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(13).FEU0[0x9a2]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(14).FEU0[0x9a4]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(15).FEU0[0x9a6]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(16).FEU0[0x9a8]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(17).FEU0[0x9aa]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(18).FEU0[0x9ac]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(19).FEU0[0x9ae]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(20).FEU0[0x9b0]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(21).FEU0[0x9b2]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(22).FEU0[0x9b4]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(23).FEU0[0x9b6]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(24).FEU0[0x9b8]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(25).FEU0[0x9ba]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(26).FEU0[0x9bc]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(27).FEU0[0x9be]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(28).FEU0[0x9c0]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(29).FEU0[0x9c2]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(30).FEU0[0x9c4]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(31).FEU0[0x9c6]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(32).FEU0[0x9c8]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(33).FEU0[0x9ca]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(34).FEU0[0x9cc]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(35).FEU0[0x9ce]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(36).FEU0[0x9d0]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(37).FEU0[0x9d2]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(38).FEU0[0x9d4]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(39).FEU0[0x9d6]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(40).FEU0[0x9d8]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(41).FEU0[0x9da]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(42).FEU0[0x9dc]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(43).FEU0[0x9de]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(44).FEU0[0x9e0]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(45).FEU0[0x9e2]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(46).FEU0[0x9e4]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(47).FEU0[0x9e6]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(48).FEU0[0x9e8]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(49).FEU0[0x9ea]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(50).FEU0[0x9ec]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(51).FEU0[0x9ee]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(52).FEU0[0x9f0]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(53).FEU0[0x9f2]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(54).FEU0[0x9f4]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(55).FEU0[0x9f6]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(56).FEU0[0x9f8]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(57).FEU0[0x9fa]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(58).FEU0[0x9fc]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(59).FEU0[0x9fe]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(60).FEU0[0xa00]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(61).FEU0[0xa02]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(62).FEU0[0xa04]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(63).FEU0[0xa06]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(64).FEU0[0xa08]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(65).FEU0[0xa0a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(66).FEU0[0xa0c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(67).FEU0[0xa0e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(68).FEU0[0xa10]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(69).FEU0[0xa12]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(70).FEU0[0xa14]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(71).FEU0[0xa16]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(72).FEU0[0xa18]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(73).FEU0[0xa1a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(74).FEU0[0xa1c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(75).FEU0[0xa1e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(76).FEU0[0xa20]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(77).FEU0[0xa22]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(78).FEU0[0xa24]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(79).FEU0[0xa26]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(80).FEU0[0xa28]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(81).FEU0[0xa2a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(82).FEU0[0xa2c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(83).FEU0[0xa2e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(84).FEU0[0xa30]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(85).FEU0[0xa32]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(86).FEU0[0xa34]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(87).FEU0[0xa36]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(88).FEU0[0xa38]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(89).FEU0[0xa3a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(90).FEU0[0xa3c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(91).FEU0[0xa3e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(92).FEU0[0xa40]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(93).FEU0[0xa42]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(94).FEU0[0xa44]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(95).FEU0[0xa46]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(96).FEU0[0xa48]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(97).FEU0[0xa4a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(98).FEU0[0xa4c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(99).FEU0[0xa4e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(100).FEU0[0xa50]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(101).FEU0[0xa52]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(102).FEU0[0xa54]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(103).FEU0[0xa56]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(104).FEU0[0xa58]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(105).FEU0[0xa5a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(106).FEU0[0xa5c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(107).FEU0[0xa5e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(108).FEU0[0xa60]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(109).FEU0[0xa62]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(110).FEU0[0xa64]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(111).FEU0[0xa66]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(112).FEU0[0xa68]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(113).FEU0[0xa6a]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(114).FEU0[0xa6c]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(115).FEU0[0xa6e]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(116).FEU0[0xa70]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(117).FEU0[0xa72]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(118).FEU0[0xa74]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(119).FEU0[0xa76]=0x800100020004000
FEU_RX_RMC_PRD_THRESHOLDS_CONFIG(120).FEU0[0xa78]=0x800100020004000
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FEU_SAR_CHANNEL_TO_CLIENT_MAP(511).FEU0[0x1a39]=0
FEU_SAR_CONFIG.FEU0[0x1af7]=0x11
FEU_SAR_INSTRUMENTATION_CLEAR_MEMORY.FEU0[0x1836]=0
FEU_SAR_INSTRUMENTATION_CONFIG.FEU0[0x182a]=7
FEU_SAR_INSTRUMENTATION_DEBUG_1.FEU0[0x182c]=0
FEU_SAR_INSTRUMENTATION_DEBUG_2.FEU0[0x182e]=0
FEU_SAR_INSTRUMENTATION_DEBUG_WRAP_AROUND.FEU0[0x1832]=0
FEU_SAR_INSTRUMENTATION_INTERVALS_COUNTER.FEU0[0x1838]=0
FEU_SAR_INSTRUMENTATION_LAST_INTERVAL_WRITTEN.FEU0[0x1834]=7
FEU_SAR_INSTRUMENTATION_OVERRIDE_MODE.FEU0[0x1830]=1
FEU_SAR_RX_ASYNCFIFO_STATUS_1.FEU0[0x10d]=0
FEU_SAR_RX_ASYNCFIFO_STATUS_2.FEU0[0x10e]=0
FEU_SAR_TX_ASYNCFIFO_STATUS_1.FEU0[0x10f]=0
FEU_SAR_TX_ASYNCFIFO_STATUS_2.FEU0[0x110]=0
FEU_SBUS_BROADCAST_ID.FEU0[0x86]=0x7ff
FEU_SBUS_LAST_IN_CHAIN.FEU0[0x87]=0
FEU_SCH_CNT_DEC_TH.FEU0[0x1abb]=0x8c
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(0).FEU0[0x1a3b]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(1).FEU0[0x1a3c]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(2).FEU0[0x1a3d]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(3).FEU0[0x1a3e]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(4).FEU0[0x1a3f]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(5).FEU0[0x1a40]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(6).FEU0[0x1a41]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(7).FEU0[0x1a42]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(8).FEU0[0x1a43]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(9).FEU0[0x1a44]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(10).FEU0[0x1a45]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(11).FEU0[0x1a46]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(12).FEU0[0x1a47]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(13).FEU0[0x1a48]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(14).FEU0[0x1a49]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(15).FEU0[0x1a4a]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(16).FEU0[0x1a4b]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(17).FEU0[0x1a4c]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(18).FEU0[0x1a4d]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(19).FEU0[0x1a4e]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(20).FEU0[0x1a4f]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(21).FEU0[0x1a50]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(22).FEU0[0x1a51]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(23).FEU0[0x1a52]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(24).FEU0[0x1a53]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(25).FEU0[0x1a54]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(26).FEU0[0x1a55]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(27).FEU0[0x1a56]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(28).FEU0[0x1a57]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(29).FEU0[0x1a58]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(30).FEU0[0x1a59]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(31).FEU0[0x1a5a]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(32).FEU0[0x1a5b]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(33).FEU0[0x1a5c]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(34).FEU0[0x1a5d]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(35).FEU0[0x1a5e]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(36).FEU0[0x1a5f]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(37).FEU0[0x1a60]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(38).FEU0[0x1a61]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(39).FEU0[0x1a62]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(40).FEU0[0x1a63]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(41).FEU0[0x1a64]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(42).FEU0[0x1a65]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(43).FEU0[0x1a66]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(44).FEU0[0x1a67]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(45).FEU0[0x1a68]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(46).FEU0[0x1a69]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(47).FEU0[0x1a6a]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(48).FEU0[0x1a6b]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(49).FEU0[0x1a6c]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(50).FEU0[0x1a6d]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(51).FEU0[0x1a6e]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(52).FEU0[0x1a6f]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(53).FEU0[0x1a70]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(54).FEU0[0x1a71]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(55).FEU0[0x1a72]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(56).FEU0[0x1a73]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(57).FEU0[0x1a74]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(58).FEU0[0x1a75]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(59).FEU0[0x1a76]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(60).FEU0[0x1a77]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(61).FEU0[0x1a78]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(62).FEU0[0x1a79]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(63).FEU0[0x1a7a]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(64).FEU0[0x1a7b]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(65).FEU0[0x1a7c]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(66).FEU0[0x1a7d]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(67).FEU0[0x1a7e]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(68).FEU0[0x1a7f]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(69).FEU0[0x1a80]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(70).FEU0[0x1a81]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(71).FEU0[0x1a82]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(72).FEU0[0x1a83]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(73).FEU0[0x1a84]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(74).FEU0[0x1a85]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(75).FEU0[0x1a86]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(76).FEU0[0x1a87]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(77).FEU0[0x1a88]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(78).FEU0[0x1a89]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(79).FEU0[0x1a8a]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(80).FEU0[0x1a8b]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(81).FEU0[0x1a8c]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(82).FEU0[0x1a8d]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(83).FEU0[0x1a8e]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(84).FEU0[0x1a8f]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(85).FEU0[0x1a90]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(86).FEU0[0x1a91]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(87).FEU0[0x1a92]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(88).FEU0[0x1a93]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(89).FEU0[0x1a94]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(90).FEU0[0x1a95]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(91).FEU0[0x1a96]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(92).FEU0[0x1a97]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(93).FEU0[0x1a98]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(94).FEU0[0x1a99]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(95).FEU0[0x1a9a]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(96).FEU0[0x1a9b]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(97).FEU0[0x1a9c]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(98).FEU0[0x1a9d]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(99).FEU0[0x1a9e]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(100).FEU0[0x1a9f]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(101).FEU0[0x1aa0]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(102).FEU0[0x1aa1]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(103).FEU0[0x1aa2]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(104).FEU0[0x1aa3]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(105).FEU0[0x1aa4]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(106).FEU0[0x1aa5]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(107).FEU0[0x1aa6]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(108).FEU0[0x1aa7]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(109).FEU0[0x1aa8]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(110).FEU0[0x1aa9]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(111).FEU0[0x1aaa]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(112).FEU0[0x1aab]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(113).FEU0[0x1aac]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(114).FEU0[0x1aad]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(115).FEU0[0x1aae]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(116).FEU0[0x1aaf]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(117).FEU0[0x1ab0]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(118).FEU0[0x1ab1]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(119).FEU0[0x1ab2]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(120).FEU0[0x1ab3]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(121).FEU0[0x1ab4]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(122).FEU0[0x1ab5]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(123).FEU0[0x1ab6]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(124).FEU0[0x1ab7]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(125).FEU0[0x1ab8]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(126).FEU0[0x1ab9]=0
FEU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT(127).FEU0[0x1aba]=0
FEU_SPECIAL_CLOCK_CONTROLS.FEU0[0xc1]=2
FEU_TSC_CK_CONTROL.FEU0[0x1f3e]=2
FEU_TX_EGRESS_CREDITS_DEBUG_PM(0).FEU0[0xc58]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(1).FEU0[0xc59]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(2).FEU0[0xc5a]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(3).FEU0[0xc5b]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(4).FEU0[0xc5c]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(5).FEU0[0xc5d]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(6).FEU0[0xc5e]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(7).FEU0[0xc5f]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(8).FEU0[0xc60]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(9).FEU0[0xc61]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(10).FEU0[0xc62]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(11).FEU0[0xc63]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(12).FEU0[0xc64]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(13).FEU0[0xc65]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(14).FEU0[0xc66]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(15).FEU0[0xc67]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(16).FEU0[0xc68]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(17).FEU0[0xc69]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(18).FEU0[0xc6a]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(19).FEU0[0xc6b]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(20).FEU0[0xc6c]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(21).FEU0[0xc6d]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(22).FEU0[0xc6e]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(23).FEU0[0xc6f]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(24).FEU0[0xc70]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(25).FEU0[0xc71]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(26).FEU0[0xc72]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(27).FEU0[0xc73]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(28).FEU0[0xc74]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(29).FEU0[0xc75]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(30).FEU0[0xc76]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(31).FEU0[0xc77]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(32).FEU0[0xc78]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(33).FEU0[0xc79]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(34).FEU0[0xc7a]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(35).FEU0[0xc7b]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(36).FEU0[0xc7c]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(37).FEU0[0xc7d]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(38).FEU0[0xc7e]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(39).FEU0[0xc7f]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(40).FEU0[0xc80]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(41).FEU0[0xc81]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(42).FEU0[0xc82]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(43).FEU0[0xc83]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(44).FEU0[0xc84]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(45).FEU0[0xc85]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(46).FEU0[0xc86]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(47).FEU0[0xc87]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(48).FEU0[0xc88]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(49).FEU0[0xc89]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(50).FEU0[0xc8a]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(51).FEU0[0xc8b]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(52).FEU0[0xc8c]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(53).FEU0[0xc8d]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(54).FEU0[0xc8e]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(55).FEU0[0xc8f]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(56).FEU0[0xc90]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(57).FEU0[0xc91]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(58).FEU0[0xc92]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(59).FEU0[0xc93]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(60).FEU0[0xc94]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(61).FEU0[0xc95]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(62).FEU0[0xc96]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(63).FEU0[0xc97]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(64).FEU0[0xc98]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(65).FEU0[0xc99]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(66).FEU0[0xc9a]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(67).FEU0[0xc9b]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(68).FEU0[0xc9c]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(69).FEU0[0xc9d]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(70).FEU0[0xc9e]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(71).FEU0[0xc9f]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(72).FEU0[0xca0]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(73).FEU0[0xca1]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(74).FEU0[0xca2]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(75).FEU0[0xca3]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(76).FEU0[0xca4]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(77).FEU0[0xca5]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(78).FEU0[0xca6]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(79).FEU0[0xca7]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(80).FEU0[0xca8]=0x640
FEU_TX_EGRESS_CREDITS_DEBUG_PM(81).FEU0[0xca9]=0x640
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(0).FEU0[0xee8]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(1).FEU0[0xee9]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(2).FEU0[0xeea]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(3).FEU0[0xeeb]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(4).FEU0[0xeec]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(5).FEU0[0xeed]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(6).FEU0[0xeee]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(7).FEU0[0xeef]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(8).FEU0[0xef0]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(9).FEU0[0xef1]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(10).FEU0[0xef2]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(11).FEU0[0xef3]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(12).FEU0[0xef4]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(13).FEU0[0xef5]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(14).FEU0[0xef6]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(15).FEU0[0xef7]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(16).FEU0[0xef8]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(17).FEU0[0xef9]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(18).FEU0[0xefa]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(19).FEU0[0xefb]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(20).FEU0[0xefc]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(21).FEU0[0xefd]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(22).FEU0[0xefe]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(23).FEU0[0xeff]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(24).FEU0[0xf00]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(25).FEU0[0xf01]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(26).FEU0[0xf02]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(27).FEU0[0xf03]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(28).FEU0[0xf04]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(29).FEU0[0xf05]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(30).FEU0[0xf06]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(31).FEU0[0xf07]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(32).FEU0[0xf08]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(33).FEU0[0xf09]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(34).FEU0[0xf0a]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(35).FEU0[0xf0b]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(36).FEU0[0xf0c]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(37).FEU0[0xf0d]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(38).FEU0[0xf0e]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(39).FEU0[0xf0f]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(40).FEU0[0xf10]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(41).FEU0[0xf11]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(42).FEU0[0xf12]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(43).FEU0[0xf13]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(44).FEU0[0xf14]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(45).FEU0[0xf15]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(46).FEU0[0xf16]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(47).FEU0[0xf17]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(48).FEU0[0xf18]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(49).FEU0[0xf19]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(50).FEU0[0xf1a]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(51).FEU0[0xf1b]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(52).FEU0[0xf1c]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(53).FEU0[0xf1d]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(54).FEU0[0xf1e]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(55).FEU0[0xf1f]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(56).FEU0[0xf20]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(57).FEU0[0xf21]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(58).FEU0[0xf22]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(59).FEU0[0xf23]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(60).FEU0[0xf24]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(61).FEU0[0xf25]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(62).FEU0[0xf26]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(63).FEU0[0xf27]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(64).FEU0[0xf28]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(65).FEU0[0xf29]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(66).FEU0[0xf2a]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(67).FEU0[0xf2b]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(68).FEU0[0xf2c]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(69).FEU0[0xf2d]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(70).FEU0[0xf2e]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(71).FEU0[0xf2f]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(72).FEU0[0xf30]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(73).FEU0[0xf31]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(74).FEU0[0xf32]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(75).FEU0[0xf33]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(76).FEU0[0xf34]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(77).FEU0[0xf35]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(78).FEU0[0xf36]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(79).FEU0[0xf37]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(80).FEU0[0xf38]=0
FEU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE(81).FEU0[0xf39]=0
FEU_TX_FIFO_FLUSH_AND_STOP_TOOL.FEU0[0xb5d]=0
FEU_TX_FIRST_MEM_UNIT(0).FEU0[0x1e94]=0
FEU_TX_FIRST_MEM_UNIT(1).FEU0[0x1e95]=0
FEU_TX_FIRST_MEM_UNIT(2).FEU0[0x1e96]=0
FEU_TX_FIRST_MEM_UNIT(3).FEU0[0x1e97]=0
FEU_TX_FIRST_MEM_UNIT(4).FEU0[0x1e98]=0
FEU_TX_FIRST_MEM_UNIT(5).FEU0[0x1e99]=0
FEU_TX_FIRST_MEM_UNIT(6).FEU0[0x1e9a]=0
FEU_TX_FIRST_MEM_UNIT(7).FEU0[0x1e9b]=0
FEU_TX_FIRST_MEM_UNIT(8).FEU0[0x1e9c]=0
FEU_TX_FIRST_MEM_UNIT(9).FEU0[0x1e9d]=0
FEU_TX_FIRST_MEM_UNIT(10).FEU0[0x1e9e]=0
FEU_TX_FIRST_MEM_UNIT(11).FEU0[0x1e9f]=0
FEU_TX_FIRST_MEM_UNIT(12).FEU0[0x1ea0]=0
FEU_TX_FIRST_MEM_UNIT(13).FEU0[0x1ea1]=0
FEU_TX_FIRST_MEM_UNIT(14).FEU0[0x1ea2]=0
FEU_TX_FIRST_MEM_UNIT(15).FEU0[0x1ea3]=0
FEU_TX_FIRST_MEM_UNIT(16).FEU0[0x1ea4]=0
FEU_TX_FIRST_MEM_UNIT(17).FEU0[0x1ea5]=0
FEU_TX_FIRST_MEM_UNIT(18).FEU0[0x1ea6]=0
FEU_TX_FIRST_MEM_UNIT(19).FEU0[0x1ea7]=0
FEU_TX_FIRST_MEM_UNIT(20).FEU0[0x1ea8]=0
FEU_TX_FIRST_MEM_UNIT(21).FEU0[0x1ea9]=0
FEU_TX_FIRST_MEM_UNIT(22).FEU0[0x1eaa]=0
FEU_TX_FIRST_MEM_UNIT(23).FEU0[0x1eab]=0
FEU_TX_FIRST_MEM_UNIT(24).FEU0[0x1eac]=0
FEU_TX_FIRST_MEM_UNIT(25).FEU0[0x1ead]=0
FEU_TX_FIRST_MEM_UNIT(26).FEU0[0x1eae]=0
FEU_TX_FIRST_MEM_UNIT(27).FEU0[0x1eaf]=0
FEU_TX_FIRST_MEM_UNIT(28).FEU0[0x1eb0]=0
FEU_TX_FIRST_MEM_UNIT(29).FEU0[0x1eb1]=0
FEU_TX_FIRST_MEM_UNIT(30).FEU0[0x1eb2]=0
FEU_TX_FIRST_MEM_UNIT(31).FEU0[0x1eb3]=0
FEU_TX_FIRST_MEM_UNIT(32).FEU0[0x1eb4]=0
FEU_TX_FIRST_MEM_UNIT(33).FEU0[0x1eb5]=0
FEU_TX_FIRST_MEM_UNIT(34).FEU0[0x1eb6]=0
FEU_TX_FIRST_MEM_UNIT(35).FEU0[0x1eb7]=0
FEU_TX_FIRST_MEM_UNIT(36).FEU0[0x1eb8]=0
FEU_TX_FIRST_MEM_UNIT(37).FEU0[0x1eb9]=0
FEU_TX_FIRST_MEM_UNIT(38).FEU0[0x1eba]=0
FEU_TX_FIRST_MEM_UNIT(39).FEU0[0x1ebb]=0
FEU_TX_FIRST_MEM_UNIT(40).FEU0[0x1ebc]=0
FEU_TX_FIRST_MEM_UNIT(41).FEU0[0x1ebd]=0
FEU_TX_FIRST_MEM_UNIT(42).FEU0[0x1ebe]=0
FEU_TX_FIRST_MEM_UNIT(43).FEU0[0x1ebf]=0
FEU_TX_FIRST_MEM_UNIT(44).FEU0[0x1ec0]=0
FEU_TX_FIRST_MEM_UNIT(45).FEU0[0x1ec1]=0
FEU_TX_FIRST_MEM_UNIT(46).FEU0[0x1ec2]=0
FEU_TX_FIRST_MEM_UNIT(47).FEU0[0x1ec3]=0
FEU_TX_FIRST_MEM_UNIT(48).FEU0[0x1ec4]=0
FEU_TX_FIRST_MEM_UNIT(49).FEU0[0x1ec5]=0
FEU_TX_FIRST_MEM_UNIT(50).FEU0[0x1ec6]=0
FEU_TX_FIRST_MEM_UNIT(51).FEU0[0x1ec7]=0
FEU_TX_FIRST_MEM_UNIT(52).FEU0[0x1ec8]=0
FEU_TX_FIRST_MEM_UNIT(53).FEU0[0x1ec9]=0
FEU_TX_FIRST_MEM_UNIT(54).FEU0[0x1eca]=0
FEU_TX_FIRST_MEM_UNIT(55).FEU0[0x1ecb]=0
FEU_TX_FIRST_MEM_UNIT(56).FEU0[0x1ecc]=0
FEU_TX_FIRST_MEM_UNIT(57).FEU0[0x1ecd]=0
FEU_TX_FIRST_MEM_UNIT(58).FEU0[0x1ece]=0
FEU_TX_FIRST_MEM_UNIT(59).FEU0[0x1ecf]=0
FEU_TX_FIRST_MEM_UNIT(60).FEU0[0x1ed0]=0
FEU_TX_FIRST_MEM_UNIT(61).FEU0[0x1ed1]=0
FEU_TX_FIRST_MEM_UNIT(62).FEU0[0x1ed2]=0
FEU_TX_FIRST_MEM_UNIT(63).FEU0[0x1ed3]=0
FEU_TX_FIRST_MEM_UNIT(64).FEU0[0x1ed4]=0
FEU_TX_FIRST_MEM_UNIT(65).FEU0[0x1ed5]=0
FEU_TX_FIRST_MEM_UNIT(66).FEU0[0x1ed6]=0
FEU_TX_FIRST_MEM_UNIT(67).FEU0[0x1ed7]=0
FEU_TX_FIRST_MEM_UNIT(68).FEU0[0x1ed8]=0
FEU_TX_FIRST_MEM_UNIT(69).FEU0[0x1ed9]=0
FEU_TX_FIRST_MEM_UNIT(70).FEU0[0x1eda]=0
FEU_TX_FIRST_MEM_UNIT(71).FEU0[0x1edb]=0
FEU_TX_FIRST_MEM_UNIT(72).FEU0[0x1edc]=0
FEU_TX_FIRST_MEM_UNIT(73).FEU0[0x1edd]=0
FEU_TX_FIRST_MEM_UNIT(74).FEU0[0x1ede]=0
FEU_TX_FIRST_MEM_UNIT(75).FEU0[0x1edf]=0
FEU_TX_FIRST_MEM_UNIT(76).FEU0[0x1ee0]=0
FEU_TX_FIRST_MEM_UNIT(77).FEU0[0x1ee1]=0
FEU_TX_FIRST_MEM_UNIT(78).FEU0[0x1ee2]=0
FEU_TX_FIRST_MEM_UNIT(79).FEU0[0x1ee3]=0
FEU_TX_FIRST_MEM_UNIT(80).FEU0[0x1ee4]=0
FEU_TX_FIRST_MEM_UNIT(81).FEU0[0x1ee5]=0
FEU_TX_IGNORE_RST_FROM_TINY_MAC.FEU0[0x109]=0
FEU_TX_INPUTSTAGE_ASYNCFIFO_STATUS_1.FEU0[0x111]=0
FEU_TX_LAST_ADDR_READ.FEU0[0x1eea]=0
FEU_TX_LAST_ADDR_WRITTEN.FEU0[0x1ee8]=0
FEU_TX_LINK_ACTIVE.FEU0[0xfe1]=0
FEU_TX_LINK_LIST_DEFINTION(0).FEU0[0x1ccb]=0x7f
FEU_TX_LINK_LIST_DEFINTION(1).FEU0[0x1ccc]=0x7f
FEU_TX_LINK_LIST_DEFINTION(2).FEU0[0x1ccd]=0x7f
FEU_TX_LINK_LIST_DEFINTION(3).FEU0[0x1cce]=0x7f
FEU_TX_LINK_LIST_DEFINTION(4).FEU0[0x1ccf]=0x7f
FEU_TX_LINK_LIST_DEFINTION(5).FEU0[0x1cd0]=0x7f
FEU_TX_LINK_LIST_DEFINTION(6).FEU0[0x1cd1]=0x7f
FEU_TX_LINK_LIST_DEFINTION(7).FEU0[0x1cd2]=0x7f
FEU_TX_LINK_LIST_DEFINTION(8).FEU0[0x1cd3]=0x7f
FEU_TX_LINK_LIST_DEFINTION(9).FEU0[0x1cd4]=0x7f
FEU_TX_LINK_LIST_DEFINTION(10).FEU0[0x1cd5]=0x7f
FEU_TX_LINK_LIST_DEFINTION(11).FEU0[0x1cd6]=0x7f
FEU_TX_LINK_LIST_DEFINTION(12).FEU0[0x1cd7]=0x7f
FEU_TX_LINK_LIST_DEFINTION(13).FEU0[0x1cd8]=0x7f
FEU_TX_LINK_LIST_DEFINTION(14).FEU0[0x1cd9]=0x7f
FEU_TX_LINK_LIST_DEFINTION(15).FEU0[0x1cda]=0x7f
FEU_TX_LINK_LIST_DEFINTION(16).FEU0[0x1cdb]=0x7f
FEU_TX_LINK_LIST_DEFINTION(17).FEU0[0x1cdc]=0x7f
FEU_TX_LINK_LIST_DEFINTION(18).FEU0[0x1cdd]=0x7f
FEU_TX_LINK_LIST_DEFINTION(19).FEU0[0x1cde]=0x7f
FEU_TX_LINK_LIST_DEFINTION(20).FEU0[0x1cdf]=0x7f
FEU_TX_LINK_LIST_DEFINTION(21).FEU0[0x1ce0]=0x7f
FEU_TX_LINK_LIST_DEFINTION(22).FEU0[0x1ce1]=0x7f
FEU_TX_LINK_LIST_DEFINTION(23).FEU0[0x1ce2]=0x7f
FEU_TX_LINK_LIST_DEFINTION(24).FEU0[0x1ce3]=0x7f
FEU_TX_LINK_LIST_DEFINTION(25).FEU0[0x1ce4]=0x7f
FEU_TX_LINK_LIST_DEFINTION(26).FEU0[0x1ce5]=0x7f
FEU_TX_LINK_LIST_DEFINTION(27).FEU0[0x1ce6]=0x7f
FEU_TX_LINK_LIST_DEFINTION(28).FEU0[0x1ce7]=0x7f
FEU_TX_LINK_LIST_DEFINTION(29).FEU0[0x1ce8]=0x7f
FEU_TX_LINK_LIST_DEFINTION(30).FEU0[0x1ce9]=0x7f
FEU_TX_LINK_LIST_DEFINTION(31).FEU0[0x1cea]=0x7f
FEU_TX_LINK_LIST_DEFINTION(32).FEU0[0x1ceb]=0x7f
FEU_TX_LINK_LIST_DEFINTION(33).FEU0[0x1cec]=0x7f
FEU_TX_LINK_LIST_DEFINTION(34).FEU0[0x1ced]=0x7f
FEU_TX_LINK_LIST_DEFINTION(35).FEU0[0x1cee]=0x7f
FEU_TX_LINK_LIST_DEFINTION(36).FEU0[0x1cef]=0x7f
FEU_TX_LINK_LIST_DEFINTION(37).FEU0[0x1cf0]=0x7f
FEU_TX_LINK_LIST_DEFINTION(38).FEU0[0x1cf1]=0x7f
FEU_TX_LINK_LIST_DEFINTION(39).FEU0[0x1cf2]=0x7f
FEU_TX_LINK_LIST_DEFINTION(40).FEU0[0x1cf3]=0x7f
FEU_TX_LINK_LIST_DEFINTION(41).FEU0[0x1cf4]=0x7f
FEU_TX_LINK_LIST_DEFINTION(42).FEU0[0x1cf5]=0x7f
FEU_TX_LINK_LIST_DEFINTION(43).FEU0[0x1cf6]=0x7f
FEU_TX_LINK_LIST_DEFINTION(44).FEU0[0x1cf7]=0x7f
FEU_TX_LINK_LIST_DEFINTION(45).FEU0[0x1cf8]=0x7f
FEU_TX_LINK_LIST_DEFINTION(46).FEU0[0x1cf9]=0x7f
FEU_TX_LINK_LIST_DEFINTION(47).FEU0[0x1cfa]=0x7f
FEU_TX_LINK_LIST_DEFINTION(48).FEU0[0x1cfb]=0x7f
FEU_TX_LINK_LIST_DEFINTION(49).FEU0[0x1cfc]=0x7f
FEU_TX_LINK_LIST_DEFINTION(50).FEU0[0x1cfd]=0x7f
FEU_TX_LINK_LIST_DEFINTION(51).FEU0[0x1cfe]=0x7f
FEU_TX_LINK_LIST_DEFINTION(52).FEU0[0x1cff]=0x7f
FEU_TX_LINK_LIST_DEFINTION(53).FEU0[0x1d00]=0x7f
FEU_TX_LINK_LIST_DEFINTION(54).FEU0[0x1d01]=0x7f
FEU_TX_LINK_LIST_DEFINTION(55).FEU0[0x1d02]=0x7f
FEU_TX_LINK_LIST_DEFINTION(56).FEU0[0x1d03]=0x7f
FEU_TX_LINK_LIST_DEFINTION(57).FEU0[0x1d04]=0x7f
FEU_TX_LINK_LIST_DEFINTION(58).FEU0[0x1d05]=0x7f
FEU_TX_LINK_LIST_DEFINTION(59).FEU0[0x1d06]=0x7f
FEU_TX_LINK_LIST_DEFINTION(60).FEU0[0x1d07]=0x7f
FEU_TX_LINK_LIST_DEFINTION(61).FEU0[0x1d08]=0x7f
FEU_TX_LINK_LIST_DEFINTION(62).FEU0[0x1d09]=0x7f
FEU_TX_LINK_LIST_DEFINTION(63).FEU0[0x1d0a]=0x7f
FEU_TX_LINK_LIST_DEFINTION(64).FEU0[0x1d0b]=0x7f
FEU_TX_LINK_LIST_DEFINTION(65).FEU0[0x1d0c]=0x7f
FEU_TX_LINK_LIST_DEFINTION(66).FEU0[0x1d0d]=0x7f
FEU_TX_LINK_LIST_DEFINTION(67).FEU0[0x1d0e]=0x7f
FEU_TX_LINK_LIST_DEFINTION(68).FEU0[0x1d0f]=0x7f
FEU_TX_LINK_LIST_DEFINTION(69).FEU0[0x1d10]=0x7f
FEU_TX_LINK_LIST_DEFINTION(70).FEU0[0x1d11]=0x7f
FEU_TX_LINK_LIST_DEFINTION(71).FEU0[0x1d12]=0x7f
FEU_TX_LINK_LIST_DEFINTION(72).FEU0[0x1d13]=0x7f
FEU_TX_LINK_LIST_DEFINTION(73).FEU0[0x1d14]=0x7f
FEU_TX_LINK_LIST_DEFINTION(74).FEU0[0x1d15]=0x7f
FEU_TX_LINK_LIST_DEFINTION(75).FEU0[0x1d16]=0x7f
FEU_TX_LINK_LIST_DEFINTION(76).FEU0[0x1d17]=0x7f
FEU_TX_LINK_LIST_DEFINTION(77).FEU0[0x1d18]=0x7f
FEU_TX_LINK_LIST_DEFINTION(78).FEU0[0x1d19]=0x7f
FEU_TX_LINK_LIST_DEFINTION(79).FEU0[0x1d1a]=0x7f
FEU_TX_LINK_LIST_DEFINTION(80).FEU0[0x1d1b]=0x7f
FEU_TX_LINK_LIST_DEFINTION(81).FEU0[0x1d1c]=0x7f
FEU_TX_MEM_ALLOCATION_PER_TMC(0).FEU0[0x1d1d]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(1).FEU0[0x1d1e]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(2).FEU0[0x1d1f]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(3).FEU0[0x1d20]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(4).FEU0[0x1d21]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(5).FEU0[0x1d22]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(6).FEU0[0x1d23]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(7).FEU0[0x1d24]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(8).FEU0[0x1d25]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(9).FEU0[0x1d26]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(10).FEU0[0x1d27]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(11).FEU0[0x1d28]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(12).FEU0[0x1d29]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(13).FEU0[0x1d2a]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(14).FEU0[0x1d2b]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(15).FEU0[0x1d2c]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(16).FEU0[0x1d2d]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(17).FEU0[0x1d2e]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(18).FEU0[0x1d2f]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(19).FEU0[0x1d30]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(20).FEU0[0x1d31]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(21).FEU0[0x1d32]=0
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FEU_TX_MEM_ALLOCATION_PER_TMC(80).FEU0[0x1d6d]=0
FEU_TX_MEM_ALLOCATION_PER_TMC(81).FEU0[0x1d6e]=0
FEU_TX_MLF_CONFIG(0).FEU0[0x4b6]=9
FEU_TX_MLF_CONFIG(1).FEU0[0x4b7]=9
FEU_TX_MLF_CONFIG(2).FEU0[0x4b8]=9
FEU_TX_MLF_CONFIG(3).FEU0[0x4b9]=9
FEU_TX_MLF_CONFIG(4).FEU0[0x4ba]=9
FEU_TX_MLF_CONFIG(5).FEU0[0x4bb]=9
FEU_TX_MLF_CONFIG(6).FEU0[0x4bc]=9
FEU_TX_MLF_CONFIG(7).FEU0[0x4bd]=9
FEU_TX_MLF_CONFIG(8).FEU0[0x4be]=9
FEU_TX_MLF_CONFIG(9).FEU0[0x4bf]=9
FEU_TX_MLF_CONFIG(10).FEU0[0x4c0]=9
FEU_TX_MLF_CONFIG(11).FEU0[0x4c1]=9
FEU_TX_MLF_CONFIG(12).FEU0[0x4c2]=9
FEU_TX_MLF_CONFIG(13).FEU0[0x4c3]=9
FEU_TX_MLF_CONFIG(14).FEU0[0x4c4]=9
FEU_TX_MLF_CONFIG(15).FEU0[0x4c5]=9
FEU_TX_MLF_CONFIG(16).FEU0[0x4c6]=9
FEU_TX_MLF_CONFIG(17).FEU0[0x4c7]=9
FEU_TX_MLF_CONFIG(18).FEU0[0x4c8]=9
FEU_TX_MLF_CONFIG(19).FEU0[0x4c9]=9
FEU_TX_MLF_CONFIG(20).FEU0[0x4ca]=9
FEU_TX_MLF_CONFIG(21).FEU0[0x4cb]=9
FEU_TX_MLF_CONFIG(22).FEU0[0x4cc]=9
FEU_TX_MLF_CONFIG(23).FEU0[0x4cd]=9
FEU_TX_MLF_CONFIG(24).FEU0[0x4ce]=9
FEU_TX_MLF_CONFIG(25).FEU0[0x4cf]=9
FEU_TX_MLF_CONFIG(26).FEU0[0x4d0]=9
FEU_TX_MLF_CONFIG(27).FEU0[0x4d1]=9
FEU_TX_MLF_CONFIG(28).FEU0[0x4d2]=9
FEU_TX_MLF_CONFIG(29).FEU0[0x4d3]=9
FEU_TX_MLF_CONFIG(30).FEU0[0x4d4]=9
FEU_TX_MLF_CONFIG(31).FEU0[0x4d5]=9
FEU_TX_MLF_CONFIG(32).FEU0[0x4d6]=9
FEU_TX_MLF_CONFIG(33).FEU0[0x4d7]=9
FEU_TX_MLF_CONFIG(34).FEU0[0x4d8]=9
FEU_TX_MLF_CONFIG(35).FEU0[0x4d9]=9
FEU_TX_MLF_CONFIG(36).FEU0[0x4da]=9
FEU_TX_MLF_CONFIG(37).FEU0[0x4db]=9
FEU_TX_MLF_CONFIG(38).FEU0[0x4dc]=9
FEU_TX_MLF_CONFIG(39).FEU0[0x4dd]=9
FEU_TX_MLF_CONFIG(40).FEU0[0x4de]=9
FEU_TX_MLF_CONFIG(41).FEU0[0x4df]=9
FEU_TX_MLF_CONFIG(42).FEU0[0x4e0]=9
FEU_TX_MLF_CONFIG(43).FEU0[0x4e1]=9
FEU_TX_MLF_CONFIG(44).FEU0[0x4e2]=9
FEU_TX_MLF_CONFIG(45).FEU0[0x4e3]=9
FEU_TX_MLF_CONFIG(46).FEU0[0x4e4]=9
FEU_TX_MLF_CONFIG(47).FEU0[0x4e5]=9
FEU_TX_MLF_CONFIG(48).FEU0[0x4e6]=9
FEU_TX_MLF_CONFIG(49).FEU0[0x4e7]=9
FEU_TX_MLF_CONFIG(50).FEU0[0x4e8]=9
FEU_TX_MLF_CONFIG(51).FEU0[0x4e9]=9
FEU_TX_MLF_CONFIG(52).FEU0[0x4ea]=9
FEU_TX_MLF_CONFIG(53).FEU0[0x4eb]=9
FEU_TX_MLF_CONFIG(54).FEU0[0x4ec]=9
FEU_TX_MLF_CONFIG(55).FEU0[0x4ed]=9
FEU_TX_MLF_CONFIG(56).FEU0[0x4ee]=9
FEU_TX_MLF_CONFIG(57).FEU0[0x4ef]=9
FEU_TX_MLF_CONFIG(58).FEU0[0x4f0]=9
FEU_TX_MLF_CONFIG(59).FEU0[0x4f1]=9
FEU_TX_MLF_CONFIG(60).FEU0[0x4f2]=9
FEU_TX_MLF_CONFIG(61).FEU0[0x4f3]=9
FEU_TX_MLF_CONFIG(62).FEU0[0x4f4]=9
FEU_TX_MLF_CONFIG(63).FEU0[0x4f5]=9
FEU_TX_MLF_CONFIG(64).FEU0[0x4f6]=9
FEU_TX_MLF_CONFIG(65).FEU0[0x4f7]=9
FEU_TX_MLF_CONFIG(66).FEU0[0x4f8]=9
FEU_TX_MLF_CONFIG(67).FEU0[0x4f9]=9
FEU_TX_MLF_CONFIG(68).FEU0[0x4fa]=9
FEU_TX_MLF_CONFIG(69).FEU0[0x4fb]=9
FEU_TX_MLF_CONFIG(70).FEU0[0x4fc]=9
FEU_TX_MLF_CONFIG(71).FEU0[0x4fd]=9
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FEU_TX_MLF_CONFIG(74).FEU0[0x500]=9
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FEU_TX_MLF_CONFIG(80).FEU0[0x506]=9
FEU_TX_MLF_CONFIG(81).FEU0[0x507]=9
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(0).FEU0[0xf3b]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(1).FEU0[0xf3d]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(2).FEU0[0xf3f]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(3).FEU0[0xf41]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(6).FEU0[0xf47]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(8).FEU0[0xf4b]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(11).FEU0[0xf51]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(15).FEU0[0xf59]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(17).FEU0[0xf5d]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(18).FEU0[0xf5f]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(19).FEU0[0xf61]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(20).FEU0[0xf63]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(21).FEU0[0xf65]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(22).FEU0[0xf67]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(26).FEU0[0xf6f]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(31).FEU0[0xf79]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(33).FEU0[0xf7d]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(70).FEU0[0xfc7]=0
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FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(78).FEU0[0xfd7]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(79).FEU0[0xfd9]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(80).FEU0[0xfdb]=0
FEU_TX_MLF_ERR_ON_MOP_FROM_EGQ(81).FEU0[0xfdd]=0
FEU_TX_MLF_FIFO_FLUSH(0).FEU0[0x464]=0
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FEU_TX_MLF_FIFO_FLUSH(37).FEU0[0x489]=0
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FEU_TX_MLF_FIFO_FLUSH(40).FEU0[0x48c]=0
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FEU_TX_MLF_FIFO_FLUSH(44).FEU0[0x490]=0
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FEU_TX_MLF_FIFO_FLUSH(46).FEU0[0x492]=0
FEU_TX_MLF_FIFO_FLUSH(47).FEU0[0x493]=0
FEU_TX_MLF_FIFO_FLUSH(48).FEU0[0x494]=0
FEU_TX_MLF_FIFO_FLUSH(49).FEU0[0x495]=0
FEU_TX_MLF_FIFO_FLUSH(50).FEU0[0x496]=0
FEU_TX_MLF_FIFO_FLUSH(51).FEU0[0x497]=0
FEU_TX_MLF_FIFO_FLUSH(52).FEU0[0x498]=0
FEU_TX_MLF_FIFO_FLUSH(53).FEU0[0x499]=0
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FEU_TX_MLF_OVERFLOW_PM(9).FEU0[0xcb3]=0
FEU_TX_MLF_OVERFLOW_PM(10).FEU0[0xcb4]=0
FEU_TX_MLF_OVERFLOW_PM(11).FEU0[0xcb5]=0
FEU_TX_MLF_OVERFLOW_PM(12).FEU0[0xcb6]=0
FEU_TX_MLF_OVERFLOW_PM(13).FEU0[0xcb7]=0
FEU_TX_MLF_OVERFLOW_PM(14).FEU0[0xcb8]=0
FEU_TX_MLF_OVERFLOW_PM(15).FEU0[0xcb9]=0
FEU_TX_MLF_OVERFLOW_PM(16).FEU0[0xcba]=0
FEU_TX_MLF_OVERFLOW_PM(17).FEU0[0xcbb]=0
FEU_TX_MLF_OVERFLOW_PM(18).FEU0[0xcbc]=0
FEU_TX_MLF_OVERFLOW_PM(19).FEU0[0xcbd]=0
FEU_TX_MLF_OVERFLOW_PM(20).FEU0[0xcbe]=0
FEU_TX_MLF_OVERFLOW_PM(21).FEU0[0xcbf]=0
FEU_TX_MLF_OVERFLOW_PM(22).FEU0[0xcc0]=0
FEU_TX_MLF_OVERFLOW_PM(23).FEU0[0xcc1]=0
FEU_TX_MLF_OVERFLOW_PM(24).FEU0[0xcc2]=0
FEU_TX_MLF_OVERFLOW_PM(25).FEU0[0xcc3]=0
FEU_TX_MLF_OVERFLOW_PM(26).FEU0[0xcc4]=0
FEU_TX_MLF_OVERFLOW_PM(27).FEU0[0xcc5]=0
FEU_TX_MLF_OVERFLOW_PM(28).FEU0[0xcc6]=0
FEU_TX_MLF_OVERFLOW_PM(29).FEU0[0xcc7]=0
FEU_TX_MLF_OVERFLOW_PM(30).FEU0[0xcc8]=0
FEU_TX_MLF_OVERFLOW_PM(31).FEU0[0xcc9]=0
FEU_TX_MLF_OVERFLOW_PM(32).FEU0[0xcca]=0
FEU_TX_MLF_OVERFLOW_PM(33).FEU0[0xccb]=0
FEU_TX_MLF_OVERFLOW_PM(34).FEU0[0xccc]=0
FEU_TX_MLF_OVERFLOW_PM(35).FEU0[0xccd]=0
FEU_TX_MLF_OVERFLOW_PM(36).FEU0[0xcce]=0
FEU_TX_MLF_OVERFLOW_PM(37).FEU0[0xccf]=0
FEU_TX_MLF_OVERFLOW_PM(38).FEU0[0xcd0]=0
FEU_TX_MLF_OVERFLOW_PM(39).FEU0[0xcd1]=0
FEU_TX_MLF_OVERFLOW_PM(40).FEU0[0xcd2]=0
FEU_TX_MLF_OVERFLOW_PM(41).FEU0[0xcd3]=0
FEU_TX_MLF_OVERFLOW_PM(42).FEU0[0xcd4]=0
FEU_TX_MLF_OVERFLOW_PM(43).FEU0[0xcd5]=0
FEU_TX_MLF_OVERFLOW_PM(44).FEU0[0xcd6]=0
FEU_TX_MLF_OVERFLOW_PM(45).FEU0[0xcd7]=0
FEU_TX_MLF_OVERFLOW_PM(46).FEU0[0xcd8]=0
FEU_TX_MLF_OVERFLOW_PM(47).FEU0[0xcd9]=0
FEU_TX_MLF_OVERFLOW_PM(48).FEU0[0xcda]=0
FEU_TX_MLF_OVERFLOW_PM(49).FEU0[0xcdb]=0
FEU_TX_MLF_OVERFLOW_PM(50).FEU0[0xcdc]=0
FEU_TX_MLF_OVERFLOW_PM(51).FEU0[0xcdd]=0
FEU_TX_MLF_OVERFLOW_PM(52).FEU0[0xcde]=0
FEU_TX_MLF_OVERFLOW_PM(53).FEU0[0xcdf]=0
FEU_TX_MLF_OVERFLOW_PM(54).FEU0[0xce0]=0
FEU_TX_MLF_OVERFLOW_PM(55).FEU0[0xce1]=0
FEU_TX_MLF_OVERFLOW_PM(56).FEU0[0xce2]=0
FEU_TX_MLF_OVERFLOW_PM(57).FEU0[0xce3]=0
FEU_TX_MLF_OVERFLOW_PM(58).FEU0[0xce4]=0
FEU_TX_MLF_OVERFLOW_PM(59).FEU0[0xce5]=0
FEU_TX_MLF_OVERFLOW_PM(60).FEU0[0xce6]=0
FEU_TX_MLF_OVERFLOW_PM(61).FEU0[0xce7]=0
FEU_TX_MLF_OVERFLOW_PM(62).FEU0[0xce8]=0
FEU_TX_MLF_OVERFLOW_PM(63).FEU0[0xce9]=0
FEU_TX_MLF_OVERFLOW_PM(64).FEU0[0xcea]=0
FEU_TX_MLF_OVERFLOW_PM(65).FEU0[0xceb]=0
FEU_TX_MLF_OVERFLOW_PM(66).FEU0[0xcec]=0
FEU_TX_MLF_OVERFLOW_PM(67).FEU0[0xced]=0
FEU_TX_MLF_OVERFLOW_PM(68).FEU0[0xcee]=0
FEU_TX_MLF_OVERFLOW_PM(69).FEU0[0xcef]=0
FEU_TX_MLF_OVERFLOW_PM(70).FEU0[0xcf0]=0
FEU_TX_MLF_OVERFLOW_PM(71).FEU0[0xcf1]=0
FEU_TX_MLF_OVERFLOW_PM(72).FEU0[0xcf2]=0
FEU_TX_MLF_OVERFLOW_PM(73).FEU0[0xcf3]=0
FEU_TX_MLF_OVERFLOW_PM(74).FEU0[0xcf4]=0
FEU_TX_MLF_OVERFLOW_PM(75).FEU0[0xcf5]=0
FEU_TX_MLF_OVERFLOW_PM(76).FEU0[0xcf6]=0
FEU_TX_MLF_OVERFLOW_PM(77).FEU0[0xcf7]=0
FEU_TX_MLF_OVERFLOW_PM(78).FEU0[0xcf8]=0
FEU_TX_MLF_OVERFLOW_PM(79).FEU0[0xcf9]=0
FEU_TX_MLF_OVERFLOW_PM(80).FEU0[0xcfa]=0
FEU_TX_MLF_OVERFLOW_PM(81).FEU0[0xcfb]=0
FEU_TX_NO_DATA_IN_BUFFER(0).FEU0[0xe96]=0
FEU_TX_NO_DATA_IN_BUFFER(1).FEU0[0xe97]=0
FEU_TX_NO_DATA_IN_BUFFER(2).FEU0[0xe98]=0
FEU_TX_NO_DATA_IN_BUFFER(3).FEU0[0xe99]=0
FEU_TX_NO_DATA_IN_BUFFER(4).FEU0[0xe9a]=0
FEU_TX_NO_DATA_IN_BUFFER(5).FEU0[0xe9b]=0
FEU_TX_NO_DATA_IN_BUFFER(6).FEU0[0xe9c]=0
FEU_TX_NO_DATA_IN_BUFFER(7).FEU0[0xe9d]=0
FEU_TX_NO_DATA_IN_BUFFER(8).FEU0[0xe9e]=0
FEU_TX_NO_DATA_IN_BUFFER(9).FEU0[0xe9f]=0
FEU_TX_NO_DATA_IN_BUFFER(10).FEU0[0xea0]=0
FEU_TX_NO_DATA_IN_BUFFER(11).FEU0[0xea1]=0
FEU_TX_NO_DATA_IN_BUFFER(12).FEU0[0xea2]=0
FEU_TX_NO_DATA_IN_BUFFER(13).FEU0[0xea3]=0
FEU_TX_NO_DATA_IN_BUFFER(14).FEU0[0xea4]=0
FEU_TX_NO_DATA_IN_BUFFER(15).FEU0[0xea5]=0
FEU_TX_NO_DATA_IN_BUFFER(16).FEU0[0xea6]=0
FEU_TX_NO_DATA_IN_BUFFER(17).FEU0[0xea7]=0
FEU_TX_NO_DATA_IN_BUFFER(18).FEU0[0xea8]=0
FEU_TX_NO_DATA_IN_BUFFER(19).FEU0[0xea9]=0
FEU_TX_NO_DATA_IN_BUFFER(20).FEU0[0xeaa]=0
FEU_TX_NO_DATA_IN_BUFFER(21).FEU0[0xeab]=0
FEU_TX_NO_DATA_IN_BUFFER(22).FEU0[0xeac]=0
FEU_TX_NO_DATA_IN_BUFFER(23).FEU0[0xead]=0
FEU_TX_NO_DATA_IN_BUFFER(24).FEU0[0xeae]=0
FEU_TX_NO_DATA_IN_BUFFER(25).FEU0[0xeaf]=0
FEU_TX_NO_DATA_IN_BUFFER(26).FEU0[0xeb0]=0
FEU_TX_NO_DATA_IN_BUFFER(27).FEU0[0xeb1]=0
FEU_TX_NO_DATA_IN_BUFFER(28).FEU0[0xeb2]=0
FEU_TX_NO_DATA_IN_BUFFER(29).FEU0[0xeb3]=0
FEU_TX_NO_DATA_IN_BUFFER(30).FEU0[0xeb4]=0
FEU_TX_NO_DATA_IN_BUFFER(31).FEU0[0xeb5]=0
FEU_TX_NO_DATA_IN_BUFFER(32).FEU0[0xeb6]=0
FEU_TX_NO_DATA_IN_BUFFER(33).FEU0[0xeb7]=0
FEU_TX_NO_DATA_IN_BUFFER(34).FEU0[0xeb8]=0
FEU_TX_NO_DATA_IN_BUFFER(35).FEU0[0xeb9]=0
FEU_TX_NO_DATA_IN_BUFFER(36).FEU0[0xeba]=0
FEU_TX_NO_DATA_IN_BUFFER(37).FEU0[0xebb]=0
FEU_TX_NO_DATA_IN_BUFFER(38).FEU0[0xebc]=0
FEU_TX_NO_DATA_IN_BUFFER(39).FEU0[0xebd]=0
FEU_TX_NO_DATA_IN_BUFFER(40).FEU0[0xebe]=0
FEU_TX_NO_DATA_IN_BUFFER(41).FEU0[0xebf]=0
FEU_TX_NO_DATA_IN_BUFFER(42).FEU0[0xec0]=0
FEU_TX_NO_DATA_IN_BUFFER(43).FEU0[0xec1]=0
FEU_TX_NO_DATA_IN_BUFFER(44).FEU0[0xec2]=0
FEU_TX_NO_DATA_IN_BUFFER(45).FEU0[0xec3]=0
FEU_TX_NO_DATA_IN_BUFFER(46).FEU0[0xec4]=0
FEU_TX_NO_DATA_IN_BUFFER(47).FEU0[0xec5]=0
FEU_TX_NO_DATA_IN_BUFFER(48).FEU0[0xec6]=0
FEU_TX_NO_DATA_IN_BUFFER(49).FEU0[0xec7]=0
FEU_TX_NO_DATA_IN_BUFFER(50).FEU0[0xec8]=0
FEU_TX_NO_DATA_IN_BUFFER(51).FEU0[0xec9]=0
FEU_TX_NO_DATA_IN_BUFFER(52).FEU0[0xeca]=0
FEU_TX_NO_DATA_IN_BUFFER(53).FEU0[0xecb]=0
FEU_TX_NO_DATA_IN_BUFFER(54).FEU0[0xecc]=0
FEU_TX_NO_DATA_IN_BUFFER(55).FEU0[0xecd]=0
FEU_TX_NO_DATA_IN_BUFFER(56).FEU0[0xece]=0
FEU_TX_NO_DATA_IN_BUFFER(57).FEU0[0xecf]=0
FEU_TX_NO_DATA_IN_BUFFER(58).FEU0[0xed0]=0
FEU_TX_NO_DATA_IN_BUFFER(59).FEU0[0xed1]=0
FEU_TX_NO_DATA_IN_BUFFER(60).FEU0[0xed2]=0
FEU_TX_NO_DATA_IN_BUFFER(61).FEU0[0xed3]=0
FEU_TX_NO_DATA_IN_BUFFER(62).FEU0[0xed4]=0
FEU_TX_NO_DATA_IN_BUFFER(63).FEU0[0xed5]=0
FEU_TX_NO_DATA_IN_BUFFER(64).FEU0[0xed6]=0
FEU_TX_NO_DATA_IN_BUFFER(65).FEU0[0xed7]=0
FEU_TX_NO_DATA_IN_BUFFER(66).FEU0[0xed8]=0
FEU_TX_NO_DATA_IN_BUFFER(67).FEU0[0xed9]=0
FEU_TX_NO_DATA_IN_BUFFER(68).FEU0[0xeda]=0
FEU_TX_NO_DATA_IN_BUFFER(69).FEU0[0xedb]=0
FEU_TX_NO_DATA_IN_BUFFER(70).FEU0[0xedc]=0
FEU_TX_NO_DATA_IN_BUFFER(71).FEU0[0xedd]=0
FEU_TX_NO_DATA_IN_BUFFER(72).FEU0[0xede]=0
FEU_TX_NO_DATA_IN_BUFFER(73).FEU0[0xedf]=0
FEU_TX_NO_DATA_IN_BUFFER(74).FEU0[0xee0]=0
FEU_TX_NO_DATA_IN_BUFFER(75).FEU0[0xee1]=0
FEU_TX_NO_DATA_IN_BUFFER(76).FEU0[0xee2]=0
FEU_TX_NO_DATA_IN_BUFFER(77).FEU0[0xee3]=0
FEU_TX_NO_DATA_IN_BUFFER(78).FEU0[0xee4]=0
FEU_TX_NO_DATA_IN_BUFFER(79).FEU0[0xee5]=0
FEU_TX_NO_DATA_IN_BUFFER(80).FEU0[0xee6]=0
FEU_TX_NO_DATA_IN_BUFFER(81).FEU0[0xee7]=0
FEU_TX_PORTS_CONFIG_2.FEU0[0xbb1]=0
FEU_TX_PORTS_CONFIG_CRC(0).FEU0[0xb5f]=2
FEU_TX_PORTS_CONFIG_CRC(1).FEU0[0xb60]=2
FEU_TX_PORTS_CONFIG_CRC(2).FEU0[0xb61]=2
FEU_TX_PORTS_CONFIG_CRC(3).FEU0[0xb62]=2
FEU_TX_PORTS_CONFIG_CRC(4).FEU0[0xb63]=2
FEU_TX_PORTS_CONFIG_CRC(5).FEU0[0xb64]=2
FEU_TX_PORTS_CONFIG_CRC(6).FEU0[0xb65]=2
FEU_TX_PORTS_CONFIG_CRC(7).FEU0[0xb66]=2
FEU_TX_PORTS_CONFIG_CRC(8).FEU0[0xb67]=2
FEU_TX_PORTS_CONFIG_CRC(9).FEU0[0xb68]=2
FEU_TX_PORTS_CONFIG_CRC(10).FEU0[0xb69]=2
FEU_TX_PORTS_CONFIG_CRC(11).FEU0[0xb6a]=2
FEU_TX_PORTS_CONFIG_CRC(12).FEU0[0xb6b]=2
FEU_TX_PORTS_CONFIG_CRC(13).FEU0[0xb6c]=2
FEU_TX_PORTS_CONFIG_CRC(14).FEU0[0xb6d]=2
FEU_TX_PORTS_CONFIG_CRC(15).FEU0[0xb6e]=2
FEU_TX_PORTS_CONFIG_CRC(16).FEU0[0xb6f]=2
FEU_TX_PORTS_CONFIG_CRC(17).FEU0[0xb70]=2
FEU_TX_PORTS_CONFIG_CRC(18).FEU0[0xb71]=2
FEU_TX_PORTS_CONFIG_CRC(19).FEU0[0xb72]=2
FEU_TX_PORTS_CONFIG_CRC(20).FEU0[0xb73]=2
FEU_TX_PORTS_CONFIG_CRC(21).FEU0[0xb74]=2
FEU_TX_PORTS_CONFIG_CRC(22).FEU0[0xb75]=2
FEU_TX_PORTS_CONFIG_CRC(23).FEU0[0xb76]=2
FEU_TX_PORTS_CONFIG_CRC(24).FEU0[0xb77]=2
FEU_TX_PORTS_CONFIG_CRC(25).FEU0[0xb78]=2
FEU_TX_PORTS_CONFIG_CRC(26).FEU0[0xb79]=2
FEU_TX_PORTS_CONFIG_CRC(27).FEU0[0xb7a]=2
FEU_TX_PORTS_CONFIG_CRC(28).FEU0[0xb7b]=2
FEU_TX_PORTS_CONFIG_CRC(29).FEU0[0xb7c]=2
FEU_TX_PORTS_CONFIG_CRC(30).FEU0[0xb7d]=2
FEU_TX_PORTS_CONFIG_CRC(31).FEU0[0xb7e]=2
FEU_TX_PORTS_CONFIG_CRC(32).FEU0[0xb7f]=2
FEU_TX_PORTS_CONFIG_CRC(33).FEU0[0xb80]=2
FEU_TX_PORTS_CONFIG_CRC(34).FEU0[0xb81]=2
FEU_TX_PORTS_CONFIG_CRC(35).FEU0[0xb82]=2
FEU_TX_PORTS_CONFIG_CRC(36).FEU0[0xb83]=2
FEU_TX_PORTS_CONFIG_CRC(37).FEU0[0xb84]=2
FEU_TX_PORTS_CONFIG_CRC(38).FEU0[0xb85]=2
FEU_TX_PORTS_CONFIG_CRC(39).FEU0[0xb86]=2
FEU_TX_PORTS_CONFIG_CRC(40).FEU0[0xb87]=2
FEU_TX_PORTS_CONFIG_CRC(41).FEU0[0xb88]=2
FEU_TX_PORTS_CONFIG_CRC(42).FEU0[0xb89]=2
FEU_TX_PORTS_CONFIG_CRC(43).FEU0[0xb8a]=2
FEU_TX_PORTS_CONFIG_CRC(44).FEU0[0xb8b]=2
FEU_TX_PORTS_CONFIG_CRC(45).FEU0[0xb8c]=2
FEU_TX_PORTS_CONFIG_CRC(46).FEU0[0xb8d]=2
FEU_TX_PORTS_CONFIG_CRC(47).FEU0[0xb8e]=2
FEU_TX_PORTS_CONFIG_CRC(48).FEU0[0xb8f]=2
FEU_TX_PORTS_CONFIG_CRC(49).FEU0[0xb90]=2
FEU_TX_PORTS_CONFIG_CRC(50).FEU0[0xb91]=2
FEU_TX_PORTS_CONFIG_CRC(51).FEU0[0xb92]=2
FEU_TX_PORTS_CONFIG_CRC(52).FEU0[0xb93]=2
FEU_TX_PORTS_CONFIG_CRC(53).FEU0[0xb94]=2
FEU_TX_PORTS_CONFIG_CRC(54).FEU0[0xb95]=2
FEU_TX_PORTS_CONFIG_CRC(55).FEU0[0xb96]=2
FEU_TX_PORTS_CONFIG_CRC(56).FEU0[0xb97]=2
FEU_TX_PORTS_CONFIG_CRC(57).FEU0[0xb98]=2
FEU_TX_PORTS_CONFIG_CRC(58).FEU0[0xb99]=2
FEU_TX_PORTS_CONFIG_CRC(59).FEU0[0xb9a]=2
FEU_TX_PORTS_CONFIG_CRC(60).FEU0[0xb9b]=2
FEU_TX_PORTS_CONFIG_CRC(61).FEU0[0xb9c]=2
FEU_TX_PORTS_CONFIG_CRC(62).FEU0[0xb9d]=2
FEU_TX_PORTS_CONFIG_CRC(63).FEU0[0xb9e]=2
FEU_TX_PORTS_CONFIG_CRC(64).FEU0[0xb9f]=2
FEU_TX_PORTS_CONFIG_CRC(65).FEU0[0xba0]=2
FEU_TX_PORTS_CONFIG_CRC(66).FEU0[0xba1]=2
FEU_TX_PORTS_CONFIG_CRC(67).FEU0[0xba2]=2
FEU_TX_PORTS_CONFIG_CRC(68).FEU0[0xba3]=2
FEU_TX_PORTS_CONFIG_CRC(69).FEU0[0xba4]=2
FEU_TX_PORTS_CONFIG_CRC(70).FEU0[0xba5]=2
FEU_TX_PORTS_CONFIG_CRC(71).FEU0[0xba6]=2
FEU_TX_PORTS_CONFIG_CRC(72).FEU0[0xba7]=2
FEU_TX_PORTS_CONFIG_CRC(73).FEU0[0xba8]=2
FEU_TX_PORTS_CONFIG_CRC(74).FEU0[0xba9]=2
FEU_TX_PORTS_CONFIG_CRC(75).FEU0[0xbaa]=2
FEU_TX_PORTS_CONFIG_CRC(76).FEU0[0xbab]=2
FEU_TX_PORTS_CONFIG_CRC(77).FEU0[0xbac]=2
FEU_TX_PORTS_CONFIG_CRC(78).FEU0[0xbad]=2
FEU_TX_PORTS_CONFIG_CRC(79).FEU0[0xbae]=2
FEU_TX_PORTS_CONFIG_CRC(80).FEU0[0xbaf]=2
FEU_TX_PORTS_CONFIG_CRC(81).FEU0[0xbb0]=2
FEU_TX_PORTS_SRSTN.FEU0[0x108]=0
FEU_TX_PORT_OVF.FEU0[0xfe0]=0
FEU_TX_QMLF_CONFIG_RESET.FEU0[0xbb2]=0
FEU_TX_QMLF_CONFIG_STOP(0).FEU0[0xbb4]=1
FEU_TX_QMLF_CONFIG_STOP(1).FEU0[0xbb6]=1
FEU_TX_QMLF_CONFIG_STOP(2).FEU0[0xbb8]=1
FEU_TX_QMLF_CONFIG_STOP(3).FEU0[0xbba]=1
FEU_TX_QMLF_CONFIG_STOP(4).FEU0[0xbbc]=1
FEU_TX_QMLF_CONFIG_STOP(5).FEU0[0xbbe]=1
FEU_TX_QMLF_CONFIG_STOP(6).FEU0[0xbc0]=1
FEU_TX_QMLF_CONFIG_STOP(7).FEU0[0xbc2]=1
FEU_TX_QMLF_CONFIG_STOP(8).FEU0[0xbc4]=1
FEU_TX_QMLF_CONFIG_STOP(9).FEU0[0xbc6]=1
FEU_TX_QMLF_CONFIG_STOP(10).FEU0[0xbc8]=1
FEU_TX_QMLF_CONFIG_STOP(11).FEU0[0xbca]=1
FEU_TX_QMLF_CONFIG_STOP(12).FEU0[0xbcc]=1
FEU_TX_QMLF_CONFIG_STOP(13).FEU0[0xbce]=1
FEU_TX_QMLF_CONFIG_STOP(14).FEU0[0xbd0]=1
FEU_TX_QMLF_CONFIG_STOP(15).FEU0[0xbd2]=1
FEU_TX_QMLF_CONFIG_STOP(16).FEU0[0xbd4]=1
FEU_TX_QMLF_CONFIG_STOP(17).FEU0[0xbd6]=1
FEU_TX_QMLF_CONFIG_STOP(18).FEU0[0xbd8]=1
FEU_TX_QMLF_CONFIG_STOP(19).FEU0[0xbda]=1
FEU_TX_QMLF_CONFIG_STOP(20).FEU0[0xbdc]=1
FEU_TX_QMLF_CONFIG_STOP(21).FEU0[0xbde]=1
FEU_TX_QMLF_CONFIG_STOP(22).FEU0[0xbe0]=1
FEU_TX_QMLF_CONFIG_STOP(23).FEU0[0xbe2]=1
FEU_TX_QMLF_CONFIG_STOP(24).FEU0[0xbe4]=1
FEU_TX_QMLF_CONFIG_STOP(25).FEU0[0xbe6]=1
FEU_TX_QMLF_CONFIG_STOP(26).FEU0[0xbe8]=1
FEU_TX_QMLF_CONFIG_STOP(27).FEU0[0xbea]=1
FEU_TX_QMLF_CONFIG_STOP(28).FEU0[0xbec]=1
FEU_TX_QMLF_CONFIG_STOP(29).FEU0[0xbee]=1
FEU_TX_QMLF_CONFIG_STOP(30).FEU0[0xbf0]=1
FEU_TX_QMLF_CONFIG_STOP(31).FEU0[0xbf2]=1
FEU_TX_QMLF_CONFIG_STOP(32).FEU0[0xbf4]=1
FEU_TX_QMLF_CONFIG_STOP(33).FEU0[0xbf6]=1
FEU_TX_QMLF_CONFIG_STOP(34).FEU0[0xbf8]=1
FEU_TX_QMLF_CONFIG_STOP(35).FEU0[0xbfa]=1
FEU_TX_QMLF_CONFIG_STOP(36).FEU0[0xbfc]=1
FEU_TX_QMLF_CONFIG_STOP(37).FEU0[0xbfe]=1
FEU_TX_QMLF_CONFIG_STOP(38).FEU0[0xc00]=1
FEU_TX_QMLF_CONFIG_STOP(39).FEU0[0xc02]=1
FEU_TX_QMLF_CONFIG_STOP(40).FEU0[0xc04]=1
FEU_TX_QMLF_CONFIG_STOP(41).FEU0[0xc06]=1
FEU_TX_QMLF_CONFIG_STOP(42).FEU0[0xc08]=1
FEU_TX_QMLF_CONFIG_STOP(43).FEU0[0xc0a]=1
FEU_TX_QMLF_CONFIG_STOP(44).FEU0[0xc0c]=1
FEU_TX_QMLF_CONFIG_STOP(45).FEU0[0xc0e]=1
FEU_TX_QMLF_CONFIG_STOP(46).FEU0[0xc10]=1
FEU_TX_QMLF_CONFIG_STOP(47).FEU0[0xc12]=1
FEU_TX_QMLF_CONFIG_STOP(48).FEU0[0xc14]=1
FEU_TX_QMLF_CONFIG_STOP(49).FEU0[0xc16]=1
FEU_TX_QMLF_CONFIG_STOP(50).FEU0[0xc18]=1
FEU_TX_QMLF_CONFIG_STOP(51).FEU0[0xc1a]=1
FEU_TX_QMLF_CONFIG_STOP(52).FEU0[0xc1c]=1
FEU_TX_QMLF_CONFIG_STOP(53).FEU0[0xc1e]=1
FEU_TX_QMLF_CONFIG_STOP(54).FEU0[0xc20]=1
FEU_TX_QMLF_CONFIG_STOP(55).FEU0[0xc22]=1
FEU_TX_QMLF_CONFIG_STOP(56).FEU0[0xc24]=1
FEU_TX_QMLF_CONFIG_STOP(57).FEU0[0xc26]=1
FEU_TX_QMLF_CONFIG_STOP(58).FEU0[0xc28]=1
FEU_TX_QMLF_CONFIG_STOP(59).FEU0[0xc2a]=1
FEU_TX_QMLF_CONFIG_STOP(60).FEU0[0xc2c]=1
FEU_TX_QMLF_CONFIG_STOP(61).FEU0[0xc2e]=1
FEU_TX_QMLF_CONFIG_STOP(62).FEU0[0xc30]=1
FEU_TX_QMLF_CONFIG_STOP(63).FEU0[0xc32]=1
FEU_TX_QMLF_CONFIG_STOP(64).FEU0[0xc34]=1
FEU_TX_QMLF_CONFIG_STOP(65).FEU0[0xc36]=1
FEU_TX_QMLF_CONFIG_STOP(66).FEU0[0xc38]=1
FEU_TX_QMLF_CONFIG_STOP(67).FEU0[0xc3a]=1
FEU_TX_QMLF_CONFIG_STOP(68).FEU0[0xc3c]=1
FEU_TX_QMLF_CONFIG_STOP(69).FEU0[0xc3e]=1
FEU_TX_QMLF_CONFIG_STOP(70).FEU0[0xc40]=1
FEU_TX_QMLF_CONFIG_STOP(71).FEU0[0xc42]=1
FEU_TX_QMLF_CONFIG_STOP(72).FEU0[0xc44]=1
FEU_TX_QMLF_CONFIG_STOP(73).FEU0[0xc46]=1
FEU_TX_QMLF_CONFIG_STOP(74).FEU0[0xc48]=1
FEU_TX_QMLF_CONFIG_STOP(75).FEU0[0xc4a]=1
FEU_TX_QMLF_CONFIG_STOP(76).FEU0[0xc4c]=1
FEU_TX_QMLF_CONFIG_STOP(77).FEU0[0xc4e]=1
FEU_TX_QMLF_CONFIG_STOP(78).FEU0[0xc50]=1
FEU_TX_QMLF_CONFIG_STOP(79).FEU0[0xc52]=1
FEU_TX_QMLF_CONFIG_STOP(80).FEU0[0xc54]=1
FEU_TX_QMLF_CONFIG_STOP(81).FEU0[0xc56]=1
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(0).FEU0[0x1d6f]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(1).FEU0[0x1d70]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(2).FEU0[0x1d71]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(3).FEU0[0x1d72]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(4).FEU0[0x1d73]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(5).FEU0[0x1d74]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(6).FEU0[0x1d75]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(7).FEU0[0x1d76]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(8).FEU0[0x1d77]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(9).FEU0[0x1d78]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(10).FEU0[0x1d79]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(11).FEU0[0x1d7a]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(12).FEU0[0x1d7b]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(13).FEU0[0x1d7c]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(14).FEU0[0x1d7d]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(15).FEU0[0x1d7e]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(16).FEU0[0x1d7f]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(17).FEU0[0x1d80]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(18).FEU0[0x1d81]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(19).FEU0[0x1d82]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(20).FEU0[0x1d83]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(21).FEU0[0x1d84]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(22).FEU0[0x1d85]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(23).FEU0[0x1d86]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(24).FEU0[0x1d87]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(25).FEU0[0x1d88]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(26).FEU0[0x1d89]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(27).FEU0[0x1d8a]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(28).FEU0[0x1d8b]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(29).FEU0[0x1d8c]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(30).FEU0[0x1d8d]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(31).FEU0[0x1d8e]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(32).FEU0[0x1d8f]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(33).FEU0[0x1d90]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(34).FEU0[0x1d91]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(35).FEU0[0x1d92]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(36).FEU0[0x1d93]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(37).FEU0[0x1d94]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(38).FEU0[0x1d95]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(39).FEU0[0x1d96]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(40).FEU0[0x1d97]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(41).FEU0[0x1d98]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(42).FEU0[0x1d99]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(43).FEU0[0x1d9a]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(44).FEU0[0x1d9b]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(45).FEU0[0x1d9c]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(46).FEU0[0x1d9d]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(47).FEU0[0x1d9e]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(48).FEU0[0x1d9f]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(49).FEU0[0x1da0]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(50).FEU0[0x1da1]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(51).FEU0[0x1da2]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(52).FEU0[0x1da3]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(53).FEU0[0x1da4]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(54).FEU0[0x1da5]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(55).FEU0[0x1da6]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(56).FEU0[0x1da7]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(57).FEU0[0x1da8]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(58).FEU0[0x1da9]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(59).FEU0[0x1daa]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(60).FEU0[0x1dab]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(61).FEU0[0x1dac]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(62).FEU0[0x1dad]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(63).FEU0[0x1dae]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(64).FEU0[0x1daf]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(65).FEU0[0x1db0]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(66).FEU0[0x1db1]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(67).FEU0[0x1db2]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(68).FEU0[0x1db3]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(69).FEU0[0x1db4]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(70).FEU0[0x1db5]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(71).FEU0[0x1db6]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(72).FEU0[0x1db7]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(73).FEU0[0x1db8]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(74).FEU0[0x1db9]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(75).FEU0[0x1dba]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(76).FEU0[0x1dbb]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(77).FEU0[0x1dbc]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(78).FEU0[0x1dbd]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(79).FEU0[0x1dbe]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(80).FEU0[0x1dbf]=0
FEU_TX_TDM_CALENDAR_1_DEFINTIONS(81).FEU0[0x1dc0]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(0).FEU0[0x1dc1]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(1).FEU0[0x1dc2]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(2).FEU0[0x1dc3]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(3).FEU0[0x1dc4]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(4).FEU0[0x1dc5]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(5).FEU0[0x1dc6]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(6).FEU0[0x1dc7]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(7).FEU0[0x1dc8]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(8).FEU0[0x1dc9]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(9).FEU0[0x1dca]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(10).FEU0[0x1dcb]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(11).FEU0[0x1dcc]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(12).FEU0[0x1dcd]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(13).FEU0[0x1dce]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(14).FEU0[0x1dcf]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(15).FEU0[0x1dd0]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(16).FEU0[0x1dd1]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(17).FEU0[0x1dd2]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(18).FEU0[0x1dd3]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(19).FEU0[0x1dd4]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(20).FEU0[0x1dd5]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(21).FEU0[0x1dd6]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(22).FEU0[0x1dd7]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(23).FEU0[0x1dd8]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(24).FEU0[0x1dd9]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(25).FEU0[0x1dda]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(26).FEU0[0x1ddb]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(27).FEU0[0x1ddc]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(28).FEU0[0x1ddd]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(29).FEU0[0x1dde]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(30).FEU0[0x1ddf]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(31).FEU0[0x1de0]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(32).FEU0[0x1de1]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(33).FEU0[0x1de2]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(34).FEU0[0x1de3]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(35).FEU0[0x1de4]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(36).FEU0[0x1de5]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(37).FEU0[0x1de6]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(38).FEU0[0x1de7]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(39).FEU0[0x1de8]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(40).FEU0[0x1de9]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(41).FEU0[0x1dea]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(42).FEU0[0x1deb]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(43).FEU0[0x1dec]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(44).FEU0[0x1ded]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(45).FEU0[0x1dee]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(46).FEU0[0x1def]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(47).FEU0[0x1df0]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(48).FEU0[0x1df1]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(49).FEU0[0x1df2]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(50).FEU0[0x1df3]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(51).FEU0[0x1df4]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(52).FEU0[0x1df5]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(53).FEU0[0x1df6]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(54).FEU0[0x1df7]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(55).FEU0[0x1df8]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(56).FEU0[0x1df9]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(57).FEU0[0x1dfa]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(58).FEU0[0x1dfb]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(59).FEU0[0x1dfc]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(60).FEU0[0x1dfd]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(61).FEU0[0x1dfe]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(62).FEU0[0x1dff]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(63).FEU0[0x1e00]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(64).FEU0[0x1e01]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(65).FEU0[0x1e02]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(66).FEU0[0x1e03]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(67).FEU0[0x1e04]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(68).FEU0[0x1e05]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(69).FEU0[0x1e06]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(70).FEU0[0x1e07]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(71).FEU0[0x1e08]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(72).FEU0[0x1e09]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(73).FEU0[0x1e0a]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(74).FEU0[0x1e0b]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(75).FEU0[0x1e0c]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(76).FEU0[0x1e0d]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(77).FEU0[0x1e0e]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(78).FEU0[0x1e0f]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(79).FEU0[0x1e10]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(80).FEU0[0x1e11]=0
FEU_TX_TDM_CALENDAR_2_DEFINTIONS(81).FEU0[0x1e12]=0
FEU_TX_TDM_CALENDAR_SELECT.FEU0[0x1e13]=0
FEU_TX_TMC_L_1_CFG(0).FEU0[0x1791]=0x7f
FEU_TX_TMC_L_1_CFG(1).FEU0[0x1792]=0x7f
FEU_TX_TMC_L_1_CFG(2).FEU0[0x1793]=0x7f
FEU_TX_TMC_L_1_CFG(3).FEU0[0x1794]=0x7f
FEU_TX_TMC_L_1_CFG(4).FEU0[0x1795]=0x7f
FEU_TX_TMC_L_1_CFG(5).FEU0[0x1796]=0x7f
FEU_TX_TMC_L_1_CFG(6).FEU0[0x1797]=0x7f
FEU_TX_TMC_L_1_CFG(7).FEU0[0x1798]=0x7f
FEU_TX_TMC_L_1_CFG(8).FEU0[0x1799]=0x7f
FEU_TX_TMC_L_1_CFG(9).FEU0[0x179a]=0x7f
FEU_TX_TMC_L_1_CFG(10).FEU0[0x179b]=0x7f
FEU_TX_TMC_L_1_CFG(11).FEU0[0x179c]=0x7f
FEU_TX_TMC_L_1_CFG(12).FEU0[0x179d]=0x7f
FEU_TX_TMC_L_1_CFG(13).FEU0[0x179e]=0x7f
FEU_TX_TMC_L_1_CFG(14).FEU0[0x179f]=0x7f
FEU_TX_TMC_L_1_CFG(15).FEU0[0x17a0]=0x7f
FEU_TX_TMC_L_1_CFG(16).FEU0[0x17a1]=0x7f
FEU_TX_TMC_L_1_CFG(17).FEU0[0x17a2]=0x7f
FEU_TX_TMC_L_1_CFG(18).FEU0[0x17a3]=0x7f
FEU_TX_TMC_L_1_CFG(19).FEU0[0x17a4]=0x7f
FEU_TX_TMC_L_1_CFG(20).FEU0[0x17a5]=0x7f
FEU_TX_TMC_L_1_CFG(21).FEU0[0x17a6]=0x7f
FEU_TX_TMC_L_1_CFG(22).FEU0[0x17a7]=0x7f
FEU_TX_TMC_L_1_CFG(23).FEU0[0x17a8]=0x7f
FEU_TX_TMC_L_1_CFG(24).FEU0[0x17a9]=0x7f
FEU_TX_TMC_L_1_CFG(25).FEU0[0x17aa]=0x7f
FEU_TX_TMC_L_1_CFG(26).FEU0[0x17ab]=0x7f
FEU_TX_TMC_L_1_CFG(27).FEU0[0x17ac]=0x7f
FEU_TX_TMC_L_1_CFG(28).FEU0[0x17ad]=0x7f
FEU_TX_TMC_L_1_CFG(29).FEU0[0x17ae]=0x7f
FEU_TX_TMC_L_1_CFG(30).FEU0[0x17af]=0x7f
FEU_TX_TMC_L_1_CFG(31).FEU0[0x17b0]=0x7f
FEU_TX_TMC_L_1_CFG(32).FEU0[0x17b1]=0x7f
FEU_TX_TMC_L_1_CFG(33).FEU0[0x17b2]=0x7f
FEU_TX_TMC_L_1_CFG(34).FEU0[0x17b3]=0x7f
FEU_TX_TMC_L_1_CFG(35).FEU0[0x17b4]=0x7f
FEU_TX_TMC_L_1_CFG(36).FEU0[0x17b5]=0x7f
FEU_TX_TMC_L_1_CFG(37).FEU0[0x17b6]=0x7f
FEU_TX_TMC_L_1_CFG(38).FEU0[0x17b7]=0x7f
FEU_TX_TMC_L_1_CFG(39).FEU0[0x17b8]=0x7f
FEU_TX_TMC_L_1_CFG(40).FEU0[0x17b9]=0x7f
FEU_TX_TMC_L_1_CFG(41).FEU0[0x17ba]=0x7f
FEU_TX_TMC_L_1_CFG(42).FEU0[0x17bb]=0x7f
FEU_TX_TMC_L_1_CFG(43).FEU0[0x17bc]=0x7f
FEU_TX_TMC_L_1_CFG(44).FEU0[0x17bd]=0x7f
FEU_TX_TMC_L_1_CFG(45).FEU0[0x17be]=0x7f
FEU_TX_TMC_L_1_CFG(46).FEU0[0x17bf]=0x7f
FEU_TX_TMC_L_1_CFG(47).FEU0[0x17c0]=0x7f
FEU_TX_TMC_L_1_CFG(48).FEU0[0x17c1]=0x7f
FEU_TX_TMC_L_1_CFG(49).FEU0[0x17c2]=0x7f
FEU_TX_TMC_L_1_CFG(50).FEU0[0x17c3]=0x7f
FEU_TX_TMC_L_1_CFG(51).FEU0[0x17c4]=0x7f
FEU_TX_TMC_RATE_LIMITER_LEVEL(0).FEU0[0xfe3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(1).FEU0[0xfe5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(2).FEU0[0xfe7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(3).FEU0[0xfe9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(4).FEU0[0xfeb]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(5).FEU0[0xfed]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(6).FEU0[0xfef]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(7).FEU0[0xff1]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(8).FEU0[0xff3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(9).FEU0[0xff5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(10).FEU0[0xff7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(11).FEU0[0xff9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(12).FEU0[0xffb]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(13).FEU0[0xffd]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(14).FEU0[0xfff]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(15).FEU0[0x1001]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(16).FEU0[0x1003]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(17).FEU0[0x1005]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(18).FEU0[0x1007]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(19).FEU0[0x1009]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(20).FEU0[0x100b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(21).FEU0[0x100d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(22).FEU0[0x100f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(23).FEU0[0x1011]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(24).FEU0[0x1013]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(25).FEU0[0x1015]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(26).FEU0[0x1017]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(27).FEU0[0x1019]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(28).FEU0[0x101b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(29).FEU0[0x101d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(30).FEU0[0x101f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(31).FEU0[0x1021]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(32).FEU0[0x1023]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(33).FEU0[0x1025]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(34).FEU0[0x1027]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(35).FEU0[0x1029]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(36).FEU0[0x102b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(37).FEU0[0x102d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(38).FEU0[0x102f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(39).FEU0[0x1031]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(40).FEU0[0x1033]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(41).FEU0[0x1035]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(42).FEU0[0x1037]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(43).FEU0[0x1039]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(44).FEU0[0x103b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(45).FEU0[0x103d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(46).FEU0[0x103f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(47).FEU0[0x1041]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(48).FEU0[0x1043]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(49).FEU0[0x1045]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(50).FEU0[0x1047]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(51).FEU0[0x1049]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(52).FEU0[0x104b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(53).FEU0[0x104d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(54).FEU0[0x104f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(55).FEU0[0x1051]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(56).FEU0[0x1053]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(57).FEU0[0x1055]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(58).FEU0[0x1057]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(59).FEU0[0x1059]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(60).FEU0[0x105b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(61).FEU0[0x105d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(62).FEU0[0x105f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(63).FEU0[0x1061]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(64).FEU0[0x1063]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(65).FEU0[0x1065]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(66).FEU0[0x1067]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(67).FEU0[0x1069]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(68).FEU0[0x106b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(69).FEU0[0x106d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(70).FEU0[0x106f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(71).FEU0[0x1071]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(72).FEU0[0x1073]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(73).FEU0[0x1075]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(74).FEU0[0x1077]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(75).FEU0[0x1079]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(76).FEU0[0x107b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(77).FEU0[0x107d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(78).FEU0[0x107f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(79).FEU0[0x1081]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(80).FEU0[0x1083]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL(81).FEU0[0x1085]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(0).FEU0[0x1087]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(1).FEU0[0x1089]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(2).FEU0[0x108b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(3).FEU0[0x108d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(4).FEU0[0x108f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(5).FEU0[0x1091]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(6).FEU0[0x1093]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(7).FEU0[0x1095]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(8).FEU0[0x1097]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(9).FEU0[0x1099]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(10).FEU0[0x109b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(11).FEU0[0x109d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(12).FEU0[0x109f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(13).FEU0[0x10a1]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(14).FEU0[0x10a3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(15).FEU0[0x10a5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(16).FEU0[0x10a7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(17).FEU0[0x10a9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(18).FEU0[0x10ab]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(19).FEU0[0x10ad]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(20).FEU0[0x10af]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(21).FEU0[0x10b1]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(22).FEU0[0x10b3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(23).FEU0[0x10b5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(24).FEU0[0x10b7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(25).FEU0[0x10b9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(26).FEU0[0x10bb]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(27).FEU0[0x10bd]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(28).FEU0[0x10bf]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(29).FEU0[0x10c1]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(30).FEU0[0x10c3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(31).FEU0[0x10c5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(32).FEU0[0x10c7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(33).FEU0[0x10c9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(34).FEU0[0x10cb]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(35).FEU0[0x10cd]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(36).FEU0[0x10cf]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(37).FEU0[0x10d1]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(38).FEU0[0x10d3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(39).FEU0[0x10d5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(40).FEU0[0x10d7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(41).FEU0[0x10d9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(42).FEU0[0x10db]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(43).FEU0[0x10dd]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(44).FEU0[0x10df]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(45).FEU0[0x10e1]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(46).FEU0[0x10e3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(47).FEU0[0x10e5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(48).FEU0[0x10e7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(49).FEU0[0x10e9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(50).FEU0[0x10eb]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(51).FEU0[0x10ed]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(52).FEU0[0x10ef]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(53).FEU0[0x10f1]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(54).FEU0[0x10f3]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(55).FEU0[0x10f5]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(56).FEU0[0x10f7]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(57).FEU0[0x10f9]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(58).FEU0[0x10fb]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(59).FEU0[0x10fd]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(60).FEU0[0x10ff]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(61).FEU0[0x1101]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(62).FEU0[0x1103]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(63).FEU0[0x1105]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(64).FEU0[0x1107]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(65).FEU0[0x1109]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(66).FEU0[0x110b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(67).FEU0[0x110d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(68).FEU0[0x110f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(69).FEU0[0x1111]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(70).FEU0[0x1113]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(71).FEU0[0x1115]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(72).FEU0[0x1117]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(73).FEU0[0x1119]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(74).FEU0[0x111b]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(75).FEU0[0x111d]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(76).FEU0[0x111f]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(77).FEU0[0x1121]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(78).FEU0[0x1123]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(79).FEU0[0x1125]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(80).FEU0[0x1127]=0
FEU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY(81).FEU0[0x1129]=0
FEU_TX_TOTAL_BYET_SENT_TO_PM_1.FEU0[0x15d8]=0
FEU_TX_TOTAL_BYTE_COUNTER_1.FEU0[0x15cf]=0
FEU_TX_TOTAL_BYTE_COUNTER_2.FEU0[0x15d0]=0
FEU_TX_TOTAL_BYTE_COUNTER_3.FEU0[0x15d1]=0
FEU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER_1.FEU0[0x15d2]=0
FEU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER_2.FEU0[0x15d3]=0
FEU_TX_TOTAL_PKT_COUNTER_1.FEU0[0x15cc]=0
FEU_TX_TOTAL_PKT_COUNTER_2.FEU0[0x15cd]=0
FEU_TX_TOTAL_PKT_COUNTER_3.FEU0[0x15ce]=0
FEU_TX_TOTAL_PKT_SENT_TO_PM_1.FEU0[0x15d6]=0
FEU_TX_TOTAL_PKT_SENT_TO_PM_2.FEU0[0x15d7]=0
FEU_TX_TOTAL_PKT_WITH_ERR_COUNTER_1.FEU0[0x15d4]=0
FEU_TX_TOTAL_PKT_WITH_ERR_COUNTER_2.FEU0[0x15d5]=0
FEU_TX_WRONG_PORT_FROM_EGQ_QMLF.FEU0[0xf3a]=0
FPRD_ECC_2B_ERR_CNT.FPRD0[0x96]=0
FPRD_ECC_INTERRUPT_REGISTER.FPRD0[0x7]=0
FPRD_ECC_INTERRUPT_REGISTER_MASK.FPRD0[0x17]=0
FPRD_ECC_INTERRUPT_REGISTER_TEST.FPRD0[0x1f]=0
FPRD_GTIMER_CONFIGURATION.FPRD0[0x89]=0
FPRD_GTIMER_CYCLE.FPRD0[0x88]=0x3b9aca00
FPRD_INTERRUPT_MASK_REGISTER.FPRD0[0x10]=0
FPRD_INTERRUPT_REGISTER.FPRD0[0x0]=0
FPRD_INTERRUPT_REGISTER_TEST.FPRD0[0x18]=0
FPRD_PARSER_HARD_CONTROL.FPRD0[0x108]=0xdc0c523819c
FPRD_PARSER_HARD_CONTROL_PLANE(0).FPRD0[0x123]=0
FPRD_PARSER_HARD_CONTROL_PLANE(1).FPRD0[0x124]=0
FPRD_PARSER_HARD_CONTROL_PLANE(2).FPRD0[0x125]=0
FPRD_PARSER_HARD_CONTROL_PLANE(3).FPRD0[0x126]=0
FPRD_PARSER_HARD_ETHER_TYPE.FPRD0[0x122]=0
FPRD_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.FPRD0[0x129]=0x6db492249000
FPRD_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.FPRD0[0x128]=0x6db6db6db6db492492492492249249249249000000000000
FPRD_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.FPRD0[0x12a]=0x6d2240
FPRD_PARSER_HARD_PORT_ETH_TPID(0).FPRD0[0x10a]=0
FPRD_PARSER_HARD_PORT_ETH_TPID(1).FPRD0[0x10b]=0
FPRD_PARSER_HARD_PORT_ETH_TPID(2).FPRD0[0x10c]=0
FPRD_PARSER_HARD_PORT_ETH_TPID(3).FPRD0[0x10d]=0
FPRD_PARSER_HARD_PORT_ETH_TPID(4).FPRD0[0x10e]=0
FPRD_PARSER_HARD_PORT_ETH_TPID(5).FPRD0[0x10f]=0
FPRD_PARSER_HARD_PORT_ETH_TPID(6).FPRD0[0x110]=0
FPRD_PARSER_HARD_PORT_ETH_TPID(7).FPRD0[0x111]=0
FPRD_PARSER_HARD_PORT_PROPERTIES(0).FPRD0[0x11a]=0xf
FPRD_PARSER_HARD_PORT_PROPERTIES(1).FPRD0[0x11b]=0xf
FPRD_PARSER_HARD_PORT_PROPERTIES(2).FPRD0[0x11c]=0xf
FPRD_PARSER_HARD_PORT_PROPERTIES(3).FPRD0[0x11d]=0xf
FPRD_PARSER_HARD_PORT_PROPERTIES(4).FPRD0[0x11e]=0xf
FPRD_PARSER_HARD_PORT_PROPERTIES(5).FPRD0[0x11f]=0xf
FPRD_PARSER_HARD_PORT_PROPERTIES(6).FPRD0[0x120]=0xf
FPRD_PARSER_HARD_PORT_PROPERTIES(7).FPRD0[0x121]=0xf
FPRD_PARSER_HARD_PORT_TYPE(0).FPRD0[0x112]=7
FPRD_PARSER_HARD_PORT_TYPE(1).FPRD0[0x113]=7
FPRD_PARSER_HARD_PORT_TYPE(2).FPRD0[0x114]=7
FPRD_PARSER_HARD_PORT_TYPE(3).FPRD0[0x115]=7
FPRD_PARSER_HARD_PORT_TYPE(4).FPRD0[0x116]=7
FPRD_PARSER_HARD_PORT_TYPE(5).FPRD0[0x117]=7
FPRD_PARSER_HARD_PORT_TYPE(6).FPRD0[0x118]=7
FPRD_PARSER_HARD_PORT_TYPE(7).FPRD0[0x119]=7
FPRD_PARSER_HARD_SPECIAL_LABEL(0).FPRD0[0x12b]=0x30
FPRD_PARSER_HARD_SPECIAL_LABEL(1).FPRD0[0x12c]=0x30
FPRD_PARSER_HARD_SPECIAL_LABEL(2).FPRD0[0x12d]=0x30
FPRD_PARSER_HARD_SPECIAL_LABEL(3).FPRD0[0x12e]=0x30
FPRD_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.FPRD0[0x127]=0x6db6db6db6db492492492492249249249249000000000000
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).FPRD0[0x147]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).FPRD0[0x148]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).FPRD0[0x149]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).FPRD0[0x14a]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).FPRD0[0x14b]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).FPRD0[0x14c]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).FPRD0[0x14d]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).FPRD0[0x14e]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).FPRD0[0x14f]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).FPRD0[0x150]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).FPRD0[0x151]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).FPRD0[0x152]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).FPRD0[0x153]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).FPRD0[0x154]=0x20
FPRD_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).FPRD0[0x155]=0x20
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).FPRD0[0x12f]=1
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).FPRD0[0x130]=1
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(2).FPRD0[0x131]=1
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(3).FPRD0[0x132]=1
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(4).FPRD0[0x133]=1
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(5).FPRD0[0x134]=1
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(6).FPRD0[0x135]=1
FPRD_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(7).FPRD0[0x136]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).FPRD0[0x137]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).FPRD0[0x138]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).FPRD0[0x139]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).FPRD0[0x13a]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).FPRD0[0x13b]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).FPRD0[0x13c]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).FPRD0[0x13d]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).FPRD0[0x13e]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).FPRD0[0x13f]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).FPRD0[0x140]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).FPRD0[0x141]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).FPRD0[0x142]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).FPRD0[0x143]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).FPRD0[0x144]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).FPRD0[0x145]=1
FPRD_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).FPRD0[0x146]=1
FPRD_PARSER_SOFT_TCAM_0_TO_7.FPRD0[0x156]=0
FPRD_PARSER_SOFT_TCAM_16_TO_23.FPRD0[0x158]=0
FPRD_PARSER_SOFT_TCAM_24_TO_31.FPRD0[0x159]=0
FPRD_PARSER_SOFT_TCAM_8_TO_15.FPRD0[0x157]=0
FPRD_REG_0094.FPRD0[0x94]=0
FPRD_REG_0098.FPRD0[0x98]=0
FPRD_REG_009A.FPRD0[0x9a]=0
FPRD_REG_009C.FPRD0[0x9c]=0
FPRD_REG_00A0.FPRD0[0xa0]=0
FPRD_REG_00C2.FPRD0[0xc2]=0x10
FPRD_RESERVED_MTCD.FPRD0[0xae]=0x30
FPRD_RESERVED_MTCP.FPRD0[0xad]=0x300000600000000
FPRD_RESERVED_SPARE_0.FPRD0[0x90]=0xffffffff
FPRD_RESERVED_SPARE_1.FPRD0[0x91]=0xffffffff
FPRD_RESERVED_SPARE_2.FPRD0[0x92]=0
FPRD_RESERVED_SPARE_3.FPRD0[0x93]=0
FPRD_SBUS_BROADCAST_ID.FPRD0[0x86]=0x7ff
FPRD_SBUS_LAST_IN_CHAIN.FPRD0[0x87]=0
FPRD_SPECIAL_CLOCK_CONTROLS.FPRD0[0xc1]=2
FQP_DEQ_COUNTERS_CONFIG.FQP0[0x164]=0
FQP_ECC_1B_ERR_CNT.FQP0[0x94]=0
FQP_ECC_2B_ERR_CNT.FQP0[0x96]=0
FQP_ECC_ERR_1B_MONITOR_MEM_MASK.FQP0[0x9a]=0x1ffffff
FQP_ECC_ERR_2B_MONITOR_MEM_MASK.FQP0[0x9c]=0x1ffffff
FQP_ECC_INTERRUPT_REGISTER.FQP0[0x7]=0
FQP_ECC_INTERRUPT_REGISTER_MASK.FQP0[0x17]=0
FQP_ECC_INTERRUPT_REGISTER_TEST.FQP0[0x1f]=0
FQP_ENABLE_DYNAMIC_MEMORY_ACCESS.FQP0[0x84]=0
FQP_ETS_PERFORMANCE_FIX_ENABLE.FQP0[0x16c]=0x2b
FQP_FQP_2_PQP_BYTES_RDY.FQP0[0x152]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
FQP_FQP_2_PQP_PD_RDY.FQP0[0x149]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
FQP_FQP_BLOCK_INIT_STATUS.FQP0[0x100]=0
FQP_FQP_BUBBLE_CONFIGURATION.FQP0[0x15d]=0x80020
FQP_FQP_BUBBLE_TRIGGER.FQP0[0x15e]=0
FQP_FQP_BYTES_COUNTER.FQP0[0x169]=0x12e7a1f97ef4
FQP_FQP_CALENDER_SETTING.FQP0[0x130]=5
FQP_FQP_CANCEL_CNT.FQP0[0x15f]=0
FQP_FQP_CONFIGURATION.FQP0[0x101]=0
FQP_FQP_DEBUG_HALT_CONFIGURATION.FQP0[0x15c]=0
FQP_FQP_DYNAMIC_RATE_ALLOCATOR.FQP0[0x11f]=0x42008000020048141e0
FQP_FQP_PACKETS_COUNTER.FQP0[0x165]=0x1e1268143
FQP_FQP_SCHEDULER_CONFIGURATION.FQP0[0x10b]=0x2301
FQP_FQP_SEGMENTS_COUNTER.FQP0[0x167]=0x18ed7cb47
FQP_FQP_TXI_BLOCK_CNT.FQP0[0x163]=0
FQP_FQP_TXI_BLOCK_CNT_CONFIGURATION.FQP0[0x162]=0
FQP_FQP_TXQ_CONFIGURATION.FQP0[0x11e]=0x106e343
FQP_FRAGMENTATION_NOT_READY_INDICATION.FQP0[0x13a]=0x83b42b89121417c0808000000fc3bfa220
FQP_FRAGMENTATION_QUEUES_EMPTY_INDICATION.FQP0[0x131]=0
FQP_GTIMER_CONFIGURATION.FQP0[0x89]=0
FQP_GTIMER_CYCLE.FQP0[0x88]=0x3b9aca00
FQP_IFC_IS_WORK_CONSERVING.FQP0[0x122]=0xffffffffffffffffffff
FQP_INDIRECT_COMMAND.FQP0[0x80]=0xe000002
FQP_INDIRECT_COMMAND_ADDRESS.FQP0[0x81]=0x170100
FQP_INDIRECT_COMMAND_RD_DATA.FQP0[0x60]=0xff
FQP_INDIRECT_COMMAND_WR_DATA.FQP0[0x20]=0xff
FQP_INDIRECT_FORCE_BUBBLE.FQP0[0x83]=0x20019
FQP_INIT_FQP_TXI.FQP0[0x127]=0x8a00000000000000000000000000000000000000000000000000000000000000000000
FQP_INTERFACE_FLUSHING_ENABLE.FQP0[0x106]=0
FQP_INTERRUPT_MASK_REGISTER.FQP0[0x10]=0
FQP_INTERRUPT_REGISTER.FQP0[0x0]=0
FQP_INTERRUPT_REGISTER_TEST.FQP0[0x18]=0
FQP_PCMI_0.FQP0[0xb0]=0x3b9aca00
FQP_PCMI_1.FQP0[0xb3]=0x3b9aca00
FQP_PCMI_2.FQP0[0xb6]=0x3b9aca00
FQP_PCMI_3.FQP0[0xb9]=0x3b9aca00
FQP_PCMI_4.FQP0[0xbc]=0x3b9aca00
FQP_PCMI_0_S.FQP0[0xb1]=0
FQP_PCMI_0_T.FQP0[0xb2]=0
FQP_PCMI_1_S.FQP0[0xb4]=0
FQP_PCMI_1_T.FQP0[0xb5]=0
FQP_PCMI_2_S.FQP0[0xb7]=0
FQP_PCMI_2_T.FQP0[0xb8]=0
FQP_PCMI_3_S.FQP0[0xba]=0
FQP_PCMI_3_T.FQP0[0xbb]=0
FQP_PCMI_4_S.FQP0[0xbd]=0
FQP_PCMI_4_T.FQP0[0xbe]=0
FQP_PHANTOM_QS_CFG.FQP0[0x10c]=0x1770
FQP_PHANTOM_QS_DEBUG.FQP0[0x10f]=3
FQP_PHANTOM_QS_PER_IFC_DISABLE.FQP0[0x119]=0xffffffffffffffffffffffffffffffffff
FQP_PHANTOM_QS_PER_IFC_PROFILE.FQP0[0x110]=0
FQP_REG_0041.FQP0[0x41]=0
FQP_REG_0098.FQP0[0x98]=0
FQP_REG_00A0.FQP0[0xa0]=0
FQP_REG_00C2.FQP0[0xc2]=0x10
FQP_REG_00C5.FQP0[0xc5]=0x400
FQP_RESERVED_MTCD.FQP0[0xae]=0x30
FQP_RESERVED_MTCP.FQP0[0xad]=0x300000600000000
FQP_RESERVED_SPARE_0.FQP0[0x90]=0xffffffff
FQP_RESERVED_SPARE_1.FQP0[0x91]=0xffffffff
FQP_RESERVED_SPARE_2.FQP0[0x92]=0
FQP_RESERVED_SPARE_3.FQP0[0x93]=0
FQP_SBUS_BROADCAST_ID.FQP0[0x86]=0x7ff
FQP_SBUS_LAST_IN_CHAIN.FQP0[0x87]=0
FQP_SPECIAL_CLOCK_CONTROLS.FQP0[0xc1]=2
FQP_TXI_CREDITS_COUNTER.FQP0[0x16b]=0x1d400
FQP_TXI_OVER_FLOW_STATUS.FQP0[0x144]=0
FQP_TXI_UNDER_FLOW_STATUS.FQP0[0x13f]=0
FQP_TXQ_WATERMARK_CONFIG.FQP0[0x15b]=0
ICFG_ARMCSSYS_CONFIG_0.CMIC0[0x411e0]=0
ICFG_ARMCSSYS_ECC_INTR_CLR.CMIC0[0x411e8]=0
ICFG_ARMCSSYS_ECC_INTR_EN.CMIC0[0x411e4]=0
ICFG_ARMCSSYS_ECC_INTR_STATUS.CMIC0[0x411ec]=0
ICFG_ARMCSSYS_ECC_LOG.CMIC0[0x411f0]=0
ICFG_CHIP_ID_REG.CMIC0[0x41000]=0x8483
ICFG_CHIP_LP_INTR_ENABLE_REG0.CMIC0[0x41730]=0
ICFG_CHIP_LP_INTR_ENABLE_REG1.CMIC0[0x41734]=0
ICFG_CHIP_LP_INTR_ENABLE_REG2.CMIC0[0x41738]=0
ICFG_CHIP_LP_INTR_ENABLE_REG3.CMIC0[0x4173c]=0
ICFG_CHIP_LP_INTR_RAW_STATUS_REG0.CMIC0[0x41740]=0
ICFG_CHIP_LP_INTR_RAW_STATUS_REG1.CMIC0[0x41744]=0
ICFG_CHIP_LP_INTR_RAW_STATUS_REG2.CMIC0[0x41748]=0
ICFG_CHIP_LP_INTR_RAW_STATUS_REG3.CMIC0[0x4174c]=0
ICFG_CHIP_LP_INTR_STATUS_REG0.CMIC0[0x41750]=0
ICFG_CHIP_LP_INTR_STATUS_REG1.CMIC0[0x41754]=0
ICFG_CHIP_LP_INTR_STATUS_REG2.CMIC0[0x41758]=0
ICFG_CHIP_LP_INTR_STATUS_REG3.CMIC0[0x4175c]=0
ICFG_CHIP_REVISION_ID.CMIC0[0x41004]=0x12
ICFG_CMICX_BASE_ADDRESS.CMIC0[0x41010]=0x3200000
ICFG_CMIC_RCPU_SW_PROG_INTR.CMIC0[0x417a0]=0
ICFG_CORTEXM0_U0_SW_PROG_INTR.CMIC0[0x41790]=0
ICFG_CORTEXM0_U1_SW_PROG_INTR.CMIC0[0x41794]=0
ICFG_CORTEXM0_U2_SW_PROG_INTR.CMIC0[0x41798]=0
ICFG_CORTEXM0_U3_SW_PROG_INTR.CMIC0[0x4179c]=0
ICFG_DMAC_CONFIG_0.CMIC0[0x41190]=0
ICFG_DMAC_CONFIG_1.CMIC0[0x41194]=0
ICFG_DMAC_ECC_INTR_CLR.CMIC0[0x4119c]=0
ICFG_DMAC_ECC_INTR_EN.CMIC0[0x41198]=0x2f
ICFG_DMAC_ECC_INTR_STATUS.CMIC0[0x411a0]=0
ICFG_DMAC_ECC_LOG_1.CMIC0[0x411a4]=0
ICFG_DMAC_ECC_LOG_2.CMIC0[0x411a8]=0
ICFG_ECC_ERR_INTR_ENABLE.CMIC0[0x4176c]=0x7ff
ICFG_ECC_ERR_INTR_RAW_STATUS.CMIC0[0x41770]=0
ICFG_ECC_ERR_INTR_STATUS.CMIC0[0x41774]=0
ICFG_EROM_BASE_ADDRESS.CMIC0[0x410fc]=0xffff1000
ICFG_GEN_PURPOSE_REG0.CMIC0[0x417d4]=0x2f
ICFG_GEN_PURPOSE_REG1.CMIC0[0x417d8]=0
ICFG_GEN_PURPOSE_REG2.CMIC0[0x417dc]=0
ICFG_GEN_PURPOSE_REG3.CMIC0[0x417e0]=0
ICFG_GEN_PURPOSE_REG4.CMIC0[0x417e4]=0
ICFG_GEN_PURPOSE_REG5.CMIC0[0x417e8]=0
ICFG_GEN_PURPOSE_REG6.CMIC0[0x417ec]=0
ICFG_GEN_PURPOSE_REG7.CMIC0[0x417f0]=0
ICFG_GEN_PURPOSE_REG8.CMIC0[0x417f4]=0
ICFG_GEN_PURPOSE_REG9.CMIC0[0x417f8]=0
ICFG_GEN_PURPOSE_REG10.CMIC0[0x417fc]=0
ICFG_GEN_PURPOSE_REG11.CMIC0[0x41800]=0
ICFG_GEN_PURPOSE_REG12.CMIC0[0x41804]=0
ICFG_GEN_PURPOSE_REG13.CMIC0[0x41808]=0
ICFG_GEN_PURPOSE_REG14.CMIC0[0x4180c]=0
ICFG_GEN_PURPOSE_REG15.CMIC0[0x41810]=0xaface8c0
ICFG_IDM_INTR_ENABLE.CMIC0[0x41760]=0
ICFG_IDM_INTR_RAW_STATUS.CMIC0[0x41764]=0
ICFG_IDM_INTR_STATUS.CMIC0[0x41768]=0
ICFG_INTR_COUNTER_CTRL.CMIC0[0x41814]=0
ICFG_INTR_COUNTER_LSB.CMIC0[0x41818]=0
ICFG_INTR_COUNTER_MSB.CMIC0[0x4181c]=0
ICFG_IPROCGENRES_SW_RST.CMIC0[0x417d0]=7
ICFG_IPROCPERIPH_COMMON.CMIC0[0x416ec]=6
ICFG_IPROCPERIPH_I2CS0.CMIC0[0x416e4]=0
ICFG_IPROCPERIPH_SPIS0.CMIC0[0x416e0]=0
ICFG_IPROCPERIPH_SW_RST.CMIC0[0x416e8]=0x3f
ICFG_IPROC_INT_ENABLE_WR1B_MODE.CMIC0[0x41780]=0
ICFG_IPROC_IOPAD_CTRL_0.CMIC0[0x415f0]=0x17171717
ICFG_IPROC_IOPAD_CTRL_1.CMIC0[0x415f4]=0xf0f1717
ICFG_IPROC_IOPAD_CTRL_2.CMIC0[0x415f8]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_3.CMIC0[0x415fc]=0xf0f170f
ICFG_IPROC_IOPAD_CTRL_4.CMIC0[0x41600]=0xf0f170f
ICFG_IPROC_IOPAD_CTRL_5.CMIC0[0x41604]=0x170f170f
ICFG_IPROC_IOPAD_CTRL_6.CMIC0[0x41608]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_7.CMIC0[0x4160c]=0x17170f0f
ICFG_IPROC_IOPAD_CTRL_8.CMIC0[0x41610]=0x17171717
ICFG_IPROC_IOPAD_CTRL_9.CMIC0[0x41614]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_10.CMIC0[0x41618]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_11.CMIC0[0x4161c]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_12.CMIC0[0x41620]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_13.CMIC0[0x41624]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_14.CMIC0[0x41628]=0xf0f0f0f
ICFG_IPROC_IOPAD_CTRL_15.CMIC0[0x4162c]=0x17171717
ICFG_IPROC_IOPAD_CTRL_16.CMIC0[0x41630]=0x17171717
ICFG_IPROC_IOPAD_CTRL_17.CMIC0[0x41634]=0x1717
ICFG_IP_CONTROL_CLK_EN.CMIC0[0x41690]=0x47fffc00
ICFG_IP_CONTROL_SOFT_RESET.CMIC0[0x41698]=0
ICFG_IP_DISABLE_STRAP_STATUS_0.CMIC0[0x41014]=0x200
ICFG_IP_REVID_0.CMIC0[0x41640]=0x3030201
ICFG_IP_REVID_1.CMIC0[0x41644]=0x3060101
ICFG_IP_REVID_2.CMIC0[0x41648]=0x8030808
ICFG_IP_REVID_3.CMIC0[0x4164c]=0x7040201
ICFG_IP_REVID_4.CMIC0[0x41650]=0x1000002
ICFG_MEM_ECC_CTRL.CMIC0[0x41018]=0
ICFG_MHOST0_STRAPS.CMIC0[0x41050]=1
ICFG_MHOST0_SW_PROG_INTR.CMIC0[0x41788]=0
ICFG_MHOST1_STRAPS.CMIC0[0x410a0]=0
ICFG_MHOST1_SW_PROG_INTR.CMIC0[0x4178c]=0
ICFG_MSIX_TABLE.CMIC0[0x41370]=0
ICFG_PAXB_0_RD_CMPL_BUF_0_MEM_CTRL.CMIC0[0x41fa4]=0
ICFG_PAXB_0_RD_CMPL_BUF_1_MEM_CTRL.CMIC0[0x41fa8]=0
ICFG_PAXB_0_RX_RD_CPL_BUF_MEM_CTRL.CMIC0[0x41fc8]=0
ICFG_PAXB_0_RX_WR_DATA_BUF_MEM_CTRL.CMIC0[0x41fc4]=0
ICFG_PAXB_0_WR_DATA_BUF_MEM_CTRL.CMIC0[0x41fa0]=0
ICFG_PCIE64B_ACCESS_MSB_31TO24.CMIC0[0x411b0]=0
ICFG_PCIE64B_ACCESS_MSB_63TO32.CMIC0[0x411b4]=0
ICFG_PCIE_0_DEBUG_BUF_MEM_CTRL.CMIC0[0x41fbc]=0
ICFG_PCIE_0_DL_TO_TL_BUF_MEM_CTRL.CMIC0[0x41fb0]=0
ICFG_PCIE_0_REPLAY_ADDR_BUF_MEM_CTRL.CMIC0[0x41fb4]=0
ICFG_PCIE_0_REPLAY_DATA_BUF_MEM_CTRL.CMIC0[0x41fb8]=0
ICFG_PCIE_0_STRAPS.CMIC0[0x41fc0]=0x48483
ICFG_PCIE_0_TL_TO_DL_BUF_MEM_CTRL.CMIC0[0x41fac]=0
ICFG_PCIE_SW_PROG_INTR.CMIC0[0x41784]=0
ICFG_ROM_STRAPS.CMIC0[0x41410]=6
ILE_ECC_1B_ERR_CNT.ILE0[0x94]=0
ILE_ECC_1B_ERR_CNT.ILE1[0x94]=0
ILE_ECC_2B_ERR_CNT.ILE0[0x96]=0
ILE_ECC_2B_ERR_CNT.ILE1[0x96]=0
ILE_ECC_ERR_1B_MONITOR_MEM_MASK.ILE0[0x9a]=0x1fffffffff
ILE_ECC_ERR_1B_MONITOR_MEM_MASK.ILE1[0x9a]=0x1fffffffff
ILE_ECC_ERR_2B_MONITOR_MEM_MASK.ILE0[0x9c]=0x1fffffffff
ILE_ECC_ERR_2B_MONITOR_MEM_MASK.ILE1[0x9c]=0x1fffffffff
ILE_ECC_INTERRUPT_REGISTER.ILE0[0x7]=0
ILE_ECC_INTERRUPT_REGISTER.ILE1[0x7]=0
ILE_ECC_INTERRUPT_REGISTER_MASK.ILE0[0x17]=0
ILE_ECC_INTERRUPT_REGISTER_MASK.ILE1[0x17]=0
ILE_ECC_INTERRUPT_REGISTER_TEST.ILE0[0x1f]=0
ILE_ECC_INTERRUPT_REGISTER_TEST.ILE1[0x1f]=0
ILE_EGW_TO_ILE_LAST_RECEIVED_CONTROLS.ILE0[0x15d]=0
ILE_EGW_TO_ILE_LAST_RECEIVED_CONTROLS.ILE1[0x15d]=0
ILE_EGW_TO_ILE_LAST_RECEIVED_DATA.ILE0[0x15e]=0
ILE_EGW_TO_ILE_LAST_RECEIVED_DATA.ILE1[0x15e]=0
ILE_EGW_TO_ILE_TX_DEBUG_EOP_AFTER_EOP.ILE0[0x191]=0
ILE_EGW_TO_ILE_TX_DEBUG_EOP_AFTER_EOP.ILE1[0x191]=0
ILE_EGW_TO_ILE_TX_DEBUG_PACKET_LARGER_THAN_256_BYTES.ILE0[0x192]=0
ILE_EGW_TO_ILE_TX_DEBUG_PACKET_LARGER_THAN_256_BYTES.ILE1[0x192]=0
ILE_EGW_TO_ILE_TX_DEBUG_SOP_AFTER_SOP.ILE0[0x190]=0
ILE_EGW_TO_ILE_TX_DEBUG_SOP_AFTER_SOP.ILE1[0x190]=0
ILE_ELK_CFG.ILE0[0x1c9]=0x207
ILE_ELK_CFG.ILE1[0x1c9]=0x207
ILE_ELK_STATUS.ILE0[0x1ca]=0
ILE_ELK_STATUS.ILE1[0x1ca]=0
ILE_ENABLE_DYNAMIC_MEMORY_ACCESS.ILE0[0x84]=0
ILE_ENABLE_DYNAMIC_MEMORY_ACCESS.ILE1[0x84]=0
ILE_ENABLE_INTERLAKEN.ILE0[0x102]=5
ILE_ENABLE_INTERLAKEN.ILE1[0x102]=5
ILE_FC_ILKN.ILE0[0x1d4]=3
ILE_FC_ILKN.ILE1[0x1d4]=3
ILE_FC_LLFC_STOP_TX_FORCE.ILE0[0x1d3]=0
ILE_FC_LLFC_STOP_TX_FORCE.ILE1[0x1d3]=0
ILE_FC_MASK_ILKN_CHFC_WHEN_LINK_FAIL.ILE0[0x1d2]=3
ILE_FC_MASK_ILKN_CHFC_WHEN_LINK_FAIL.ILE1[0x1d2]=3
ILE_FORCE_DATA_ON_FOUR_SEG_ONLY.ILE0[0x210]=0
ILE_FORCE_DATA_ON_FOUR_SEG_ONLY.ILE1[0x210]=0
ILE_GTIMER_CONFIGURATION.ILE0[0x89]=0
ILE_GTIMER_CONFIGURATION.ILE1[0x89]=0
ILE_GTIMER_CYCLE.ILE0[0x88]=0x3b9aca00
ILE_GTIMER_CYCLE.ILE1[0x88]=0x3b9aca00
ILE_HRF_SEGMENTATION_PORT_0_BUFF.ILE0[0x25f]=0
ILE_HRF_SEGMENTATION_PORT_0_BUFF.ILE1[0x25f]=0
ILE_HRF_SEGMENTATION_PORT_0_BUFF_HAS_DATA.ILE0[0x1c8]=0
ILE_HRF_SEGMENTATION_PORT_0_BUFF_HAS_DATA.ILE1[0x1c8]=0
ILE_ILE_TO_EGW_LAST_SENT_CONTROLS.ILE0[0x193]=0
ILE_ILE_TO_EGW_LAST_SENT_CONTROLS.ILE1[0x193]=0
ILE_ILE_TO_EGW_LAST_SENT_DATA.ILE0[0x194]=0
ILE_ILE_TO_EGW_LAST_SENT_DATA.ILE1[0x194]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(0).ILE0[0x1a4]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(1).ILE0[0x1a5]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(2).ILE0[0x1a6]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(3).ILE0[0x1a7]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(4).ILE0[0x1a8]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(5).ILE0[0x1a9]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(6).ILE0[0x1aa]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(7).ILE0[0x1ab]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(0).ILE1[0x1a4]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(1).ILE1[0x1a5]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(2).ILE1[0x1a6]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(3).ILE1[0x1a7]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(4).ILE1[0x1a8]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(5).ILE1[0x1a9]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(6).ILE1[0x1aa]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS(7).ILE1[0x1ab]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(0).ILE0[0x230]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(1).ILE0[0x231]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(2).ILE0[0x232]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(3).ILE0[0x233]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(4).ILE0[0x234]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(5).ILE0[0x235]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(6).ILE0[0x236]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(7).ILE0[0x237]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(0).ILE1[0x230]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(1).ILE1[0x231]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(2).ILE1[0x232]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(3).ILE1[0x233]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(4).ILE1[0x234]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(5).ILE1[0x235]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(6).ILE1[0x236]=0
ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA(7).ILE1[0x237]=0
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(0).ILE0[0x16c]=0x7fe38
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(1).ILE0[0x16d]=0x1f3bfe
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(2).ILE0[0x16e]=0x1bd76e
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(3).ILE0[0x16f]=0xbe67a
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(4).ILE0[0x170]=0x17fe7e
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(5).ILE0[0x171]=0x1ffff6
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(6).ILE0[0x172]=0x1fff7e
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(7).ILE0[0x173]=0x1cfffe
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(0).ILE1[0x16c]=0xf7ffc
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(1).ILE1[0x16d]=0x1be2fc
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(2).ILE1[0x16e]=0x1ffbfc
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(3).ILE1[0x16f]=0x1ffdf6
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(4).ILE1[0x170]=0x1b67f8
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(5).ILE1[0x171]=0x1ffffe
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(6).ILE1[0x172]=0x1bdfde
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS(7).ILE1[0x173]=0x1ffefe
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(0).ILE0[0x240]=0xffffffba7eaffbaeff3ffffbefbfbdf69efffeffeffffffc7fef9df1bfb8f3fd
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(1).ILE0[0x241]=0xfe6dfdda4f43e673ecdd7c3efa4dfcdcedcf5cfd7ef6f7aea47ededf679e7f23
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(2).ILE0[0x242]=0xfed7ff7e7ffbfbf7f7f5effff7bcffafbffbfffffecffd7ffafff7fdf7efbf7f
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(3).ILE0[0x243]=0x4088378231ab044811906a238d843fc75361041a2449da47852d104574accb1
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(4).ILE0[0x244]=0xffffffffffdfffffffbfffffffffffffffffffffffbfffffffffffffffff7fff
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(5).ILE0[0x245]=0xffffdfffffffffff7fffffffbbfffffffffffffffffffffffffeffffffffbfff
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(6).ILE0[0x246]=0xff7fdfffffeffffffdfffffffffffffffffffbffffffbffffffefffdffffffff
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(7).ILE0[0x247]=0xffffebfffffd7ffbbfffffffffffffffffffffffff7fffffffffffbfffffffff
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(0).ILE1[0x240]=0xfe7d7dcf37eddd7efcfffa3fffdcf7ffff7ff9ff442fe73e6feef77eb7f7fdef
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(1).ILE1[0x241]=0x187f9f9fefedeef3a1b737fefdfff5ff79ad68a7e6bdffbeddf4efebee6fbfff
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(2).ILE1[0x242]=0xbfef6edbfdefffeefffe7ff7cddf5bdaff7dffffff7fffdfef77fff3f4efff7f
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(3).ILE1[0x243]=0x8f5de7f3a995fdfdff5f6feffbf6d7bfd5fff6dfffdbffd3fff37ffffffbedfd
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(4).ILE1[0x244]=0xdf59debfb77df7bff6bfedfbffdedbfffb8ffbdb7d6eaf77b8fbbffff77dbd5c
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(5).ILE1[0x245]=0xffffffffff7fffebffffffffffbfffffff7f3ffff7ffffffffef9ffffffffffe
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(6).ILE1[0x246]=0x6f7d4e8af5cef5feadefbcfb3d6fdfa02bbbf7fd65b33f69fb4ccafacafdef5f
ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA(7).ILE1[0x247]=0xfffffffffffffffffeffffffffffffff7ffffffffbffffffffffffffffffffff
ILE_ILKN_DEBUG_SELECT_LANE_FOR_COUNTERS.ILE0[0x12d]=0
ILE_ILKN_DEBUG_SELECT_LANE_FOR_COUNTERS.ILE1[0x12d]=0
ILE_ILKN_INVERT_POLARITY_SIGNALS(0).ILE0[0x12f]=0
ILE_ILKN_INVERT_POLARITY_SIGNALS(1).ILE0[0x130]=0
ILE_ILKN_INVERT_POLARITY_SIGNALS(0).ILE1[0x12f]=0
ILE_ILKN_INVERT_POLARITY_SIGNALS(1).ILE1[0x130]=0
ILE_ILKN_RESET.ILE0[0x100]=0
ILE_ILKN_RESET.ILE1[0x100]=0
ILE_ILKN_REVERT_SERDES_DATA_ORDER.ILE0[0x110]=0
ILE_ILKN_REVERT_SERDES_DATA_ORDER.ILE1[0x110]=0
ILE_ILKN_RX_0_DEBUG_BUS(0).ILE0[0x132]=0
ILE_ILKN_RX_0_DEBUG_BUS(1).ILE0[0x133]=0
ILE_ILKN_RX_0_DEBUG_BUS(2).ILE0[0x134]=0
ILE_ILKN_RX_0_DEBUG_BUS(3).ILE0[0x135]=0
ILE_ILKN_RX_0_DEBUG_BUS(4).ILE0[0x136]=0
ILE_ILKN_RX_0_DEBUG_BUS(0).ILE1[0x132]=0
ILE_ILKN_RX_0_DEBUG_BUS(1).ILE1[0x133]=0
ILE_ILKN_RX_0_DEBUG_BUS(2).ILE1[0x134]=0
ILE_ILKN_RX_0_DEBUG_BUS(3).ILE1[0x135]=0
ILE_ILKN_RX_0_DEBUG_BUS(4).ILE1[0x136]=0
ILE_ILKN_RX_1_DEBUG_BUS(0).ILE0[0x13c]=0
ILE_ILKN_RX_1_DEBUG_BUS(1).ILE0[0x13d]=0
ILE_ILKN_RX_1_DEBUG_BUS(2).ILE0[0x13e]=0
ILE_ILKN_RX_1_DEBUG_BUS(3).ILE0[0x13f]=0
ILE_ILKN_RX_1_DEBUG_BUS(4).ILE0[0x140]=0
ILE_ILKN_RX_1_DEBUG_BUS(0).ILE1[0x13c]=0
ILE_ILKN_RX_1_DEBUG_BUS(1).ILE1[0x13d]=0
ILE_ILKN_RX_1_DEBUG_BUS(2).ILE1[0x13e]=0
ILE_ILKN_RX_1_DEBUG_BUS(3).ILE1[0x13f]=0
ILE_ILKN_RX_1_DEBUG_BUS(4).ILE1[0x140]=0
ILE_ILKN_RX_ALIGNMENT_OVERRIDE(0).ILE0[0x250]=0
ILE_ILKN_RX_ALIGNMENT_OVERRIDE(1).ILE0[0x251]=0
ILE_ILKN_RX_ALIGNMENT_OVERRIDE(0).ILE1[0x250]=0
ILE_ILKN_RX_ALIGNMENT_OVERRIDE(1).ILE1[0x251]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_ACHIEVED_COUNTER(0).ILE0[0x15b]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_ACHIEVED_COUNTER(1).ILE0[0x15c]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_ACHIEVED_COUNTER(0).ILE1[0x15b]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_ACHIEVED_COUNTER(1).ILE1[0x15c]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_LOST_COUNTER(0).ILE0[0x159]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_LOST_COUNTER(1).ILE0[0x15a]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_LOST_COUNTER(0).ILE1[0x159]=0
ILE_ILKN_RX_DEBUG_ALIGNMENT_LOST_COUNTER(1).ILE1[0x15a]=0
ILE_ILKN_RX_DEBUG_VALID_COUNTER.ILE0[0x12a]=0
ILE_ILKN_RX_DEBUG_VALID_COUNTER.ILE1[0x12a]=0
ILE_ILKN_RX_DISABLE_RECEIVED_EOP_ERR.ILE0[0x111]=0
ILE_ILKN_RX_DISABLE_RECEIVED_EOP_ERR.ILE1[0x111]=0
ILE_ILKN_RX_DISABLE_RECEIVED_PORT_ERR.ILE0[0x112]=0
ILE_ILKN_RX_DISABLE_RECEIVED_PORT_ERR.ILE1[0x112]=0
ILE_ILKN_RX_DISABLE_RECEIVED_RX_ERR.ILE0[0x113]=0
ILE_ILKN_RX_DISABLE_RECEIVED_RX_ERR.ILE1[0x113]=0
ILE_ILKN_RX_DISABLE_WORD(0).ILE0[0x216]=0
ILE_ILKN_RX_DISABLE_WORD(1).ILE0[0x217]=0
ILE_ILKN_RX_DISABLE_WORD(2).ILE0[0x218]=0
ILE_ILKN_RX_DISABLE_WORD(3).ILE0[0x219]=0
ILE_ILKN_RX_DISABLE_WORD(4).ILE0[0x21a]=0
ILE_ILKN_RX_DISABLE_WORD(5).ILE0[0x21b]=0
ILE_ILKN_RX_DISABLE_WORD(6).ILE0[0x21c]=0
ILE_ILKN_RX_DISABLE_WORD(7).ILE0[0x21d]=0
ILE_ILKN_RX_DISABLE_WORD(0).ILE1[0x216]=0
ILE_ILKN_RX_DISABLE_WORD(1).ILE1[0x217]=0
ILE_ILKN_RX_DISABLE_WORD(2).ILE1[0x218]=0
ILE_ILKN_RX_DISABLE_WORD(3).ILE1[0x219]=0
ILE_ILKN_RX_DISABLE_WORD(4).ILE1[0x21a]=0
ILE_ILKN_RX_DISABLE_WORD(5).ILE1[0x21b]=0
ILE_ILKN_RX_DISABLE_WORD(6).ILE1[0x21c]=0
ILE_ILKN_RX_DISABLE_WORD(7).ILE1[0x21d]=0
ILE_ILKN_RX_RETRANSMIT_DEBUG_INFORMATION(0).ILE0[0x14c]=0
ILE_ILKN_RX_RETRANSMIT_DEBUG_INFORMATION(1).ILE0[0x14d]=0
ILE_ILKN_RX_RETRANSMIT_DEBUG_INFORMATION(0).ILE1[0x14c]=0
ILE_ILKN_RX_RETRANSMIT_DEBUG_INFORMATION(1).ILE1[0x14d]=0
ILE_ILKN_RX_RETRANS_FSM_CLKS_IN_STATE_CNT(0).ILE0[0x148]=0
ILE_ILKN_RX_RETRANS_FSM_CLKS_IN_STATE_CNT(1).ILE0[0x149]=0
ILE_ILKN_RX_RETRANS_FSM_CLKS_IN_STATE_CNT(0).ILE1[0x148]=0
ILE_ILKN_RX_RETRANS_FSM_CLKS_IN_STATE_CNT(1).ILE1[0x149]=0
ILE_ILKN_RX_RETRANS_FSM_ENTER_STATE_CNT(0).ILE0[0x146]=0
ILE_ILKN_RX_RETRANS_FSM_ENTER_STATE_CNT(1).ILE0[0x147]=0
ILE_ILKN_RX_RETRANS_FSM_ENTER_STATE_CNT(0).ILE1[0x146]=0
ILE_ILKN_RX_RETRANS_FSM_ENTER_STATE_CNT(1).ILE1[0x147]=0
ILE_ILKN_RX_RETRANS_FSM_STATE_TO_MONITOR(0).ILE0[0x14a]=0
ILE_ILKN_RX_RETRANS_FSM_STATE_TO_MONITOR(1).ILE0[0x14b]=0
ILE_ILKN_RX_RETRANS_FSM_STATE_TO_MONITOR(0).ILE1[0x14a]=0
ILE_ILKN_RX_RETRANS_FSM_STATE_TO_MONITOR(1).ILE1[0x14b]=0
ILE_ILKN_RX_SERDES_VALID.ILE0[0x20e]=1
ILE_ILKN_RX_SERDES_VALID.ILE1[0x20e]=1
ILE_ILKN_SERDES_DISABLE_MASKS.ILE0[0x103]=0
ILE_ILKN_SERDES_DISABLE_MASKS.ILE1[0x103]=0
ILE_ILKN_TX_0_DEBUG_BUS(0).ILE0[0x137]=0
ILE_ILKN_TX_0_DEBUG_BUS(1).ILE0[0x138]=0
ILE_ILKN_TX_0_DEBUG_BUS(2).ILE0[0x139]=0
ILE_ILKN_TX_0_DEBUG_BUS(3).ILE0[0x13a]=0
ILE_ILKN_TX_0_DEBUG_BUS(4).ILE0[0x13b]=0
ILE_ILKN_TX_0_DEBUG_BUS(0).ILE1[0x137]=0
ILE_ILKN_TX_0_DEBUG_BUS(1).ILE1[0x138]=0
ILE_ILKN_TX_0_DEBUG_BUS(2).ILE1[0x139]=0
ILE_ILKN_TX_0_DEBUG_BUS(3).ILE1[0x13a]=0
ILE_ILKN_TX_0_DEBUG_BUS(4).ILE1[0x13b]=0
ILE_ILKN_TX_1_DEBUG_BUS(0).ILE0[0x141]=0
ILE_ILKN_TX_1_DEBUG_BUS(1).ILE0[0x142]=0
ILE_ILKN_TX_1_DEBUG_BUS(2).ILE0[0x143]=0
ILE_ILKN_TX_1_DEBUG_BUS(3).ILE0[0x144]=0
ILE_ILKN_TX_1_DEBUG_BUS(4).ILE0[0x145]=0
ILE_ILKN_TX_1_DEBUG_BUS(0).ILE1[0x141]=0
ILE_ILKN_TX_1_DEBUG_BUS(1).ILE1[0x142]=0
ILE_ILKN_TX_1_DEBUG_BUS(2).ILE1[0x143]=0
ILE_ILKN_TX_1_DEBUG_BUS(3).ILE1[0x144]=0
ILE_ILKN_TX_1_DEBUG_BUS(4).ILE1[0x145]=0
ILE_ILKN_TX_CONF.ILE0[0x105]=0
ILE_ILKN_TX_CONF.ILE1[0x105]=0
ILE_ILKN_TX_DEBUG_CREDIT_COUNTER.ILE0[0x12c]=0
ILE_ILKN_TX_DEBUG_CREDIT_COUNTER.ILE1[0x12c]=0
ILE_ILKN_TX_DEBUG_VALID_COUNTER.ILE0[0x12b]=0
ILE_ILKN_TX_DEBUG_VALID_COUNTER.ILE1[0x12b]=0
ILE_ILKN_TX_DISABLE_WORD(0).ILE0[0x21f]=0
ILE_ILKN_TX_DISABLE_WORD(1).ILE0[0x220]=0
ILE_ILKN_TX_DISABLE_WORD(2).ILE0[0x221]=0
ILE_ILKN_TX_DISABLE_WORD(3).ILE0[0x222]=0
ILE_ILKN_TX_DISABLE_WORD(4).ILE0[0x223]=0
ILE_ILKN_TX_DISABLE_WORD(5).ILE0[0x224]=0
ILE_ILKN_TX_DISABLE_WORD(6).ILE0[0x225]=0
ILE_ILKN_TX_DISABLE_WORD(7).ILE0[0x226]=0
ILE_ILKN_TX_DISABLE_WORD(0).ILE1[0x21f]=0
ILE_ILKN_TX_DISABLE_WORD(1).ILE1[0x220]=0
ILE_ILKN_TX_DISABLE_WORD(2).ILE1[0x221]=0
ILE_ILKN_TX_DISABLE_WORD(3).ILE1[0x222]=0
ILE_ILKN_TX_DISABLE_WORD(4).ILE1[0x223]=0
ILE_ILKN_TX_DISABLE_WORD(5).ILE1[0x224]=0
ILE_ILKN_TX_DISABLE_WORD(6).ILE1[0x225]=0
ILE_ILKN_TX_DISABLE_WORD(7).ILE1[0x226]=0
ILE_ILKN_TX_FLUSH_SELECTOR.ILE0[0x1d5]=3
ILE_ILKN_TX_FLUSH_SELECTOR.ILE1[0x1d5]=3
ILE_ILKN_TX_MANUAL_SERDES_CREDIT_DEBUG.ILE0[0x12e]=3
ILE_ILKN_TX_MANUAL_SERDES_CREDIT_DEBUG.ILE1[0x12e]=3
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(0).ILE0[0x228]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(1).ILE0[0x229]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(2).ILE0[0x22a]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(3).ILE0[0x22b]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(4).ILE0[0x22c]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(5).ILE0[0x22d]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(6).ILE0[0x22e]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(7).ILE0[0x22f]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(0).ILE1[0x228]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(1).ILE1[0x229]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(2).ILE1[0x22a]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(3).ILE1[0x22b]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(4).ILE1[0x22c]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(5).ILE1[0x22d]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(6).ILE1[0x22e]=1
ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(7).ILE1[0x22f]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(4).ILE0[0x212]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(5).ILE0[0x213]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(6).ILE0[0x214]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(7).ILE0[0x215]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(4).ILE1[0x212]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(5).ILE1[0x213]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(6).ILE1[0x214]=1
ILE_ILKN_TX_PORT_1_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES(7).ILE1[0x215]=1
ILE_ILKN_TX_PORT_DATA_PCK_DEADLOCK_HAPPENED(0).ILE0[0x153]=0
ILE_ILKN_TX_PORT_DATA_PCK_DEADLOCK_HAPPENED(1).ILE0[0x154]=0
ILE_ILKN_TX_PORT_DATA_PCK_DEADLOCK_HAPPENED(0).ILE1[0x153]=0
ILE_ILKN_TX_PORT_DATA_PCK_DEADLOCK_HAPPENED(1).ILE1[0x154]=0
ILE_ILKN_TX_PORT_DISABLE_DATA_PCK_FLUSH_WHEN_DEADLOCK(0).ILE0[0x14e]=0
ILE_ILKN_TX_PORT_DISABLE_DATA_PCK_FLUSH_WHEN_DEADLOCK(1).ILE0[0x14f]=0
ILE_ILKN_TX_PORT_DISABLE_DATA_PCK_FLUSH_WHEN_DEADLOCK(0).ILE1[0x14e]=0
ILE_ILKN_TX_PORT_DISABLE_DATA_PCK_FLUSH_WHEN_DEADLOCK(1).ILE1[0x14f]=0
ILE_ILKN_TX_PORT_FORCE_DATA_PCK_FLUSH(0).ILE0[0x151]=0
ILE_ILKN_TX_PORT_FORCE_DATA_PCK_FLUSH(1).ILE0[0x152]=0
ILE_ILKN_TX_PORT_FORCE_DATA_PCK_FLUSH(0).ILE1[0x151]=0
ILE_ILKN_TX_PORT_FORCE_DATA_PCK_FLUSH(1).ILE1[0x152]=0
ILE_INDIRECT_COMMAND.ILE0[0x80]=0xe000002
ILE_INDIRECT_COMMAND.ILE1[0x80]=0xe000002
ILE_INDIRECT_COMMAND_ADDRESS.ILE0[0x81]=0x102200
ILE_INDIRECT_COMMAND_ADDRESS.ILE1[0x81]=0x102200
ILE_INDIRECT_COMMAND_RD_DATA.ILE0[0x60]=0x57debebf539bd67756f652f59ecc927e7afbfd58baadc127ce4cf568b6a6d37fdfbc7d3d0
ILE_INDIRECT_COMMAND_RD_DATA.ILE1[0x60]=0x777f17ffeef6c6feb9f3dfe1fffe6bbed796debff2fffee09dff767ff5c77e6f7ff33bef1
ILE_INDIRECT_COMMAND_WR_DATA.ILE0[0x20]=0
ILE_INDIRECT_COMMAND_WR_DATA.ILE1[0x20]=0
ILE_INDIRECT_FORCE_BUBBLE.ILE0[0x83]=0x20019
ILE_INDIRECT_FORCE_BUBBLE.ILE1[0x83]=0x20019
ILE_INTERRUPT_MASK_REGISTER.ILE0[0x10]=0
ILE_INTERRUPT_MASK_REGISTER.ILE1[0x10]=0
ILE_INTERRUPT_REGISTER.ILE0[0x0]=0
ILE_INTERRUPT_REGISTER.ILE1[0x0]=0
ILE_INTERRUPT_REGISTER_TEST.ILE0[0x18]=0
ILE_INTERRUPT_REGISTER_TEST.ILE1[0x18]=0
ILE_OUTPUT_FROM_ILKN_CORES.ILE0[0x254]=0
ILE_OUTPUT_FROM_ILKN_CORES.ILE1[0x254]=0
ILE_REG_0041.ILE0[0x41]=0
ILE_REG_0041.ILE1[0x41]=0
ILE_REG_0098.ILE0[0x98]=0
ILE_REG_0098.ILE1[0x98]=0
ILE_REG_00A0.ILE0[0xa0]=0
ILE_REG_00A0.ILE1[0xa0]=0
ILE_REG_00C2.ILE0[0xc2]=0x10
ILE_REG_00C2.ILE1[0xc2]=0x10
ILE_RESERVED_MTCD.ILE0[0xae]=0x30
ILE_RESERVED_MTCD.ILE1[0xae]=0x30
ILE_RESERVED_MTCP.ILE0[0xad]=0x300000600000000
ILE_RESERVED_MTCP.ILE1[0xad]=0x300000600000000
ILE_RESERVED_SPARE_0.ILE0[0x90]=0xffffffff
ILE_RESERVED_SPARE_0.ILE1[0x90]=0xffffffff
ILE_RESERVED_SPARE_1.ILE0[0x91]=0xffffffff
ILE_RESERVED_SPARE_1.ILE1[0x91]=0xffffffff
ILE_RESERVED_SPARE_2.ILE0[0x92]=0
ILE_RESERVED_SPARE_2.ILE1[0x92]=0
ILE_RESERVED_SPARE_3.ILE0[0x93]=0
ILE_RESERVED_SPARE_3.ILE1[0x93]=0
ILE_RESET_WRAP_WITHOUT_ILKN_PORTS.ILE0[0x101]=1
ILE_RESET_WRAP_WITHOUT_ILKN_PORTS.ILE1[0x101]=1
ILE_RX_BYTES_COUNTER(0).ILE0[0x122]=0
ILE_RX_BYTES_COUNTER(1).ILE0[0x123]=0
ILE_RX_BYTES_COUNTER(0).ILE1[0x122]=0
ILE_RX_BYTES_COUNTER(1).ILE1[0x123]=0
ILE_RX_ELK_BURSTS_CNT.ILE0[0x1cb]=0
ILE_RX_ELK_BURSTS_CNT.ILE1[0x1cb]=0
ILE_RX_ELK_BURST_DROP_CNT.ILE0[0x1ce]=0
ILE_RX_ELK_BURST_DROP_CNT.ILE1[0x1ce]=0
ILE_RX_ELK_ERR_BURSTS_CNT.ILE0[0x1cc]=0
ILE_RX_ELK_ERR_BURSTS_CNT.ILE1[0x1cc]=0
ILE_RX_ELK_OCTETS_CNT.ILE0[0x1cd]=0
ILE_RX_ELK_OCTETS_CNT.ILE1[0x1cd]=0
ILE_RX_ERR_PKT_COUNTER(0).ILE0[0x120]=0
ILE_RX_ERR_PKT_COUNTER(1).ILE0[0x121]=0
ILE_RX_ERR_PKT_COUNTER(0).ILE1[0x120]=0
ILE_RX_ERR_PKT_COUNTER(1).ILE1[0x121]=0
ILE_RX_FRAMELOCK.ILE0[0x10d]=0xffffff
ILE_RX_FRAMELOCK.ILE1[0x10d]=0xffffff
ILE_RX_ILKN_STATUS(0).ILE0[0x10b]=0x11
ILE_RX_ILKN_STATUS(1).ILE0[0x10c]=0x11
ILE_RX_ILKN_STATUS(0).ILE1[0x10b]=0x11
ILE_RX_ILKN_STATUS(1).ILE1[0x10c]=0x11
ILE_RX_PKT_COUNTER(0).ILE0[0x11e]=0
ILE_RX_PKT_COUNTER(1).ILE0[0x11f]=0
ILE_RX_PKT_COUNTER(0).ILE1[0x11e]=0
ILE_RX_PKT_COUNTER(1).ILE1[0x11f]=0
ILE_SBUS_BROADCAST_ID.ILE0[0x86]=0x7ff
ILE_SBUS_BROADCAST_ID.ILE1[0x86]=0x7ff
ILE_SBUS_LAST_IN_CHAIN.ILE0[0x87]=0
ILE_SBUS_LAST_IN_CHAIN.ILE1[0x87]=0
ILE_SPECIAL_CLOCK_CONTROLS.ILE0[0xc1]=2
ILE_SPECIAL_CLOCK_CONTROLS.ILE1[0xc1]=2
ILE_TRANSMIT_RETRANSMIT_DEBUG.ILE0[0x131]=0
ILE_TRANSMIT_RETRANSMIT_DEBUG.ILE1[0x131]=0
ILE_TX_BYTES_COUNTER(0).ILE0[0x128]=0
ILE_TX_BYTES_COUNTER(1).ILE0[0x129]=0
ILE_TX_BYTES_COUNTER(0).ILE1[0x128]=0
ILE_TX_BYTES_COUNTER(1).ILE1[0x129]=0
ILE_TX_ELK_BURSTS_CNT.ILE0[0x1cf]=0
ILE_TX_ELK_BURSTS_CNT.ILE1[0x1cf]=0
ILE_TX_ELK_ERR_BURSTS_CNT.ILE0[0x1d1]=0
ILE_TX_ELK_ERR_BURSTS_CNT.ILE1[0x1d1]=0
ILE_TX_ELK_OCTETS_CNT.ILE0[0x1d0]=0
ILE_TX_ELK_OCTETS_CNT.ILE1[0x1d0]=0
ILE_TX_ERR_PKT_COUNTER(0).ILE0[0x126]=0
ILE_TX_ERR_PKT_COUNTER(1).ILE0[0x127]=0
ILE_TX_ERR_PKT_COUNTER(0).ILE1[0x126]=0
ILE_TX_ERR_PKT_COUNTER(1).ILE1[0x127]=0
ILE_TX_ILKN_0_FLUSHED_PACKETS_CNT.ILE0[0x11c]=0
ILE_TX_ILKN_0_FLUSHED_PACKETS_CNT.ILE1[0x11c]=0
ILE_TX_ILKN_1_FLUSHED_PACKETS_CNT.ILE0[0x11d]=0
ILE_TX_ILKN_1_FLUSHED_PACKETS_CNT.ILE1[0x11d]=0
ILE_TX_ILKN_CONTROL(0).ILE0[0x107]=0x1c
ILE_TX_ILKN_CONTROL(1).ILE0[0x109]=0x1c
ILE_TX_ILKN_CONTROL(0).ILE1[0x107]=0x1c
ILE_TX_ILKN_CONTROL(1).ILE1[0x109]=0x1c
ILE_TX_ILKN_STATUS(0).ILE0[0x10e]=0
ILE_TX_ILKN_STATUS(1).ILE0[0x10f]=0
ILE_TX_ILKN_STATUS(0).ILE1[0x10e]=0
ILE_TX_ILKN_STATUS(1).ILE1[0x10f]=0
ILE_TX_PKT_COUNTER(0).ILE0[0x124]=0
ILE_TX_PKT_COUNTER(1).ILE0[0x125]=0
ILE_TX_PKT_COUNTER(0).ILE1[0x124]=0
ILE_TX_PKT_COUNTER(1).ILE1[0x125]=0
ILU_ALLOW_HRF_SEGMENTATION_PREVENT_SEG_3.ILU0[0x1a6]=1
ILU_ALLOW_HRF_SEGMENTATION_PREVENT_SEG_3.ILU1[0x1a6]=1
ILU_BURST_DROP_COUNTER_TX_HRF(0).ILU0[0x171]=0
ILU_BURST_DROP_COUNTER_TX_HRF(1).ILU0[0x172]=0
ILU_BURST_DROP_COUNTER_TX_HRF(0).ILU1[0x171]=0
ILU_BURST_DROP_COUNTER_TX_HRF(1).ILU1[0x172]=0
ILU_ECC_1B_ERR_CNT.ILU0[0x94]=0
ILU_ECC_1B_ERR_CNT.ILU1[0x94]=0
ILU_ECC_2B_ERR_CNT.ILU0[0x96]=0
ILU_ECC_2B_ERR_CNT.ILU1[0x96]=0
ILU_ECC_ERR_1B_MONITOR_MEM_MASK.ILU0[0x9a]=0x3ffffff
ILU_ECC_ERR_1B_MONITOR_MEM_MASK.ILU1[0x9a]=0x3ffffff
ILU_ECC_ERR_2B_MONITOR_MEM_MASK.ILU0[0x9c]=0x3ffffff
ILU_ECC_ERR_2B_MONITOR_MEM_MASK.ILU1[0x9c]=0x3ffffff
ILU_ECC_INTERRUPT_REGISTER.ILU0[0x7]=0
ILU_ECC_INTERRUPT_REGISTER.ILU1[0x7]=0
ILU_ECC_INTERRUPT_REGISTER_MASK.ILU0[0x17]=0
ILU_ECC_INTERRUPT_REGISTER_MASK.ILU1[0x17]=0
ILU_ECC_INTERRUPT_REGISTER_TEST.ILU0[0x1f]=0
ILU_ECC_INTERRUPT_REGISTER_TEST.ILU1[0x1f]=0
ILU_ENABLE_DYNAMIC_MEMORY_ACCESS.ILU0[0x84]=3
ILU_ENABLE_DYNAMIC_MEMORY_ACCESS.ILU1[0x84]=3
ILU_FC_ILKN.ILU0[0x149]=0
ILU_FC_ILKN.ILU1[0x149]=0
ILU_FC_ILKN_RX_CHFC_CAL_LEN.ILU0[0x14a]=0x20100
ILU_FC_ILKN_RX_CHFC_CAL_LEN.ILU1[0x14a]=0x20100
ILU_FC_ILKN_RX_CHFC_FORCE(0).ILU0[0x14d]=0
ILU_FC_ILKN_RX_CHFC_FORCE(1).ILU0[0x14e]=0
ILU_FC_ILKN_RX_CHFC_FORCE(0).ILU1[0x14d]=0
ILU_FC_ILKN_RX_CHFC_FORCE(1).ILU1[0x14e]=0
ILU_FC_ILKN_RX_CHFC_TO_CFC_MASK(0).ILU0[0x151]=0xffffffffffffffff
ILU_FC_ILKN_RX_CHFC_TO_CFC_MASK(1).ILU0[0x152]=0xffffffffffffffff
ILU_FC_ILKN_RX_CHFC_TO_CFC_MASK(0).ILU1[0x151]=0xffffffffffffffff
ILU_FC_ILKN_RX_CHFC_TO_CFC_MASK(1).ILU1[0x152]=0xffffffffffffffff
ILU_FC_ILKN_RX_IB_CHFC_FROM_CFC_RAW(0).ILU0[0x157]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_CFC_RAW(1).ILU0[0x158]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_CFC_RAW(0).ILU1[0x157]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_CFC_RAW(1).ILU1[0x158]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_RAW(0).ILU0[0x155]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_RAW(1).ILU0[0x156]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_RAW(0).ILU1[0x155]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_RAW(1).ILU1[0x156]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_ROC(0).ILU0[0x159]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_ROC(1).ILU0[0x15a]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_ROC(0).ILU1[0x159]=0
ILU_FC_ILKN_RX_IB_CHFC_FROM_PORT_ROC(1).ILU1[0x15a]=0
ILU_FC_ILKN_TX_GEN_CHFC_FROM_CFC_MASK(0).ILU0[0x14f]=0xffffffffffffffff
ILU_FC_ILKN_TX_GEN_CHFC_FROM_CFC_MASK(1).ILU0[0x150]=0xffffffffffffffff
ILU_FC_ILKN_TX_GEN_CHFC_FROM_CFC_MASK(0).ILU1[0x14f]=0xffffffffffffffff
ILU_FC_ILKN_TX_GEN_CHFC_FROM_CFC_MASK(1).ILU1[0x150]=0xffffffffffffffff
ILU_FC_ILKN_TX_GEN_IB_CHFC_FORCE(0).ILU0[0x14b]=0
ILU_FC_ILKN_TX_GEN_IB_CHFC_FORCE(1).ILU0[0x14c]=0
ILU_FC_ILKN_TX_GEN_IB_CHFC_FORCE(0).ILU1[0x14b]=0
ILU_FC_ILKN_TX_GEN_IB_CHFC_FORCE(1).ILU1[0x14c]=0
ILU_FC_ILKN_TX_GEN_IB_CHFC_ROC(0).ILU0[0x15b]=0
ILU_FC_ILKN_TX_GEN_IB_CHFC_ROC(1).ILU0[0x15c]=0
ILU_FC_ILKN_TX_GEN_IB_CHFC_ROC(0).ILU1[0x15b]=0
ILU_FC_ILKN_TX_GEN_IB_CHFC_ROC(1).ILU1[0x15c]=0
ILU_FC_LLFC_STOP_TX_FORCE.ILU0[0x145]=0
ILU_FC_LLFC_STOP_TX_FORCE.ILU1[0x145]=0
ILU_FC_LLFC_STOP_TX_FROM_CFC_MASK.ILU0[0x147]=3
ILU_FC_LLFC_STOP_TX_FROM_CFC_MASK.ILU1[0x147]=3
ILU_FC_MASK_ILKN_CHFC_WHEN_LINK_FAIL.ILU0[0x148]=3
ILU_FC_MASK_ILKN_CHFC_WHEN_LINK_FAIL.ILU1[0x148]=3
ILU_FC_MASK_ILKN_LLFC_STOP_TX_WHEN_LINK_FAIL.ILU0[0x163]=3
ILU_FC_MASK_ILKN_LLFC_STOP_TX_WHEN_LINK_FAIL.ILU1[0x163]=3
ILU_FC_RESET.ILU0[0x143]=0
ILU_FC_RESET.ILU1[0x143]=0
ILU_FC_TX_GEN_LLFC_FORCE.ILU0[0x144]=0
ILU_FC_TX_GEN_LLFC_FORCE.ILU1[0x144]=0
ILU_FC_TX_GEN_LLFC_FROM_CFC.ILU0[0x154]=0
ILU_FC_TX_GEN_LLFC_FROM_CFC.ILU1[0x154]=0
ILU_FC_TX_GEN_LLFC_FROM_CFC_MASK.ILU0[0x146]=3
ILU_FC_TX_GEN_LLFC_FROM_CFC_MASK.ILU1[0x146]=3
ILU_FC_TX_LLFC_STOP_TX_FROM_CFC.ILU0[0x153]=0
ILU_FC_TX_LLFC_STOP_TX_FROM_CFC.ILU1[0x153]=0
ILU_GTIMER_CONFIGURATION.ILU0[0x89]=0
ILU_GTIMER_CONFIGURATION.ILU1[0x89]=0
ILU_GTIMER_CYCLE.ILU0[0x88]=0x3b9aca00
ILU_GTIMER_CYCLE.ILU1[0x88]=0x3b9aca00
ILU_HRF_RESET.ILU0[0x105]=0
ILU_HRF_RESET.ILU1[0x105]=0
ILU_HRF_RX_CONFIG_HRF(0).ILU0[0x106]=0x7320400400
ILU_HRF_RX_CONFIG_HRF(1).ILU0[0x109]=0x7320400400
ILU_HRF_RX_CONFIG_HRF(2).ILU0[0x10c]=0x7320400400
ILU_HRF_RX_CONFIG_HRF(3).ILU0[0x10f]=0x7320400400
ILU_HRF_RX_CONFIG_HRF(0).ILU1[0x106]=0x7320400400
ILU_HRF_RX_CONFIG_HRF(1).ILU1[0x109]=0x7320400400
ILU_HRF_RX_CONFIG_HRF(2).ILU1[0x10c]=0x7320400400
ILU_HRF_RX_CONFIG_HRF(3).ILU1[0x10f]=0x7320400400
ILU_HRF_RX_CONTROLLER_DEBUG(0).ILU0[0x11f]=0
ILU_HRF_RX_CONTROLLER_DEBUG(1).ILU0[0x120]=0
ILU_HRF_RX_CONTROLLER_DEBUG(2).ILU0[0x121]=0
ILU_HRF_RX_CONTROLLER_DEBUG(3).ILU0[0x122]=0
ILU_HRF_RX_CONTROLLER_DEBUG(0).ILU1[0x11f]=0
ILU_HRF_RX_CONTROLLER_DEBUG(1).ILU1[0x120]=0
ILU_HRF_RX_CONTROLLER_DEBUG(2).ILU1[0x121]=0
ILU_HRF_RX_CONTROLLER_DEBUG(3).ILU1[0x122]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(0).ILU0[0x123]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(1).ILU0[0x124]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(2).ILU0[0x125]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(3).ILU0[0x126]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(0).ILU1[0x123]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(1).ILU1[0x124]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(2).ILU1[0x125]=0
ILU_HRF_RX_CONTROLLER_MAX_OCCUPANCY(3).ILU1[0x126]=0
ILU_HRF_RX_DROP_ALL_DATA(0).ILU0[0x112]=0
ILU_HRF_RX_DROP_ALL_DATA(1).ILU0[0x113]=0
ILU_HRF_RX_DROP_ALL_DATA(2).ILU0[0x114]=0
ILU_HRF_RX_DROP_ALL_DATA(3).ILU0[0x115]=0
ILU_HRF_RX_DROP_ALL_DATA(0).ILU1[0x112]=0
ILU_HRF_RX_DROP_ALL_DATA(1).ILU1[0x113]=0
ILU_HRF_RX_DROP_ALL_DATA(2).ILU1[0x114]=0
ILU_HRF_RX_DROP_ALL_DATA(3).ILU1[0x115]=0
ILU_HRF_RX_PRD_THRESHOLDS_CONFIG_0.ILU0[0x116]=0xfffffffffffff
ILU_HRF_RX_PRD_THRESHOLDS_CONFIG_0.ILU1[0x116]=0xfffffffffffff
ILU_HRF_RX_PRD_THRESHOLDS_CONFIG_1.ILU0[0x118]=0xfffffffffffff
ILU_HRF_RX_PRD_THRESHOLDS_CONFIG_1.ILU1[0x118]=0xfffffffffffff
ILU_HRF_RX_USE_EXTENDED_MEM_HRF_0.ILU0[0x11a]=0
ILU_HRF_RX_USE_EXTENDED_MEM_HRF_0.ILU1[0x11a]=0
ILU_HRF_RX_USE_EXTENDED_MEM_HRF_2.ILU0[0x11b]=0
ILU_HRF_RX_USE_EXTENDED_MEM_HRF_2.ILU1[0x11b]=0
ILU_HRF_SEGMENTATION_PORT_BUFF(0).ILU0[0x128]=0
ILU_HRF_SEGMENTATION_PORT_BUFF(1).ILU0[0x129]=0
ILU_HRF_SEGMENTATION_PORT_BUFF(0).ILU1[0x128]=0
ILU_HRF_SEGMENTATION_PORT_BUFF(1).ILU1[0x129]=0
ILU_HRF_TX_CONFIG_HRF(0).ILU0[0x11c]=0x181008
ILU_HRF_TX_CONFIG_HRF(1).ILU0[0x11d]=0x181008
ILU_HRF_TX_CONFIG_HRF(0).ILU1[0x11c]=0x181008
ILU_HRF_TX_CONFIG_HRF(1).ILU1[0x11d]=0x181008
ILU_HRF_TX_CONTROLLER_DEBUG(0).ILU0[0x12a]=0
ILU_HRF_TX_CONTROLLER_DEBUG(1).ILU0[0x12b]=0
ILU_HRF_TX_CONTROLLER_DEBUG(0).ILU1[0x12a]=0
ILU_HRF_TX_CONTROLLER_DEBUG(1).ILU1[0x12b]=0
ILU_HRF_TX_EGRESS_CREDITS_DEBUG.ILU0[0x11e]=0
ILU_HRF_TX_EGRESS_CREDITS_DEBUG.ILU1[0x11e]=0
ILU_ILKN_CHANNEL_IS_TDM_PORT(0).ILU0[0x134]=0
ILU_ILKN_CHANNEL_IS_TDM_PORT(1).ILU0[0x135]=0
ILU_ILKN_CHANNEL_IS_TDM_PORT(0).ILU1[0x134]=0
ILU_ILKN_CHANNEL_IS_TDM_PORT(1).ILU1[0x135]=0
ILU_ILKN_RX_LLFC_FROM_RX_CNT(0).ILU0[0x161]=0
ILU_ILKN_RX_LLFC_FROM_RX_CNT(1).ILU0[0x162]=0
ILU_ILKN_RX_LLFC_FROM_RX_CNT(0).ILU1[0x161]=0
ILU_ILKN_RX_LLFC_FROM_RX_CNT(1).ILU1[0x162]=0
ILU_ILKN_RX_SEND_TDM_WITH_ERR_TO_DATA_HRF.ILU0[0x137]=0
ILU_ILKN_RX_SEND_TDM_WITH_ERR_TO_DATA_HRF.ILU1[0x137]=0
ILU_ILKN_RX_TDM_AND_DATA_TRAFFIC_ON_SAME_HRF.ILU0[0x136]=0
ILU_ILKN_RX_TDM_AND_DATA_TRAFFIC_ON_SAME_HRF.ILU1[0x136]=0
ILU_ILKN_TX_GEN_LLFC_CNT(0).ILU0[0x15f]=0xb7d15663
ILU_ILKN_TX_GEN_LLFC_CNT(1).ILU0[0x160]=0xb7d19096
ILU_ILKN_TX_GEN_LLFC_CNT(0).ILU1[0x15f]=0xb7d1da20
ILU_ILKN_TX_GEN_LLFC_CNT(1).ILU1[0x160]=0xb7d227bb
ILU_ILKN_TX_LLFC_STOP_TX_CNT(0).ILU0[0x15d]=0
ILU_ILKN_TX_LLFC_STOP_TX_CNT(1).ILU0[0x15e]=0
ILU_ILKN_TX_LLFC_STOP_TX_CNT(0).ILU1[0x15d]=0
ILU_ILKN_TX_LLFC_STOP_TX_CNT(1).ILU1[0x15e]=0
ILU_ILU_MISCONFIGURATION.ILU0[0x183]=0
ILU_ILU_MISCONFIGURATION.ILU1[0x183]=0
ILU_ILU_RX_NUM_TOTAL_DROPPED_EOPS.ILU0[0x166]=0
ILU_ILU_RX_NUM_TOTAL_DROPPED_EOPS.ILU1[0x166]=0
ILU_INDIRECT_COMMAND.ILU0[0x80]=0xe000002
ILU_INDIRECT_COMMAND.ILU1[0x80]=0xe000002
ILU_INDIRECT_COMMAND_ADDRESS.ILU0[0x81]=0x2820
ILU_INDIRECT_COMMAND_ADDRESS.ILU1[0x81]=0x2820
ILU_INDIRECT_COMMAND_RD_DATA.ILU0[0x60]=0
ILU_INDIRECT_COMMAND_RD_DATA.ILU1[0x60]=0
ILU_INDIRECT_COMMAND_WIDE_MEM.ILU0[0x41]=0
ILU_INDIRECT_COMMAND_WIDE_MEM.ILU1[0x41]=0
ILU_INDIRECT_COMMAND_WR_DATA.ILU0[0x20]=0
ILU_INDIRECT_COMMAND_WR_DATA.ILU1[0x20]=0
ILU_INDIRECT_FORCE_BUBBLE.ILU0[0x83]=0x20019
ILU_INDIRECT_FORCE_BUBBLE.ILU1[0x83]=0x20019
ILU_INSTRUMENTATION_CURRENT_INTERVAL_DROPPED_DATA_PORT(0).ILU0[0x18c]=0
ILU_INSTRUMENTATION_CURRENT_INTERVAL_DROPPED_DATA_PORT(1).ILU0[0x18d]=0
ILU_INSTRUMENTATION_CURRENT_INTERVAL_DROPPED_DATA_PORT(0).ILU1[0x18c]=0
ILU_INSTRUMENTATION_CURRENT_INTERVAL_DROPPED_DATA_PORT(1).ILU1[0x18d]=0
ILU_INSTRUMENTATION_CURRENT_INTERVAL_RECEIVED_DATA_PORT(0).ILU0[0x18a]=0
ILU_INSTRUMENTATION_CURRENT_INTERVAL_RECEIVED_DATA_PORT(1).ILU0[0x18b]=0
ILU_INSTRUMENTATION_CURRENT_INTERVAL_RECEIVED_DATA_PORT(0).ILU1[0x18a]=0
ILU_INSTRUMENTATION_CURRENT_INTERVAL_RECEIVED_DATA_PORT(1).ILU1[0x18b]=0
ILU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION.ILU0[0x19c]=0
ILU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION.ILU1[0x19c]=0
ILU_INSTRUMENTATION_DEBUG_WRAP_AROUND_PORT(0).ILU0[0x192]=0
ILU_INSTRUMENTATION_DEBUG_WRAP_AROUND_PORT(1).ILU0[0x193]=0
ILU_INSTRUMENTATION_DEBUG_WRAP_AROUND_PORT(0).ILU1[0x192]=0
ILU_INSTRUMENTATION_DEBUG_WRAP_AROUND_PORT(1).ILU1[0x193]=0
ILU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.ILU0[0x196]=0
ILU_INSTRUMENTATION_ECI_SIGNALS_COUNTER.ILU1[0x196]=0
ILU_INSTRUMENTATION_INTERVALS_COUNTER_PORT(0).ILU0[0x197]=0
ILU_INSTRUMENTATION_INTERVALS_COUNTER_PORT(1).ILU0[0x198]=0
ILU_INSTRUMENTATION_INTERVALS_COUNTER_PORT(0).ILU1[0x197]=0
ILU_INSTRUMENTATION_INTERVALS_COUNTER_PORT(1).ILU1[0x198]=0
ILU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN_PORT(0).ILU0[0x194]=0
ILU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN_PORT(1).ILU0[0x195]=0
ILU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN_PORT(0).ILU1[0x194]=0
ILU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN_PORT(1).ILU1[0x195]=0
ILU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED_PORT(0).ILU0[0x18e]=0xf
ILU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED_PORT(1).ILU0[0x18f]=0xf
ILU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED_PORT(0).ILU1[0x18e]=0xf
ILU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED_PORT(1).ILU1[0x18f]=0xf
ILU_INSTRUMENTATION_OVERRIDE_MODE_PORT(0).ILU0[0x190]=1
ILU_INSTRUMENTATION_OVERRIDE_MODE_PORT(1).ILU0[0x191]=1
ILU_INSTRUMENTATION_OVERRIDE_MODE_PORT(0).ILU1[0x190]=1
ILU_INSTRUMENTATION_OVERRIDE_MODE_PORT(1).ILU1[0x191]=1
ILU_INSTRUMENTATION_RESET_LOW.ILU0[0x199]=0
ILU_INSTRUMENTATION_RESET_LOW.ILU1[0x199]=0
ILU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS_PORT(0).ILU0[0x19a]=0
ILU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS_PORT(1).ILU0[0x19b]=0
ILU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS_PORT(0).ILU1[0x19a]=0
ILU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS_PORT(1).ILU1[0x19b]=0
ILU_INTERRUPT_MASK_REGISTER.ILU0[0x10]=0
ILU_INTERRUPT_MASK_REGISTER.ILU1[0x10]=0
ILU_INTERRUPT_REGISTER.ILU0[0x0]=0
ILU_INTERRUPT_REGISTER.ILU1[0x0]=0
ILU_INTERRUPT_REGISTER_TEST.ILU0[0x18]=0
ILU_INTERRUPT_REGISTER_TEST.ILU1[0x18]=0
ILU_LAST_RECEIVED_CONTROLS.ILU0[0x164]=0x1011bdb9d8536daa
ILU_LAST_RECEIVED_CONTROLS.ILU1[0x164]=0x7ffffffff3fff3fe
ILU_LAST_RECEIVED_DATA_ON_SOP.ILU0[0x165]=0x7b7f55fbefccbcffbfdf7ffc757bfeffbeff9efefddf3dcfdaea7a3eb78babf9
ILU_LAST_RECEIVED_DATA_ON_SOP.ILU1[0x165]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffff7effbfbfff
ILU_LAST_SENT_BURST_DATA_ON_SOP(0).ILU0[0x16c]=0x7837689ffb28fc538efbaabbfcd49fdffff9ffed7ffdfffffaeed7ddf3c98a3c
ILU_LAST_SENT_BURST_DATA_ON_SOP(0).ILU1[0x16c]=0x19fd76ddfddfbddfbfbf7eebbcfbbebd7ffdffdfb1eed7bffedff3f1cfb77fbf
ILU_LAST_SENT_CONTROLS(0).ILU0[0x16b]=0x39bac6
ILU_LAST_SENT_CONTROLS(0).ILU1[0x16b]=0x5ff5fe
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(0).ILU0[0x130]=0
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(1).ILU0[0x131]=0
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(2).ILU0[0x132]=0
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(3).ILU0[0x133]=0
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(0).ILU1[0x130]=0
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(1).ILU1[0x131]=0
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(2).ILU1[0x132]=0
ILU_NUM_DROPPED_BURSTS_COUNTER_RX_HRF(3).ILU1[0x133]=0
ILU_PARITY_ERR_CNT.ILU0[0x98]=0
ILU_PARITY_ERR_CNT.ILU1[0x98]=0
ILU_PARSER_DISABLE_BUFFER_HRF.ILU0[0x1a5]=0
ILU_PARSER_DISABLE_BUFFER_HRF.ILU1[0x1a5]=0
ILU_PARSER_HARD_CONTROL.ILU0[0x400]=0xdc0c523819c
ILU_PARSER_HARD_CONTROL.ILU1[0x400]=0xdc0c523819c
ILU_PARSER_HARD_CONTROL_PLANE(0).ILU0[0x409]=0
ILU_PARSER_HARD_CONTROL_PLANE(1).ILU0[0x40a]=0
ILU_PARSER_HARD_CONTROL_PLANE(2).ILU0[0x40b]=0
ILU_PARSER_HARD_CONTROL_PLANE(3).ILU0[0x40c]=0
ILU_PARSER_HARD_CONTROL_PLANE(0).ILU1[0x409]=0
ILU_PARSER_HARD_CONTROL_PLANE(1).ILU1[0x40a]=0
ILU_PARSER_HARD_CONTROL_PLANE(2).ILU1[0x40b]=0
ILU_PARSER_HARD_CONTROL_PLANE(3).ILU1[0x40c]=0
ILU_PARSER_HARD_ETHER_TYPE.ILU0[0x408]=0
ILU_PARSER_HARD_ETHER_TYPE.ILU1[0x408]=0
ILU_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.ILU0[0x40f]=0x6db492249000
ILU_PARSER_HARD_ETH_PCP_DEI_TO_TDM_PRIORITY_TABLE.ILU1[0x40f]=0x6db492249000
ILU_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.ILU0[0x40e]=0x6db6db6db6db492492492492249249249249000000000000
ILU_PARSER_HARD_IP_DSCP_TO_TDM_PRIORITY_TABLE.ILU1[0x40e]=0x6db6db6db6db492492492492249249249249000000000000
ILU_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.ILU0[0x410]=0x6d2240
ILU_PARSER_HARD_MPLS_EXP_TO_TDM_PRIORITY_TABLE.ILU1[0x410]=0x6d2240
ILU_PARSER_HARD_PORT_ETH_TPID(0).ILU0[0x402]=0
ILU_PARSER_HARD_PORT_ETH_TPID(1).ILU0[0x403]=0
ILU_PARSER_HARD_PORT_ETH_TPID(0).ILU1[0x402]=0
ILU_PARSER_HARD_PORT_ETH_TPID(1).ILU1[0x403]=0
ILU_PARSER_HARD_PORT_PROPERTIES(0).ILU0[0x406]=0xf
ILU_PARSER_HARD_PORT_PROPERTIES(1).ILU0[0x407]=0xf
ILU_PARSER_HARD_PORT_PROPERTIES(0).ILU1[0x406]=0xf
ILU_PARSER_HARD_PORT_PROPERTIES(1).ILU1[0x407]=0xf
ILU_PARSER_HARD_PORT_TYPE(0).ILU0[0x404]=7
ILU_PARSER_HARD_PORT_TYPE(1).ILU0[0x405]=7
ILU_PARSER_HARD_PORT_TYPE(0).ILU1[0x404]=7
ILU_PARSER_HARD_PORT_TYPE(1).ILU1[0x405]=7
ILU_PARSER_HARD_SPECIAL_LABEL(0).ILU0[0x411]=0x30
ILU_PARSER_HARD_SPECIAL_LABEL(1).ILU0[0x412]=0x30
ILU_PARSER_HARD_SPECIAL_LABEL(2).ILU0[0x413]=0x30
ILU_PARSER_HARD_SPECIAL_LABEL(3).ILU0[0x414]=0x30
ILU_PARSER_HARD_SPECIAL_LABEL(0).ILU1[0x411]=0x30
ILU_PARSER_HARD_SPECIAL_LABEL(1).ILU1[0x412]=0x30
ILU_PARSER_HARD_SPECIAL_LABEL(2).ILU1[0x413]=0x30
ILU_PARSER_HARD_SPECIAL_LABEL(3).ILU1[0x414]=0x30
ILU_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.ILU0[0x40d]=0x6db6db6db6db492492492492249249249249000000000000
ILU_PARSER_HARD_TM_TC_DP_TO_TDM_PRIORITY_TABLE.ILU1[0x40d]=0x6db6db6db6db492492492492249249249249000000000000
ILU_PARSER_OUTPUT_MORE_THAN_FOUR_WORDS.ILU0[0x1a4]=0
ILU_PARSER_OUTPUT_MORE_THAN_FOUR_WORDS.ILU1[0x1a4]=0
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).ILU0[0x427]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).ILU0[0x428]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).ILU0[0x429]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).ILU0[0x42a]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).ILU0[0x42b]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).ILU0[0x42c]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).ILU0[0x42d]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).ILU0[0x42e]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).ILU0[0x42f]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).ILU0[0x430]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).ILU0[0x431]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).ILU0[0x432]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).ILU0[0x433]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).ILU0[0x434]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).ILU0[0x435]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(0).ILU1[0x427]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(1).ILU1[0x428]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(2).ILU1[0x429]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(3).ILU1[0x42a]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(4).ILU1[0x42b]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(5).ILU1[0x42c]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(6).ILU1[0x42d]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(7).ILU1[0x42e]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(8).ILU1[0x42f]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(9).ILU1[0x430]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(10).ILU1[0x431]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(11).ILU1[0x432]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(12).ILU1[0x433]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(13).ILU1[0x434]=0x20
ILU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES(14).ILU1[0x435]=0x20
ILU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).ILU0[0x415]=1
ILU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).ILU0[0x416]=1
ILU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(0).ILU1[0x415]=1
ILU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE(1).ILU1[0x416]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).ILU0[0x417]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).ILU0[0x418]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).ILU0[0x419]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).ILU0[0x41a]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).ILU0[0x41b]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).ILU0[0x41c]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).ILU0[0x41d]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).ILU0[0x41e]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).ILU0[0x41f]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).ILU0[0x420]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).ILU0[0x421]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).ILU0[0x422]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).ILU0[0x423]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).ILU0[0x424]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).ILU0[0x425]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).ILU0[0x426]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(0).ILU1[0x417]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(1).ILU1[0x418]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(2).ILU1[0x419]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(3).ILU1[0x41a]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(4).ILU1[0x41b]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(5).ILU1[0x41c]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(6).ILU1[0x41d]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(7).ILU1[0x41e]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(8).ILU1[0x41f]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(9).ILU1[0x420]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(10).ILU1[0x421]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(11).ILU1[0x422]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(12).ILU1[0x423]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(13).ILU1[0x424]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(14).ILU1[0x425]=1
ILU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION(15).ILU1[0x426]=1
ILU_PARSER_SOFT_TCAM_0_TO_7.ILU0[0x436]=0
ILU_PARSER_SOFT_TCAM_0_TO_7.ILU1[0x436]=0
ILU_PARSER_SOFT_TCAM_16_TO_23.ILU0[0x438]=0
ILU_PARSER_SOFT_TCAM_16_TO_23.ILU1[0x438]=0
ILU_PARSER_SOFT_TCAM_24_TO_31.ILU0[0x439]=0
ILU_PARSER_SOFT_TCAM_24_TO_31.ILU1[0x439]=0
ILU_PARSER_SOFT_TCAM_8_TO_15.ILU0[0x437]=0
ILU_PARSER_SOFT_TCAM_8_TO_15.ILU1[0x437]=0
ILU_PAR_ERR_MEM_MASK.ILU0[0xa0]=0xffff
ILU_PAR_ERR_MEM_MASK.ILU1[0xa0]=0xffff
ILU_PCMI_0.ILU0[0xb0]=0x3b9aca00
ILU_PCMI_0.ILU1[0xb0]=0x3b9aca00
ILU_PCMI_1.ILU0[0xb3]=0x3b9aca00
ILU_PCMI_1.ILU1[0xb3]=0x3b9aca00
ILU_PCMI_2.ILU0[0xb6]=0x3b9aca00
ILU_PCMI_2.ILU1[0xb6]=0x3b9aca00
ILU_PCMI_3.ILU0[0xb9]=0x3b9aca00
ILU_PCMI_3.ILU1[0xb9]=0x3b9aca00
ILU_PCMI_4.ILU0[0xbc]=0x3b9aca00
ILU_PCMI_4.ILU1[0xbc]=0x3b9aca00
ILU_PCMI_0_S.ILU0[0xb1]=0
ILU_PCMI_0_S.ILU1[0xb1]=0
ILU_PCMI_0_T.ILU0[0xb2]=0
ILU_PCMI_0_T.ILU1[0xb2]=0
ILU_PCMI_1_S.ILU0[0xb4]=0
ILU_PCMI_1_S.ILU1[0xb4]=0
ILU_PCMI_1_T.ILU0[0xb5]=0
ILU_PCMI_1_T.ILU1[0xb5]=0
ILU_PCMI_2_S.ILU0[0xb7]=0
ILU_PCMI_2_S.ILU1[0xb7]=0
ILU_PCMI_2_T.ILU0[0xb8]=0
ILU_PCMI_2_T.ILU1[0xb8]=0
ILU_PCMI_3_S.ILU0[0xba]=0
ILU_PCMI_3_S.ILU1[0xba]=0
ILU_PCMI_3_T.ILU0[0xbb]=0
ILU_PCMI_3_T.ILU1[0xbb]=0
ILU_PCMI_4_S.ILU0[0xbd]=0
ILU_PCMI_4_S.ILU1[0xbd]=0
ILU_PCMI_4_T.ILU0[0xbe]=0
ILU_PCMI_4_T.ILU1[0xbe]=0
ILU_PKT_DROP_COUNTER_RX_HRF(0).ILU0[0x12c]=0
ILU_PKT_DROP_COUNTER_RX_HRF(1).ILU0[0x12d]=0
ILU_PKT_DROP_COUNTER_RX_HRF(2).ILU0[0x12e]=0
ILU_PKT_DROP_COUNTER_RX_HRF(3).ILU0[0x12f]=0
ILU_PKT_DROP_COUNTER_RX_HRF(0).ILU1[0x12c]=0
ILU_PKT_DROP_COUNTER_RX_HRF(1).ILU1[0x12d]=0
ILU_PKT_DROP_COUNTER_RX_HRF(2).ILU1[0x12e]=0
ILU_PKT_DROP_COUNTER_RX_HRF(3).ILU1[0x12f]=0
ILU_PKT_DROP_COUNTER_TX_HRF(0).ILU0[0x16f]=0
ILU_PKT_DROP_COUNTER_TX_HRF(1).ILU0[0x170]=0
ILU_PKT_DROP_COUNTER_TX_HRF(0).ILU1[0x16f]=0
ILU_PKT_DROP_COUNTER_TX_HRF(1).ILU1[0x170]=0
ILU_PORT_0_NUM_USER_IF_SEGS.ILU0[0x1a7]=0
ILU_PORT_0_NUM_USER_IF_SEGS.ILU1[0x1a7]=0
ILU_PRD_CFG.ILU0[0x19d]=0
ILU_PRD_CFG.ILU1[0x19d]=0
ILU_PRD_ERR_PKT_DROP_CNT_HRF(0).ILU0[0x1a0]=0
ILU_PRD_ERR_PKT_DROP_CNT_HRF(1).ILU0[0x1a1]=0
ILU_PRD_ERR_PKT_DROP_CNT_HRF(0).ILU1[0x1a0]=0
ILU_PRD_ERR_PKT_DROP_CNT_HRF(1).ILU1[0x1a1]=0
ILU_PRD_PKT_DROP_CNT_HRF(0).ILU0[0x19e]=0
ILU_PRD_PKT_DROP_CNT_HRF(1).ILU0[0x19f]=0
ILU_PRD_PKT_DROP_CNT_HRF(0).ILU1[0x19e]=0
ILU_PRD_PKT_DROP_CNT_HRF(1).ILU1[0x19f]=0
ILU_PRD_PP_PARSER_CFG(0).ILU0[0x1a2]=0
ILU_PRD_PP_PARSER_CFG(1).ILU0[0x1a3]=0
ILU_PRD_PP_PARSER_CFG(0).ILU1[0x1a2]=0
ILU_PRD_PP_PARSER_CFG(1).ILU1[0x1a3]=0
ILU_REG_00C2.ILU0[0xc2]=0x10
ILU_REG_00C2.ILU1[0xc2]=0x10
ILU_RESERVED_MTCD.ILU0[0xae]=0x30
ILU_RESERVED_MTCD.ILU1[0xae]=0x30
ILU_RESERVED_MTCP.ILU0[0xad]=0x300000600000000
ILU_RESERVED_MTCP.ILU1[0xad]=0x300000600000000
ILU_RESERVED_SPARE_0.ILU0[0x90]=0xffffffff
ILU_RESERVED_SPARE_0.ILU1[0x90]=0xffffffff
ILU_RESERVED_SPARE_1.ILU0[0x91]=0xffffffff
ILU_RESERVED_SPARE_1.ILU1[0x91]=0xffffffff
ILU_RESERVED_SPARE_2.ILU0[0x92]=3
ILU_RESERVED_SPARE_2.ILU1[0x92]=3
ILU_RESERVED_SPARE_3.ILU0[0x93]=0
ILU_RESERVED_SPARE_3.ILU1[0x93]=0
ILU_RX_HRF_SEGMENTATION_SRSTN.ILU0[0x127]=0x1f
ILU_RX_HRF_SEGMENTATION_SRSTN.ILU1[0x127]=0x1f
ILU_RX_PRSR_WRAP_SRSTN.ILU0[0x103]=0
ILU_RX_PRSR_WRAP_SRSTN.ILU1[0x103]=0
ILU_RX_SAMPLER_NUM_OF_SAMPLES_CFG.ILU0[0x104]=0x12
ILU_RX_SAMPLER_NUM_OF_SAMPLES_CFG.ILU1[0x104]=0x12
ILU_RX_SCH_CNT_DEC_TH.ILU0[0x138]=0
ILU_RX_SCH_CNT_DEC_TH.ILU1[0x138]=0
ILU_RX_SCH_DATA_HRFS_PRIORITY.ILU0[0x142]=0
ILU_RX_SCH_DATA_HRFS_PRIORITY.ILU1[0x142]=0
ILU_RX_SCH_DEBUG_CONF.ILU0[0x13a]=0
ILU_RX_SCH_DEBUG_CONF.ILU1[0x13a]=0
ILU_RX_SCH_DEBUG_RESULT.ILU0[0x139]=0x2000
ILU_RX_SCH_DEBUG_RESULT.ILU1[0x139]=0x2000
ILU_RX_SCH_FLUSH_OR_STOP_RX_FIFO.ILU0[0x13b]=0
ILU_RX_SCH_FLUSH_OR_STOP_RX_FIFO.ILU1[0x13b]=0
ILU_RX_SCH_LOW_HRF_EN_IS_ALL_MASKED.ILU0[0x13c]=0
ILU_RX_SCH_LOW_HRF_EN_IS_ALL_MASKED.ILU1[0x13c]=0
ILU_RX_SCH_LOW_RMC_REQ_EN.ILU0[0x13d]=3
ILU_RX_SCH_LOW_RMC_REQ_EN.ILU1[0x13d]=3
ILU_RX_SCH_MORE_THAN_ONE_RD_FROM_MAIN_SCH.ILU0[0x13e]=0
ILU_RX_SCH_MORE_THAN_ONE_RD_FROM_MAIN_SCH.ILU1[0x13e]=0
ILU_RX_SCH_WIN_PRIOR_HIGH_WITH_NO_WIN_HRF_CNT.ILU0[0x140]=0
ILU_RX_SCH_WIN_PRIOR_HIGH_WITH_NO_WIN_HRF_CNT.ILU1[0x140]=0
ILU_RX_SCH_WIN_PRIOR_LOW_WITH_NO_WIN_HRF_CNT.ILU0[0x141]=0
ILU_RX_SCH_WIN_PRIOR_LOW_WITH_NO_WIN_HRF_CNT.ILU1[0x141]=0
ILU_RX_SCH_WIN_PRIOR_TDM_WITH_NO_WIN_HRF_CNT.ILU0[0x13f]=0
ILU_RX_SCH_WIN_PRIOR_TDM_WITH_NO_WIN_HRF_CNT.ILU1[0x13f]=0
ILU_RX_TDM_BYTE_COUNTER.ILU0[0x16a]=0
ILU_RX_TDM_BYTE_COUNTER.ILU1[0x16a]=0
ILU_RX_TDM_PKT_COUNTER.ILU0[0x169]=0
ILU_RX_TDM_PKT_COUNTER.ILU1[0x169]=0
ILU_RX_TOTAL_BYTE_COUNTER.ILU0[0x168]=0
ILU_RX_TOTAL_BYTE_COUNTER.ILU1[0x168]=0
ILU_RX_TOTAL_PKT_COUNTER.ILU0[0x167]=0
ILU_RX_TOTAL_PKT_COUNTER.ILU1[0x167]=0
ILU_SBUS_BROADCAST_ID.ILU0[0x86]=0x7ff
ILU_SBUS_BROADCAST_ID.ILU1[0x86]=0x7ff
ILU_SBUS_LAST_IN_CHAIN.ILU0[0x87]=0
ILU_SBUS_LAST_IN_CHAIN.ILU1[0x87]=0
ILU_SPECIAL_CLOCK_CONTROLS.ILU0[0xc1]=3
ILU_SPECIAL_CLOCK_CONTROLS.ILU1[0xc1]=3
ILU_TX_ILKN_CONFIG.ILU0[0x189]=0
ILU_TX_ILKN_CONFIG.ILU1[0x189]=0
ILU_TX_ILKN_IBE_BURST_COUNTER(0).ILU0[0x17d]=0
ILU_TX_ILKN_IBE_BURST_COUNTER(1).ILU0[0x17e]=0
ILU_TX_ILKN_IBE_BURST_COUNTER(0).ILU1[0x17d]=0
ILU_TX_ILKN_IBE_BURST_COUNTER(1).ILU1[0x17e]=0
ILU_TX_ILKN_IBE_BYTE_COUNTER(0).ILU0[0x173]=0
ILU_TX_ILKN_IBE_BYTE_COUNTER(1).ILU0[0x174]=0
ILU_TX_ILKN_IBE_BYTE_COUNTER(0).ILU1[0x173]=0
ILU_TX_ILKN_IBE_BYTE_COUNTER(1).ILU1[0x174]=0
ILU_TX_ILKN_IBE_CONFIG.ILU0[0x186]=2
ILU_TX_ILKN_IBE_CONFIG.ILU1[0x186]=2
ILU_TX_ILKN_IBE_ERROR_PKT_COUNTER(0).ILU0[0x17b]=0
ILU_TX_ILKN_IBE_ERROR_PKT_COUNTER(1).ILU0[0x17c]=0
ILU_TX_ILKN_IBE_ERROR_PKT_COUNTER(0).ILU1[0x17b]=0
ILU_TX_ILKN_IBE_ERROR_PKT_COUNTER(1).ILU1[0x17c]=0
ILU_TX_ILKN_IBE_PKTS_INTERLEAVED(0).ILU0[0x187]=0
ILU_TX_ILKN_IBE_PKTS_INTERLEAVED(1).ILU0[0x188]=0
ILU_TX_ILKN_IBE_PKTS_INTERLEAVED(0).ILU1[0x187]=0
ILU_TX_ILKN_IBE_PKTS_INTERLEAVED(1).ILU1[0x188]=0
ILU_TX_ILKN_IBE_PKT_COUNTER(0).ILU0[0x175]=0
ILU_TX_ILKN_IBE_PKT_COUNTER(1).ILU0[0x176]=0
ILU_TX_ILKN_IBE_PKT_COUNTER(0).ILU1[0x175]=0
ILU_TX_ILKN_IBE_PKT_COUNTER(1).ILU1[0x176]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_EGQ_TRANS(0).ILU0[0x181]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_EGQ_TRANS(1).ILU0[0x182]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_EGQ_TRANS(0).ILU1[0x181]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_EGQ_TRANS(1).ILU1[0x182]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_PKT_INTERLEAVE(0).ILU0[0x17f]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_PKT_INTERLEAVE(1).ILU0[0x180]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_PKT_INTERLEAVE(0).ILU1[0x17f]=0
ILU_TX_ILKN_IBE_RECEIVED_ILLEGAL_PKT_INTERLEAVE(1).ILU1[0x180]=0
ILU_TX_ILKN_IBE_TDM_BYTE_COUNTER(0).ILU0[0x177]=0
ILU_TX_ILKN_IBE_TDM_BYTE_COUNTER(1).ILU0[0x178]=0
ILU_TX_ILKN_IBE_TDM_BYTE_COUNTER(0).ILU1[0x177]=0
ILU_TX_ILKN_IBE_TDM_BYTE_COUNTER(1).ILU1[0x178]=0
ILU_TX_ILKN_IBE_TDM_PKT_COUNTER(0).ILU0[0x179]=0
ILU_TX_ILKN_IBE_TDM_PKT_COUNTER(1).ILU0[0x17a]=0
ILU_TX_ILKN_IBE_TDM_PKT_COUNTER(0).ILU1[0x179]=0
ILU_TX_ILKN_IBE_TDM_PKT_COUNTER(1).ILU1[0x17a]=0
ILU_TX_ILKN_PORT_IBE_CONFIG(0).ILU0[0x184]=0
ILU_TX_ILKN_PORT_IBE_CONFIG(1).ILU0[0x185]=0
ILU_TX_ILKN_PORT_IBE_CONFIG(0).ILU1[0x184]=0
ILU_TX_ILKN_PORT_IBE_CONFIG(1).ILU1[0x185]=0
ILU_TX_TOTAL_BYTE_COUNTER.ILU0[0x16e]=0
ILU_TX_TOTAL_BYTE_COUNTER.ILU1[0x16e]=0
ILU_TX_TOTAL_PKT_COUNTER.ILU0[0x16d]=0
ILU_TX_TOTAL_PKT_COUNTER.ILU1[0x16d]=0
IPPA_CFG_MAP_CTX_TO_LIF_LOOKUP_ENABLE(3).IPPA0[0x1dd]=0x3fffff33f
IPPA_CFG_MAP_CTX_TO_LIF_LOOKUP_ENABLE(4).IPPA0[0x1de]=0x3fffffe07f
IPPA_CFG_PROTOCOL_IS_ETH.IPPA0[0x1c9]=0xffffffff
IPPA_CFG_PROTOCOL_IS_IPV4.IPPA0[0x1c6]=4
IPPA_CFG_PROTOCOL_IS_IPV6.IPPA0[0x1c7]=8
IPPA_CFG_PROTOCOL_IS_MAC_IN_MAC.IPPA0[0x1c8]=0
IPPA_CFG_PROTOCOL_IS_MPLS.IPPA0[0x1ca]=0x10
IPPA_CS_INLIF_PROFILE_MAP_LSB.IPPA0[0x1cb]=0
IPPA_CS_INLIF_PROFILE_MAP_MSB.IPPA0[0x1db]=0x4440000000000000000000000000000044400000000000000000000000000000444000000000000000000000000000004440
IPPA_ECC_1B_ERR_CNT.IPPA0[0x94]=0
IPPA_ECC_2B_ERR_CNT.IPPA0[0x96]=0
IPPA_ECC_ERR_1B_MONITOR_MEM_MASK.IPPA0[0x9a]=0xfffffffffffff
IPPA_ECC_ERR_2B_MONITOR_MEM_MASK.IPPA0[0x9c]=0xfffffffffffff
IPPA_ECC_INTERRUPT_REGISTER.IPPA0[0x7]=0
IPPA_ECC_INTERRUPT_REGISTER_MASK.IPPA0[0x17]=0
IPPA_ECC_INTERRUPT_REGISTER_TEST.IPPA0[0x1f]=0
IPPA_ENABLE_DYNAMIC_MEMORY_ACCESS.IPPA0[0x84]=0xf
IPPA_ETHERNET_TRAP.IPPA0[0x19f]=0x18171816001518140000
IPPA_ETHERNET_TRAP_ACTION_PROFILE_VECTOR.IPPA0[0x19e]=0x2400000000000000000000000000000000001b012249000
IPPA_ETH_PCP_TO_OAM_PCP.IPPA0[0x197]=0xfac688
IPPA_EXTEND_VCP_ENABLE.IPPA0[0x1ee]=0
IPPA_FWD_DOMAIN_MASKS(3).IPPA0[0x1b0]=0xffffc000003fffffff00003ffff
IPPA_FWD_DOMAIN_MASKS(4).IPPA0[0x1b1]=0xffffc000003fffffff00003ffff
IPPA_FWD_DOMAIN_MASK_PROFILE_MAP(3).IPPA0[0x1ae]=0x800050000
IPPA_FWD_DOMAIN_MASK_PROFILE_MAP(4).IPPA0[0x1af]=0x800050000
IPPA_GTIMER_CONFIGURATION.IPPA0[0x89]=0
IPPA_GTIMER_CYCLE.IPPA0[0x88]=0x3b9aca00
IPPA_INDIRECT_COMMAND.IPPA0[0x80]=0x3fff0000
IPPA_INDIRECT_COMMAND_ADDRESS.IPPA0[0x81]=0x80910100
IPPA_INDIRECT_COMMAND_RD_DATA.IPPA0[0x60]=0
IPPA_INDIRECT_COMMAND_WIDE_MEM.IPPA0[0x41]=0
IPPA_INDIRECT_COMMAND_WR_DATA.IPPA0[0x20]=0
IPPA_INDIRECT_FORCE_BUBBLE.IPPA0[0x83]=0x20019
IPPA_INDIRECT_WR_MASK.IPPA0[0x40]=0xff
IPPA_INITIAL_PCP_DEI_MAP_TYPE.IPPA0[0x1bc]=8
IPPA_INTERRUPT_MASK_REGISTER.IPPA0[0x10]=0
IPPA_INTERRUPT_REGISTER.IPPA0[0x0]=0
IPPA_INTERRUPT_REGISTER_TEST.IPPA0[0x18]=0
IPPA_IPPA_SAMPLE_VALIDS.IPPA0[0x100]=0x300
IPPA_IP_STAGE_SEL.IPPA0[0x168]=1
IPPA_IP_TOS_TO_OAM_PCP_0.IPPA0[0x17f]=0
IPPA_IP_TOS_TO_OAM_PCP_1.IPPA0[0x18b]=0
IPPA_LEARN_KEY_CONTEXT.IPPA0[0x1ba]=0x116a4a0
IPPA_LIF_TRAPS(3).IPPA0[0x1a1]=0x16f00000
IPPA_LIF_TRAPS(4).IPPA0[0x1a2]=0x16f00000
IPPA_MAC_IN_MAC_VSI.IPPA0[0x1ed]=0
IPPA_MAP_PARSER_CTX_TO_PROTOCOL.IPPA0[0x1ec]=0x128800110008008000
IPPA_MAP_PORT_TO_LEARN_LIF_VEC_LSB.IPPA0[0x1bd]=0xfffffffff60000000000004ffffffffff
IPPA_MAP_PORT_TO_LEARN_LIF_VEC_MSB.IPPA0[0x1c5]=0
IPPA_MAP_VRID_TO_IP_VERSION.IPPA0[0x1a3]=0x70
IPPA_MEF_L_2_CP_TRANSPARENT_BITMAP.IPPA0[0x177]=0
IPPA_MPLS_EXP_TO_OAM_PCP.IPPA0[0x198]=0xfac688
IPPA_MPLS_LABEL_PROCEDURE_CONFIG.IPPA0[0x199]=5
IPPA_MPLS_SPECIAL_LABEL_ATTRIBUTES.IPPA0[0x19a]=0x1c30000000400046000000080020c0000001200618000000100007800228020000d00045004
IPPA_MY_B_MAC_LSB_BITMAP.IPPA0[0x16b]=0
IPPA_MY_B_MAC_MC.IPPA0[0x169]=0x11e83
IPPA_MY_B_MAC_MSB.IPPA0[0x16a]=0
IPPA_PARITY_ERR_CNT.IPPA0[0x98]=0
IPPA_PAR_ERR_MEM_MASK.IPPA0[0xa0]=0x7ffffff
IPPA_PCMI_0.IPPA0[0xb0]=0x3b9aca00
IPPA_PCMI_1.IPPA0[0xb3]=0x3b9aca00
IPPA_PCMI_2.IPPA0[0xb6]=0x3b9aca00
IPPA_PCMI_3.IPPA0[0xb9]=0x3b9aca00
IPPA_PCMI_4.IPPA0[0xbc]=0x3b9aca00
IPPA_PCMI_0_S.IPPA0[0xb1]=0
IPPA_PCMI_0_T.IPPA0[0xb2]=0
IPPA_PCMI_1_S.IPPA0[0xb4]=0
IPPA_PCMI_1_T.IPPA0[0xb5]=0
IPPA_PCMI_2_S.IPPA0[0xb7]=0
IPPA_PCMI_2_T.IPPA0[0xb8]=0
IPPA_PCMI_3_S.IPPA0[0xba]=0
IPPA_PCMI_3_T.IPPA0[0xbb]=0
IPPA_PCMI_4_S.IPPA0[0xbd]=0
IPPA_PCMI_4_T.IPPA0[0xbe]=0
IPPA_REG_0420.IPPA0[0x420]=0x19a0300
IPPA_REG_0421.IPPA0[0x421]=0x6cb2d400137f0000000000000000000004486d036b8d6fe6947c0cc88c329959c0a5cb32ada4e1ed4f0b8a3e3399fa645c3e2988afa0dc0d66d2b81476a3d64f0e868e406024ed0a324f98d8a7555c1d
IPPA_REG_0905.IPPA0[0x905]=0
IPPA_REG_0908.IPPA0[0x908]=0xa100000000
IPPA_REG_0955.IPPA0[0x955]=0
IPPA_REG_0958.IPPA0[0x958]=0x9900000000
IPPA_REG_00C2.IPPA0[0xc2]=0x10
IPPA_REG_00F0.IPPA0[0xf0]=0
IPPA_REG_090A.IPPA0[0x90a]=0
IPPA_REG_095A.IPPA0[0x95a]=0
IPPA_RESERVED_MTCD.IPPA0[0xae]=0x30
IPPA_RESERVED_MTCP.IPPA0[0xad]=0x300000600000000
IPPA_RESERVED_SPARE_0.IPPA0[0x90]=0xffffffff
IPPA_RESERVED_SPARE_1.IPPA0[0x91]=0xffffffff
IPPA_RESERVED_SPARE_2.IPPA0[0x92]=0
IPPA_RESERVED_SPARE_3.IPPA0[0x93]=0
IPPA_SBUS_BROADCAST_ID.IPPA0[0x86]=0x7ff
IPPA_SBUS_LAST_IN_CHAIN.IPPA0[0x87]=0
IPPA_SECOND_STAGE_PARSING_SELECT.IPPA0[0x167]=5
IPPA_SPECIAL_CLOCK_CONTROLS.IPPA0[0xc1]=2
IPPA_STATISTICS_INFO.IPPA0[0x1df]=0
IPPA_STAT_OBJ_PROFILE_ATTR.IPPA0[0x1e6]=0
IPPA_VTB_ETHERNET_PROC_STAGE_SEL.IPPA0[0x166]=0xb
IPPA_VTDCS_TCAM_ECC_FIX_EN.IPPA0[0x902]=0
IPPA_VTDCS_TCAM_PROTECTION_ERROR.IPPA0[0x904]=0
IPPA_VTDCS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPA0[0x900]=0xff
IPPA_VTDCS_TCAM_RESET_BLOCK.IPPA0[0x903]=0
IPPA_VTECS_TCAM_ECC_FIX_EN.IPPA0[0x952]=0
IPPA_VTECS_TCAM_PROTECTION_ERROR.IPPA0[0x954]=0
IPPA_VTECS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPA0[0x950]=0xff
IPPA_VTECS_TCAM_RESET_BLOCK.IPPA0[0x953]=0
IPPA_VTT_ACTION_PROFILE_ACCEPTABLE_FRAME_TYPES.IPPA0[0x1bb]=0x200
IPPA_VTT_ETHERNET_TERMINATION_ACTION.IPPA0[0x19d]=0xaaaaaaaaaaaaaaaaa4a4a4a4a4a4a4a400000000000000000000000000000000aaaaaaaaaaaaaaaaa484a484a484a484
IPPA_VTT_GENERAL_CONFIGS_0.IPPA0[0x165]=2
IPPA_VTT_MPLS_LABEL_RANGE_PROFILE.IPPA0[0x1a5]=0xf
IPPA_VTT_MPLS_PREPROCESSING_BOS_OR_TTL_TRAP.IPPA0[0x19c]=0xf80
IPPA_VTT_MY_MAC_VRID_VMV_SHIFT_VALUE.IPPA0[0x19b]=4
IPPA_VTT_QOS_PROPAG_PROFILE_MAPPING.IPPA0[0x1aa]=0x444414115455
IPPA_VTT_SPECIAL_LABELS_PROFILE.IPPA0[0x1a7]=0xdad936db6db66f6db6d8949b
IPPA_VTT_SPECIAL_LABEL_VALUES.IPPA0[0x1a8]=0
IPPA_VTT_ST_TH_LE_CONFIG.IPPA0[0x480]=0xac
IPPA_VTT_ST_TH_LE_CONTROL_FIFO_CFG(0).IPPA0[0x481]=1
IPPA_VTT_ST_TH_LE_CONTROL_FIFO_CFG(1).IPPA0[0x482]=1
IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG(0).IPPA0[0x483]=0
IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG(1).IPPA0[0x484]=0
IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG(2).IPPA0[0x485]=0
IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG(3).IPPA0[0x486]=0
IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG(4).IPPA0[0x487]=0
IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG(5).IPPA0[0x488]=0
IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG(6).IPPA0[0x489]=0
IPPA_VTT_ST_TH_LE_VMV_SHIFT_VALUE_MAP(0).IPPA0[0x48a]=0x924924924000924924924000924924924000924924924924
IPPA_VTT_ST_TH_LE_VMV_SHIFT_VALUE_MAP(1).IPPA0[0x48b]=0x492492492492492492492492000000000000492492492492
IPPA_VTT_ST_TH_LE_VMV_SHIFT_VALUE_MAP(2).IPPA0[0x48c]=0x492492492492492492492492000000000000492492492492
IPPA_VTT_TRAP_STRENGTHS_0.IPPA0[0x16c]=0xc1800000
IPPA_VTT_TRAP_STRENGTHS_1.IPPA0[0x16d]=0
IPPA_VTT_TRAP_STRENGTHS_2.IPPA0[0x16e]=0x3068d
IPPA_VTT_TRAP_STRENGTHS_3.IPPA0[0x16f]=0xc1830600
IPPA_VTT_TRAP_STRENGTHS_4.IPPA0[0x170]=0x60c163058c
IPPA_VTT_TRAP_STRENGTHS_5.IPPA0[0x172]=0xb160000c
IPPA_VTT_TRAP_STRENGTHS_6.IPPA0[0x173]=0xc0000000
IPPA_VTT_TRAP_STRENGTHS_7.IPPA0[0x175]=0x16000000000
IPPA_VTT_TRAP_STRENGTHS_8.IPPA0[0x176]=0
IPPB_ACTION_PROFILE_IEEE_1588.IPPB0[0x102]=0x78c
IPPB_ACTION_PROFILE_SA_DROP_MAP.IPPB0[0x100]=0
IPPB_ACTION_PROFILE_SA_NOT_FOUND_MAP.IPPB0[0x101]=0x810000
IPPB_ALL_ESADI_RBRIDGES.IPPB0[0x10d]=0
IPPB_APP_DB_INDEX_MAP.IPPB0[0x708]=0x100c2
IPPB_ARP_TRAP_CFG.IPPB0[0x1ad]=0
IPPB_CS_INLIF_PROFILE_MAP_0.IPPB0[0x1b2]=0
IPPB_CS_INLIF_PROFILE_MAP_1.IPPB0[0x1c2]=0
IPPB_CURRENT_LAYER_STATISTICS_META_DATA_INFORMATION_MAP.IPPB0[0x1e4]=0
IPPB_CURRENT_LAYER_STATISTICS_META_DATA_INSTRUCTION_MAP.IPPB0[0x1de]=0
IPPB_DBG_FLP_DATA_PATH_TRAP.IPPB0[0x11c]=0x80008813
IPPB_DBG_FLP_LPM.IPPB0[0x120]=0
IPPB_DBG_FLP_PACKETS_REJECTED_BY_EGW_CNT.IPPB0[0x11f]=0
IPPB_DBG_IEEE_1588_IDENTIFICATION_CAM_LINE.IPPB0[0x11b]=0x4000
IPPB_DSCP_REMARK_INHERITANCE_RESOLUTION_MPLS_CFG.IPPB0[0x126]=4
IPPB_DSCP_REMARK_PORT_CFG.IPPB0[0x217]=0
IPPB_ECC_1B_ERR_CNT.IPPB0[0x94]=0
IPPB_ECC_2B_ERR_CNT.IPPB0[0x96]=0
IPPB_ECC_ERR_1B_MONITOR_MEM_MASK.IPPB0[0x9a]=0x3fffffffffffffffffffff
IPPB_ECC_ERR_2B_MONITOR_MEM_MASK.IPPB0[0x9c]=0x3fffffffffffffffffffff
IPPB_ECC_INTERRUPT_REGISTER.IPPB0[0x7]=0
IPPB_ECC_INTERRUPT_REGISTER_MASK.IPPB0[0x17]=0
IPPB_ECC_INTERRUPT_REGISTER_TEST.IPPB0[0x1f]=0
IPPB_ECN_PORT_CFG.IPPB0[0x216]=0
IPPB_EGRESS_OPPORTUNISTIC_FIFO_PROPERTIES.IPPB0[0x706]=0
IPPB_EGW_BACK_PRESSURE_CHICKEN_BIT.IPPB0[0x21f]=0
IPPB_EGW_ENABLE_OPCODE_ERROR_HANDLING.IPPB0[0x21b]=0
IPPB_EGW_OPCODE_ERROR_DROP_COUNTER.IPPB0[0x21a]=0
IPPB_ELK_ERROR_TRAP_ACTION_PROFILE.IPPB0[0x1b0]=0
IPPB_ELK_FWD_RESULT_SIZE_MAP(0).IPPB0[0x1e5]=0x8002040000204080000408102000
IPPB_ELK_FWD_RESULT_SIZE_MAP(1).IPPB0[0x1e6]=0
IPPB_ELK_FWD_RESULT_SIZE_MAP(2).IPPB0[0x1e7]=0
IPPB_ELK_FWD_RESULT_SIZE_MAP(3).IPPB0[0x1e8]=0
IPPB_ELK_KAPS_ACL_CFG.IPPB0[0x1f3]=0
IPPB_ELK_RESULT_TYPE.IPPB0[0x158]=0
IPPB_ENABLE_DYNAMIC_MEMORY_ACCESS.IPPB0[0x84]=0x7f
IPPB_ENABLE_KAPS_INTERFACE_DEFAULT.IPPB0[0x163]=0xf
IPPB_ETHERNET_TRAPS_ACTION_PROFILES_CFG.IPPB0[0x110]=0
IPPB_EXEM_SELECTOR.IPPB0[0x19]=1
IPPB_FC_ACTION_PROFILES.IPPB0[0x117]=0
IPPB_FLPACS_TCAM_ECC_FIX_EN.IPPB0[0x1001]=0
IPPB_FLPACS_TCAM_PROTECTION_ERROR.IPPB0[0x1003]=0
IPPB_FLPACS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPB0[0x1000]=0xff
IPPB_FLPACS_TCAM_RESET_BLOCK.IPPB0[0x1002]=0
IPPB_FLPBCS_TCAM_ECC_FIX_EN.IPPB0[0x1101]=0
IPPB_FLPBCS_TCAM_PROTECTION_ERROR.IPPB0[0x1103]=0
IPPB_FLPBCS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPB0[0x1100]=0xff
IPPB_FLPBCS_TCAM_RESET_BLOCK.IPPB0[0x1102]=0
IPPB_FLPLE_CONFIG.IPPB0[0x2000]=0x609e57
IPPB_FLPLE_CONTROL_FIFO_0_DEBUG_CFG.IPPB0[0x2013]=5
IPPB_FLPLE_CONTROL_FIFO_1_DEBUG_CFG.IPPB0[0x2014]=5
IPPB_FLPLE_DE_FIFO_DEBUG_CFG.IPPB0[0x2016]=0
IPPB_FLPLE_ELK_FIFO_DEBUG_CFG.IPPB0[0x2015]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(0).IPPB0[0x2001]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(1).IPPB0[0x2002]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(2).IPPB0[0x2003]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(3).IPPB0[0x2004]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(4).IPPB0[0x2005]=1
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(5).IPPB0[0x2006]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(6).IPPB0[0x2007]=3
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(7).IPPB0[0x2008]=1
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(8).IPPB0[0x2009]=4
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(9).IPPB0[0x200a]=4
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(10).IPPB0[0x200b]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(11).IPPB0[0x200c]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(12).IPPB0[0x200d]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(13).IPPB0[0x200e]=0
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(14).IPPB0[0x200f]=2
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(15).IPPB0[0x2010]=2
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(16).IPPB0[0x2011]=2
IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG(17).IPPB0[0x2012]=2
IPPB_FLPLE_VMV_SHIFT_VALUE_MAP(0).IPPB0[0x2017]=0x9249249249249249246db6db6db6db6db6db0000006db6db
IPPB_FLPLE_VMV_SHIFT_VALUE_MAP(1).IPPB0[0x2018]=0x924924924000924924924000924924924000924924924924
IPPB_FLPLE_VMV_SHIFT_VALUE_MAP(2).IPPB0[0x2019]=0x492492492492492492492492492492492492492492492492
IPPB_FLP_EGW_CREDIT_THRESHOLD.IPPB0[0x11e]=0
IPPB_FLP_GENERAL_CFG.IPPB0[0x10c]=0x3e8
IPPB_FLP_L_4_TRAP_TCP_EQUAL_PORTS.IPPB0[0x137]=0
IPPB_FLP_L_4_TRAP_TCP_FRAGMENT_INCOMPLETE_HEADER.IPPB0[0x138]=0
IPPB_FLP_L_4_TRAP_TCP_FRAGMENT_OFFSET_LARGER_THAN_8.IPPB0[0x139]=0
IPPB_FLP_L_4_TRAP_TCP_SN_FLAGS_ZERO.IPPB0[0x134]=0
IPPB_FLP_L_4_TRAP_TCP_SN_ZERO_FLAGS.IPPB0[0x135]=0
IPPB_FLP_L_4_TRAP_TCP_SYN_FIN.IPPB0[0x136]=0
IPPB_FLP_L_4_TRAP_UDP_EQUAL_PORTS.IPPB0[0x13a]=0
IPPB_FLP_VLAN_EDIT_PCP_DEI_MAP_CFG.IPPB0[0x133]=0
IPPB_GENERAL_CONFIG.IPPB0[0x700]=0
IPPB_GTIMER_CONFIGURATION.IPPB0[0x89]=0
IPPB_GTIMER_CYCLE.IPPB0[0x88]=0x3b9aca00
IPPB_ICMP_NDP_NEIGHBOR_SOLICITATION_TYPE.IPPB0[0x213]=0x87
IPPB_ICMP_TRAP_CFG.IPPB0[0x164]=7
IPPB_IDENTIFICATION_APPDB.IPPB0[0x1b1]=0x40
IPPB_IEEE_1588_HEADER_OFFSET_ERROR_ACTION_PROFILE.IPPB0[0x21c]=0
IPPB_INDIRECT_COMMAND.IPPB0[0x80]=0x3fff0000
IPPB_INDIRECT_COMMAND_ADDRESS.IPPB0[0x81]=0x82720007
IPPB_INDIRECT_COMMAND_RD_DATA.IPPB0[0x60]=0x38ebf
IPPB_INDIRECT_COMMAND_WIDE_MEM.IPPB0[0x41]=0
IPPB_INDIRECT_COMMAND_WR_DATA.IPPB0[0x20]=0
IPPB_INDIRECT_FORCE_BUBBLE.IPPB0[0x83]=0x20019
IPPB_INDIRECT_WR_MASK.IPPB0[0x40]=0xff
IPPB_INGRESS_TRAP_PROFILE_SELECTOR_CFG.IPPB0[0x203]=0
IPPB_INTERRUPT_MASK_REGISTER.IPPB0[0x10]=0
IPPB_INTERRUPT_REGISTER.IPPB0[0x0]=0
IPPB_INTERRUPT_REGISTER_TEST.IPPB0[0x18]=0
IPPB_IPPB_SAMPLE_VALIDS.IPPB0[0x600]=0x7b0250f3943
IPPB_IPV4_ACTION_PROFILES_CFG.IPPB0[0x111]=0x183060c183060c
IPPB_IPV6_ACTION_PROFILES_0_CFG.IPPB0[0x113]=0x300000000000
IPPB_IPV6_ACTION_PROFILES_1_CFG.IPPB0[0x116]=0
IPPB_IS_8021_X_2_VAL.IPPB0[0x146]=0
IPPB_IS_ARP_VAL.IPPB0[0x147]=0x40
IPPB_IS_ETHERNET_VAL.IPPB0[0x13f]=2
IPPB_IS_ICMPV6_VAL.IPPB0[0x144]=0x8000
IPPB_IS_ICMP_VAL.IPPB0[0x143]=0x8000
IPPB_IS_IGMP_VAL.IPPB0[0x145]=0x400000
IPPB_IS_IPV4_VAL.IPPB0[0x140]=4
IPPB_IS_IPV6_VAL.IPPB0[0x141]=8
IPPB_IS_LARGE_EM.IPPB0[0x703]=0x1000c
IPPB_IS_LAYER_PROTOCOL_BFD_M_HOP_VAL.IPPB0[0x13e]=0x800
IPPB_IS_LAYER_PROTOCOL_BFD_ONE_HOP_VAL.IPPB0[0x13d]=0x400
IPPB_IS_LM_PACKET.IPPB0[0x21e]=2
IPPB_IS_MPLS_VAL.IPPB0[0x142]=0x8000010
IPPB_IS_UDP_VAL.IPPB0[0x13c]=0x200
IPPB_LARGE_EM_LEARN_FILTER_PROPERTIES.IPPB0[0x70f]=0x6461
IPPB_LAYER_PLUS_ONE_STATISTICS_META_DATA_INFORMATION_MAP.IPPB0[0x1d8]=0
IPPB_LAYER_PLUS_ONE_STATISTICS_META_DATA_INSTRUCTION_MAP.IPPB0[0x1d2]=0
IPPB_LB_CLIENTS_CRC_32_BITS_SELECTION_BITMAP(0).IPPB0[0x128]=0
IPPB_LB_CLIENTS_CRC_32_BITS_SELECTION_BITMAP(1).IPPB0[0x129]=0
IPPB_LB_CLIENTS_CRC_32_BITS_SELECTION_BITMAP(2).IPPB0[0x12a]=0
IPPB_LB_CLIENTS_CRC_32_BITS_SELECTION_BITMAP(3).IPPB0[0x12b]=0
IPPB_LB_CLIENTS_CRC_32_BITS_SELECTION_BITMAP(4).IPPB0[0x12c]=0
IPPB_LEARNING_CFG.IPPB0[0x10f]=1
IPPB_LEL_BURST_FIFO_PROPERTIES.IPPB0[0x705]=1
IPPB_LEL_CONTROL_FIFO_PROPERTIES.IPPB0[0x707]=5
IPPB_LEL_ENTRY_FORMAT_INDEX_TO_VMV.IPPB0[0x710]=0x18818
IPPB_LEL_ERR_DATA.IPPB0[0x711]=0
IPPB_LEL_INTERRUPT_MASK_REGISTER_ONE.IPPB0[0x12]=0
IPPB_LEL_INTERRUPT_REGISTER_ONE.IPPB0[0x2]=0
IPPB_LEL_INTERRUPT_REGISTER_ONE_TEST.IPPB0[0x1a]=0
IPPB_LEL_USE_INSERT_CMD.IPPB0[0x716]=1
IPPB_LEL_VMV_SHIFT_VALUE_MAP.IPPB0[0x709]=0x9249249249249249246db6db6db6db6db6db0000006db6db
IPPB_L_3_PROTOCOL_L_4_VALUES.IPPB0[0x21d]=0x1106
IPPB_MPLS_CRC_16_SEED.IPPB0[0x12d]=0
IPPB_MPLS_CRC_32_FUNCTIONS_SELECTION_CFG.IPPB0[0x123]=0
IPPB_MPLS_LABEL_CRC_32_SEEDS.IPPB0[0x218]=0
IPPB_MPLS_LAYER_IDENTIFICATION_BITMAP_CFG.IPPB0[0x122]=0x8000010
IPPB_MPLS_RESERVED_LABEL_TYPES.IPPB0[0x131]=0xffffffff00000000
IPPB_MY_BFD_DIP_DESTINATION.IPPB0[0x13b]=0
IPPB_MY_NDP_IP_1.IPPB0[0x20b]=0
IPPB_MY_NDP_IP_2.IPPB0[0x20f]=0
IPPB_OAM_BFD_MISCONFIG.IPPB0[0x10a]=0
IPPB_OAM_BFD_YOUR_DISCR_TO_LIF_CFG.IPPB0[0x107]=0x2fffff0000000
IPPB_OAM_COUNTER_IN_RANGE_CFG_0.IPPB0[0x904]=0
IPPB_OAM_COUNTER_IN_RANGE_CFG_1.IPPB0[0x905]=0
IPPB_OAM_COUNTER_IN_RANGE_CFG_2.IPPB0[0x906]=0
IPPB_OAM_COUNTER_NOT_IN_RANGE_CFG_0.IPPB0[0x907]=0x400000
IPPB_OAM_COUNTER_NOT_IN_RANGE_CFG_1.IPPB0[0x908]=0x400000
IPPB_OAM_COUNTER_NOT_IN_RANGE_CFG_2.IPPB0[0x909]=0x400000
IPPB_OAM_COUNTER_RANGE.IPPB0[0x902]=0xfffff00000
IPPB_OAM_DEFAULT_ACC_MEP_PROFILES.IPPB0[0x912]=0x12
IPPB_OAM_DEFAULT_COUNTERS.IPPB0[0x90d]=0
IPPB_OAM_DEFAULT_INTERFACE.IPPB0[0x913]=0
IPPB_OAM_DEFAULT_MP_TYPE_VECTOR.IPPB0[0x910]=0
IPPB_OAM_ETHERNET_CFG.IPPB0[0x105]=0x4000
IPPB_OAM_IDENTIFICATION_ENABLE.IPPB0[0x104]=0x1ff
IPPB_OAM_ID_RIF_THRESHOLD.IPPB0[0x214]=0xfff
IPPB_OAM_IN_LIF_PROFILE_MAP.IPPB0[0x148]=0
IPPB_OAM_LIF_DB_ACCESS_PROFILE_EN_0.IPPB0[0x90a]=0
IPPB_OAM_LIF_DB_ACCESS_PROFILE_EN_1.IPPB0[0x90b]=0
IPPB_OAM_LIF_DB_ACCESS_PROFILE_EN_2.IPPB0[0x90c]=0
IPPB_OAM_LM_COUNTER_READ_IDX_SEL_MEM.IPPB0[0x915]=0x555500aaaa0000000000000000000000555500aaaa00
IPPB_OAM_PACKET_INJECTED_BITMAP.IPPB0[0x914]=0x80
IPPB_OAM_STATISTICS_CFG.IPPB0[0x162]=0
IPPB_OAM_VMV_SHIFT_VALUE_MAP.IPPB0[0x91d]=0x492492492492492492492492000000000000492492492492
IPPB_OUTLIF_PROFILE_CONFIGURATION.IPPB0[0x1f4]=0
IPPB_PARITY_ERR_CNT.IPPB0[0x98]=0
IPPB_PAR_ERR_MEM_MASK.IPPB0[0xa0]=0x3fffffff
IPPB_PCMI_0.IPPB0[0xb0]=0x3b9aca00
IPPB_PCMI_1.IPPB0[0xb3]=0x3b9aca00
IPPB_PCMI_2.IPPB0[0xb6]=0x3b9aca00
IPPB_PCMI_3.IPPB0[0xb9]=0x3b9aca00
IPPB_PCMI_4.IPPB0[0xbc]=0x3b9aca00
IPPB_PCMI_0_S.IPPB0[0xb1]=0
IPPB_PCMI_0_T.IPPB0[0xb2]=0
IPPB_PCMI_1_S.IPPB0[0xb4]=0
IPPB_PCMI_1_T.IPPB0[0xb5]=0
IPPB_PCMI_2_S.IPPB0[0xb7]=0
IPPB_PCMI_2_T.IPPB0[0xb8]=0
IPPB_PCMI_3_S.IPPB0[0xba]=0
IPPB_PCMI_3_T.IPPB0[0xbb]=0
IPPB_PCMI_4_S.IPPB0[0xbd]=0
IPPB_PCMI_4_T.IPPB0[0xbe]=0
IPPB_PHB_ECN_INHERITANCE_RESOLUTION_MPLS_CFG.IPPB0[0x125]=4
IPPB_PHB_TC_DP_INHERITANCE_RESOLUTION_MPLS_CFG.IPPB0[0x124]=4
IPPB_PROG_TRAP_CFG(0).IPPB0[0x165]=0
IPPB_PROG_TRAP_CFG(1).IPPB0[0x166]=0
IPPB_PROG_TRAP_CFG(2).IPPB0[0x167]=0
IPPB_PROG_TRAP_CFG(3).IPPB0[0x168]=0
IPPB_PROG_TRAP_CFG(4).IPPB0[0x169]=0
IPPB_PROG_TRAP_CFG(5).IPPB0[0x16a]=0
IPPB_PROG_TRAP_CFG(6).IPPB0[0x16b]=0
IPPB_PROG_TRAP_CFG(7).IPPB0[0x16c]=0
IPPB_REG_0300.IPPB0[0x300]=0x160400
IPPB_REG_0301.IPPB0[0x301]=0xa1f8888456c2000000000000000000005398148ed86739992cc19e5eaf9d5638a31d7aafbce2d00dbdf5068f5c792327fadf5301f06512d2cf5b46221210b49a83008a9bd4baf51e5a9bb4831c5badfd
IPPB_REG_0500.IPPB0[0x500]=0x220300
IPPB_REG_0501.IPPB0[0x501]=0x712e13c12df6000000000000000000001390a20ea155bb0c2e00d5c8e61c96dd7a87bfd7e4e26231914c599dfa17030100a0fbcaf1d2d8dd593b2cbc6a2f2ae78706ffe17423cfecdb935d8c2f34a27e
IPPB_REG_1004.IPPB0[0x1004]=0
IPPB_REG_1007.IPPB0[0x1007]=0x9f00000000
IPPB_REG_1009.IPPB0[0x1009]=0
IPPB_REG_1104.IPPB0[0x1104]=0
IPPB_REG_1107.IPPB0[0x1107]=0x7f00000000
IPPB_REG_1109.IPPB0[0x1109]=0
IPPB_REG_00C2.IPPB0[0xc2]=0x10
IPPB_REG_00C5.IPPB0[0xc5]=0x2d0
IPPB_REG_00F0.IPPB0[0xf0]=0
IPPB_RESERVED_MTCD.IPPB0[0xae]=0x30
IPPB_RESERVED_MTCP.IPPB0[0xad]=0x300000600000000
IPPB_RESERVED_SPARE_0.IPPB0[0x90]=0xffffffff
IPPB_RESERVED_SPARE_1.IPPB0[0x91]=0xffffffff
IPPB_RESERVED_SPARE_2.IPPB0[0x92]=0
IPPB_RESERVED_SPARE_3.IPPB0[0x93]=0
IPPB_RFC_6374_FLAGS.IPPB0[0x121]=0x580
IPPB_SBUS_BROADCAST_ID.IPPB0[0x86]=0x7ff
IPPB_SBUS_LAST_IN_CHAIN.IPPB0[0x87]=0
IPPB_SPECIAL_CLOCK_CONTROLS.IPPB0[0xc1]=2
IPPB_TCDP_PORT_CFG.IPPB0[0x215]=0
IPPB_TCP_ACTION_PROFILES_CFG.IPPB0[0x118]=0
IPPB_TRANSPLANT_WITH_WEAKER_STRENGTH_CFG.IPPB0[0x160]=0
IPPB_TTL_0_ACTION_PROFILE.IPPB0[0x207]=0x408d398c360c
IPPB_TTL_1_ACTION_PROFILE.IPPB0[0x209]=0x410d3a0c370c
IPPB_TTL_INHERITANCE_RESOLUTION_MPLS_CFG.IPPB0[0x127]=4
IPPB_UDP_ACTION_PROFILES_CFG.IPPB0[0x11a]=0
IPPC_ACL_CONTEXT_PROFILE_MAP.IPPC0[0x156]=0x34d30c2cb28920714e1041020820000c304104038e18000038000e
IPPC_ACTION_DISABLE.IPPC0[0x100]=0
IPPC_BIER_CFG.IPPC0[0x149]=0x30000
IPPC_CPU_TRAP_CODE_PROFILE.IPPC0[0x10b]=0
IPPC_DBG_LAST_FEM.IPPC0[0x1b2]=0x279
IPPC_DBG_LAST_FEM_NUM.IPPC0[0x1b5]=0
IPPC_DBG_LAST_FES.IPPC0[0x1ad]=0x1e44
IPPC_DBG_LAST_FES_NUM.IPPC0[0x1b1]=0
IPPC_DBG_LAST_KEY_A.IPPC0[0x17b]=0x128248120222e8379b7b00004008020
IPPC_DBG_LAST_KEY_B.IPPC0[0x180]=0x1118820011400063800102000063de26794a6d19
IPPC_DBG_LAST_KEY_C.IPPC0[0x185]=0x4000406ef494c44282dd8cd223d68d14899
IPPC_DBG_LAST_KEY_D.IPPC0[0x18a]=0x445d00043
IPPC_DBG_LAST_KEY_E.IPPC0[0x18f]=0
IPPC_DBG_LAST_KEY_F.IPPC0[0x194]=0x986000a040312b4d006384b7899e529b4640445d
IPPC_DBG_LAST_KEY_G.IPPC0[0x199]=0x940020002000003426806ec18282deb49818364
IPPC_DBG_LAST_KEY_H.IPPC0[0x19e]=0
IPPC_DBG_LAST_KEY_I.IPPC0[0x1a3]=0
IPPC_DBG_LAST_KEY_J.IPPC0[0x1a8]=0
IPPC_DEFAULT_EXEM_ACTION.IPPC0[0x13d]=0
IPPC_DEFAULT_MAPS_ACTION.IPPC0[0x139]=0
IPPC_DEFAULT_TCAM_ACTION.IPPC0[0x137]=0
IPPC_ECC_1B_ERR_CNT.IPPC0[0x94]=0
IPPC_ECC_2B_ERR_CNT.IPPC0[0x96]=0
IPPC_ECC_ERR_1B_MONITOR_MEM_MASK.IPPC0[0x9a]=0x3ffffffffffffff
IPPC_ECC_ERR_2B_MONITOR_MEM_MASK.IPPC0[0x9c]=0x3ffffffffffffff
IPPC_ECC_INTERRUPT_REGISTER.IPPC0[0x7]=0
IPPC_ECC_INTERRUPT_REGISTER_MASK.IPPC0[0x17]=0
IPPC_ECC_INTERRUPT_REGISTER_TEST.IPPC0[0x1f]=0
IPPC_EGRESS_PARSING_INDEX.IPPC0[0x147]=0x20000000c
IPPC_ELEPHANT_LEARN.IPPC0[0x1b6]=0
IPPC_ENABLE_DYNAMIC_MEMORY_ACCESS.IPPC0[0x84]=0x3f
IPPC_EVENTOR_FIFO_CFG.IPPC0[0x176]=0x3f4900000000000000000000000000000000
IPPC_FWD_CONTEXT_PROFILE_MAP.IPPC0[0x14c]=0x6b58c5ad4941cae210821080018c21081ce300007000e
IPPC_GTIMER_CONFIGURATION.IPPC0[0x89]=0
IPPC_GTIMER_CYCLE.IPPC0[0x88]=0x3b9aca00
IPPC_INDIRECT_COMMAND.IPPC0[0x80]=0x3fff0000
IPPC_INDIRECT_COMMAND_ADDRESS.IPPC0[0x81]=0x809e0020
IPPC_INDIRECT_COMMAND_RD_DATA.IPPC0[0x60]=0x6c400020
IPPC_INDIRECT_COMMAND_WIDE_MEM.IPPC0[0x41]=0
IPPC_INDIRECT_COMMAND_WR_DATA.IPPC0[0x20]=0
IPPC_INDIRECT_FORCE_BUBBLE.IPPC0[0x83]=0x20019
IPPC_INDIRECT_WR_MASK.IPPC0[0x40]=0xff
IPPC_INTERRUPT_MASK_REGISTER.IPPC0[0x10]=0
IPPC_INTERRUPT_REGISTER.IPPC0[0x0]=0
IPPC_INTERRUPT_REGISTER_TEST.IPPC0[0x18]=0
IPPC_IPPC_SAMPLE_VALIDS.IPPC0[0x700]=0x1f
IPPC_MAP_1ST_CONTEXT_PROFILE.IPPC0[0x157]=0x20000000000000000000000000000000000000000000000000000000000000
IPPC_MDB_INTERFACES_MUX.IPPC0[0x175]=0
IPPC_OUT_LIF_RANGE(0).IPPC0[0x104]=1
IPPC_OUT_LIF_RANGE(1).IPPC0[0x106]=1
IPPC_OUT_LIF_RANGE(2).IPPC0[0x108]=1
IPPC_PACKET_HEADER_SIZE_RANGE(0).IPPC0[0x13f]=1
IPPC_PACKET_HEADER_SIZE_RANGE(1).IPPC0[0x140]=1
IPPC_PACKET_HEADER_SIZE_RANGE(2).IPPC0[0x141]=1
IPPC_PARITY_ERR_CNT.IPPC0[0x98]=0
IPPC_PAR_ERR_MEM_MASK.IPPC0[0xa0]=3
IPPC_PCMI_0.IPPC0[0xb0]=0x3b9aca00
IPPC_PCMI_1.IPPC0[0xb3]=0x3b9aca00
IPPC_PCMI_2.IPPC0[0xb6]=0x3b9aca00
IPPC_PCMI_3.IPPC0[0xb9]=0x3b9aca00
IPPC_PCMI_4.IPPC0[0xbc]=0x3b9aca00
IPPC_PCMI_0_S.IPPC0[0xb1]=0
IPPC_PCMI_0_T.IPPC0[0xb2]=0
IPPC_PCMI_1_S.IPPC0[0xb4]=0
IPPC_PCMI_1_T.IPPC0[0xb5]=0
IPPC_PCMI_2_S.IPPC0[0xb7]=0
IPPC_PCMI_2_T.IPPC0[0xb8]=0
IPPC_PCMI_3_S.IPPC0[0xba]=0
IPPC_PCMI_3_T.IPPC0[0xbb]=0
IPPC_PCMI_4_S.IPPC0[0xbd]=0
IPPC_PCMI_4_T.IPPC0[0xbe]=0
IPPC_PER_CONTEXT_LOOKUP_VALID_PASS_1.IPPC0[0x11b]=0x1000001130000000ff0000fff0000
IPPC_PER_CONTEXT_LOOKUP_VALID_PASS_2.IPPC0[0x129]=0x18700000000000000000000000000000000000000000000000000000000000000000000330000bb30000
IPPC_PMFACSA_TCAM_ECC_FIX_EN.IPPC0[0x502]=0
IPPC_PMFACSA_TCAM_PROTECTION_ERROR.IPPC0[0x504]=0
IPPC_PMFACSA_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPC0[0x500]=0xff
IPPC_PMFACSA_TCAM_RESET_BLOCK.IPPC0[0x503]=0
IPPC_PMFACSB_TCAM_ECC_FIX_EN.IPPC0[0x602]=0
IPPC_PMFACSB_TCAM_PROTECTION_ERROR.IPPC0[0x604]=0
IPPC_PMFACSB_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPC0[0x600]=0xff
IPPC_PMFACSB_TCAM_RESET_BLOCK.IPPC0[0x603]=0
IPPC_PMF_GENERAL.IPPC0[0x10a]=0xfc900
IPPC_PMF_PRTOCOL_IS_ETH.IPPC0[0x145]=2
IPPC_PMF_PRTOCOL_IS_L_4.IPPC0[0x144]=0x300
IPPC_PMF_STATE_TABLE_CFG.IPPC0[0x14b]=0
IPPC_PMF_STATISTIC_10_MAP.IPPC0[0x146]=0x924688
IPPC_REG_0330.IPPC0[0x330]=0
IPPC_REG_0331.IPPC0[0x331]=0x18004ca092004800000f000020040c0020f04c0004080044600000000000000000000000000000000038000000000000000000000000000000000000001e00003a080000260200001201000c00
IPPC_REG_0505.IPPC0[0x505]=0
IPPC_REG_0508.IPPC0[0x508]=0xbd00000000
IPPC_REG_0605.IPPC0[0x605]=0
IPPC_REG_0608.IPPC0[0x608]=0x7f00000000
IPPC_REG_00C2.IPPC0[0xc2]=0x10
IPPC_REG_00F0.IPPC0[0xf0]=0
IPPC_REG_050A.IPPC0[0x50a]=0
IPPC_REG_060A.IPPC0[0x60a]=0
IPPC_RESERVED_MTCD.IPPC0[0xae]=0x30
IPPC_RESERVED_MTCP.IPPC0[0xad]=0x300000600000000
IPPC_RESERVED_SPARE_0.IPPC0[0x90]=0xffffffff
IPPC_RESERVED_SPARE_1.IPPC0[0x91]=0xffffffff
IPPC_RESERVED_SPARE_2.IPPC0[0x92]=0
IPPC_RESERVED_SPARE_3.IPPC0[0x93]=0
IPPC_SBUS_BROADCAST_ID.IPPC0[0x86]=0x7ff
IPPC_SBUS_LAST_IN_CHAIN.IPPC0[0x87]=0
IPPC_SPECIAL_CLOCK_CONTROLS.IPPC0[0xc1]=2
IPPC_TRJ_CFG.IPPC0[0x161]=0
IPPC_VID_VALID.IPPC0[0x142]=0
IPPC_VMV_SHIFT_VALUE_MAP(0).IPPC0[0x1b8]=0x2db6d00000002db6d00000002db6d00000002db6d02d
IPPC_VMV_SHIFT_VALUE_MAP(1).IPPC0[0x1b9]=0x924924924000924924924000924924924000924924924924
IPPD_ACL_CONTEXT_PROFILE_MAP.IPPD0[0x123]=0xffef7cefae78df6d74cf2c70beeb6caeaa689e69648e28607de75c6da6585d65544d24503ce34c2ca2481c61440c2040
IPPD_ACTION_DISABLE.IPPD0[0x100]=0
IPPD_ADDITIONAL_INFO_TO_UNKNOWN_ADDRESS_MAP.IPPD0[0x307]=0xaaaa
IPPD_ALLOW_DEFAULT_ROUTE.IPPD0[0x1f2]=0
IPPD_APP_PREFIX_CONTROL.IPPD0[0x512]=0
IPPD_BAD_REPLIES_COUNTER.IPPD0[0x504]=0
IPPD_BUILD_OAM_TS_HEADER.IPPD0[0x30c]=0x2ffe
IPPD_COUNTER_PROFILE_MAP(0).IPPD0[0x139]=0
IPPD_COUNTER_PROFILE_MAP(1).IPPD0[0x13a]=0
IPPD_COUNTER_PROFILE_MAP(2).IPPD0[0x13b]=0
IPPD_CPU_INFO_REPLY_COUNTER.IPPD0[0x555]=0
IPPD_CPU_INFO_REPLY_ERROR_COUNTER.IPPD0[0x556]=0
IPPD_CPU_INFO_REPLY_OVF_COUNTER.IPPD0[0x557]=0
IPPD_CPU_LOOKUP_REPLY_COUNTER.IPPD0[0x552]=0
IPPD_CPU_LOOKUP_REPLY_ERROR_COUNTER.IPPD0[0x553]=0
IPPD_CPU_LOOKUP_REPLY_OVF_COUNTER.IPPD0[0x554]=0
IPPD_CPU_RECORDS_COUNTER.IPPD0[0x551]=0
IPPD_CPU_RECORD_CONTROL.IPPD0[0x51c]=4
IPPD_CPU_RECORD_DATA_LSB.IPPD0[0x51d]=0xbffd7fffbbfd7fffdfbf8f77ffdeb5fdffee4afff7bfffff77fefeffefff5f7bfb6dfffffffdffefbeefffb6ffffbd5ffffff7f5dbffffffbf7f1ffcf9fff8bd
IPPD_CPU_RECORD_DATA_MSB.IPPD0[0x52d]=0xffffdfffffffffdffffffdfefff7fdbffff9bffdffffffdffffffffff7efeff7effbd77ff79ef5fff6dffffedf3dbbfdfbf7fff7febf6bcdbf7ffd7ffaf7ffa7
IPPD_CPU_RECORD_OPCODE.IPPD0[0x53d]=0
IPPD_CPU_TRAP_CODE_PROFILE.IPPD0[0x113]=0
IPPD_DBG_LAST_FES.IPPD0[0x155]=0x1fc0
IPPD_DBG_LAST_FES_NUM.IPPD0[0x159]=0
IPPD_DBG_LAST_KEY_A.IPPD0[0x146]=0
IPPD_DBG_LAST_KEY_B.IPPD0[0x14b]=0
IPPD_DBG_LAST_KEY_C.IPPD0[0x150]=0xffe6bcdffdfeadafd7ff
IPPD_DBG_LAST_RESOLVED_TRAP.IPPD0[0x20d]=0x21012a3
IPPD_DBG_LAST_TRAP_CHANGE_DESTINATION_REG.IPPD0[0x20e]=9
IPPD_DEFAULT_EXEM_PAYLOAD.IPPD0[0x13f]=0
IPPD_DEFAULT_MAPS_PAYLOAD.IPPD0[0x141]=0
IPPD_DEFAULT_TCAM_ACTION.IPPD0[0x137]=0
IPPD_ECC_1B_ERR_CNT.IPPD0[0x94]=0
IPPD_ECC_2B_ERR_CNT.IPPD0[0x96]=0
IPPD_ECC_ERR_1B_MONITOR_MEM_MASK.IPPD0[0x9a]=0x3ffffffffffffffffffffffffffffff
IPPD_ECC_ERR_2B_MONITOR_MEM_MASK.IPPD0[0x9c]=0x3ffffffffffffffffffffffffffffff
IPPD_ECC_INTERRUPT_REGISTER.IPPD0[0x7]=0
IPPD_ECC_INTERRUPT_REGISTER_MASK.IPPD0[0x17]=0
IPPD_ECC_INTERRUPT_REGISTER_TEST.IPPD0[0x1f]=0
IPPD_ECMP_STAGE_BASE.IPPD0[0x20f]=0
IPPD_ENABLE_DYNAMIC_MEMORY_ACCESS.IPPD0[0x84]=0xf
IPPD_FER_POINTER_CONSRUCTION.IPPD0[0x1c0]=0x18000000180000000000000000000000037fffe1e0000000001
IPPD_FER_TRAP_CFG(0).IPPD0[0x1f3]=0xc5
IPPD_FER_TRAP_CFG(1).IPPD0[0x1f4]=0x8c3
IPPD_FER_TRAP_CFG(2).IPPD0[0x1f5]=0x8c4
IPPD_FER_TRAP_CFG(3).IPPD0[0x1f6]=0x8a6
IPPD_FER_TRAP_CFG(4).IPPD0[0x1f7]=0x8c2
IPPD_FER_TRAP_CFG(5).IPPD0[0x1f8]=0
IPPD_FER_TRAP_CFG(6).IPPD0[0x1f9]=0xc0
IPPD_FER_TRAP_CFG(7).IPPD0[0x1fa]=0xbf
IPPD_GENERAL_CFGS.IPPD0[0x51b]=0
IPPD_GOOD_REPLIES_COUNTER.IPPD0[0x503]=0
IPPD_GTIMER_CONFIGURATION.IPPD0[0x89]=0
IPPD_GTIMER_CYCLE.IPPD0[0x88]=0x3b9aca00
IPPD_INDIRECT_COMMAND.IPPD0[0x80]=0x3fff0000
IPPD_INDIRECT_COMMAND_ADDRESS.IPPD0[0x81]=0x810a0004
IPPD_INDIRECT_COMMAND_RD_DATA.IPPD0[0x60]=0
IPPD_INDIRECT_COMMAND_WIDE_MEM.IPPD0[0x41]=0
IPPD_INDIRECT_COMMAND_WR_DATA.IPPD0[0x20]=0
IPPD_INDIRECT_FORCE_BUBBLE.IPPD0[0x83]=0x20019
IPPD_INDIRECT_WR_MASK.IPPD0[0x40]=0xffffffff
IPPD_INFO_REPLY.IPPD0[0x548]=0
IPPD_INTERLAKEN_CFGS.IPPD0[0x50a]=0
IPPD_INTERRUPT_MASK_REGISTER.IPPD0[0x10]=0
IPPD_INTERRUPT_REGISTER.IPPD0[0x0]=0x2000000
IPPD_INTERRUPT_REGISTER_TEST.IPPD0[0x18]=0
IPPD_INVALID_DESTINATION.IPPD0[0x30d]=0x6ffffe
IPPD_IN_LIF_ORIENTATION_MAP.IPPD0[0x33e]=0
IPPD_IPPD_SAMPLE_VALIDS.IPPD0[0x800]=0x3a001
IPPD_IS_ETHERNET.IPPD0[0x339]=2
IPPD_IS_IP.IPPD0[0x338]=0xc
IPPD_IS_TYPE_IPV6.IPPD0[0x210]=0
IPPD_ITPP_TERMINATE_NETWORK_HEADERS.IPPD0[0x308]=0x7f7f7f7f7f7f7f7f7f7f7f7f7f7f7f7f
IPPD_JR_2_TO_JR_IN_LIF_PROFILE_MAP.IPPD0[0x328]=0
IPPD_LAST_ERROR_SEQUENCE_RX.IPPD0[0x502]=0
IPPD_LBP_GENERAL_CONFIG_0.IPPD0[0x300]=0
IPPD_LBP_GENERAL_CONFIG_1.IPPD0[0x301]=0x8b8
IPPD_LBP_GENERAL_CONFIG_3.IPPD0[0x302]=0x3e6ffffe00001f57ffff
IPPD_LBP_HEADER_CONFIG.IPPD0[0x306]=0x1f6b4a26
IPPD_LBP_TIME_STAMP_FIFO_CONFIG.IPPD0[0x355]=0xef13bc402c
IPPD_LEARN_PAYLOAD_STRENGTH_SIZE.IPPD0[0x357]=0
IPPD_LOOKUPS_COUNTER.IPPD0[0x505]=0
IPPD_LOOKUP_REPLY.IPPD0[0x53e]=0x7b78bb3d5effe953bdebffd3756deffd9ebf75e3c7befdff1fbf97d5fb2fb177fdfcef36e
IPPD_MUX_EXEM_INTERFACE.IPPD0[0x145]=0
IPPD_NIF_PHYSICAL_ERR_COUNTER.IPPD0[0x506]=0
IPPD_OAM_SUB_TYPE_MAP.IPPD0[0x326]=0x30090
IPPD_OUTLIF_OVERLOAD.IPPD0[0x20c]=0
IPPD_OUT_LIF_RANGE(0).IPPD0[0x104]=1
IPPD_OUT_LIF_RANGE(1).IPPD0[0x106]=1
IPPD_OUT_LIF_RANGE(2).IPPD0[0x108]=1
IPPD_OUT_LIF_RANGE(3).IPPD0[0x10a]=1
IPPD_OUT_LIF_RANGE(4).IPPD0[0x10c]=1
IPPD_OUT_LIF_RANGE(5).IPPD0[0x10e]=1
IPPD_OUT_LIF_RANGE(6).IPPD0[0x110]=1
IPPD_OUT_RIF_RANGE.IPPD0[0x34e]=0
IPPD_PACKET_SIZE.IPPD0[0x50c]=0x800100
IPPD_PARITY_ERR_CNT.IPPD0[0x98]=0
IPPD_PAR_ERR_MEM_MASK.IPPD0[0xa0]=0x1f
IPPD_PCMI_0.IPPD0[0xb0]=0x3b9aca00
IPPD_PCMI_1.IPPD0[0xb3]=0x3b9aca00
IPPD_PCMI_2.IPPD0[0xb6]=0x3b9aca00
IPPD_PCMI_3.IPPD0[0xb9]=0x3b9aca00
IPPD_PCMI_4.IPPD0[0xbc]=0x3b9aca00
IPPD_PCMI_0_S.IPPD0[0xb1]=0
IPPD_PCMI_0_T.IPPD0[0xb2]=0
IPPD_PCMI_1_S.IPPD0[0xb4]=0
IPPD_PCMI_1_T.IPPD0[0xb5]=0
IPPD_PCMI_2_S.IPPD0[0xb7]=0
IPPD_PCMI_2_T.IPPD0[0xb8]=0
IPPD_PCMI_3_S.IPPD0[0xba]=0
IPPD_PCMI_3_T.IPPD0[0xbb]=0
IPPD_PCMI_4_S.IPPD0[0xbd]=0
IPPD_PCMI_4_T.IPPD0[0xbe]=0
IPPD_PER_CONTEXT_LOOKUP_VALID.IPPD0[0x12f]=0
IPPD_PHY_CHANNEL_CFGS.IPPD0[0x50b]=0
IPPD_PMFBCS_TCAM_ECC_FIX_EN.IPPD0[0x702]=0
IPPD_PMFBCS_TCAM_PROTECTION_ERROR.IPPD0[0x704]=0
IPPD_PMFBCS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPD0[0x700]=0xff
IPPD_PMFBCS_TCAM_RESET_BLOCK.IPPD0[0x703]=0
IPPD_PMF_GENERAL.IPPD0[0x112]=0x500
IPPD_PPH_FHEI_FWD_SIZE.IPPD0[0x316]=0
IPPD_PPH_FHEI_IVE_SIZE.IPPD0[0x30e]=0xaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
IPPD_PPH_VSI_SOURCE.IPPD0[0x34f]=0
IPPD_RECEIVE_FIFO_STATUS.IPPD0[0x510]=0
IPPD_REG_0400.IPPD0[0x400]=0
IPPD_REG_0401.IPPD0[0x401]=0x10020a8e1ce5f00000018004ca092004800000f000020040c00040000000000000000000000000000000038000000800000000000000000000000000000001e00003a080000260200001201000c00
IPPD_REG_0705.IPPD0[0x705]=0
IPPD_REG_0708.IPPD0[0x708]=0xff00000000
IPPD_REG_00C2.IPPD0[0xc2]=0x10
IPPD_REG_00C5.IPPD0[0xc5]=0x2d6
IPPD_REG_00C6.IPPD0[0xc6]=0x53
IPPD_REG_00F0.IPPD0[0xf0]=0
IPPD_REG_070A.IPPD0[0x70a]=0
IPPD_RESERVED_MIRROR_ADDR.IPPD0[0x85]=0
IPPD_RESERVED_MTCD.IPPD0[0xae]=0x30
IPPD_RESERVED_MTCP.IPPD0[0xad]=0x300000600000000
IPPD_RESERVED_SPARE_0.IPPD0[0x90]=0xffffffff
IPPD_RESERVED_SPARE_1.IPPD0[0x91]=0xffffffff
IPPD_RESERVED_SPARE_2.IPPD0[0x92]=0
IPPD_RESERVED_SPARE_3.IPPD0[0x93]=0
IPPD_RESOLUTION_CFG.IPPD0[0x1c7]=0xffffbffff00000000
IPPD_RESOLUTION_FACILITY_PROTECTION_LOGIC.IPPD0[0x1cc]=0xaa2aaa2a00000000ffff0000f000f000ea2aea2a00000000ffff0000000000002a2a2a2a00000000ffff0000f000f000aa2aaa2a00000000ffff0000
IPPD_RESOLUTION_FACILITY_TRAP_LOGIC.IPPD0[0x1dc]=0xf000f000c000c0000000000000000000
IPPD_SBUS_BROADCAST_ID.IPPD0[0x86]=0x7ff
IPPD_SBUS_LAST_IN_CHAIN.IPPD0[0x87]=0
IPPD_SEQUENCE_EXPECTED.IPPD0[0x501]=0
IPPD_SEQUENCE_TX.IPPD0[0x500]=0
IPPD_SLB_PER_CONTEXT_ENABLE.IPPD0[0x1ec]=0
IPPD_SPECIAL_CLOCK_CONTROLS.IPPD0[0xc1]=2
IPPD_SPR_CFGS.IPPD0[0x509]=0
IPPD_SPR_DLY_CFGS.IPPD0[0x507]=0x1ff0a0000
IPPD_STATISTIC_PROFILE_MAP.IPPD0[0x1ee]=0xaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
IPPD_TOD_LAST_VALUE.IPPD0[0x33a]=0x62d6d7a1192d21f6e6815621ba88ff19
IPPD_TRANSMIT_CFGS.IPPD0[0x50d]=0x415ea
IPPD_TRANSMIT_FIFO_STATUS.IPPD0[0x50e]=0
IPPD_TX_APP_PREFIX.IPPD0[0x513]=0
IPPD_UDH_TYPE_TO_SIZE_MAP.IPPD0[0x327]=0x920
IPPD_VMV_SHIFT_VALUE_MAP.IPPD0[0x15a]=0x924924924000924924924000924924924000924924924924
IPPD_XOR_INIT_DONE_REG.IPPD0[0x20b]=1
IPPD_XOR_INIT_DONE_TABLE(0).IPPD0[0x1fb]=1
IPPD_XOR_INIT_DONE_TABLE(1).IPPD0[0x1fc]=1
IPPD_XOR_INIT_DONE_TABLE(2).IPPD0[0x1fd]=1
IPPD_XOR_INIT_DONE_TABLE(3).IPPD0[0x1fe]=1
IPPD_XOR_INIT_DONE_TABLE(4).IPPD0[0x1ff]=1
IPPD_XOR_INIT_DONE_TABLE(5).IPPD0[0x200]=1
IPPD_XOR_INIT_DONE_TABLE(6).IPPD0[0x201]=1
IPPD_XOR_INIT_DONE_TABLE(7).IPPD0[0x202]=1
IPPD_XOR_INIT_DONE_TABLE(8).IPPD0[0x203]=1
IPPD_XOR_INIT_DONE_TABLE(9).IPPD0[0x204]=1
IPPD_XOR_INIT_DONE_TABLE(10).IPPD0[0x205]=1
IPPD_XOR_INIT_DONE_TABLE(11).IPPD0[0x206]=1
IPPD_XOR_INIT_DONE_TABLE(12).IPPD0[0x207]=1
IPPD_XOR_INIT_DONE_TABLE(13).IPPD0[0x208]=1
IPPD_XOR_INIT_DONE_TABLE(14).IPPD0[0x209]=1
IPPD_XOR_INIT_DONE_TABLE(15).IPPD0[0x20a]=1
IPPE_ACTION_PROFILE_ACCEPTABLE_FRAME_TYPES.IPPE0[0x12e]=0
IPPE_APP_INJECTTION.IPPE0[0x400]=0
IPPE_DBG_LLR_TRAP_0.IPPE0[0x12f]=9
IPPE_DEBUG_SELECT.IPPE0[0x114]=0
IPPE_ECC_1B_ERR_CNT.IPPE0[0x94]=0
IPPE_ECC_2B_ERR_CNT.IPPE0[0x96]=0
IPPE_ECC_ERR_1B_MONITOR_MEM_MASK.IPPE0[0x9a]=0x3ffffffffff
IPPE_ECC_ERR_2B_MONITOR_MEM_MASK.IPPE0[0x9c]=0x3ffffffffff
IPPE_ECC_INTERRUPT_REGISTER.IPPE0[0x7]=0
IPPE_ECC_INTERRUPT_REGISTER_MASK.IPPE0[0x17]=0
IPPE_ECC_INTERRUPT_REGISTER_TEST.IPPE0[0x1f]=0
IPPE_ENABLE_DYNAMIC_MEMORY_ACCESS.IPPE0[0x84]=0xf
IPPE_EXTEND_VCP_EN.IPPE0[0x147]=0
IPPE_FILTERING_ACTION_PROFILES.IPPE0[0x12d]=0x60c
IPPE_GTIMER_CONFIGURATION.IPPE0[0x89]=0
IPPE_GTIMER_CYCLE.IPPE0[0x88]=0x3b9aca00
IPPE_INDIRECT_COMMAND.IPPE0[0x80]=0x3fff0000
IPPE_INDIRECT_COMMAND_ADDRESS.IPPE0[0x81]=0x80550020
IPPE_INDIRECT_COMMAND_RD_DATA.IPPE0[0x60]=1
IPPE_INDIRECT_COMMAND_WIDE_MEM.IPPE0[0x41]=0
IPPE_INDIRECT_COMMAND_WR_DATA.IPPE0[0x20]=0
IPPE_INDIRECT_FORCE_BUBBLE.IPPE0[0x83]=0x20019
IPPE_INDIRECT_WR_MASK.IPPE0[0x40]=0xff
IPPE_INTERRUPT_MASK_REGISTER.IPPE0[0x10]=0
IPPE_INTERRUPT_REGISTER.IPPE0[0x0]=0x1f08
IPPE_INTERRUPT_REGISTER_TEST.IPPE0[0x18]=0
IPPE_IPPE_SAMPLE_VALIDS.IPPE0[0x500]=0xf
IPPE_IPP_ENABLERS.IPPE0[0x120]=0xff
IPPE_IRE_VISIBILITY_BIT.IPPE0[0x801]=1
IPPE_LLRCS_TCAM_ECC_FIX_EN.IPPE0[0xa02]=0
IPPE_LLRCS_TCAM_PROTECTION_ERROR.IPPE0[0xa04]=0
IPPE_LLRCS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPE0[0xa00]=0xff
IPPE_LLRCS_TCAM_RESET_BLOCK.IPPE0[0xa03]=0
IPPE_LL_MIRROR_VID_01.IPPE0[0x12a]=0
IPPE_LL_MIRROR_VID_23.IPPE0[0x12b]=0
IPPE_LL_MIRROR_VID_45.IPPE0[0x12c]=0
IPPE_MIRROR_PROFILE_MAPPING.IPPE0[0x142]=0xf7fbbdbecf5fabd3e8f3f9bcbe4f1f8bc3e0
IPPE_PARITY_ERR_CNT.IPPE0[0x98]=0
IPPE_PAR_ERR_MEM_MASK.IPPE0[0xa0]=1
IPPE_PCMI_0.IPPE0[0xb0]=0x3b9aca00
IPPE_PCMI_1.IPPE0[0xb3]=0x3b9aca00
IPPE_PCMI_2.IPPE0[0xb6]=0x3b9aca00
IPPE_PCMI_3.IPPE0[0xb9]=0x3b9aca00
IPPE_PCMI_4.IPPE0[0xbc]=0x3b9aca00
IPPE_PCMI_0_S.IPPE0[0xb1]=0
IPPE_PCMI_0_T.IPPE0[0xb2]=0
IPPE_PCMI_1_S.IPPE0[0xb4]=0
IPPE_PCMI_1_T.IPPE0[0xb5]=0
IPPE_PCMI_2_S.IPPE0[0xb7]=0
IPPE_PCMI_2_T.IPPE0[0xb8]=0
IPPE_PCMI_3_S.IPPE0[0xba]=0
IPPE_PCMI_3_T.IPPE0[0xbb]=0
IPPE_PCMI_4_S.IPPE0[0xbd]=0
IPPE_PCMI_4_T.IPPE0[0xbe]=0
IPPE_PORT_VISIBILITY_CONFIG(0).IPPE0[0x124]=0xffffffffffffffffffffffff0000000000000000000000000000000fffffffff000000000000000000000000
IPPE_PORT_VISIBILITY_CONFIG(1).IPPE0[0x125]=0
IPPE_PORT_VISIBILITY_CONFIG(2).IPPE0[0x126]=0
IPPE_PORT_VISIBILITY_CONFIG(3).IPPE0[0x127]=0
IPPE_PRSE_CONFIG(0).IPPE0[0x105]=0x10
IPPE_PRSE_CONFIG(1).IPPE0[0x106]=0x10
IPPE_PRSE_CONFIG(2).IPPE0[0x107]=0x11
IPPE_PRSE_CONFIG(3).IPPE0[0x108]=0x12
IPPE_PRSE_CONFIG(4).IPPE0[0x109]=0x13
IPPE_PRSE_CONFIG(5).IPPE0[0x10a]=0x14
IPPE_PRSE_CONFIG(6).IPPE0[0x10b]=0x15
IPPE_PRSE_CONFIG(7).IPPE0[0x10c]=0x11
IPPE_PRSE_CONFIG(8).IPPE0[0x10d]=0x12
IPPE_PRSE_CONFIG(9).IPPE0[0x10e]=0x13
IPPE_PRSE_CONFIG(10).IPPE0[0x10f]=0x14
IPPE_PRSE_CONFIG(11).IPPE0[0x110]=0x15
IPPE_PRSE_CONFIG(12).IPPE0[0x111]=0x16
IPPE_PRSE_CONFIG(13).IPPE0[0x112]=0x17
IPPE_PRSE_CONFIG(14).IPPE0[0x113]=0x18
IPPE_PRSE_LOAD_BALANCING_SEED.IPPE0[0x600]=0
IPPE_PRTCAM_TCAM_ECC_FIX_EN.IPPE0[0x201]=0
IPPE_PRTCAM_TCAM_PROTECTION_ERROR.IPPE0[0x203]=0
IPPE_PRTCAM_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPE0[0x200]=0xff
IPPE_PRTCAM_TCAM_RESET_BLOCK.IPPE0[0x202]=0
IPPE_PRT_FIFO_CONFIG.IPPE0[0x134]=0x1805
IPPE_RECYC_FWD_PROFILE_MAPPING.IPPE0[0x130]=0xf578024012009004f877d59ea2f7000000000000000003c16000
IPPE_RECYC_MRR_PROFILE_MAPPING.IPPE0[0x13d]=0xf3f9bcbe4f1f8bc3e0
IPPE_RECYC_SNP_PROFILE_MAPPING.IPPE0[0x137]=0x66163165f65e65d65c65b630
IPPE_REG_0204.IPPE0[0x204]=0
IPPE_REG_0207.IPPE0[0x207]=0x7f00000000
IPPE_REG_0209.IPPE0[0x209]=0
IPPE_REG_0401.IPPE0[0x401]=0x1004
IPPE_REG_0402.IPPE0[0x402]=0
IPPE_REG_0403.IPPE0[0x403]=0
IPPE_REG_00C2.IPPE0[0xc2]=0x10
IPPE_REG_0A05.IPPE0[0xa05]=0
IPPE_REG_0A08.IPPE0[0xa08]=0xcd00000000
IPPE_REG_0A0A.IPPE0[0xa0a]=0
IPPE_RESERVED_MTCD.IPPE0[0xae]=0x30
IPPE_RESERVED_MTCP.IPPE0[0xad]=0x300000600000000
IPPE_RESERVED_SPARE_0.IPPE0[0x90]=0xffffffff
IPPE_RESERVED_SPARE_1.IPPE0[0x91]=0xffffffff
IPPE_RESERVED_SPARE_2.IPPE0[0x92]=0
IPPE_RESERVED_SPARE_3.IPPE0[0x93]=0
IPPE_SBUS_BROADCAST_ID.IPPE0[0x86]=0x7ff
IPPE_SBUS_LAST_IN_CHAIN.IPPE0[0x87]=0
IPPE_SPECIAL_CLOCK_CONTROLS.IPPE0[0xc1]=2
IPPE_SYNC_COUNTER_CFG.IPPE0[0x121]=0x2be8
IPPE_VISIBILITY_CONFIG.IPPE0[0x122]=0x20800000000
IPPE_VTT_FIFO_CONFIG.IPPE0[0x135]=0xe04
IPPE_XBR_CONFIG(0).IPPE0[0x100]=0
IPPE_XBR_CONFIG(1).IPPE0[0x101]=1
IPPE_XBR_CONFIG(2).IPPE0[0x102]=0
IPPE_XBR_CONFIG(3).IPPE0[0x103]=1
IPPE_XBR_CONFIG(4).IPPE0[0x104]=0
IPPF_CFG_MAP_CTX_TO_LIF_LOOKUP_ENABLE(0).IPPF0[0x239]=0x7f0ffffff
IPPF_CFG_MAP_CTX_TO_LIF_LOOKUP_ENABLE(1).IPPF0[0x23a]=0x3f93ff
IPPF_CFG_MAP_CTX_TO_LIF_LOOKUP_ENABLE(2).IPPF0[0x23b]=0x7fff31ff
IPPF_CFG_PROTOCOL_IS_ETH.IPPF0[0x20a]=0xffffffff
IPPF_CFG_PROTOCOL_IS_IPV4.IPPF0[0x207]=4
IPPF_CFG_PROTOCOL_IS_IPV6.IPPF0[0x208]=8
IPPF_CFG_PROTOCOL_IS_MAC_IN_MAC.IPPF0[0x209]=0
IPPF_CFG_PROTOCOL_IS_MPLS.IPPF0[0x20b]=0x10
IPPF_COE_CFGS.IPPF0[0x1e1]=0x2000000000000000000000fc060fc803
IPPF_CS_INLIF_PROFILE_MAP_LSB(0).IPPF0[0x20c]=0
IPPF_CS_INLIF_PROFILE_MAP_LSB(1).IPPF0[0x20d]=0
IPPF_CS_INLIF_PROFILE_MAP_LSB(2).IPPF0[0x20e]=0
IPPF_CS_INLIF_PROFILE_MAP_MSB(0).IPPF0[0x21c]=0x4440000000000000000000000000000044400000000000000000000000000000444000000000000000000000000000004440
IPPF_CS_INLIF_PROFILE_MAP_MSB(1).IPPF0[0x21d]=0x4440000000000000000000000000000044400000000000000000000000000000444000000000000000000000000000004440
IPPF_CS_INLIF_PROFILE_MAP_MSB(2).IPPF0[0x21e]=0x4440000000000000000000000000000044400000000000000000000000000000444000000000000000000000000000004440
IPPF_ECC_1B_ERR_CNT.IPPF0[0x94]=0
IPPF_ECC_2B_ERR_CNT.IPPF0[0x96]=0
IPPF_ECC_ERR_1B_MONITOR_MEM_MASK.IPPF0[0x9a]=0x7fffffffffffffff
IPPF_ECC_ERR_2B_MONITOR_MEM_MASK.IPPF0[0x9c]=0x7fffffffffffffff
IPPF_ECC_INTERRUPT_REGISTER.IPPF0[0x7]=0
IPPF_ECC_INTERRUPT_REGISTER_MASK.IPPF0[0x17]=0
IPPF_ECC_INTERRUPT_REGISTER_TEST.IPPF0[0x1f]=0
IPPF_ENABLE_DYNAMIC_MEMORY_ACCESS.IPPF0[0x84]=0x3f
IPPF_ETHERNET_TRAP.IPPF0[0x1c7]=0x18171816001518140000
IPPF_ETHERNET_TRAP_ACTION_PROFILE_VECTOR.IPPF0[0x1c1]=0x2400000000000000000000000000000000001b012249000
IPPF_ETH_PCP_TO_OAM_PCP.IPPF0[0x1a2]=0xfac688
IPPF_FWD_DOMAIN_MASKS(0).IPPF0[0x1db]=0xffffc000003fffffff00003ffff
IPPF_FWD_DOMAIN_MASKS(1).IPPF0[0x1dc]=0xffffc000003fffffff00003ffff
IPPF_FWD_DOMAIN_MASKS(2).IPPF0[0x1dd]=0xffffc000003fffffff00003ffff
IPPF_FWD_DOMAIN_MASK_PROFILE_MAP(0).IPPF0[0x1d8]=0x800050000
IPPF_FWD_DOMAIN_MASK_PROFILE_MAP(1).IPPF0[0x1d9]=0x800050000
IPPF_FWD_DOMAIN_MASK_PROFILE_MAP(2).IPPF0[0x1da]=0x800050000
IPPF_GTIMER_CONFIGURATION.IPPF0[0x89]=0
IPPF_GTIMER_CYCLE.IPPF0[0x88]=0x3b9aca00
IPPF_INDIRECT_COMMAND.IPPF0[0x80]=0x3fff0000
IPPF_INDIRECT_COMMAND_ADDRESS.IPPF0[0x81]=0x8afc0000
IPPF_INDIRECT_COMMAND_RD_DATA.IPPF0[0x60]=0
IPPF_INDIRECT_COMMAND_WIDE_MEM.IPPF0[0x41]=0
IPPF_INDIRECT_COMMAND_WR_DATA.IPPF0[0x20]=0
IPPF_INDIRECT_FORCE_BUBBLE.IPPF0[0x83]=0x20019
IPPF_INDIRECT_WR_MASK.IPPF0[0x40]=0xff
IPPF_INITIAL_PCP_DEI_MAP_TYPE.IPPF0[0x1e6]=8
IPPF_INTERRUPT_MASK_REGISTER.IPPF0[0x10]=0
IPPF_INTERRUPT_REGISTER.IPPF0[0x0]=0
IPPF_INTERRUPT_REGISTER_TEST.IPPF0[0x18]=0
IPPF_IPPF_SAMPLE_VALIDS.IPPF0[0x100]=0x1ddc00
IPPF_IP_TOS_TO_OAM_PCP_0.IPPF0[0x18a]=0
IPPF_IP_TOS_TO_OAM_PCP_1.IPPF0[0x196]=0
IPPF_LEARN_KEY_CONTEXT.IPPF0[0x1de]=0x116a4a0
IPPF_LIF_TRAPS(0).IPPF0[0x1c8]=0x16f00000
IPPF_LIF_TRAPS(1).IPPF0[0x1c9]=0x16f00000
IPPF_LIF_TRAPS(2).IPPF0[0x1ca]=0x16f00000
IPPF_MAC_IN_MAC_VSI.IPPF0[0x23d]=0
IPPF_MAP_PARSER_CTX_TO_PROTOCOL.IPPF0[0x23c]=0x128800111888208000
IPPF_MAP_PORT_TO_LEARN_LIF_VEC_LSB.IPPF0[0x1e7]=0xfffffffff60000000000004ffffffffff
IPPF_MAP_PORT_TO_LEARN_LIF_VEC_MSB.IPPF0[0x1f7]=0
IPPF_MAP_VRID_TO_IP_VERSION.IPPF0[0x1cb]=0x70
IPPF_MEF_L_2_CP_TRANSPARENT_BITMAP.IPPF0[0x182]=0
IPPF_MPLS_EXP_TO_OAM_PCP.IPPF0[0x1a3]=0xfac688
IPPF_MPLS_LABEL_PROCEDURE_CONFIG.IPPF0[0x1a4]=5
IPPF_MPLS_SPECIAL_LABEL_ATTRIBUTES.IPPF0[0x1a5]=0x1c30000000400046000000080020c0000001200618000000100007800228020000d00045004
IPPF_MY_B_MAC_LSB_BITMAP.IPPF0[0x169]=0
IPPF_MY_B_MAC_MC.IPPF0[0x166]=0x11e83
IPPF_MY_B_MAC_MSB.IPPF0[0x167]=0
IPPF_PARITY_ERR_CNT.IPPF0[0x98]=0
IPPF_PAR_ERR_MEM_MASK.IPPF0[0xa0]=0x3fffffff
IPPF_PCMI_0.IPPF0[0xb0]=0x3b9aca00
IPPF_PCMI_1.IPPF0[0xb3]=0x3b9aca00
IPPF_PCMI_2.IPPF0[0xb6]=0x3b9aca00
IPPF_PCMI_3.IPPF0[0xb9]=0x3b9aca00
IPPF_PCMI_4.IPPF0[0xbc]=0x3b9aca00
IPPF_PCMI_0_S.IPPF0[0xb1]=0
IPPF_PCMI_0_T.IPPF0[0xb2]=0
IPPF_PCMI_1_S.IPPF0[0xb4]=0
IPPF_PCMI_1_T.IPPF0[0xb5]=0
IPPF_PCMI_2_S.IPPF0[0xb7]=0
IPPF_PCMI_2_T.IPPF0[0xb8]=0
IPPF_PCMI_3_S.IPPF0[0xba]=0
IPPF_PCMI_3_T.IPPF0[0xbb]=0
IPPF_PCMI_4_S.IPPF0[0xbd]=0
IPPF_PCMI_4_T.IPPF0[0xbe]=0
IPPF_REG_0310.IPPF0[0x310]=0xd20400
IPPF_REG_0311.IPPF0[0x311]=0xfc5603c1368810f7fbdceb8c6a51d25040ba48b11b09bc05177f41d9aa4877211b406ae94fc2f5bba88c151d33831c32bc697450b29c1cf13fbeed49687d1a338bdc30d2b37e09e9c62624e1ad8fcdb6
IPPF_REG_0555.IPPF0[0x555]=0
IPPF_REG_0558.IPPF0[0x558]=0x9e00000000
IPPF_REG_0605.IPPF0[0x605]=0
IPPF_REG_0608.IPPF0[0x608]=0xb700000000
IPPF_REG_0855.IPPF0[0x855]=0
IPPF_REG_0858.IPPF0[0x858]=0xa500000000
IPPF_REG_00C2.IPPF0[0xc2]=0x10
IPPF_REG_00F0.IPPF0[0xf0]=0
IPPF_REG_03A0.IPPF0[0x3a0]=0xfa0400
IPPF_REG_03A1.IPPF0[0x3a1]=0xf7a003c136887a188994a07d9e930e4a5f58fbd2fff7d4956b3e6e6509c89fc8543822ec456a7abe832d88af0d36d10bc8c4462ac23d44a800b7accfc7fcbc1ead4e6b9bd7a507878d8a78cb7c196222
IPPF_REG_055A.IPPF0[0x55a]=0
IPPF_REG_060A.IPPF0[0x60a]=0
IPPF_REG_085A.IPPF0[0x85a]=0
IPPF_RESERVED_MTCD.IPPF0[0xae]=0x30
IPPF_RESERVED_MTCP.IPPF0[0xad]=0x300000600000000
IPPF_RESERVED_SPARE_0.IPPF0[0x90]=0xffffffff
IPPF_RESERVED_SPARE_1.IPPF0[0x91]=0xffffffff
IPPF_RESERVED_SPARE_2.IPPF0[0x92]=0
IPPF_RESERVED_SPARE_3.IPPF0[0x93]=0
IPPF_SBUS_BROADCAST_ID.IPPF0[0x86]=0x7ff
IPPF_SBUS_LAST_IN_CHAIN.IPPF0[0x87]=0
IPPF_SPECIAL_CLOCK_CONTROLS.IPPF0[0xc1]=2
IPPF_STATISTICS_INFO.IPPF0[0x22c]=0
IPPF_STAT_OBJ_PROFILE_ATTR.IPPF0[0x233]=0
IPPF_VTACS_TCAM_ECC_FIX_EN.IPPF0[0x552]=0
IPPF_VTACS_TCAM_PROTECTION_ERROR.IPPF0[0x554]=0
IPPF_VTACS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPF0[0x550]=0xff
IPPF_VTACS_TCAM_RESET_BLOCK.IPPF0[0x553]=0
IPPF_VTBCS_TCAM_ECC_FIX_EN.IPPF0[0x602]=0
IPPF_VTBCS_TCAM_PROTECTION_ERROR.IPPF0[0x604]=0
IPPF_VTBCS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPF0[0x600]=0xff
IPPF_VTBCS_TCAM_RESET_BLOCK.IPPF0[0x603]=0
IPPF_VTCCS_TCAM_ECC_FIX_EN.IPPF0[0x852]=0
IPPF_VTCCS_TCAM_PROTECTION_ERROR.IPPF0[0x854]=0
IPPF_VTCCS_TCAM_PROTECTION_MACHINE_CONFIGURATION.IPPF0[0x850]=0xff
IPPF_VTCCS_TCAM_RESET_BLOCK.IPPF0[0x853]=0
IPPF_VTT_ACTION_PROFILE_ACCEPTABLE_FRAME_TYPES.IPPF0[0x1e0]=0x200
IPPF_VTT_ETHERNET_TERMINATION_ACTION.IPPF0[0x1b1]=0xaaaaaaaaaaaaaaaaa4a4a4a4a4a4a4a400000000000000000000000000000000aaaaaaaaaaaaaaaaa484a484a484a484
IPPF_VTT_GENERAL_CONFIGS_0.IPPF0[0x165]=0x14
IPPF_VTT_MPLS_LABEL_RANGE_PROFILE.IPPF0[0x1cd]=0xf
IPPF_VTT_MPLS_PREPROCESSING_BOS_OR_TTL_TRAP.IPPF0[0x1b0]=0xf80
IPPF_VTT_MY_MAC_VRID_VMV_SHIFT_VALUE.IPPF0[0x1af]=2
IPPF_VTT_QOS_PROPAG_PROFILE_MAPPING.IPPF0[0x1d4]=0x444414115455
IPPF_VTT_SPECIAL_LABELS_PROFILE.IPPF0[0x1cf]=0xdad936db6db66f6db6d8949b
IPPF_VTT_SPECIAL_LABEL_VALUES.IPPF0[0x1d2]=0
IPPF_VTT_ST_ONE_LE_CONTROL_FIFO_CFG.IPPF0[0x460]=4
IPPF_VTT_ST_ONE_LE_LATENCY_COMPENSATION_FIFO_CFG(0).IPPF0[0x461]=4
IPPF_VTT_ST_ONE_LE_LATENCY_COMPENSATION_FIFO_CFG(1).IPPF0[0x462]=4
IPPF_VTT_ST_ONE_LE_LATENCY_COMPENSATION_FIFO_CFG(2).IPPF0[0x463]=3
IPPF_VTT_ST_ONE_LE_LATENCY_COMPENSATION_FIFO_CFG(3).IPPF0[0x464]=1
IPPF_VTT_ST_ONE_LE_LATENCY_COMPENSATION_FIFO_CFG(4).IPPF0[0x465]=1
IPPF_VTT_ST_ONE_LE_LATENCY_COMPENSATION_FIFO_CFG(5).IPPF0[0x466]=0
IPPF_VTT_ST_ONE_LE_VMV_SHIFT_VALUE_MAP(0).IPPF0[0x467]=0x492492492492492492492492492492492492492492492492
IPPF_VTT_ST_ONE_LE_VMV_SHIFT_VALUE_MAP(1).IPPF0[0x468]=0x2492492492492492492492494924924924920000006db6db
IPPF_VTT_ST_ONE_LE_VMV_SHIFT_VALUE_MAP(2).IPPF0[0x469]=0x2492492492492492492492494924924924920000006db6db
IPPF_VTT_ST_TWO_LE_CONFIG.IPPF0[0x470]=0x14ad
IPPF_VTT_ST_TWO_LE_CONTROL_FIFO_CFG(0).IPPF0[0x471]=1
IPPF_VTT_ST_TWO_LE_CONTROL_FIFO_CFG(1).IPPF0[0x472]=1
IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG(0).IPPF0[0x473]=0
IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG(1).IPPF0[0x474]=0
IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG(2).IPPF0[0x475]=0
IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG(3).IPPF0[0x476]=0
IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG(4).IPPF0[0x477]=0
IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG(5).IPPF0[0x478]=0
IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG(6).IPPF0[0x479]=0
IPPF_VTT_ST_TWO_LE_VMV_SHIFT_VALUE_MAP(0).IPPF0[0x47a]=0x492492492492492492492492492492492492492492492492
IPPF_VTT_ST_TWO_LE_VMV_SHIFT_VALUE_MAP(1).IPPF0[0x47b]=0x492492492492492492492492000000000000492492492492
IPPF_VTT_ST_TWO_LE_VMV_SHIFT_VALUE_MAP(2).IPPF0[0x47c]=0x492492492492492492492492000000000000492492492492
IPPF_VTT_TRAP_STRENGTHS_0.IPPF0[0x171]=0xc1800000
IPPF_VTT_TRAP_STRENGTHS_1.IPPF0[0x173]=0
IPPF_VTT_TRAP_STRENGTHS_2.IPPF0[0x174]=0x3068d
IPPF_VTT_TRAP_STRENGTHS_3.IPPF0[0x175]=0xc1830600
IPPF_VTT_TRAP_STRENGTHS_4.IPPF0[0x177]=0x60c163058c
IPPF_VTT_TRAP_STRENGTHS_5.IPPF0[0x179]=0xb160000c
IPPF_VTT_TRAP_STRENGTHS_6.IPPF0[0x17b]=0xc0000000
IPPF_VTT_TRAP_STRENGTHS_7.IPPF0[0x17d]=0x16000000000
IPPF_VTT_TRAP_STRENGTHS_8.IPPF0[0x17f]=0
IPPF_VTT_TRAP_STRENGTHS_9.IPPF0[0x180]=0xb000000b
IPROCPERIPH_GPIO_GP_AUX_SEL.CMIC0[0x25028]=0
IPROCPERIPH_GPIO_GP_DATA_IN.CMIC0[0x25000]=0
IPROCPERIPH_GPIO_GP_DATA_OUT.CMIC0[0x25004]=0
IPROCPERIPH_GPIO_GP_INIT_VAL.CMIC0[0x25030]=0
IPROCPERIPH_GPIO_GP_INT_CLR.CMIC0[0x25024]=0
IPROCPERIPH_GPIO_GP_INT_DE.CMIC0[0x25010]=0
IPROCPERIPH_GPIO_GP_INT_EDGE.CMIC0[0x25014]=0
IPROCPERIPH_GPIO_GP_INT_MSK.CMIC0[0x25018]=0
IPROCPERIPH_GPIO_GP_INT_MSTAT.CMIC0[0x25020]=0
IPROCPERIPH_GPIO_GP_INT_STAT.CMIC0[0x2501c]=0
IPROCPERIPH_GPIO_GP_INT_TYPE.CMIC0[0x2500c]=0
IPROCPERIPH_GPIO_GP_OUT_EN.CMIC0[0x25008]=0
IPROCPERIPH_GPIO_GP_PAD_RES.CMIC0[0x25034]=0
IPROCPERIPH_GPIO_GP_PRB_ENABLE.CMIC0[0x25048]=0
IPROCPERIPH_GPIO_GP_PRB_OE.CMIC0[0x2504c]=0
IPROCPERIPH_GPIO_GP_RES_EN.CMIC0[0x25038]=0
IPROCPERIPH_GPIO_GP_TEST_ENABLE.CMIC0[0x25044]=0
IPROCPERIPH_GPIO_GP_TEST_INPUT.CMIC0[0x2503c]=0
IPROCPERIPH_GPIO_GP_TEST_OUTPUT.CMIC0[0x25040]=0
IPROCPERIPH_PL022_SPI_SSPCPSR.CMIC0[0x24010]=0
IPROCPERIPH_PL022_SPI_SSPCR0.CMIC0[0x24000]=0
IPROCPERIPH_PL022_SPI_SSPCR1.CMIC0[0x24004]=0
IPROCPERIPH_PL022_SPI_SSPDMACR.CMIC0[0x24024]=0
IPROCPERIPH_PL022_SPI_SSPDR.CMIC0[0x24008]=0
IPROCPERIPH_PL022_SPI_SSPICR.CMIC0[0x24020]=0
IPROCPERIPH_PL022_SPI_SSPIMSC.CMIC0[0x24014]=0
IPROCPERIPH_PL022_SPI_SSPITIP.CMIC0[0x24084]=0
IPROCPERIPH_PL022_SPI_SSPITOP.CMIC0[0x24088]=0
IPROCPERIPH_PL022_SPI_SSPMIS.CMIC0[0x2401c]=0
IPROCPERIPH_PL022_SPI_SSPPCELLID0.CMIC0[0x24ff0]=0
IPROCPERIPH_PL022_SPI_SSPPCELLID1.CMIC0[0x24ff4]=0
IPROCPERIPH_PL022_SPI_SSPPCELLID2.CMIC0[0x24ff8]=0
IPROCPERIPH_PL022_SPI_SSPPCELLID3.CMIC0[0x24ffc]=0
IPROCPERIPH_PL022_SPI_SSPPERIPHID0.CMIC0[0x24fe0]=0
IPROCPERIPH_PL022_SPI_SSPPERIPHID1.CMIC0[0x24fe4]=0
IPROCPERIPH_PL022_SPI_SSPPERIPHID2.CMIC0[0x24fe8]=0
IPROCPERIPH_PL022_SPI_SSPPERIPHID3.CMIC0[0x24fec]=0
IPROCPERIPH_PL022_SPI_SSPRIS.CMIC0[0x24018]=0
IPROCPERIPH_PL022_SPI_SSPSR.CMIC0[0x2400c]=0
IPROCPERIPH_PL022_SPI_SSPTCR.CMIC0[0x24080]=0
IPROCPERIPH_PL022_SPI_SSPTDR.CMIC0[0x2408c]=0
IPROCPERIPH_SMBUS0_SMBUS_ADDRESS.CMIC0[0x22008]=0
IPROCPERIPH_SMBUS0_SMBUS_BIT_BANG_CONTROL.CMIC0[0x22014]=0x50000000
IPROCPERIPH_SMBUS0_SMBUS_CONFIG.CMIC0[0x22000]=0xf0c00
IPROCPERIPH_SMBUS0_SMBUS_EVENT_ENABLE.CMIC0[0x22038]=0
IPROCPERIPH_SMBUS0_SMBUS_EVENT_STATUS.CMIC0[0x2203c]=0
IPROCPERIPH_SMBUS0_SMBUS_MASTER_COMMAND.CMIC0[0x22030]=0
IPROCPERIPH_SMBUS0_SMBUS_MASTER_DATA_READ.CMIC0[0x22044]=0
IPROCPERIPH_SMBUS0_SMBUS_MASTER_DATA_WRITE.CMIC0[0x22040]=0
IPROCPERIPH_SMBUS0_SMBUS_MASTER_FIFO_CONTROL.CMIC0[0x2200c]=0
IPROCPERIPH_SMBUS0_SMBUS_SLAVE_COMMAND.CMIC0[0x22034]=0
IPROCPERIPH_SMBUS0_SMBUS_SLAVE_DATA_READ.CMIC0[0x2204c]=0
IPROCPERIPH_SMBUS0_SMBUS_SLAVE_DATA_WRITE.CMIC0[0x22048]=0
IPROCPERIPH_SMBUS0_SMBUS_SLAVE_FIFO_CONTROL.CMIC0[0x22010]=0
IPROCPERIPH_SMBUS0_SMBUS_TIMING_CONFIG.CMIC0[0x22004]=0x19003200
IPROCPERIPH_SMBUS0_SMBUS_TIMING_CONFIG_2.CMIC0[0x220b0]=0xa113843
IPROCPERIPH_SMBUS1_SMBUS_ADDRESS.CMIC0[0x23008]=0
IPROCPERIPH_SMBUS1_SMBUS_BIT_BANG_CONTROL.CMIC0[0x23014]=0x50000000
IPROCPERIPH_SMBUS1_SMBUS_CONFIG.CMIC0[0x23000]=0xf0c00
IPROCPERIPH_SMBUS1_SMBUS_EVENT_ENABLE.CMIC0[0x23038]=0
IPROCPERIPH_SMBUS1_SMBUS_EVENT_STATUS.CMIC0[0x2303c]=0
IPROCPERIPH_SMBUS1_SMBUS_MASTER_COMMAND.CMIC0[0x23030]=0
IPROCPERIPH_SMBUS1_SMBUS_MASTER_DATA_READ.CMIC0[0x23044]=0
IPROCPERIPH_SMBUS1_SMBUS_MASTER_DATA_WRITE.CMIC0[0x23040]=0
IPROCPERIPH_SMBUS1_SMBUS_MASTER_FIFO_CONTROL.CMIC0[0x2300c]=0
IPROCPERIPH_SMBUS1_SMBUS_SLAVE_COMMAND.CMIC0[0x23034]=0
IPROCPERIPH_SMBUS1_SMBUS_SLAVE_DATA_READ.CMIC0[0x2304c]=0
IPROCPERIPH_SMBUS1_SMBUS_SLAVE_DATA_WRITE.CMIC0[0x23048]=0
IPROCPERIPH_SMBUS1_SMBUS_SLAVE_FIFO_CONTROL.CMIC0[0x23010]=0
IPROCPERIPH_SMBUS1_SMBUS_TIMING_CONFIG.CMIC0[0x23004]=0x19003200
IPROCPERIPH_SMBUS1_SMBUS_TIMING_CONFIG_2.CMIC0[0x230b0]=0xa113843
IPROCPERIPH_UART0_UART_CPR.CMIC0[0x200f4]=0x43f72
IPROCPERIPH_UART0_UART_CTR.CMIC0[0x200fc]=0x44570110
IPROCPERIPH_UART0_UART_DLH_IER.CMIC0[0x20004]=0
IPROCPERIPH_UART0_UART_DMASA.CMIC0[0x200a8]=0
IPROCPERIPH_UART0_UART_FAR.CMIC0[0x20070]=0
IPROCPERIPH_UART0_UART_HTX.CMIC0[0x200a4]=0
IPROCPERIPH_UART0_UART_IIR_FCR.CMIC0[0x20008]=1
IPROCPERIPH_UART0_UART_LCR.CMIC0[0x2000c]=0
IPROCPERIPH_UART0_UART_LSR.CMIC0[0x20014]=0x60
IPROCPERIPH_UART0_UART_MCR.CMIC0[0x20010]=0
IPROCPERIPH_UART0_UART_MSR.CMIC0[0x20018]=0
IPROCPERIPH_UART0_UART_RBR_THR_DLL.CMIC0[0x20000]=0
IPROCPERIPH_UART0_UART_RFL.CMIC0[0x20084]=0
IPROCPERIPH_UART0_UART_RFW.CMIC0[0x20078]=0
IPROCPERIPH_UART0_UART_SBCR.CMIC0[0x20090]=0
IPROCPERIPH_UART0_UART_SCR.CMIC0[0x2001c]=0
IPROCPERIPH_UART0_UART_SDMAM.CMIC0[0x20094]=0
IPROCPERIPH_UART0_UART_SFE.CMIC0[0x20098]=0
IPROCPERIPH_UART0_UART_SRBR_STHR0.CMIC0[0x20030]=0
IPROCPERIPH_UART0_UART_SRBR_STHR1.CMIC0[0x20034]=0
IPROCPERIPH_UART0_UART_SRBR_STHR2.CMIC0[0x20038]=0
IPROCPERIPH_UART0_UART_SRBR_STHR3.CMIC0[0x2003c]=0
IPROCPERIPH_UART0_UART_SRBR_STHR4.CMIC0[0x20040]=0
IPROCPERIPH_UART0_UART_SRBR_STHR5.CMIC0[0x20044]=0
IPROCPERIPH_UART0_UART_SRBR_STHR6.CMIC0[0x20048]=0
IPROCPERIPH_UART0_UART_SRBR_STHR7.CMIC0[0x2004c]=0
IPROCPERIPH_UART0_UART_SRBR_STHR8.CMIC0[0x20050]=0
IPROCPERIPH_UART0_UART_SRBR_STHR9.CMIC0[0x20054]=0
IPROCPERIPH_UART0_UART_SRBR_STHR10.CMIC0[0x20058]=0
IPROCPERIPH_UART0_UART_SRBR_STHR11.CMIC0[0x2005c]=0
IPROCPERIPH_UART0_UART_SRBR_STHR12.CMIC0[0x20060]=0
IPROCPERIPH_UART0_UART_SRBR_STHR13.CMIC0[0x20064]=0
IPROCPERIPH_UART0_UART_SRBR_STHR14.CMIC0[0x20068]=0
IPROCPERIPH_UART0_UART_SRBR_STHR15.CMIC0[0x2006c]=0
IPROCPERIPH_UART0_UART_SRR.CMIC0[0x20088]=0
IPROCPERIPH_UART0_UART_SRT.CMIC0[0x2009c]=0
IPROCPERIPH_UART0_UART_SRTS.CMIC0[0x2008c]=0
IPROCPERIPH_UART0_UART_STET.CMIC0[0x200a0]=0
IPROCPERIPH_UART0_UART_TFL.CMIC0[0x20080]=0
IPROCPERIPH_UART0_UART_TFR.CMIC0[0x20074]=0
IPROCPERIPH_UART0_UART_UCV.CMIC0[0x200f8]=0x3331342a
IPROCPERIPH_UART0_UART_USR.CMIC0[0x2007c]=6
IPROCPERIPH_UART1_UART_CPR.CMIC0[0x210f4]=0x43f72
IPROCPERIPH_UART1_UART_CTR.CMIC0[0x210fc]=0x44570110
IPROCPERIPH_UART1_UART_DLH_IER.CMIC0[0x21004]=0
IPROCPERIPH_UART1_UART_DMASA.CMIC0[0x210a8]=0
IPROCPERIPH_UART1_UART_FAR.CMIC0[0x21070]=0
IPROCPERIPH_UART1_UART_HTX.CMIC0[0x210a4]=0
IPROCPERIPH_UART1_UART_IIR_FCR.CMIC0[0x21008]=1
IPROCPERIPH_UART1_UART_LCR.CMIC0[0x2100c]=0
IPROCPERIPH_UART1_UART_LSR.CMIC0[0x21014]=0x60
IPROCPERIPH_UART1_UART_MCR.CMIC0[0x21010]=0
IPROCPERIPH_UART1_UART_MSR.CMIC0[0x21018]=0
IPROCPERIPH_UART1_UART_RBR_THR_DLL.CMIC0[0x21000]=0
IPROCPERIPH_UART1_UART_RFL.CMIC0[0x21084]=0
IPROCPERIPH_UART1_UART_RFW.CMIC0[0x21078]=0
IPROCPERIPH_UART1_UART_SBCR.CMIC0[0x21090]=0
IPROCPERIPH_UART1_UART_SCR.CMIC0[0x2101c]=0
IPROCPERIPH_UART1_UART_SDMAM.CMIC0[0x21094]=0
IPROCPERIPH_UART1_UART_SFE.CMIC0[0x21098]=0
IPROCPERIPH_UART1_UART_SRBR_STHR0.CMIC0[0x21030]=0
IPROCPERIPH_UART1_UART_SRBR_STHR1.CMIC0[0x21034]=0
IPROCPERIPH_UART1_UART_SRBR_STHR2.CMIC0[0x21038]=0
IPROCPERIPH_UART1_UART_SRBR_STHR3.CMIC0[0x2103c]=0
IPROCPERIPH_UART1_UART_SRBR_STHR4.CMIC0[0x21040]=0
IPROCPERIPH_UART1_UART_SRBR_STHR5.CMIC0[0x21044]=0
IPROCPERIPH_UART1_UART_SRBR_STHR6.CMIC0[0x21048]=0
IPROCPERIPH_UART1_UART_SRBR_STHR7.CMIC0[0x2104c]=0
IPROCPERIPH_UART1_UART_SRBR_STHR8.CMIC0[0x21050]=0
IPROCPERIPH_UART1_UART_SRBR_STHR9.CMIC0[0x21054]=0
IPROCPERIPH_UART1_UART_SRBR_STHR10.CMIC0[0x21058]=0
IPROCPERIPH_UART1_UART_SRBR_STHR11.CMIC0[0x2105c]=0
IPROCPERIPH_UART1_UART_SRBR_STHR12.CMIC0[0x21060]=0
IPROCPERIPH_UART1_UART_SRBR_STHR13.CMIC0[0x21064]=0
IPROCPERIPH_UART1_UART_SRBR_STHR14.CMIC0[0x21068]=0
IPROCPERIPH_UART1_UART_SRBR_STHR15.CMIC0[0x2106c]=0
IPROCPERIPH_UART1_UART_SRR.CMIC0[0x21088]=0
IPROCPERIPH_UART1_UART_SRT.CMIC0[0x2109c]=0
IPROCPERIPH_UART1_UART_SRTS.CMIC0[0x2108c]=0
IPROCPERIPH_UART1_UART_STET.CMIC0[0x210a0]=0
IPROCPERIPH_UART1_UART_TFL.CMIC0[0x21080]=0
IPROCPERIPH_UART1_UART_TFR.CMIC0[0x21074]=0
IPROCPERIPH_UART1_UART_UCV.CMIC0[0x210f8]=0x3331342a
IPROCPERIPH_UART1_UART_USR.CMIC0[0x2107c]=6
IPS_ACTIVE_PUSH_QUEUE_QNUM.IPS0[0x256]=0
IPS_ACTIVE_QUEUE_COUNT.IPS0[0x21d]=0
IPS_ACTIVE_QUEUE_COUNT_ERR_INTERRUPT_MASK_REGISTER.IPS0[0x111]=0
IPS_ACTIVE_QUEUE_COUNT_ERR_INTERRUPT_REGISTER.IPS0[0x110]=0
IPS_ACTIVE_QUEUE_COUNT_ERR_INTERRUPT_REGISTER_TEST.IPS0[0x112]=0
IPS_AUTO_CREDIT_MECHANISM_RANGE.IPS0[0x24b]=0
IPS_AUTO_CREDIT_MECHANISM_RATE.IPS0[0x24c]=0
IPS_CRBAL_OVERFLOW_QNUM.IPS0[0x255]=0
IPS_CRDT_FLOW_ID_CHECK.IPS0[0x251]=0
IPS_CRDT_FLOW_ID_ERR_CAPTURE.IPS0[0x252]=0
IPS_CRDT_FLOW_ID_ERR_CTR.IPS0[0x25a]=0
IPS_CRDT_LTNCY_CTR.IPS0[0x213]=0
IPS_CRDT_LTNCY_QNUM.IPS0[0x211]=0
IPS_CRDT_WD_CURRENT_TIME.IPS0[0x257]=0x3ec5
IPS_CRDT_WD_EVNT_CTR.IPS0[0x26e]=0x2c5e911ea
IPS_CRDT_WD_SCAN_RANGE.IPS0[0x20f]=0x3fff8000
IPS_CREDIT_BALANCE_RESOLUTION_REGISTER.IPS0[0x218]=0
IPS_CREDIT_CONFIG.IPS0[0x238]=0x1000800
IPS_CREDIT_VALUE_CONFIG.IPS0[0x24f]=1
IPS_CREDIT_WATCHDOG_CONFIGURATION.IPS0[0x210]=0x18024800804
IPS_DEBUG_FILTER.IPS0[0x27b]=0x2b3fc03ff800fffe0003e0
IPS_DELETED_CRDT_CTR.IPS0[0x25d]=0x22
IPS_DEL_QNUM.IPS0[0x259]=0
IPS_DEQ_CMD_DRAM_TO_FABRIC_CRDT_ADJUST.IPS0[0x23b]=0
IPS_DEQ_CMD_SRAM_TO_DRAM_CRDT_ADJUST.IPS0[0x23a]=0
IPS_DEQ_CMD_SRAM_TO_FABRIC_CRDT_ADJUST.IPS0[0x239]=0x338019c00ce00670
IPS_DISCARD_CRDT_CTR.IPS0[0x25f]=0
IPS_DQM_ACTIVE_QUEUE_COUNT.IPS0[0x229]=0
IPS_DQM_ACTIVE_QUEUE_COUNT_A.IPS0[0x22b]=0
IPS_DQM_ACTIVE_QUEUE_COUNT_B.IPS0[0x22d]=0
IPS_DQM_ACTIVE_QUEUE_COUNT_C.IPS0[0x22f]=0
IPS_DQM_ACTIVE_QUEUE_COUNT_D.IPS0[0x231]=0
IPS_DQM_DEQ_CMD_BYTES_CTR.IPS0[0x279]=0
IPS_DQM_DEQ_CMD_CTR.IPS0[0x278]=0
IPS_DQM_DEQ_EVNT_CTR.IPS0[0x269]=0
IPS_DQM_DQCQ_DEPTH_CONFIG.IPS0[0x237]=0x100100100100100100100100100
IPS_DQM_DQCQ_ERR_STATUS.IPS0[0x254]=0
IPS_DQM_DQCQ_MAX_OCCUPANCY.IPS0[0x284]=0
IPS_DQM_DQCQ_STATUS.IPS0[0x280]=0
IPS_DQM_ENQ_EVNT_CTR.IPS0[0x268]=0
IPS_DQM_MAX_DEQ_CMD_CRDT.IPS0[0x20c]=0x807f3f9fc3232190c81e1e0f078080804020
IPS_DQM_MAX_DEQ_CMD_CRDT_SEL.IPS0[0x20b]=0x1401400
IPS_DQM_MAX_DEQ_CMD_CRDT_TH.IPS0[0x20a]=0x2002002
IPS_DRAM_ONLY_QUEUE_TYPE.IPS0[0x250]=0
IPS_ECC_1B_ERR_CNT.IPS0[0x94]=0
IPS_ECC_2B_ERR_CNT.IPS0[0x96]=0
IPS_ECC_ERR_1B_MONITOR_MEM_MASK.IPS0[0x9a]=0x1fff
IPS_ECC_ERR_2B_MONITOR_MEM_MASK.IPS0[0x9c]=0x1fff
IPS_ECC_INTERRUPT_REGISTER.IPS0[0x7]=0
IPS_ECC_INTERRUPT_REGISTER_MASK.IPS0[0x17]=0
IPS_ECC_INTERRUPT_REGISTER_TEST.IPS0[0x1f]=0
IPS_EIR_FC_SETTINGS.IPS0[0x217]=0
IPS_ENABLE_DYNAMIC_MEMORY_ACCESS.IPS0[0x84]=0
IPS_FCR_CRDT_EVNT_CTR.IPS0[0x26b]=0x25511de9e
IPS_FORCE_DQCQ_FC.IPS0[0x202]=0
IPS_FSMRQ_DEBUG.IPS0[0x262]=0
IPS_FSMRQ_DELAY_CTR_SETTINGS.IPS0[0x27c]=0
IPS_FSMRQ_FLOW_STATUS_CTR.IPS0[0x270]=0x25491d70e
IPS_FSM_EVNT_CTR.IPS0[0x26f]=0x254c67cb2
IPS_FSM_FIFO_SETTINGS.IPS0[0x23d]=0x801380100
IPS_FSM_HP_FIFO_MAX_STATUS.IPS0[0x23f]=0
IPS_FSM_HP_FIFO_STATUS.IPS0[0x23e]=0
IPS_FSM_LP_FIFO_MAX_STATUS.IPS0[0x241]=2
IPS_FSM_LP_FIFO_STATUS.IPS0[0x240]=0
IPS_FSM_ON_MESSAGE_SHAPER.IPS0[0x23c]=0x10000
IPS_FSM_STAMP_CONFIGURATION.IPS0[0x243]=0
IPS_GLBL_CRDT_EVNT_CTR.IPS0[0x26d]=0x25511dea4
IPS_GLBL_FLOW_STATUS_CTR.IPS0[0x271]=0x2ebafd5dd
IPS_GLBL_QM_EVNT_CTR.IPS0[0x26a]=0x355422be2
IPS_GLBL_TX_FLOW_STATUS_CTR.IPS0[0x272]=0x2ebafd5dd
IPS_GTIMER_CONFIGURATION.IPS0[0x89]=0
IPS_GTIMER_CYCLE.IPS0[0x88]=0x3b9aca00
IPS_HIGH_QSIZE_IN_DQM_DQCQ_FC_SETTINGS.IPS0[0x234]=0
IPS_HIGH_QSIZE_IN_DQM_DQCQ_FC_STATUS.IPS0[0x235]=0
IPS_HIGH_QSIZE_IN_SQM_DQCQ_FC_SETTINGS.IPS0[0x232]=0
IPS_HIGH_QSIZE_IN_SQM_DQCQ_FC_STATUS.IPS0[0x233]=0
IPS_INDIRECT_COMMAND.IPS0[0x80]=0xe000002
IPS_INDIRECT_COMMAND_ADDRESS.IPS0[0x81]=0x200028
IPS_INDIRECT_COMMAND_RD_DATA.IPS0[0x60]=0
IPS_INDIRECT_COMMAND_WR_DATA.IPS0[0x20]=0x38030028020018010008038030000002108421084
IPS_INDIRECT_FORCE_BUBBLE.IPS0[0x83]=0x20019
IPS_INS_CRDT_LTNCY_CTR.IPS0[0x212]=0
IPS_INTERRUPT_MASK_REGISTER.IPS0[0x10]=0
IPS_INTERRUPT_REGISTER.IPS0[0x0]=0
IPS_INTERRUPT_REGISTER_TEST.IPS0[0x18]=0
IPS_IPS_GENERAL_CONFIGURATIONS.IPS0[0x200]=0x182d03ffe0a00
IPS_IPT_DQCQ_FC_STATUS.IPS0[0x281]=0
IPS_IPT_EIR_FC_STATUS.IPS0[0x282]=0
IPS_LCL_CRDT_EVNT_CTR.IPS0[0x26c]=0
IPS_LOST_CRDT_CTR.IPS0[0x25e]=0
IPS_LOST_CRDT_STATUS.IPS0[0x258]=0
IPS_MANUAL_OPERATION_QNUM.IPS0[0x21a]=0
IPS_MANUAL_QUEUE_OPERATION.IPS0[0x21b]=0x200
IPS_MAX_ACTIVE_QUEUE_COUNT.IPS0[0x21c]=0x20
IPS_MAX_CRBAL.IPS0[0x27d]=0x8d80137
IPS_MAX_DQM_ACTIVE_QUEUE_COUNT.IPS0[0x228]=0
IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_A.IPS0[0x22a]=0
IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_B.IPS0[0x22c]=0
IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_C.IPS0[0x22e]=0
IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_D.IPS0[0x230]=0
IPS_MAX_PORT_QUEUE_SIZE.IPS0[0x27a]=0
IPS_MAX_SQM_ACTIVE_QUEUE_COUNT.IPS0[0x21e]=9
IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_A.IPS0[0x220]=9
IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_B.IPS0[0x222]=0
IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_C.IPS0[0x224]=0
IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_D.IPS0[0x226]=0
IPS_MIN_CRBAL.IPS0[0x27e]=0x1eaa18118
IPS_MULT_PKT_DEQ_SETTINGS.IPS0[0x215]=0x1000001f80
IPS_ONE_PKT_DEQ_LIMIT_SETTINGS_1.IPS0[0x244]=0x8102040
IPS_ONE_PKT_DEQ_LIMIT_SETTINGS_2.IPS0[0x245]=0x3f
IPS_ONE_PKT_DEQ_LIMIT_SETTINGS_3.IPS0[0x246]=0
IPS_OPDL_HP_CTR_MAX_STATUS.IPS0[0x248]=0
IPS_OPDL_HP_CTR_STATUS.IPS0[0x247]=0
IPS_OPDL_HP_MAP.IPS0[0x24d]=0
IPS_OPDL_LP_CTR_MAX_STATUS.IPS0[0x24a]=0x1f
IPS_OPDL_LP_CTR_STATUS.IPS0[0x249]=0x1e
IPS_OPDL_LP_MAP.IPS0[0x24e]=0x1e3a7851db102e3c
IPS_OPDL_RJCT_CTR.IPS0[0x273]=0
IPS_PUSH_QUEUE_TYPES_CONFIG.IPS0[0x216]=0
IPS_QPRIORITY_IS_HIGH.IPS0[0x205]=0
IPS_QUEUE_INTERDIGITATED_MODE.IPS0[0x20e]=0
IPS_QUEUE_IS_OCB_ONLY.IPS0[0x203]=0
IPS_REG_0041.IPS0[0x41]=0
IPS_REG_0201.IPS0[0x201]=0x7fb
IPS_REG_0204.IPS0[0x204]=0
IPS_REG_0214.IPS0[0x214]=0x14
IPS_REG_0219.IPS0[0x219]=0x7ffffffff
IPS_REG_0242.IPS0[0x242]=0x7a58
IPS_REG_0285.IPS0[0x285]=0
IPS_REG_0286.IPS0[0x286]=0
IPS_REG_0287.IPS0[0x287]=0xe007
IPS_REG_00C2.IPS0[0xc2]=0x10
IPS_REG_020D.IPS0[0x20d]=0xffffffffffffffff
IPS_REG_025B.IPS0[0x25b]=0
IPS_REG_025C.IPS0[0x25c]=0
IPS_RESERVED_MTCD.IPS0[0xae]=0x30
IPS_RESERVED_MTCP.IPS0[0xad]=0x300000600000000
IPS_RESERVED_SPARE_0.IPS0[0x90]=0xffffffff
IPS_RESERVED_SPARE_1.IPS0[0x91]=0xffffffff
IPS_RESERVED_SPARE_2.IPS0[0x92]=0
IPS_RESERVED_SPARE_3.IPS0[0x93]=0
IPS_RJCT_CRDT_CTR.IPS0[0x261]=0
IPS_RTRN_CRDT_CTR.IPS0[0x260]=0
IPS_SBUS_BROADCAST_ID.IPS0[0x86]=0x7ff
IPS_SBUS_LAST_IN_CHAIN.IPS0[0x87]=0
IPS_SPECIAL_CLOCK_CONTROLS.IPS0[0xc1]=2
IPS_SQM_ACTIVE_QUEUE_COUNT.IPS0[0x21f]=0
IPS_SQM_ACTIVE_QUEUE_COUNT_A.IPS0[0x221]=0
IPS_SQM_ACTIVE_QUEUE_COUNT_B.IPS0[0x223]=0
IPS_SQM_ACTIVE_QUEUE_COUNT_C.IPS0[0x225]=0
IPS_SQM_ACTIVE_QUEUE_COUNT_D.IPS0[0x227]=0
IPS_SQM_DEQ_CMD_BYTES_CTR.IPS0[0x275]=0x2c6414000
IPS_SQM_DEQ_CMD_CTR.IPS0[0x274]=0x273be4575
IPS_SQM_DEQ_EVNT_CTR.IPS0[0x266]=0x273c42a4a
IPS_SQM_DEQ_TO_DRAM_CMD_BYTES_CTR.IPS0[0x277]=0
IPS_SQM_DEQ_TO_DRAM_CMD_CTR.IPS0[0x276]=0
IPS_SQM_DEQ_TO_DRAM_EVNT_CTR.IPS0[0x267]=0
IPS_SQM_DQCQ_DEPTH_CONFIG.IPS0[0x236]=0x200100080040020010008004002001000800400200100080040020010008004002001000800400200100
IPS_SQM_DQCQ_ERR_STATUS.IPS0[0x253]=0
IPS_SQM_DQCQ_MAX_OCCUPANCY.IPS0[0x283]=0x7002200000000
IPS_SQM_DQCQ_STATUS.IPS0[0x27f]=0
IPS_SQM_ENQ_EVNT_CTR.IPS0[0x265]=0x2e17e02bf
IPS_SQM_MAX_DEQ_CMD_CRDT.IPS0[0x208]=0x807f3f9fc3232190c81e1e0f078080804020
IPS_SQM_MAX_DEQ_CMD_CRDT_SEL.IPS0[0x207]=0x1401400
IPS_SQM_MAX_DEQ_CMD_CRDT_TH.IPS0[0x206]=0x2002002
IPS_SRAM_TO_DRAM_MAX_DEQ_CMD_CRDT.IPS0[0x209]=0x807f3f9fc3232190c81e1e0f078080804020
IPS_TIME_IN_NORM.IPS0[0x264]=0
IPS_TIME_IN_SLOW.IPS0[0x263]=0
IPT_CONTEXT_DEBUG(0).IPT0[0x145]=0
IPT_CONTEXT_DEBUG(1).IPT0[0x146]=0x84000
IPT_CONTEXT_EIR_CFG(0).IPT0[0x137]=0xc88004bff6fffc0010028018c0050320014bb8
IPT_CONTEXT_TC_DEBUG(0).IPT0[0x147]=0
IPT_CONTEXT_TC_DEBUG(1).IPT0[0x148]=0
IPT_CONTEXT_TC_DEBUG(2).IPT0[0x149]=0
IPT_CONTEXT_TC_DEBUG(3).IPT0[0x14a]=0
IPT_CONTEXT_TC_DEBUG(4).IPT0[0x14b]=0
IPT_CONTEXT_TC_DEBUG(5).IPT0[0x14c]=0
IPT_CONTEXT_TC_DEBUG(6).IPT0[0x14d]=0
IPT_CONTEXT_TC_DEBUG(7).IPT0[0x14e]=0
IPT_DEST_DEBUG(0).IPT0[0x14f]=0
IPT_DTQ_CONFIG.IPT0[0x108]=2
IPT_DTQ_DEBUG(0).IPT0[0x169]=0x1c34cd99b1ec47ae03120100
IPT_DTQ_LOC_FC_TH.IPT0[0x111]=0
IPT_ECC_1B_ERR_CNT.IPT0[0x94]=0x8000
IPT_ECC_2B_ERR_CNT.IPT0[0x96]=0x8000
IPT_ECC_ERR_1B_MONITOR_MEM_MASK.IPT0[0x9a]=0xffffff
IPT_ECC_ERR_2B_MONITOR_MEM_MASK.IPT0[0x9c]=0xffffff
IPT_ECC_INTERRUPT_REGISTER.IPT0[0x7]=0
IPT_ECC_INTERRUPT_REGISTER_MASK.IPT0[0x17]=0
IPT_ECC_INTERRUPT_REGISTER_TEST.IPT0[0x1f]=0
IPT_ENABLE_DYNAMIC_MEMORY_ACCESS.IPT0[0x84]=1
IPT_FCB_CONFIG.IPT0[0x121]=0
IPT_FIFO_INTERRUPT_REGISTER.IPT0[0x101]=0
IPT_FIFO_INTERRUPT_REGISTER_MASK.IPT0[0x102]=0
IPT_FIFO_INTERRUPT_REGISTER_TEST.IPT0[0x103]=0
IPT_FLOW_CONTROL_DEBUG.IPT0[0x16d]=1
IPT_GTIMER_CONFIGURATION.IPT0[0x89]=2
IPT_GTIMER_CYCLE.IPT0[0x88]=0x23c34600
IPT_INDIRECT_COMMAND.IPT0[0x80]=0xe000002
IPT_INDIRECT_COMMAND_ADDRESS.IPT0[0x81]=0x100
IPT_INDIRECT_COMMAND_RD_DATA.IPT0[0x60]=0x789fab3488000
IPT_INDIRECT_COMMAND_WR_DATA.IPT0[0x20]=0
IPT_INDIRECT_FORCE_BUBBLE.IPT0[0x83]=0x20019
IPT_INTERRUPT_MASK_REGISTER.IPT0[0x10]=0
IPT_INTERRUPT_REGISTER.IPT0[0x0]=0
IPT_INTERRUPT_REGISTER_TEST.IPT0[0x18]=0
IPT_IPT_CHICKEN_BITS.IPT0[0x10b]=0x14
IPT_IPT_DEBUG_CONTEXT_CONTROLS(0).IPT0[0x10e]=4
IPT_IPT_DEBUG_CONTEXT_CONTROLS(1).IPT0[0x10f]=4
IPT_IPT_DEBUG_CONTEXT_OCB_CONTROLS(0).IPT0[0x110]=1
IPT_IPT_DEBUG_CONTROLS.IPT0[0x10d]=0
IPT_IPT_FLOW_CONTROL_CONFIG.IPT0[0x10c]=0
IPT_ITE_CONFIG.IPT0[0x109]=0x20
IPT_ITE_DEBUG.IPT0[0x16a]=0x9000200780e0fdbb0f6b000000000000000000008f623eb88f623eb8
IPT_ITE_DEBUG_FROM_ITPP.IPT0[0x16c]=0x11a301ac00100180044620e0efc70cbab32971000008002e0222f807fa0002000000000000dc2c6e7e8e83de26794a6d1981
IPT_ITE_DEBUG_TO_ITPP.IPT0[0x16b]=0x7ffffc008060f3000001000800445c0e097433fbab47a6d00000800280222e807fa0002000000000000085531f9b5bcde26794a6d1981
IPT_ITE_FIX_CONFIG.IPT0[0x10a]=0
IPT_ITE_INTERRUPT_REGISTER.IPT0[0x104]=0
IPT_ITE_INTERRUPT_REGISTER_MASK.IPT0[0x105]=0
IPT_ITE_INTERRUPT_REGISTER_TEST.IPT0[0x106]=0
IPT_MOP_FC_CONFIG.IPT0[0x11e]=0xb222d50b862ee0
IPT_PCMI_0.IPT0[0xb0]=0x3b9aca00
IPT_PCMI_1.IPT0[0xb3]=0x3b9aca00
IPT_PCMI_2.IPT0[0xb6]=0x3b9aca00
IPT_PCMI_3.IPT0[0xb9]=0x3b9aca00
IPT_PCMI_4.IPT0[0xbc]=0x3b9aca00
IPT_PCMI_0_S.IPT0[0xb1]=0
IPT_PCMI_0_T.IPT0[0xb2]=0
IPT_PCMI_1_S.IPT0[0xb4]=0
IPT_PCMI_1_T.IPT0[0xb5]=0
IPT_PCMI_2_S.IPT0[0xb7]=0
IPT_PCMI_2_T.IPT0[0xb8]=0
IPT_PCMI_3_S.IPT0[0xba]=0
IPT_PCMI_3_T.IPT0[0xbb]=0
IPT_PCMI_4_S.IPT0[0xbd]=0
IPT_PCMI_4_T.IPT0[0xbe]=0
IPT_PDQ_CFG(0).IPT0[0x135]=0x52ee000000000000000000000000000000000000000007fe3ff
IPT_PDQ_CFG(1).IPT0[0x136]=0x52ee159e26af159e26af159e26af159e26af159e26af07fe3ff
IPT_PDQ_CONFIG.IPT0[0x120]=0x6140006050
IPT_PDQ_DEBUG.IPT0[0x13e]=0xe1c3098613000000000000158f623fc2e1a66d4be1a66d4be1a66d4b00009a1a0
IPT_PDQ_DQCQ_FC_TH_CFG(0).IPT0[0x125]=0
IPT_PDQ_DQCQ_FC_TH_CFG(1).IPT0[0x126]=0x7e03f
IPT_PDQ_DQCQ_FC_TH_CFG(2).IPT0[0x127]=0xfc07e
IPT_PDQ_DQCQ_FC_TH_CFG(3).IPT0[0x128]=0x17a0bd
IPT_PDQ_DQCQ_FC_TH_CFG(4).IPT0[0x129]=0x1f80fc
IPT_PDQ_DQCQ_FC_TH_CFG(5).IPT0[0x12a]=0x27613b
IPT_PDQ_DQCQ_FC_TH_CFG(6).IPT0[0x12b]=0x2f417a
IPT_PDQ_DQCQ_FC_TH_CFG(7).IPT0[0x12c]=0x3721b9
IPT_PDQ_DQCQ_FC_TH_CFG(8).IPT0[0x12d]=0x3f01f8
IPT_PDQ_DQCQ_FC_TH_CFG(9).IPT0[0x12e]=0x46e237
IPT_PDQ_DQCQ_FC_TH_CFG(10).IPT0[0x12f]=0x4ec276
IPT_PDQ_DQCQ_FC_TH_CFG(11).IPT0[0x130]=0x56a2b5
IPT_PDQ_DQCQ_FC_TH_CFG(12).IPT0[0x131]=0x5e82f4
IPT_PDQ_DQCQ_FC_TH_CFG(13).IPT0[0x132]=0x666333
IPT_PDQ_DQCQ_FC_TH_CFG(14).IPT0[0x133]=0x6e4372
IPT_PDQ_DQCQ_FC_TH_CFG(15).IPT0[0x134]=0x7623b1
IPT_PDQ_DRAM_DELETE_CFG.IPT0[0x13c]=0x7083ff
IPT_PDQ_DTQ_FC_ENABLE(0).IPT0[0x114]=4
IPT_PDQ_DTQ_FC_ENABLE(1).IPT0[0x115]=2
IPT_PDQ_DTQ_MIX_FC_ENABLE(0).IPT0[0x116]=0
IPT_PDQ_DTQ_MIX_FC_ENABLE(1).IPT0[0x117]=0
IPT_PDQ_DTQ_SRAM_FC_ENABLE(0).IPT0[0x118]=0
IPT_PDQ_DTQ_SRAM_FC_ENABLE(1).IPT0[0x119]=0
IPT_PDQ_OCB_CFG(0).IPT0[0x138]=0x5783ff
IPT_PDQ_OCB_DTQ_FC_ENABLE(0).IPT0[0x11a]=0
IPT_PDQ_PRIOIRTY_DEBUG(0).IPT0[0x142]=0
IPT_PDQ_PRIOIRTY_DEBUG(1).IPT0[0x143]=0
IPT_PDQ_PRIOIRTY_DEBUG(2).IPT0[0x144]=0x4c0000
IPT_PDQ_QUEUE_DEBUG(0).IPT0[0x15a]=0
IPT_PDQ_QUEUE_DEBUG(1).IPT0[0x15b]=0x29000042000
IPT_PDQ_QUEUE_DEBUG(2).IPT0[0x15c]=0
IPT_PDQ_QUEUE_DEBUG(3).IPT0[0x15d]=0
IPT_PDQ_QUEUE_DEBUG(4).IPT0[0x15e]=0
IPT_PDQ_QUEUE_DEBUG(5).IPT0[0x15f]=0
IPT_PDQ_SRAM_DELETE_CFG.IPT0[0x13b]=0xc8
IPT_PDQ_S_2D_CFG(0).IPT0[0x139]=0x3ff
IPT_PDQ_S_2D_CFG(1).IPT0[0x13a]=0x2b3c4d5e3ff
IPT_PDQ_S_2D_DEBUG(0).IPT0[0x140]=0
IPT_PDQ_S_2D_DEBUG(1).IPT0[0x141]=0
IPT_PDQ_S_2D_GLB_DEBUG.IPT0[0x13f]=0x96a5
IPT_RDF_CONFIG.IPT0[0x123]=0x2020057f050505
IPT_RDF_DEBUG(0).IPT0[0x164]=0x70d336c7f0d336c7c7b12084830000600
IPT_RDF_DEBUG(1).IPT0[0x165]=0
IPT_RDF_DEBUG(2).IPT0[0x166]=0
IPT_RDF_DEBUG(3).IPT0[0x167]=0
IPT_RDF_GLB_DEBUG.IPT0[0x168]=0xa2e48f62411800000000000000a4000
IPT_READ_FIFO_MIX_DTQ_FC_ENABLE.IPT0[0x112]=8
IPT_READ_FIFO_SRAM_DTQ_FC_ENABLE.IPT0[0x113]=8
IPT_REG_0041.IPT0[0x41]=0
IPT_REG_00C2.IPT0[0xc2]=0x10
IPT_REG_00C3.IPT0[0xc3]=1
IPT_REG_00C4.IPT0[0xc4]=0
IPT_REG_00C5.IPT0[0xc5]=0x786df
IPT_REG_00C6.IPT0[0xc6]=0x53
IPT_RESERVED_MTCD.IPT0[0xae]=0x30
IPT_RESERVED_MTCP.IPT0[0xad]=0x300000600000000
IPT_RESERVED_SPARE_0.IPT0[0x90]=0xffffffff
IPT_RESERVED_SPARE_1.IPT0[0x91]=0xffffffff
IPT_RESERVED_SPARE_2.IPT0[0x92]=0
IPT_RESERVED_SPARE_3.IPT0[0x93]=0
IPT_RRF_CONFIG.IPT0[0x122]=0x4000100f802b2b2b
IPT_RRF_FC_TH.IPT0[0x11f]=0x780500230169f1efb17c7bf1408c046787bcc5e1ef45
IPT_SBUS_BROADCAST_ID.IPT0[0x86]=0x7ff
IPT_SBUS_LAST_IN_CHAIN.IPT0[0x87]=0
IPT_SCS_DEBUG(0).IPT0[0x158]=0
IPT_SCS_DEBUG(1).IPT0[0x159]=0
IPT_SHAPER_DTQ_FC_ENABLE(0).IPT0[0x11b]=0
IPT_SHAPER_DTQ_FC_ENABLE(1).IPT0[0x11c]=0
IPT_SHAPER_DTQ_FC_ENABLE(2).IPT0[0x11d]=0
IPT_SHAPER_GENERAL_CONFIG.IPT0[0x107]=0x7eb
IPT_SHAPER_STATUS.IPT0[0x13d]=0x3ff
IPT_SPECIAL_CLOCK_CONTROLS.IPT0[0xc1]=2
IPT_SRAM_RRF_DEBUG(0).IPT0[0x160]=0xa000
IPT_SRAM_RRF_DEBUG(1).IPT0[0x161]=0
IPT_SRAM_RRF_DEBUG(2).IPT0[0x162]=0
IPT_SRAM_RRF_GLB_DEBUG.IPT0[0x163]=0x1c34cdb63c34cdb631ec48358000000000000000
IPT_TC_DEBUG(0).IPT0[0x150]=0
IPT_TC_DEBUG(1).IPT0[0x151]=0
IPT_TC_DEBUG(2).IPT0[0x152]=0
IPT_TC_DEBUG(3).IPT0[0x153]=0
IPT_TC_DEBUG(4).IPT0[0x154]=0
IPT_TC_DEBUG(5).IPT0[0x155]=0
IPT_TC_DEBUG(6).IPT0[0x156]=0
IPT_TC_DEBUG(7).IPT0[0x157]=0
IPT_WFQ_CFG(0).IPT0[0x124]=0x6000040
IQM_ECC_1B_ERR_CNT.IQM0[0x94]=0
IQM_ECC_2B_ERR_CNT.IQM0[0x96]=0
IQM_ECC_ERR_1B_MONITOR_MEM_MASK.IQM0[0x9a]=0x3f
IQM_ECC_ERR_2B_MONITOR_MEM_MASK.IQM0[0x9c]=0x3f
IQM_ECC_INTERRUPT_REGISTER.IQM0[0x7]=0
IQM_ECC_INTERRUPT_REGISTER_MASK.IQM0[0x17]=0
IQM_ECC_INTERRUPT_REGISTER_TEST.IQM0[0x1f]=0
IQM_ENABLE_DYNAMIC_MEMORY_ACCESS.IQM0[0x84]=0
IQM_GTIMER_CONFIGURATION.IQM0[0x89]=0
IQM_GTIMER_CYCLE.IQM0[0x88]=0x3b9aca00
IQM_INDIRECT_COMMAND.IQM0[0x80]=0xe000002
IQM_INDIRECT_COMMAND_ADDRESS.IQM0[0x81]=0x40400
IQM_INDIRECT_COMMAND_RD_DATA.IQM0[0x60]=0x4000000100
IQM_INDIRECT_COMMAND_WR_DATA.IQM0[0x20]=0
IQM_INDIRECT_FORCE_BUBBLE.IQM0[0x83]=0x20019
IQM_INTERRUPT_MASK_REGISTER.IQM0[0x10]=0
IQM_INTERRUPT_REGISTER.IQM0[0x0]=0
IQM_INTERRUPT_REGISTER_TEST.IQM0[0x18]=0
IQM_LATENCY_CTR.IQM0[0x202]=0
IQM_LATENCY_SETTINGS.IQM0[0x201]=0x1bfff8000
IQM_PCMI_0.IQM0[0xb0]=0x3b9aca00
IQM_PCMI_1.IQM0[0xb3]=0x3b9aca00
IQM_PCMI_2.IQM0[0xb6]=0x3b9aca00
IQM_PCMI_3.IQM0[0xb9]=0x3b9aca00
IQM_PCMI_4.IQM0[0xbc]=0x3b9aca00
IQM_PCMI_0_S.IQM0[0xb1]=0
IQM_PCMI_0_T.IQM0[0xb2]=0
IQM_PCMI_1_S.IQM0[0xb4]=0
IQM_PCMI_1_T.IQM0[0xb5]=0
IQM_PCMI_2_S.IQM0[0xb7]=0
IQM_PCMI_2_T.IQM0[0xb8]=0
IQM_PCMI_3_S.IQM0[0xba]=0
IQM_PCMI_3_T.IQM0[0xbb]=0
IQM_PCMI_4_S.IQM0[0xbd]=0
IQM_PCMI_4_T.IQM0[0xbe]=0
IQM_PERFORMANCE_DEBUG.IQM0[0x204]=0xc05e0675
IQM_QM_RPRT_FIFO_STATUS_DEBUG.IQM0[0x203]=0x100
IQM_QM_RPRT_FIFO_THS.IQM0[0x200]=0xa1e50
IQM_REG_0041.IQM0[0x41]=0
IQM_REG_0205.IQM0[0x205]=0x230
IQM_REG_0206.IQM0[0x206]=0
IQM_REG_0207.IQM0[0x207]=0
IQM_REG_00C2.IQM0[0xc2]=0x10
IQM_RESERVED_MTCD.IQM0[0xae]=0x30
IQM_RESERVED_MTCP.IQM0[0xad]=0x300000600000000
IQM_RESERVED_SPARE_0.IQM0[0x90]=0xffffffff
IQM_RESERVED_SPARE_1.IQM0[0x91]=0xffffffff
IQM_RESERVED_SPARE_2.IQM0[0x92]=0
IQM_RESERVED_SPARE_3.IQM0[0x93]=0
IQM_SBUS_BROADCAST_ID.IQM0[0x86]=0x7ff
IQM_SBUS_LAST_IN_CHAIN.IQM0[0x87]=0
IQM_SPECIAL_CLOCK_CONTROLS.IQM0[0xc1]=2
IRE_ALIGN_DEBUG.IRE0[0x145]=0x140920028124a00000001589d8a744000000140327e74b000000140327e74b00000000000000000000001589d8a744
IRE_ALLIGNER_CONFIGURATION.IRE0[0x148]=1
IRE_AUTO_DOC_NAME_2.IRE0[0x10e]=0
IRE_BAD_REASSEMBLY_CONTEXT_PACKET_COUNTER.IRE0[0x137]=0
IRE_BLAME_REGISTER.IRE0[0x15f]=0
IRE_CPU_CHANNEL_IS_TDM.IRE0[0x111]=0
IRE_CPU_CREDITS_COUNTER.IRE0[0x13d]=0x1e517353
IRE_CPU_PACKET_COUNTER.IRE0[0x132]=0x3013800
IRE_CPU_SHAPER.IRE0[0x11a]=0x4000200
IRE_DYNAMIC_CONFIGURATION.IRE0[0x10b]=1
IRE_ECC_1B_ERR_CNT.IRE0[0x94]=0x8000
IRE_ECC_2B_ERR_CNT.IRE0[0x96]=0x8000
IRE_ECC_ERR_1B_MONITOR_MEM_MASK.IRE0[0x9a]=0x1ffffff
IRE_ECC_ERR_2B_MONITOR_MEM_MASK.IRE0[0x9c]=0x1ffffff
IRE_ECC_INTERRUPT_REGISTER.IRE0[0x7]=0
IRE_ECC_INTERRUPT_REGISTER_MASK.IRE0[0x17]=0
IRE_ECC_INTERRUPT_REGISTER_TEST.IRE0[0x1f]=0
IRE_EGQ_INTERFACE_COUNTER.IRE0[0x141]=0
IRE_ENABLE_DYNAMIC_MEMORY_ACCESS.IRE0[0x84]=1
IRE_EVENTOR_CREDITS_COUNTER.IRE0[0x13f]=0
IRE_EVENTOR_PACKET_COUNTER.IRE0[0x134]=0
IRE_EVENTOR_REASSEMBLY_CONTEXT_CONFIGURATION.IRE0[0x114]=0xff
IRE_GTIMER_CONFIGURATION.IRE0[0x89]=2
IRE_GTIMER_CYCLE.IRE0[0x88]=0x23c34600
IRE_IHB_DEBUG_REGISTER_1.IRE0[0x149]=0x1180
IRE_IHB_DEBUG_REGISTER_2.IRE0[0x14a]=0x300000100180044620e09512a0bb2a9672000008002e0222f807fa000200000000000000000000000000000000000000000000f0000000000000000000000000
IRE_IHB_INTERFACE_COUNTER.IRE0[0x143]=0x4e12d4fdc
IRE_IHB_TM_CMD_HALF_1.IRE0[0x14b]=0x8000002e4fd1800000003c0090000001000000638020000000000000000000000000000000000000000000000000000001000000000000000000000006c0001
IRE_IHB_TM_CMD_HALF_2.IRE0[0x14c]=0xa6f133ca5368c9802c00200111740008
IRE_IHP_DEBUG_REGISTER.IRE0[0x14d]=0xbb2e8d3be3c20085531f9b5bcde26794a6d1981000002
IRE_IHP_FIFO_STATUS.IRE0[0x11f]=0x201
IRE_IHP_FIFO_THRESHOLDS.IRE0[0x11e]=0x817af
IRE_IHP_INTERFACE_COUNTER.IRE0[0x142]=0x4e12d4fe10000000000000000000207cc406f964a
IRE_IHP_SHAPER.IRE0[0x11d]=0x6403f00
IRE_IHP_STATUS_REGISTER.IRE0[0x125]=0xb800000
IRE_INDIRECT_COMMAND.IRE0[0x80]=0xe000002
IRE_INDIRECT_COMMAND_ADDRESS.IRE0[0x81]=0x342b
IRE_INDIRECT_COMMAND_RD_DATA.IRE0[0x60]=0
IRE_INDIRECT_COMMAND_WIDE_MEM.IRE0[0x41]=0
IRE_INDIRECT_COMMAND_WR_DATA.IRE0[0x20]=0x4000003fffe0400008e79
IRE_INDIRECT_FORCE_BUBBLE.IRE0[0x83]=0x20019
IRE_INTERFACE_BASE_ADDR_CONFIGURATION.IRE0[0x110]=0x2e016009000002801300
IRE_INTERNAL_INTERFACE_ERROR_INTERRUPT_REGISTER.IRE0[0x103]=0
IRE_INTERNAL_INTERFACE_ERROR_INTERRUPT_REGISTER_MASK.IRE0[0x104]=0
IRE_INTERNAL_INTERFACE_ERROR_INTERRUPT_REGISTER_TEST.IRE0[0x105]=0
IRE_INTERRUPT_MASK_REGISTER.IRE0[0x10]=0
IRE_INTERRUPT_REGISTER.IRE0[0x0]=0
IRE_INTERRUPT_REGISTER_TEST.IRE0[0x18]=0
IRE_INVALID_INTERFACE.IRE0[0x129]=0
IRE_IPV6_SR_CONFIGURATION.IRE0[0x119]=0x4a86dd2b
IRE_IPV6_SR_DEBUG.IRE0[0x144]=0x110000
IRE_IRE_REGISTER_0.IRE0[0x10f]=0
IRE_LAST_CONTEXT_MAPPING.IRE0[0x12a]=0x2020
IRE_LAST_RECEIVED_PACKET_RECORD.IRE0[0x147]=0
IRE_NETWORK_INTERFACE_SHAPER.IRE0[0x11c]=0xf0003ff00
IRE_NIF_CREDITS_COUNTER.IRE0[0x139]=0x1400263fd6
IRE_NIF_ERROR_INTERRUPT_REGISTER.IRE0[0x106]=2
IRE_NIF_ERROR_INTERRUPT_REGISTER_MASK.IRE0[0x107]=0
IRE_NIF_ERROR_INTERRUPT_REGISTER_TEST.IRE0[0x108]=0
IRE_NIF_PACKET_COUNTER.IRE0[0x12d]=0x4de2c1666
IRE_OAMP_CREDITS_COUNTER.IRE0[0x140]=0
IRE_OAMP_PACKET_COUNTER.IRE0[0x135]=0
IRE_OAMP_REASSEMBLY_CONTEXT_CONFIGURATION.IRE0[0x113]=0xe828
IRE_OLP_CREDITS_COUNTER.IRE0[0x13e]=0x1a8a
IRE_OLP_PACKET_COUNTER.IRE0[0x133]=0x1a6
IRE_OLP_REASSEMBLY_CONTEXT_CONFIGURATION.IRE0[0x112]=0xf029
IRE_PACKET_EDIT_FIFO_STATUS.IRE0[0x123]=1
IRE_PACKET_EDIT_FIFO_THRESHOLDS.IRE0[0x122]=0x17c4be2
IRE_PARITY_ERR_CNT.IRE0[0x98]=0x8000
IRE_PAR_ERR_MEM_MASK.IRE0[0xa0]=1
IRE_PCMI_0.IRE0[0xb0]=0x3b9aca00
IRE_PCMI_1.IRE0[0xb3]=0x3b9aca00
IRE_PCMI_2.IRE0[0xb6]=0x3b9aca00
IRE_PCMI_3.IRE0[0xb9]=0x3b9aca00
IRE_PCMI_4.IRE0[0xbc]=0x3b9aca00
IRE_PCMI_0_S.IRE0[0xb1]=0
IRE_PCMI_0_T.IRE0[0xb2]=0
IRE_PCMI_1_S.IRE0[0xb4]=0
IRE_PCMI_1_T.IRE0[0xb5]=0
IRE_PCMI_2_S.IRE0[0xb7]=0
IRE_PCMI_2_T.IRE0[0xb8]=0
IRE_PCMI_3_S.IRE0[0xba]=0
IRE_PCMI_3_T.IRE0[0xbb]=0
IRE_PCMI_4_S.IRE0[0xbd]=0
IRE_PCMI_4_T.IRE0[0xbe]=0
IRE_PEF_STATUS_REGISTER.IRE0[0x124]=0xc000000
IRE_PPLB_CFG_LSB.IRE0[0x12b]=0
IRE_PPLB_CFG_MSB.IRE0[0x12c]=0
IRE_RCYH_CREDITS_COUNTER.IRE0[0x13a]=0
IRE_RCYH_PACKET_COUNTER.IRE0[0x12e]=0
IRE_RCYL_CREDITS_COUNTER.IRE0[0x13b]=0
IRE_RCYL_PACKET_COUNTER.IRE0[0x12f]=0
IRE_RCY_CONFIGURATIONS.IRE0[0x117]=0
IRE_RCY_INTERFACE_ERROR_INTERRUPT_REGISTER.IRE0[0x100]=0
IRE_RCY_INTERFACE_ERROR_INTERRUPT_REGISTER_MASK.IRE0[0x101]=0
IRE_RCY_INTERFACE_ERROR_INTERRUPT_REGISTER_TEST.IRE0[0x102]=0
IRE_RECYCLING_SHAPER.IRE0[0x11b]=0
IRE_REGISTER_INTERFACE_PACKET_CONTROL.IRE0[0x126]=0
IRE_REGISTER_INTERFACE_PACKET_COUNTER.IRE0[0x136]=0
IRE_REGISTER_INTERFACE_PACKET_DATA_BITS_1023_512.IRE0[0x128]=0
IRE_REGISTER_INTERFACE_PACKET_DATA_BITS_511_0.IRE0[0x127]=0
IRE_REG_00C2.IRE0[0xc2]=0x10
IRE_REG_00C4.IRE0[0xc4]=0
IRE_REG_00C5.IRE0[0xc5]=0x786df
IRE_REG_00C6.IRE0[0xc6]=0x53
IRE_REG_REASSEMBLY_CONTEXT_CONFIGURATION.IRE0[0x115]=0x3d3d
IRE_RESERVED_MTCD.IRE0[0xae]=0x30
IRE_RESERVED_MTCP.IRE0[0xad]=0x300000600000000
IRE_RESERVED_SPARE_0.IRE0[0x90]=0xffffffff
IRE_RESERVED_SPARE_1.IRE0[0x91]=0xffffffff
IRE_RESERVED_SPARE_2.IRE0[0x92]=0
IRE_RESERVED_SPARE_3.IRE0[0x93]=0
IRE_RESET_STATUS_REGISTER.IRE0[0x109]=1
IRE_SAT_CREDITS_COUNTER.IRE0[0x13c]=0
IRE_SAT_PACKET_COUNTER.IRE0[0x130]=0
IRE_SAT_TDM_PACKET_COUNTER.IRE0[0x131]=0
IRE_SBUS_BROADCAST_ID.IRE0[0x86]=0x7ff
IRE_SBUS_LAST_IN_CHAIN.IRE0[0x87]=0
IRE_SPB_SHAPER.IRE0[0x146]=0x320001
IRE_SPECIAL_CLOCK_CONTROLS.IRE0[0xc1]=2
IRE_STATIC_CONFIGURATION.IRE0[0x10a]=0x1ff
IRE_TAG_SWAP_CONFIGURATION.IRE0[0x118]=0x4000003fffe040224fd8c
IRE_TDM_CONFIGURATIONS.IRE0[0x116]=0x20041
IRE_TDM_CONTEXT_DROP_LSB.IRE0[0x10d]=0
IRE_TDM_CONTEXT_DROP_MSB.IRE0[0x10c]=0
IRE_TDM_PACKET_COUNTER.IRE0[0x138]=0
IRE_WORD_FIFO_STATUS.IRE0[0x121]=0x198001
IRE_WORD_FIFO_THRESHOLDS.IRE0[0x120]=0x17c4be2
ITPPD_BIG_LAT_CNI_CNTR.ITPPD0[0x20e]=0
ITPPD_DELETED_LAT_PKTS_CNT.ITPPD0[0x20d]=0
ITPPD_ECC_1B_ERR_CNT.ITPPD0[0x94]=0x1006e0000
ITPPD_ECC_2B_ERR_CNT.ITPPD0[0x96]=0x3003d0000
ITPPD_ECC_ERR_1B_MONITOR_MEM_MASK.ITPPD0[0x9a]=7
ITPPD_ECC_ERR_2B_MONITOR_MEM_MASK.ITPPD0[0x9c]=7
ITPPD_ECC_INTERRUPT_REGISTER.ITPPD0[0x7]=0
ITPPD_ECC_INTERRUPT_REGISTER_MASK.ITPPD0[0x17]=0
ITPPD_ECC_INTERRUPT_REGISTER_TEST.ITPPD0[0x1f]=0
ITPPD_ENABLE_DYNAMIC_MEMORY_ACCESS.ITPPD0[0x84]=0
ITPPD_FLOW_PROFILE_VALID_BITMAP.ITPPD0[0x253]=0
ITPPD_GTIMER_CONFIGURATION.ITPPD0[0x89]=0
ITPPD_GTIMER_CYCLE.ITPPD0[0x88]=0x3b9aca00
ITPPD_INCOMING_PACKET_CNTR.ITPPD0[0x20f]=0
ITPPD_INDIRECT_COMMAND.ITPPD0[0x80]=0xe000002
ITPPD_INDIRECT_COMMAND_ADDRESS.ITPPD0[0x81]=0x3002d
ITPPD_INDIRECT_COMMAND_RD_DATA.ITPPD0[0x60]=0x3bfffe69b716eb7cdbbefdee7bea5ea74f51de14cfe76f5fffbcbd59bfedbf3fffaffcf3904033f8d6ea6c9e6c2de8df25169ad5ebb66bd7efc77bbee7189c3c94e
ITPPD_INDIRECT_COMMAND_WR_DATA.ITPPD0[0x20]=0x1000000000000000000000000000000000000000000000000000000000000000000000000000000000000038000001c0000000000020000000800000000
ITPPD_INDIRECT_FORCE_BUBBLE.ITPPD0[0x83]=0x20019
ITPPD_INTERRUPT_MASK_REGISTER.ITPPD0[0x10]=0
ITPPD_INTERRUPT_REGISTER.ITPPD0[0x0]=0
ITPPD_INTERRUPT_REGISTER_TEST.ITPPD0[0x18]=0
ITPPD_ITPP_GENERAL_CFG.ITPPD0[0x204]=0x4904904904904b1a61fffffffe
ITPPD_LAST_GENERATED_HDR.ITPPD0[0x24b]=0
ITPPD_LAST_GENERATED_VALUES.ITPPD0[0x239]=0
ITPPD_LAST_RECEIVED_ATTRIBUTES.ITPPD0[0x234]=0
ITPPD_LAST_RECEIVED_HEADER_0.ITPPD0[0x214]=0
ITPPD_LAST_RECEIVED_HEADER_1.ITPPD0[0x224]=0
ITPPD_MAPPING_FWD_INFO_TO_EN_TERM.ITPPD0[0x210]=0x7f7f7f7f7f7f7f7f7f7f7f7f7f7f7f7f
ITPPD_MAPPING_QUEUE_TYPE_TO_SNIFF_PACKET.ITPPD0[0x203]=0xe
ITPPD_MAX_LATENCY_LAT_PKT.ITPPD0[0x209]=0
ITPPD_PACKET_LATENCY_FORMAT.ITPPD0[0x208]=0x10
ITPPD_REG_0041.ITPPD0[0x41]=0
ITPPD_REG_00C2.ITPPD0[0xc2]=0x10
ITPPD_REG_00C6.ITPPD0[0xc6]=0x53
ITPPD_RESERVED_MTCD.ITPPD0[0xae]=0x30
ITPPD_RESERVED_MTCP.ITPPD0[0xad]=0x300000600000000
ITPPD_RESERVED_SPARE_0.ITPPD0[0x90]=0xffffffff
ITPPD_RESERVED_SPARE_1.ITPPD0[0x91]=0xffffffff
ITPPD_RESERVED_SPARE_2.ITPPD0[0x92]=0
ITPPD_RESERVED_SPARE_3.ITPPD0[0x93]=0
ITPPD_SBUS_BROADCAST_ID.ITPPD0[0x86]=0x7ff
ITPPD_SBUS_LAST_IN_CHAIN.ITPPD0[0x87]=0
ITPPD_SPECIAL_CLOCK_CONTROLS.ITPPD0[0xc1]=2
ITPPD_STAMPING_FABRIC_HEADER_ENABLE.ITPPD0[0x200]=0xd
ITPPD_SYSTEM_HEADERS_PPH.ITPPD0[0x24a]=0
ITPPD_VOQ_TC_MAP.ITPPD0[0x201]=0
ITPP_BIG_LAT_CNI_CNTR.ITPP0[0x20e]=0
ITPP_DELETED_LAT_PKTS_CNT.ITPP0[0x20d]=0
ITPP_ECC_1B_ERR_CNT.ITPP0[0x94]=0
ITPP_ECC_2B_ERR_CNT.ITPP0[0x96]=0
ITPP_ECC_ERR_1B_MONITOR_MEM_MASK.ITPP0[0x9a]=7
ITPP_ECC_ERR_2B_MONITOR_MEM_MASK.ITPP0[0x9c]=7
ITPP_ECC_INTERRUPT_REGISTER.ITPP0[0x7]=0
ITPP_ECC_INTERRUPT_REGISTER_MASK.ITPP0[0x17]=0
ITPP_ECC_INTERRUPT_REGISTER_TEST.ITPP0[0x1f]=0
ITPP_ENABLE_DYNAMIC_MEMORY_ACCESS.ITPP0[0x84]=0
ITPP_FLOW_PROFILE_VALID_BITMAP.ITPP0[0x253]=0
ITPP_GTIMER_CONFIGURATION.ITPP0[0x89]=0
ITPP_GTIMER_CYCLE.ITPP0[0x88]=0x3b9aca00
ITPP_INCOMING_PACKET_CNTR.ITPP0[0x20f]=0xe1a66ee8
ITPP_INDIRECT_COMMAND.ITPP0[0x80]=0xe000002
ITPP_INDIRECT_COMMAND_ADDRESS.ITPP0[0x81]=0x3002d
ITPP_INDIRECT_COMMAND_RD_DATA.ITPP0[0x60]=0x562681c7388885d436043801221109031804cc187328bd802498024b241b84bb502d08421db10c202f24a405064059d8c02000131088172500b2704981220583482
ITPP_INDIRECT_COMMAND_WR_DATA.ITPP0[0x20]=0x1000000000000000000000000000000000000000000000000000000000000000000000000000000000000038000001c0000000000020000000800000000
ITPP_INDIRECT_FORCE_BUBBLE.ITPP0[0x83]=0x20019
ITPP_INTERRUPT_MASK_REGISTER.ITPP0[0x10]=0
ITPP_INTERRUPT_REGISTER.ITPP0[0x0]=0
ITPP_INTERRUPT_REGISTER_TEST.ITPP0[0x18]=0
ITPP_ITPP_GENERAL_CFG.ITPP0[0x204]=0x4904904904904b1a61fffffffe
ITPP_LAST_GENERATED_HDR.ITPP0[0x24b]=0xc50a0b78ea976541a4f7ed01bb15c78b81c4db823f801008009ad10000010108
ITPP_LAST_GENERATED_VALUES.ITPP0[0x239]=0x2346307800200100088b81c12e867f7739743800001000500445d00ff4000400000000000010aa63f36b79bc4cf294da330200000410008a100bb0c98e80006e0ce6
ITPP_LAST_RECEIVED_ATTRIBUTES.ITPP0[0x234]=0x1f4457739dd34001c200010001fffff00613
ITPP_LAST_RECEIVED_HEADER_0.ITPP0[0x214]=0x300000100200044630e0a8e15fbb9ce7f8000008003002230007fa0002000000000000cc2de0f83a78de26794a6d19810000050800450005dce1ef40003306a1
ITPP_LAST_RECEIVED_HEADER_1.ITPP0[0x224]=0xdf924b52fc0a0b761e01bbca2f26ac09a83b65d22280100ccbd4dd00000101080aaf3ff7a203c13688c7c07f2dee1b0a735dd1e5ea5be6b71f4f0f887c436484
ITPP_MAPPING_FWD_INFO_TO_EN_TERM.ITPP0[0x210]=0x7f7f7f7f7f7f7f7f7f7f7f7f7f7f7f7f
ITPP_MAPPING_QUEUE_TYPE_TO_SNIFF_PACKET.ITPP0[0x203]=0xe
ITPP_MAX_LATENCY_LAT_PKT.ITPP0[0x209]=0
ITPP_PACKET_LATENCY_FORMAT.ITPP0[0x208]=0x10
ITPP_REG_0041.ITPP0[0x41]=0
ITPP_REG_00C2.ITPP0[0xc2]=0x10
ITPP_REG_00C6.ITPP0[0xc6]=0x53
ITPP_RESERVED_MTCD.ITPP0[0xae]=0x30
ITPP_RESERVED_MTCP.ITPP0[0xad]=0x300000600000000
ITPP_RESERVED_SPARE_0.ITPP0[0x90]=0xffffffff
ITPP_RESERVED_SPARE_1.ITPP0[0x91]=0xffffffff
ITPP_RESERVED_SPARE_2.ITPP0[0x92]=0
ITPP_RESERVED_SPARE_3.ITPP0[0x93]=0
ITPP_SBUS_BROADCAST_ID.ITPP0[0x86]=0x7ff
ITPP_SBUS_LAST_IN_CHAIN.ITPP0[0x87]=0
ITPP_SPECIAL_CLOCK_CONTROLS.ITPP0[0xc1]=2
ITPP_STAMPING_FABRIC_HEADER_ENABLE.ITPP0[0x200]=0xd
ITPP_SYSTEM_HEADERS_PPH.ITPP0[0x24a]=0
ITPP_VOQ_TC_MAP.ITPP0[0x201]=0
KAPS_BB_GLOBAL_CONFIG(0).KAPS0[0x129]=0
KAPS_BB_GLOBAL_CONFIG(1).KAPS0[0x12a]=0
KAPS_BB_GLOBAL_CONFIG(2).KAPS0[0x12b]=0
KAPS_BB_GLOBAL_CONFIG(3).KAPS0[0x12c]=0
KAPS_BB_GLOBAL_CONFIG(4).KAPS0[0x12d]=0
KAPS_BB_GLOBAL_CONFIG(5).KAPS0[0x12e]=0
KAPS_BB_GLOBAL_CONFIG(6).KAPS0[0x12f]=0
KAPS_BB_GLOBAL_CONFIG(7).KAPS0[0x130]=0
KAPS_BB_GLOBAL_CONFIG(8).KAPS0[0x131]=0
KAPS_BB_GLOBAL_CONFIG(9).KAPS0[0x132]=0
KAPS_BB_GLOBAL_CONFIG(10).KAPS0[0x133]=0
KAPS_BB_GLOBAL_CONFIG(11).KAPS0[0x134]=0
KAPS_BB_GLOBAL_CONFIG(12).KAPS0[0x135]=0
KAPS_BB_GLOBAL_CONFIG(13).KAPS0[0x136]=0
KAPS_BB_GLOBAL_CONFIG(14).KAPS0[0x137]=0
KAPS_BB_GLOBAL_CONFIG(15).KAPS0[0x138]=0
KAPS_BB_LAST_SELECTED.KAPS0[0x13d]=0x40246430f520100680d06cbc09000b08ff3e00c2fc00002c
KAPS_BRR_DEBUG(0).KAPS0[0x139]=0xd23a8b7
KAPS_BRR_DEBUG(1).KAPS0[0x13a]=0x2fdffbdfb9dbbff
KAPS_ECC_1B_ERR_CNT.KAPS0[0x94]=0
KAPS_ECC_2B_ERR_CNT.KAPS0[0x96]=0
KAPS_ECC_ERR_1B_MONITOR_MEM_MASK.KAPS0[0x9a]=0x3ffff
KAPS_ECC_ERR_2B_MONITOR_MEM_MASK.KAPS0[0x9c]=0x3ffff
KAPS_ECC_INTERRUPT_REGISTER.KAPS0[0x7]=0
KAPS_ECC_INTERRUPT_REGISTER_MASK.KAPS0[0x17]=0
KAPS_ECC_INTERRUPT_REGISTER_TEST.KAPS0[0x1f]=0
KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS.KAPS0[0x84]=0x3fffff
KAPS_GTIMER_CONFIGURATION.KAPS0[0x89]=0
KAPS_GTIMER_CYCLE.KAPS0[0x88]=0x3b9aca00
KAPS_INDIRECT_COMMAND.KAPS0[0x80]=0x58200002
KAPS_INDIRECT_COMMAND_ADDRESS.KAPS0[0x81]=0x40001
KAPS_INDIRECT_COMMAND_RD_DATA.KAPS0[0x60]=0x6bf9
KAPS_INDIRECT_COMMAND_WR_DATA.KAPS0[0x20]=0x800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
KAPS_INDIRECT_FORCE_BUBBLE.KAPS0[0x83]=0x20019
KAPS_INDIRECT_WR_MASK.KAPS0[0x40]=0xffff
KAPS_INTERRUPT_MASK_REGISTER.KAPS0[0x10]=0
KAPS_INTERRUPT_REGISTER.KAPS0[0x0]=0
KAPS_INTERRUPT_REGISTER_TEST.KAPS0[0x18]=0
KAPS_PCMI_0.KAPS0[0xb0]=0x3b9aca00
KAPS_PCMI_1.KAPS0[0xb3]=0x3b9aca00
KAPS_PCMI_2.KAPS0[0xb6]=0x3b9aca00
KAPS_PCMI_3.KAPS0[0xb9]=0x3b9aca00
KAPS_PCMI_4.KAPS0[0xbc]=0x3b9aca00
KAPS_PCMI_0_S.KAPS0[0xb1]=0
KAPS_PCMI_0_T.KAPS0[0xb2]=0
KAPS_PCMI_1_S.KAPS0[0xb4]=0
KAPS_PCMI_1_T.KAPS0[0xb5]=0
KAPS_PCMI_2_S.KAPS0[0xb7]=0
KAPS_PCMI_2_T.KAPS0[0xb8]=0
KAPS_PCMI_3_S.KAPS0[0xba]=0
KAPS_PCMI_3_T.KAPS0[0xbb]=0
KAPS_PCMI_4_S.KAPS0[0xbd]=0
KAPS_PCMI_4_T.KAPS0[0xbe]=0
KAPS_REG_0041.KAPS0[0x41]=0
KAPS_REG_0149.KAPS0[0x149]=0
KAPS_REG_00C2.KAPS0[0xc2]=0x10
KAPS_REG_014D.KAPS0[0x14d]=0xc1700000000
KAPS_RESERVED_MTCD.KAPS0[0xae]=0x30
KAPS_RESERVED_MTCP.KAPS0[0xad]=0x300000600000000
KAPS_RESERVED_SPARE_0.KAPS0[0x90]=0xffffffff
KAPS_RESERVED_SPARE_1.KAPS0[0x91]=0xffffffff
KAPS_RESERVED_SPARE_2.KAPS0[0x92]=0
KAPS_RESERVED_SPARE_3.KAPS0[0x93]=0
KAPS_REVISION.KAPS0[0x100]=0x40004
KAPS_RPB_DEBUG(0).KAPS0[0x111]=0x1b68a00170000016c0a80afd000000000000000000073fffd3cfffbffdbffffdffefffff9ffffffffbffdddf
KAPS_RPB_DEBUG(1).KAPS0[0x112]=0x3fe05ffbefffdfffeffe7ffffffbffffbfffffbffffff821fffffefff9fdff9ffcffdfffd47ffffd7cfff7fcd7
KAPS_RPB_GLOBAL_CONFIG(0).KAPS0[0x101]=0x10
KAPS_RPB_GLOBAL_CONFIG(1).KAPS0[0x102]=0x10
KAPS_RPB_MEM_CONFIG(0).KAPS0[0x103]=0
KAPS_RPB_MEM_CONFIG(1).KAPS0[0x104]=0
KAPS_RPB_TCAM_A_SCAN_PAUSE(0).KAPS0[0x10b]=0
KAPS_RPB_TCAM_A_SCAN_PAUSE(1).KAPS0[0x10c]=0
KAPS_RPB_TCAM_B_SCAN_PAUSE(0).KAPS0[0x10d]=0
KAPS_RPB_TCAM_B_SCAN_PAUSE(1).KAPS0[0x10e]=0
KAPS_RPB_TCAM_ECC_CONFIG(0).KAPS0[0x105]=0
KAPS_RPB_TCAM_ECC_CONFIG(1).KAPS0[0x106]=0
KAPS_RPB_TCAM_SCAN_CFGS(0).KAPS0[0x107]=0x16e2d
KAPS_RPB_TCAM_SCAN_CFGS(1).KAPS0[0x108]=0x16e2d
KAPS_RPB_TCAM_SCAN_INDEX(0).KAPS0[0x10f]=0x1d5bab
KAPS_RPB_TCAM_SCAN_INDEX(1).KAPS0[0x110]=0x1d93b2
KAPS_SBUS_BROADCAST_ID.KAPS0[0x86]=0x7ff
KAPS_SBUS_LAST_IN_CHAIN.KAPS0[0x87]=0
KAPS_SPECIAL_CLOCK_CONTROLS.KAPS0[0xc1]=2
MACT_APP_DB_TO_APP_DB_INDEX_MAP.MACT0[0x21f]=0x200000040
MACT_ECC_1B_ERR_CNT.MACT0[0x94]=0
MACT_ECC_2B_ERR_CNT.MACT0[0x96]=0
MACT_ECC_ERR_1B_MONITOR_MEM_MASK.MACT0[0x9a]=0x3ff
MACT_ECC_ERR_2B_MONITOR_MEM_MASK.MACT0[0x9c]=0x3ff
MACT_ECC_INTERRUPT_REGISTER.MACT0[0x7]=0
MACT_ECC_INTERRUPT_REGISTER_MASK.MACT0[0x17]=0
MACT_ECC_INTERRUPT_REGISTER_TEST.MACT0[0x1f]=0
MACT_ENABLE_DYNAMIC_MEMORY_ACCESS.MACT0[0x84]=7
MACT_GTIMER_CONFIGURATION.MACT0[0x89]=0
MACT_GTIMER_CYCLE.MACT0[0x88]=0x3b9aca00
MACT_INDIRECT_COMMAND.MACT0[0x80]=0x58200002
MACT_INDIRECT_COMMAND_ADDRESS.MACT0[0x81]=0x81630007
MACT_INDIRECT_COMMAND_RD_DATA.MACT0[0x60]=0x8d00000000000000000001e
MACT_INDIRECT_COMMAND_WR_DATA.MACT0[0x20]=2
MACT_INDIRECT_FORCE_BUBBLE.MACT0[0x83]=0x20019
MACT_INTERRUPT_MASK_REGISTER.MACT0[0x10]=0
MACT_INTERRUPT_REGISTER.MACT0[0x0]=0
MACT_INTERRUPT_REGISTER_TEST.MACT0[0x18]=0
MACT_IS_LARGE_EM.MACT0[0x219]=0x1000c
MACT_LARGE_EM_COUNTER_LIMIT_CONFIGURATION.MACT0[0x201]=0x1e1e16258000000
MACT_LARGE_EM_CPU_EVENT.MACT0[0x213]=0x217b09ec01600008088b80600c80014744d28ac24fb
MACT_LARGE_EM_DB_ENTRIES_COUNTER.MACT0[0x203]=0x9f
MACT_LARGE_EM_ERROR_DELETE_NON_EXIST_COUNTER.MACT0[0x236]=0
MACT_LARGE_EM_ERROR_LEARN_REQUEST_OVER_STRONGER_COUNTER.MACT0[0x234]=0
MACT_LARGE_EM_ERROR_REFRESH_REQUEST_OVER_STRONGER_COUNTER.MACT0[0x238]=0
MACT_LARGE_EM_ERROR_TRANSPLANT_REQUEST_OVER_STRONGER_COUNTER.MACT0[0x237]=0
MACT_LARGE_EM_EVENT_FIFO_CONFIGURATION.MACT0[0x224]=1
MACT_LARGE_EM_EVENT_FIFO_EVENT_COUNTER.MACT0[0x227]=0x3ddde2
MACT_LARGE_EM_EVENT_FIFO_EVENT_FIFO_ENTRY_COUNT.MACT0[0x226]=0
MACT_LARGE_EM_EVENT_FIFO_HIGH_THRESHOLD.MACT0[0x225]=0x7f
MACT_LARGE_EM_INTERRUPT_MASK_REGISTER.MACT0[0x12]=0
MACT_LARGE_EM_INTERRUPT_REGISTER.MACT0[0x2]=0
MACT_LARGE_EM_LELA_COUNTERS_A.MACT0[0x240]=0
MACT_LARGE_EM_LELA_COUNTERS_B.MACT0[0x241]=0
MACT_LARGE_EM_LELA_EXCEED_LIMIT_FID.MACT0[0x23f]=0
MACT_LARGE_EM_LELA_RXI_COUNTERS.MACT0[0x23c]=0
MACT_LARGE_EM_LELB_COUNTERS_A.MACT0[0x243]=0
MACT_LARGE_EM_LELB_COUNTERS_B.MACT0[0x244]=0
MACT_LARGE_EM_LELB_EXCEED_LIMIT_FID.MACT0[0x242]=0
MACT_LARGE_EM_LELB_RXI_COUNTERS.MACT0[0x23d]=0
MACT_LARGE_EM_MANAGEMENT_REQUEST_FIFO_PROPERTIES.MACT0[0x23b]=0x23000000
MACT_LARGE_EM_MNGMNT_REQ_CONFIGURATION.MACT0[0x200]=0
MACT_LARGE_EM_MNGMNT_REQ_COUNTERS_A.MACT0[0x204]=0
MACT_LARGE_EM_MNGMNT_REQ_COUNTERS_B.MACT0[0x205]=0
MACT_LARGE_EM_MNGMNT_REQ_COUNTERS_C.MACT0[0x206]=0
MACT_LARGE_EM_MNGMNT_REQ_EXCEED_LIMIT_ALLOWED_FID.MACT0[0x20b]=0
MACT_LARGE_EM_MNGMNT_REQ_EXCEED_LIMIT_FID.MACT0[0x20a]=0
MACT_LARGE_EM_MNGMNT_REQ_REQUEST_COUNTER.MACT0[0x208]=0x1d0
MACT_LARGE_EM_MNGMNT_REQ_REQUEST_FIFO_ENTRY_COUNT.MACT0[0x207]=0
MACT_LARGE_EM_MNGMNT_REQ_REQUEST_FIFO_WATERMARK.MACT0[0x209]=2
MACT_LARGE_EM_MRQ_CONFIGURATION.MACT0[0x223]=1
MACT_LARGE_EM_OLP_REQUEST_REQUEST.MACT0[0x20c]=0
MACT_LARGE_EM_OLP_REQUEST_TRIGGER.MACT0[0x212]=0
MACT_LARGE_EM_REPLY.MACT0[0x228]=0x207e09ec01600008088b80600c80014744d28ac24fb
MACT_LARGE_EM_REPLY_FIFO_CONFIGURATION.MACT0[0x22e]=0
MACT_LARGE_EM_REPLY_FIFO_ENTRY_COUNT.MACT0[0x231]=0
MACT_LARGE_EM_REPLY_FIFO_HIGH_THRESHOLD.MACT0[0x22f]=0x7f
MACT_LARGE_EM_REPLY_FIFO_REPLY_COUNTER.MACT0[0x233]=0x8e278cb
MACT_LARGE_EM_REPLY_FIFO_REPLY_DROP_COUNTERS.MACT0[0x230]=0
MACT_LARGE_EM_REPLY_FIFO_WATERMARK.MACT0[0x232]=0x26
MACT_LARGE_EM_WARNING_LEARN_OVER_EXISTING_COUNTER.MACT0[0x235]=0
MACT_LARGE_EM_WARNING_REFRESH_NON_EXIST_COUNTER.MACT0[0x23a]=0
MACT_LARGE_EM_WARNING_TRANSPLANT_NON_EXIST_COUNTER.MACT0[0x239]=0
MACT_MACT_GENERAL_CONFIGURATION.MACT0[0x23e]=0xd
MACT_MACT_INTERRUPT_REGISTER_TEST.MACT0[0x1a]=0
MACT_PCMI_0.MACT0[0xb0]=0x3b9aca00
MACT_PCMI_0_S.MACT0[0xb1]=0
MACT_PCMI_0_T.MACT0[0xb2]=0
MACT_REG_0041.MACT0[0x41]=0
MACT_REG_00C2.MACT0[0xc2]=0x12
MACT_RESERVED_MTCD.MACT0[0xae]=0x30
MACT_RESERVED_MTCP.MACT0[0xad]=0x300000600000000
MACT_RESERVED_SPARE_0.MACT0[0x90]=0xffffffff
MACT_RESERVED_SPARE_1.MACT0[0x91]=0xffffffff
MACT_RESERVED_SPARE_2.MACT0[0x92]=0
MACT_RESERVED_SPARE_3.MACT0[0x93]=0
MACT_SBUS_BROADCAST_ID.MACT0[0x86]=0x7ff
MACT_SBUS_LAST_IN_CHAIN.MACT0[0x87]=0
MACT_SPECIAL_CLOCK_CONTROLS.MACT0[0xc1]=2
MACT_VMV_TO_ENTRY_FORMAT_INDEX_MAP.MACT0[0x21b]=0x10000000000000000
MCP_ECC_1B_ERR_CNT.MCP0[0x94]=0
MCP_ECC_2B_ERR_CNT.MCP0[0x96]=0
MCP_ECC_ERR_1B_MONITOR_MEM_MASK.MCP0[0x9a]=0xfffffff
MCP_ECC_ERR_2B_MONITOR_MEM_MASK.MCP0[0x9c]=0xfffffff
MCP_ECC_INTERRUPT_REGISTER.MCP0[0x7]=0
MCP_ECC_INTERRUPT_REGISTER_MASK.MCP0[0x17]=0
MCP_ECC_INTERRUPT_REGISTER_TEST.MCP0[0x1f]=0
MCP_ENABLE_DYNAMIC_MEMORY_ACCESS.MCP0[0x84]=0xfffffff
MCP_ENG_DB_BANK_ACCESS_ERR_SOURCE.MCP0[0x101]=0xffff
MCP_ENG_DB_BANK_SOURCE.MCP0[0x100]=0x15401
MCP_GTIMER_CONFIGURATION.MCP0[0x89]=0
MCP_GTIMER_CYCLE.MCP0[0x88]=0x3b9aca00
MCP_INDIRECT_COMMAND.MCP0[0x80]=0xe000002
MCP_INDIRECT_COMMAND_ADDRESS.MCP0[0x81]=0x80087000
MCP_INDIRECT_COMMAND_RD_DATA.MCP0[0x60]=0
MCP_INDIRECT_COMMAND_WR_DATA.MCP0[0x20]=0
MCP_INDIRECT_FORCE_BUBBLE.MCP0[0x83]=0x20019
MCP_INTERRUPT_MASK_REGISTER.MCP0[0x10]=0
MCP_INTERRUPT_REGISTER.MCP0[0x0]=0
MCP_INTERRUPT_REGISTER_TEST.MCP0[0x18]=0
MCP_PCMI_0.MCP0[0xb0]=0x3b9aca00
MCP_PCMI_1.MCP0[0xb3]=0x3b9aca00
MCP_PCMI_2.MCP0[0xb6]=0x3b9aca00
MCP_PCMI_3.MCP0[0xb9]=0x3b9aca00
MCP_PCMI_4.MCP0[0xbc]=0x3b9aca00
MCP_PCMI_0_S.MCP0[0xb1]=0
MCP_PCMI_0_T.MCP0[0xb2]=0
MCP_PCMI_1_S.MCP0[0xb4]=0
MCP_PCMI_1_T.MCP0[0xb5]=0
MCP_PCMI_2_S.MCP0[0xb7]=0
MCP_PCMI_2_T.MCP0[0xb8]=0
MCP_PCMI_3_S.MCP0[0xba]=0
MCP_PCMI_3_T.MCP0[0xbb]=0
MCP_PCMI_4_S.MCP0[0xbd]=0
MCP_PCMI_4_T.MCP0[0xbe]=0
MCP_REG_0041.MCP0[0x41]=0
MCP_REG_00C2.MCP0[0xc2]=0x10
MCP_RESERVED_MTCD.MCP0[0xae]=0x30
MCP_RESERVED_MTCP.MCP0[0xad]=0x300000600000000
MCP_RESERVED_SPARE_0.MCP0[0x90]=0xffffffff
MCP_RESERVED_SPARE_1.MCP0[0x91]=0xffffffff
MCP_RESERVED_SPARE_2.MCP0[0x92]=0
MCP_RESERVED_SPARE_3.MCP0[0x93]=0
MCP_SBUS_BROADCAST_ID.MCP0[0x86]=0x7ff
MCP_SBUS_LAST_IN_CHAIN.MCP0[0x87]=0
MCP_SPECIAL_CLOCK_CONTROLS.MCP0[0xc1]=2
MDB_ARM_KAPS_CONFIG.MDB_ARM0[0x100]=0
MDB_ARM_KAPS_CONFIG_CFIFO(0).MDB_ARM0[0x2700]=0
MDB_ARM_KAPS_CONFIG_CFIFO(1).MDB_ARM0[0x2701]=0
MDB_ARM_KAPS_CONFIG_CFIFO(2).MDB_ARM0[0x2702]=0
MDB_ARM_KAPS_CONFIG_CFIFO(3).MDB_ARM0[0x2703]=0
MDB_ARM_KAPS_CONFIG_CFIFO_THRESH(0).MDB_ARM0[0x2b00]=0
MDB_ARM_KAPS_CONFIG_CFIFO_THRESH(1).MDB_ARM0[0x2b01]=0
MDB_ARM_KAPS_CONFIG_CFIFO_THRESH(2).MDB_ARM0[0x2b02]=0
MDB_ARM_KAPS_CONFIG_CFIFO_THRESH(3).MDB_ARM0[0x2b03]=0
MDB_ARM_KAPS_CONFIG_FIFO_MON.MDB_ARM0[0x3b00]=0
MDB_ARM_KAPS_CONFIG_RFIFO(0).MDB_ARM0[0x3300]=0
MDB_ARM_KAPS_CONFIG_RFIFO(1).MDB_ARM0[0x3301]=0
MDB_ARM_KAPS_CONFIG_RFIFO(2).MDB_ARM0[0x3302]=0
MDB_ARM_KAPS_CONFIG_RFIFO(3).MDB_ARM0[0x3303]=0
MDB_ARM_KAPS_GLOBAL_DEBUG.MDB_ARM0[0x8500]=0
MDB_ARM_KAPS_GLOBAL_EVENT.MDB_ARM0[0x300]=0x10
MDB_ARM_KAPS_GLOBAL_EVENT_MASK.MDB_ARM0[0x400]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(0).MDB_ARM0[0x4000]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(1).MDB_ARM0[0x4001]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(2).MDB_ARM0[0x4002]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(3).MDB_ARM0[0x4003]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(4).MDB_ARM0[0x4004]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(5).MDB_ARM0[0x4005]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(6).MDB_ARM0[0x4006]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(7).MDB_ARM0[0x4007]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(8).MDB_ARM0[0x4008]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(9).MDB_ARM0[0x4009]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(10).MDB_ARM0[0x400a]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(11).MDB_ARM0[0x400b]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(12).MDB_ARM0[0x400c]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(13).MDB_ARM0[0x400d]=0
MDB_ARM_KAPS_IBC_COMMAND_DATA(14).MDB_ARM0[0x400e]=0
MDB_ARM_KAPS_IBC_COMMAND_WORD.MDB_ARM0[0x4f00]=0
MDB_ARM_KAPS_IBC_CONFIG.MDB_ARM0[0x200]=0
MDB_ARM_KAPS_IBC_FIFO_CORRECTABLE_STATUS.MDB_ARM0[0x6300]=0
MDB_ARM_KAPS_IBC_FIFO_ECC_DEBUG.MDB_ARM0[0x6200]=0
MDB_ARM_KAPS_IBC_FIFO_MEM_CONTROL.MDB_ARM0[0x6100]=0
MDB_ARM_KAPS_IBC_FIFO_TM_TEST_CTRL.MDB_ARM0[0x8700]=0
MDB_ARM_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS.MDB_ARM0[0x6400]=0
MDB_ARM_KAPS_IBC_QUEUE_STATUS.MDB_ARM0[0x6000]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(0).MDB_ARM0[0x5000]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(1).MDB_ARM0[0x5001]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(2).MDB_ARM0[0x5002]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(3).MDB_ARM0[0x5003]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(4).MDB_ARM0[0x5004]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(5).MDB_ARM0[0x5005]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(6).MDB_ARM0[0x5006]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(7).MDB_ARM0[0x5007]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(8).MDB_ARM0[0x5008]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(9).MDB_ARM0[0x5009]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(10).MDB_ARM0[0x500a]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(11).MDB_ARM0[0x500b]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(12).MDB_ARM0[0x500c]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(13).MDB_ARM0[0x500d]=0
MDB_ARM_KAPS_IBC_RESPONSE_DATA(14).MDB_ARM0[0x500e]=0
MDB_ARM_KAPS_IBC_RESPONSE_WORD.MDB_ARM0[0x5f00]=0
MDB_ARM_KAPS_MEMORY_A_ERROR.MDB_ARM0[0x1b00]=0
MDB_ARM_KAPS_MEMORY_A_ERROR_MASK.MDB_ARM0[0x1e00]=0
MDB_ARM_KAPS_MEMORY_B_ERROR.MDB_ARM0[0x1c00]=0
MDB_ARM_KAPS_MEMORY_B_ERROR_MASK.MDB_ARM0[0x1f00]=0
MDB_ARM_KAPS_PD_ASSIST_DEBUG.MDB_ARM0[0x8800]=0xffff0000
MDB_ARM_KAPS_REVISION.MDB_ARM0[0x0]=0x10000
MDB_ARM_KAPS_R_5_ATTN(0).MDB_ARM0[0x700]=0
MDB_ARM_KAPS_R_5_ATTN(1).MDB_ARM0[0x701]=0
MDB_ARM_KAPS_R_5_ATTN(2).MDB_ARM0[0x702]=0
MDB_ARM_KAPS_R_5_ATTN(3).MDB_ARM0[0x703]=0
MDB_ARM_KAPS_R_5_AXI_CONFIG.MDB_ARM0[0x7200]=0
MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_0.MDB_ARM0[0x7300]=0
MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_1.MDB_ARM0[0x7400]=0
MDB_ARM_KAPS_R_5_CONFIGA.MDB_ARM0[0x7700]=0
MDB_ARM_KAPS_R_5_CORE_CONFIGA.MDB_ARM0[0x6d00]=0x1c885003
MDB_ARM_KAPS_R_5_CORE_CONFIGB.MDB_ARM0[0x6e00]=0x10010b
MDB_ARM_KAPS_R_5_CORE_CONFIGC.MDB_ARM0[0x6f00]=0
MDB_ARM_KAPS_R_5_CORE_CONFIGD.MDB_ARM0[0x7000]=0
MDB_ARM_KAPS_R_5_CORE_CONFIGE.MDB_ARM0[0x7100]=0
MDB_ARM_KAPS_R_5_CORE_CONTROL.MDB_ARM0[0x6500]=0x30
MDB_ARM_KAPS_R_5_CORE_MEM_CONTROL.MDB_ARM0[0x6600]=0x3f
MDB_ARM_KAPS_R_5_COUNTERS(0).MDB_ARM0[0xb00]=0
MDB_ARM_KAPS_R_5_COUNTERS(1).MDB_ARM0[0xb01]=0
MDB_ARM_KAPS_R_5_COUNTERS(2).MDB_ARM0[0xb02]=0
MDB_ARM_KAPS_R_5_COUNTERS(3).MDB_ARM0[0xb03]=0
MDB_ARM_KAPS_R_5_COUNTERS(4).MDB_ARM0[0xb04]=0
MDB_ARM_KAPS_R_5_COUNTERS(5).MDB_ARM0[0xb05]=0
MDB_ARM_KAPS_R_5_COUNTERS(6).MDB_ARM0[0xb06]=0
MDB_ARM_KAPS_R_5_COUNTERS(7).MDB_ARM0[0xb07]=0
MDB_ARM_KAPS_R_5_COUNTERS(8).MDB_ARM0[0xb08]=0
MDB_ARM_KAPS_R_5_COUNTERS(9).MDB_ARM0[0xb09]=0
MDB_ARM_KAPS_R_5_COUNTERS(10).MDB_ARM0[0xb0a]=0
MDB_ARM_KAPS_R_5_COUNTERS(11).MDB_ARM0[0xb0b]=0
MDB_ARM_KAPS_R_5_COUNTERS(12).MDB_ARM0[0xb0c]=0
MDB_ARM_KAPS_R_5_COUNTERS(13).MDB_ARM0[0xb0d]=0
MDB_ARM_KAPS_R_5_COUNTERS(14).MDB_ARM0[0xb0e]=0
MDB_ARM_KAPS_R_5_COUNTERS(15).MDB_ARM0[0xb0f]=0
MDB_ARM_KAPS_R_5_DAP_APB_ADDR.MDB_ARM0[0x8200]=0
MDB_ARM_KAPS_R_5_DAP_APB_CTRL.MDB_ARM0[0x8100]=0
MDB_ARM_KAPS_R_5_DAP_APB_RDATA.MDB_ARM0[0x8400]=0
MDB_ARM_KAPS_R_5_DAP_APB_WDATA.MDB_ARM0[0x8300]=0
MDB_ARM_KAPS_R_5_DEBUG_CONFIGA.MDB_ARM0[0x7500]=0x1007
MDB_ARM_KAPS_R_5_DEBUG_CONFIGB.MDB_ARM0[0x7600]=0
MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_0.MDB_ARM0[0x7d00]=0
MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_1.MDB_ARM0[0x7e00]=0
MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK.MDB_ARM0[0x7f00]=0
MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK.MDB_ARM0[0x8000]=0
MDB_ARM_KAPS_R_5_DEBUG_STATUS.MDB_ARM0[0x7800]=0x418
MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0.MDB_ARM0[0x7900]=0
MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1.MDB_ARM0[0x7b00]=0
MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK.MDB_ARM0[0x7a00]=0
MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK.MDB_ARM0[0x7c00]=0
MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_A.MDB_ARM0[0x6a00]=0x7ffe0000
MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_0.MDB_ARM0[0x6b00]=0x7ffe0000
MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_1.MDB_ARM0[0x6c00]=0x7ffe0000
MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_A.MDB_ARM0[0x6700]=0x7ffe0000
MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_0.MDB_ARM0[0x6800]=0x7ffe0000
MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_1.MDB_ARM0[0x6900]=0x7ffe0000
MDB_ARM_KAPS_R_5_FIFO_MON_EVENT.MDB_ARM0[0x500]=0
MDB_ARM_KAPS_R_5_FIFO_MON_EVENT_MASK.MDB_ARM0[0x600]=0
MDB_ARM_KAPS_R_5_TM_TEST_CTRL.MDB_ARM0[0x8600]=0
MDB_ARM_KAPS_SEARCH_0_A_ERROR.MDB_ARM0[0x1d00]=0
MDB_ARM_KAPS_SEARCH_0_A_ERROR_MASK.MDB_ARM0[0x2000]=0
MDB_ARM_KAPS_SEARCH_0_B_ERROR.MDB_ARM0[0x2300]=0
MDB_ARM_KAPS_SEARCH_0_B_ERROR_MASK.MDB_ARM0[0x2400]=0
MDB_ARM_KAPS_SEARCH_1_A_ERROR.MDB_ARM0[0x2100]=0
MDB_ARM_KAPS_SEARCH_1_A_ERROR_MASK.MDB_ARM0[0x2200]=0
MDB_ARM_KAPS_SEARCH_1_B_ERROR.MDB_ARM0[0x2500]=0
MDB_ARM_KAPS_SEARCH_1_B_ERROR_MASK.MDB_ARM0[0x2600]=0
MDB_ARM_KAPS_STATUS_CFIFO(0).MDB_ARM0[0x2f00]=0
MDB_ARM_KAPS_STATUS_CFIFO(1).MDB_ARM0[0x2f01]=0
MDB_ARM_KAPS_STATUS_CFIFO(2).MDB_ARM0[0x2f02]=0
MDB_ARM_KAPS_STATUS_CFIFO(3).MDB_ARM0[0x2f03]=0
MDB_ARM_KAPS_STATUS_RFIFO(0).MDB_ARM0[0x3700]=0
MDB_ARM_KAPS_STATUS_RFIFO(1).MDB_ARM0[0x3701]=0
MDB_ARM_KAPS_STATUS_RFIFO(2).MDB_ARM0[0x3702]=0
MDB_ARM_KAPS_STATUS_RFIFO(3).MDB_ARM0[0x3703]=0
MDB_ECC_1B_ERR_CNT.MDB0[0x94]=0
MDB_ECC_2B_ERR_CNT.MDB0[0x96]=0
MDB_ECC_ERR_1B_MONITOR_MEM_MASK.MDB0[0x9a]=0x1fffffffffffff
MDB_ECC_ERR_2B_MONITOR_MEM_MASK.MDB0[0x9c]=0x1fffffffffffff
MDB_ECC_INTERRUPT_REGISTER.MDB0[0x7]=0
MDB_ECC_INTERRUPT_REGISTER_MASK.MDB0[0x17]=0
MDB_ECC_INTERRUPT_REGISTER_TEST.MDB0[0x1f]=0
MDB_ENABLE_DYNAMIC_MEMORY_ACCESS.MDB0[0x84]=0xffffffffffffff
MDB_GTIMER_CONFIGURATION.MDB0[0x89]=0
MDB_GTIMER_CYCLE.MDB0[0x88]=0x3b9aca00
MDB_INDIRECT_COMMAND.MDB0[0x80]=0x34070002
MDB_INDIRECT_COMMAND_ADDRESS.MDB0[0x81]=0x19010
MDB_INDIRECT_COMMAND_RD_DATA.MDB0[0x60]=0x200111bfc4000bf0000000000800bf0000081380008400
MDB_INDIRECT_COMMAND_WR_DATA.MDB0[0x20]=0
MDB_INDIRECT_FORCE_BUBBLE.MDB0[0x83]=0x20019
MDB_INDIRECT_WR_MASK.MDB0[0x40]=0xffff
MDB_PARITY_ERR_CNT.MDB0[0x98]=0
MDB_PAR_ERR_MEM_MASK.MDB0[0xa0]=0x1fffffffffffffff
MDB_PCMI_0.MDB0[0xb0]=0x3b9aca00
MDB_PCMI_1.MDB0[0xb3]=0x3b9aca00
MDB_PCMI_2.MDB0[0xb6]=0x3b9aca00
MDB_PCMI_3.MDB0[0xb9]=0x3b9aca00
MDB_PCMI_4.MDB0[0xbc]=0x3b9aca00
MDB_PCMI_0_S.MDB0[0xb1]=0
MDB_PCMI_0_T.MDB0[0xb2]=0
MDB_PCMI_1_S.MDB0[0xb4]=0
MDB_PCMI_1_T.MDB0[0xb5]=0
MDB_PCMI_2_S.MDB0[0xb7]=0
MDB_PCMI_2_T.MDB0[0xb8]=0
MDB_PCMI_3_S.MDB0[0xba]=0
MDB_PCMI_3_T.MDB0[0xbb]=0
MDB_PCMI_4_S.MDB0[0xbd]=0
MDB_PCMI_4_T.MDB0[0xbe]=0
MDB_REG_0000.MDB0[0x0]=0x40000
MDB_REG_0010.MDB0[0x10]=0
MDB_REG_0018.MDB0[0x18]=0
MDB_REG_0041.MDB0[0x41]=0
MDB_REG_100.MDB0[0x100]=0x80200040
MDB_REG_103.MDB0[0x103]=0xb4b4
MDB_REG_104.MDB0[0x104]=0x492492492492492492492492249249249249000000ffffff
MDB_REG_110.MDB0[0x110]=0x77777f757f7f7f7f
MDB_REG_112.MDB0[0x112]=0x800000001000000003380b40005b00800
MDB_REG_117.MDB0[0x117]=0
MDB_REG_118.MDB0[0x118]=0
MDB_REG_119.MDB0[0x119]=0x5a0
MDB_REG_121.MDB0[0x121]=0
MDB_REG_122.MDB0[0x122]=0x2edd462
MDB_REG_123.MDB0[0x123]=0x200201
MDB_REG_125.MDB0[0x125]=0x14a9
MDB_REG_126.MDB0[0x126]=0x249249249249000000000000ffffffffffff
MDB_REG_132.MDB0[0x132]=0x855fbfffffffff9f
MDB_REG_134.MDB0[0x134]=0x200000000400000000cc0a9000009a002
MDB_REG_139.MDB0[0x139]=0
MDB_REG_140.MDB0[0x140]=0
MDB_REG_141.MDB0[0x141]=0x70
MDB_REG_143.MDB0[0x143]=0
MDB_REG_144.MDB0[0x144]=0
MDB_REG_145.MDB0[0x145]=0x2000048
MDB_REG_147.MDB0[0x147]=0x1b36
MDB_REG_148.MDB0[0x148]=0x249249249249000000000000ffffffffffff
MDB_REG_154.MDB0[0x154]=0x855fbfffffffff9f
MDB_REG_156.MDB0[0x156]=0x200000000400000000cc836000004ac02
MDB_REG_161.MDB0[0x161]=0
MDB_REG_162.MDB0[0x162]=0
MDB_REG_163.MDB0[0x163]=0x70
MDB_REG_165.MDB0[0x165]=0
MDB_REG_166.MDB0[0x166]=0
MDB_REG_167.MDB0[0x167]=0x10fff36ff500000e0006800300016000a00030001000000002000000000001b9ad6b5ee0380e
MDB_REG_177.MDB0[0x177]=0x21a76e700
MDB_REG_179.MDB0[0x179]=0x240
MDB_REG_185.MDB0[0x185]=0xfffd0200000000000000000000000000000000
MDB_REG_194.MDB0[0x194]=0
MDB_REG_195.MDB0[0x195]=0
MDB_REG_196.MDB0[0x196]=0xfea8925a082
MDB_REG_199.MDB0[0x199]=0x3faff5
MDB_REG_200.MDB0[0x200]=0x249249249249249249000000249249492492000000ffffff
MDB_REG_206.MDB0[0x206]=0x80008000801fff7f
MDB_REG_208.MDB0[0x208]=0x4000000008000000019ff50008e51d003
MDB_REG_213.MDB0[0x213]=0
MDB_REG_214.MDB0[0x214]=0
MDB_REG_215.MDB0[0x215]=0x9f0
MDB_REG_217(0).MDB0[0x217]=0x14f19e
MDB_REG_217(1).MDB0[0x218]=0
MDB_REG_217(2).MDB0[0x219]=0
MDB_REG_217(3).MDB0[0x21a]=0
MDB_REG_217(4).MDB0[0x21b]=0
MDB_REG_217(5).MDB0[0x21c]=0
MDB_REG_217(6).MDB0[0x21d]=0
MDB_REG_217(7).MDB0[0x21e]=0
MDB_REG_217(8).MDB0[0x21f]=0
MDB_REG_217(9).MDB0[0x220]=0
MDB_REG_217(10).MDB0[0x221]=0
MDB_REG_217(11).MDB0[0x222]=0
MDB_REG_217(12).MDB0[0x223]=0
MDB_REG_217(13).MDB0[0x224]=0
MDB_REG_217(14).MDB0[0x225]=0
MDB_REG_217(15).MDB0[0x226]=0
MDB_REG_233.MDB0[0x233]=0
MDB_REG_234.MDB0[0x234]=0xe119edd1
MDB_REG_235.MDB0[0x235]=1
MDB_REG_237.MDB0[0x237]=0x33
MDB_REG_238.MDB0[0x238]=0x249249249249000000000000ffffffffffff
MDB_REG_244.MDB0[0x244]=0x303030303030303
MDB_REG_246.MDB0[0x246]=0x8000000010000000033030000000402
MDB_REG_250.MDB0[0x250]=0
MDB_REG_251.MDB0[0x251]=0
MDB_REG_252.MDB0[0x252]=0
MDB_REG_254.MDB0[0x254]=0
MDB_REG_255.MDB0[0x255]=0xe12d5326
MDB_REG_256.MDB0[0x256]=0
MDB_REG_258.MDB0[0x258]=0xcc
MDB_REG_259.MDB0[0x259]=0x249249249249000000000000ffffffffffff
MDB_REG_265.MDB0[0x265]=0x303030303030303
MDB_REG_267.MDB0[0x267]=0x80000000100000000330c0000000402
MDB_REG_271.MDB0[0x271]=0
MDB_REG_272.MDB0[0x272]=0
MDB_REG_273.MDB0[0x273]=0
MDB_REG_275.MDB0[0x275]=0
MDB_REG_276.MDB0[0x276]=0xe12d5332
MDB_REG_277.MDB0[0x277]=0
MDB_REG_279.MDB0[0x279]=0x39c
MDB_REG_280.MDB0[0x280]=0x4f
MDB_REG_286.MDB0[0x286]=0xf
MDB_REG_287.MDB0[0x287]=0x200000000400000000cc1c0023900803
MDB_REG_291.MDB0[0x291]=0
MDB_REG_292.MDB0[0x292]=0
MDB_REG_293.MDB0[0x293]=0
MDB_REG_295.MDB0[0x295]=0
MDB_REG_296.MDB0[0x296]=0xe126a16d
MDB_REG_297.MDB0[0x297]=0x200
MDB_REG_299.MDB0[0x299]=0x618
MDB_REG_300.MDB0[0x300]=0x492492492492492492492492ffffffffffffffffffffffff
MDB_REG_306.MDB0[0x306]=0xf
MDB_REG_307.MDB0[0x307]=0x8000000010000000033018000040000
MDB_REG_311.MDB0[0x311]=0
MDB_REG_312.MDB0[0x312]=0
MDB_REG_313.MDB0[0x313]=0x810
MDB_REG_315.MDB0[0x315]=0
MDB_REG_316.MDB0[0x316]=0xddb6ee7f
MDB_REG_317.MDB0[0x317]=0x8200
MDB_REG_319.MDB0[0x319]=0xa28
MDB_REG_320.MDB0[0x320]=0x492492492492492492492492ffffffffffffffffffffffff
MDB_REG_326.MDB0[0x326]=0xf
MDB_REG_327.MDB0[0x327]=0x8000000010000000033028000040000
MDB_REG_331.MDB0[0x331]=0
MDB_REG_332.MDB0[0x332]=0
MDB_REG_333.MDB0[0x333]=0x810
MDB_REG_335.MDB0[0x335]=0
MDB_REG_336.MDB0[0x336]=0
MDB_REG_337.MDB0[0x337]=1
MDB_REG_339.MDB0[0x339]=0x55
MDB_REG_340.MDB0[0x340]=0x249249249249000000000000ffffffffffff
MDB_REG_346.MDB0[0x346]=0x303030303030303
MDB_REG_348.MDB0[0x348]=0x8000000010000000033050000000402
MDB_REG_352.MDB0[0x352]=0
MDB_REG_353.MDB0[0x353]=0
MDB_REG_354.MDB0[0x354]=0x10
MDB_REG_356.MDB0[0x356]=0
MDB_REG_357.MDB0[0x357]=0xe126a198
MDB_REG_358.MDB0[0x358]=1
MDB_REG_360.MDB0[0x360]=0x55
MDB_REG_361.MDB0[0x361]=0x249249249249000000000000ffffffffffff
MDB_REG_367.MDB0[0x367]=0x303030303030303
MDB_REG_369.MDB0[0x369]=0x8000000010000000033050000000402
MDB_REG_373.MDB0[0x373]=0
MDB_REG_374.MDB0[0x374]=0
MDB_REG_375.MDB0[0x375]=0x10
MDB_REG_377.MDB0[0x377]=0
MDB_REG_378.MDB0[0x378]=0xe126a1b7
MDB_REG_379.MDB0[0x379]=1
MDB_REG_381.MDB0[0x381]=0x231
MDB_REG_382.MDB0[0x382]=0x249249249249000000ffffff
MDB_REG_388.MDB0[0x388]=0x7c7c7c7c7c7c7cff
MDB_REG_390.MDB0[0x390]=0x200000000400000000cc110000000402
MDB_REG_394.MDB0[0x394]=0
MDB_REG_395.MDB0[0x395]=0
MDB_REG_396.MDB0[0x396]=0
MDB_REG_398.MDB0[0x398]=0
MDB_REG_399.MDB0[0x399]=0
MDB_REG_400.MDB0[0x400]=0x89
MDB_REG_402.MDB0[0x402]=0xf
MDB_REG_403.MDB0[0x403]=0x492492492492000000000000249249249249ffffffffffff
MDB_REG_409.MDB0[0x409]=0x280808080
MDB_REG_411.MDB0[0x411]=0x8000000010000000033b0023900803
MDB_REG_415.MDB0[0x415]=0
MDB_REG_416.MDB0[0x416]=0
MDB_REG_417.MDB0[0x417]=0
MDB_REG_419.MDB0[0x419]=0
MDB_REG_420.MDB0[0x420]=0xe119ee58
MDB_REG_421.MDB0[0x421]=0x4a
MDB_REG_423.MDB0[0x423]=0xf
MDB_REG_424.MDB0[0x424]=0x492492492492249249249249ffffffffffff
MDB_REG_430.MDB0[0x430]=0x302
MDB_REG_432.MDB0[0x432]=0x800000001000000003370023900803
MDB_REG_436.MDB0[0x436]=0
MDB_REG_437.MDB0[0x437]=0
MDB_REG_438.MDB0[0x438]=0
MDB_REG_440.MDB0[0x440]=0
MDB_REG_441.MDB0[0x441]=0xe12d53b4
MDB_REG_442.MDB0[0x442]=0x11fffebe0000280010002000000036b9ae
MDB_REG_447.MDB0[0x447]=0
MDB_REG_449.MDB0[0x449]=0
MDB_REG_455.MDB0[0x455]=0xffff0000000000000000000000000000000000
MDB_REG_468.MDB0[0x468]=0
MDB_REG_469.MDB0[0x469]=0
MDB_REG_470.MDB0[0x470]=0xca
MDB_REG_472.MDB0[0x472]=0xf
MDB_REG_473.MDB0[0x473]=0x492000249000492000249000492000249000492000249fff
MDB_REG_479.MDB0[0x479]=0x280808080
MDB_REG_481.MDB0[0x481]=0x8000000010000000033f0023900803
MDB_REG_485.MDB0[0x485]=0
MDB_REG_486.MDB0[0x486]=0
MDB_REG_487.MDB0[0x487]=0
MDB_REG_489(0).MDB0[0x489]=0
MDB_REG_489(1).MDB0[0x48a]=0
MDB_REG_489(2).MDB0[0x48b]=0
MDB_REG_489(3).MDB0[0x48c]=0
MDB_REG_493.MDB0[0x493]=0
MDB_REG_494.MDB0[0x494]=0
MDB_REG_495.MDB0[0x495]=0x41fffef000010000000dad
MDB_REG_498.MDB0[0x498]=0
MDB_REG_500.MDB0[0x500]=0
MDB_REG_506.MDB0[0x506]=0xffff0000000000000000000000000000000000
MDB_REG_519.MDB0[0x519]=0
MDB_REG_520.MDB0[0x520]=0
MDB_REG_521.MDB0[0x521]=0xc9
MDB_REG_523.MDB0[0x523]=0xf
MDB_REG_524.MDB0[0x524]=0x25200000000025200000000025200000000025203f
MDB_REG_530.MDB0[0x530]=0x200000000
MDB_REG_532.MDB0[0x532]=0x200000000400000000cf0000100803
MDB_REG_536.MDB0[0x536]=0
MDB_REG_537.MDB0[0x537]=0
MDB_REG_538.MDB0[0x538]=0
MDB_REG_540(0).MDB0[0x540]=0
MDB_REG_540(1).MDB0[0x541]=0
MDB_REG_540(2).MDB0[0x542]=0
MDB_REG_540(3).MDB0[0x543]=0
MDB_REG_544.MDB0[0x544]=0
MDB_REG_545.MDB0[0x545]=0
MDB_REG_546.MDB0[0x546]=0x41
MDB_REG_548.MDB0[0x548]=0xf
MDB_REG_549.MDB0[0x549]=0x249249249249000000ffffff
MDB_REG_555.MDB0[0x555]=0xff
MDB_REG_556.MDB0[0x556]=0x80000000100000000337000009a002
MDB_REG_560.MDB0[0x560]=0
MDB_REG_561.MDB0[0x561]=0
MDB_REG_562.MDB0[0x562]=0
MDB_REG_564.MDB0[0x564]=0
MDB_REG_565.MDB0[0x565]=0
MDB_REG_1000.MDB0[0x1000]=0x4a00000005b2004
MDB_REG_1002.MDB0[0x1002]=0xc71
MDB_REG_1003.MDB0[0x1003]=0xe119eeaf
MDB_REG_1004.MDB0[0x1004]=0x6e00004
MDB_REG_1005.MDB0[0x1005]=5
MDB_REG_1006.MDB0[0x1006]=0xe119eeb4
MDB_REG_1007.MDB0[0x1007]=0x4a00004
MDB_REG_1008.MDB0[0x1008]=3
MDB_REG_1009.MDB0[0x1009]=0
MDB_REG_1010.MDB0[0x1010]=0
MDB_REG_1011.MDB0[0x1011]=0
MDB_REG_1012.MDB0[0x1012]=0x4a00064
MDB_REG_1013.MDB0[0x1013]=0xa
MDB_REG_1014.MDB0[0x1014]=0
MDB_REG_1015.MDB0[0x1015]=0
MDB_REG_1016.MDB0[0x1016]=0x90064
MDB_REG_1017.MDB0[0x1017]=0xa
MDB_REG_1018.MDB0[0x1018]=0
MDB_REG_1019.MDB0[0x1019]=0
MDB_REG_1020.MDB0[0x1020]=0x90004
MDB_REG_1021.MDB0[0x1021]=0
MDB_REG_1022.MDB0[0x1022]=0
MDB_REG_1023.MDB0[0x1023]=0
MDB_REG_1024.MDB0[0x1024]=0x4800004
MDB_REG_1025.MDB0[0x1025]=5
MDB_REG_1026.MDB0[0x1026]=0
MDB_REG_1027.MDB0[0x1027]=0x1ff779bd6717b56939460f7250730407314831041b600000000155400004
MDB_REG_1035.MDB0[0x1035]=0x24
MDB_REG_1036.MDB0[0x1036]=0
MDB_REG_1037.MDB0[0x1037]=0
MDB_REG_1038.MDB0[0x1038]=0x1ff7f9bd6717b56939460f7358b52507314831041b610000000000000003
MDB_REG_1046.MDB0[0x1046]=0x24
MDB_REG_1047.MDB0[0x1047]=0
MDB_REG_1048.MDB0[0x1048]=0
MDB_REG_1049.MDB0[0x1049]=0x1ff779de6717b56939460f7358b52507314831041b601400000000000003
MDB_REG_1057.MDB0[0x1057]=0x44
MDB_REG_1058.MDB0[0x1058]=0
MDB_REG_1059.MDB0[0x1059]=0
MDB_REG_1060.MDB0[0x1060]=0xde2c1a8d
MDB_REG_1061.MDB0[0x1061]=0x1249ffffffffffffffffffffffffffffffffffffffffffffffffffff5554abfffffe2
MDB_REG_1070.MDB0[0x1070]=0xee
MDB_REG_1071.MDB0[0x1071]=0xddb6ef7e
MDB_REG_1072.MDB0[0x1072]=0
MDB_REG_1073.MDB0[0x1073]=0x12495555555555555555555555555555555555555555555555555555555554aa00002
MDB_REG_1082.MDB0[0x1082]=0x3f
MDB_REG_1083.MDB0[0x1083]=0x9c359
MDB_REG_1084.MDB0[0x1084]=0
MDB_REG_1085.MDB0[0x1085]=0x1249ffffffffffffffffffffffffe1fffffe2
MDB_REG_1090.MDB0[0x1090]=0xf
MDB_REG_1091.MDB0[0x1091]=0
MDB_REG_1092.MDB0[0x1092]=0
MDB_REG_1093.MDB0[0x1093]=0x1249fffffffffffffffffffffffffffffffffffffffffffffffe01fffffffffffffe2
MDB_REG_1102.MDB0[0x1102]=0x99
MDB_REG_1103.MDB0[0x1103]=0
MDB_REG_1104.MDB0[0x1104]=0
MDB_REG_1105.MDB0[0x1105]=0x24000155544
MDB_REG_1107.MDB0[0x1107]=0x24
MDB_REG_1108.MDB0[0x1108]=0xe126a2a0
MDB_REG_1109.MDB0[0x1109]=0xe126a2a1
MDB_REG_1110.MDB0[0x1110]=0x25fffffffffffffffe4
MDB_REG_1113.MDB0[0x1113]=3
MDB_REG_1114.MDB0[0x1114]=0xddb6efa9
MDB_REG_1115.MDB0[0x1115]=0
MDB_REG_1116.MDB0[0x1116]=0x25fffffffffffffffe4
MDB_REG_1119.MDB0[0x1119]=3
MDB_REG_1120.MDB0[0x1120]=0x9c359
MDB_REG_1121.MDB0[0x1121]=0
MDB_REG_1122.MDB0[0x1122]=0x25fffffffffffffffe4
MDB_REG_1125.MDB0[0x1125]=3
MDB_REG_1126.MDB0[0x1126]=0
MDB_REG_1127.MDB0[0x1127]=0
MDB_REG_1128.MDB0[0x1128]=0x25ffffffffdffffffe4
MDB_REG_1131.MDB0[0x1131]=3
MDB_REG_1132.MDB0[0x1132]=0
MDB_REG_1133.MDB0[0x1133]=0
MDB_REG_2000.MDB0[0x2000]=2
MDB_REG_2001.MDB0[0x2001]=0xa4148
MDB_REG_2002.MDB0[0x2002]=0x35f7ffff
MDB_REG_2004.MDB0[0x2004]=0
MDB_REG_2005.MDB0[0x2005]=0x3ffe9ffb
MDB_REG_2007.MDB0[0x2007]=0
MDB_REG_2008.MDB0[0x2008]=0
MDB_REG_2009.MDB0[0x2009]=0
MDB_REG_2010.MDB0[0x2010]=0x37ffbffc
MDB_REG_2012.MDB0[0x2012]=0
MDB_REG_2013.MDB0[0x2013]=0xffff5b5
MDB_REG_2015.MDB0[0x2015]=0
MDB_REG_3000.MDB0[0x3000]=0
MDB_REG_3001.MDB0[0x3001]=0
MDB_REG_3002.MDB0[0x3002]=0
MDB_REG_3003.MDB0[0x3003]=0x924924924000924924924000924924924000924924924924
MDB_REG_3009.MDB0[0x3009]=0
MDB_REG_3014.MDB0[0x3014]=0
MDB_REG_3015.MDB0[0x3015]=0
MDB_REG_3016.MDB0[0x3016]=0x9249249249249249246db6db6db6db6db6db0000006db6db
MDB_REG_5000.MDB0[0x5000]=1
MDB_REG_5001.MDB0[0x5001]=0xffffffffe33bf7f3fb7c17fdfc3f7f72
MDB_REG_5005.MDB0[0x5005]=0
MDB_REG_5006.MDB0[0x5006]=0x6a1c2f
MDB_REG_5007.MDB0[0x5007]=0xcdfa2
MDB_REG_5008.MDB0[0x5008]=0x6a1c2f
MDB_REG_5009.MDB0[0x5009]=0xcdfa2
MDB_REG_00C2.MDB0[0xc2]=0x10
MDB_REG_00F0.MDB0[0xf0]=0
MDB_REG_300A.MDB0[0x300a]=0
MDB_REG_300B.MDB0[0x300b]=0
MDB_REG_300C.MDB0[0x300c]=0
MDB_REG_300D.MDB0[0x300d]=0
MDB_REG_300E.MDB0[0x300e]=0x2db6d00000002db6d00000002db6d00000002db6d02d
MDB_REG_301C.MDB0[0x301c]=0
MDB_REG_301D.MDB0[0x301d]=0
MDB_REG_301E.MDB0[0x301e]=0
MDB_REG_500A.MDB0[0x500a]=2
MDB_REG_500D.MDB0[0x500d]=0
MDB_REG_500F.MDB0[0x500f]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffdc
MDB_RESERVED_MIRROR_ADDR.MDB0[0x85]=0
MDB_RESERVED_MTCD.MDB0[0xae]=0x30
MDB_RESERVED_MTCP.MDB0[0xad]=0x300000600000000
MDB_RESERVED_SPARE_0.MDB0[0x90]=0xffffffff
MDB_RESERVED_SPARE_1.MDB0[0x91]=0xffffffff
MDB_RESERVED_SPARE_2.MDB0[0x92]=0
MDB_RESERVED_SPARE_3.MDB0[0x93]=0
MDB_SBUS_BROADCAST_ID.MDB0[0x86]=0x7ff
MDB_SBUS_LAST_IN_CHAIN.MDB0[0x87]=0
MDB_SPECIAL_CLOCK_CONTROLS.MDB0[0xc1]=2
MRPS_AUTO_DOC_NAME_19.MRPS0[0x1c2]=0
MRPS_AUTO_DOC_NAME_24.MRPS0[0x1c3]=3
MRPS_ECC_1B_ERR_CNT.MRPS0[0x94]=0
MRPS_ECC_2B_ERR_CNT.MRPS0[0x96]=0
MRPS_ECC_ERR_1B_MONITOR_MEM_MASK.MRPS0[0x9a]=0xfffff
MRPS_ECC_ERR_2B_MONITOR_MEM_MASK.MRPS0[0x9c]=0xfffff
MRPS_ECC_INTERRUPT_REGISTER.MRPS0[0x7]=0
MRPS_ECC_INTERRUPT_REGISTER_MASK.MRPS0[0x17]=0
MRPS_ECC_INTERRUPT_REGISTER_TEST.MRPS0[0x1f]=0
MRPS_EGR_ENG_ADDR_MAP(0).MRPS0[0x145]=0x11c50c0fbceb8db4cb0bacaa89a48a079c69859449038c288184081
MRPS_EGR_ENG_ADDR_MAP(1).MRPS0[0x146]=0x11c50c0fbceb8db4cb0bacaa89a48a079c69859449038c288184081
MRPS_EGR_ENG_ADDR_RANGE(0).MRPS0[0x12e]=0
MRPS_EGR_ENG_ADDR_RANGE(1).MRPS0[0x12f]=0
MRPS_EGR_ENG_FILTER(0).MRPS0[0x11a]=0
MRPS_EGR_ENG_FILTER(1).MRPS0[0x11b]=0
MRPS_EGR_ENG_GLOBAL_SETTINGS(0).MRPS0[0x112]=0x407fe
MRPS_EGR_ENG_GLOBAL_SETTINGS(1).MRPS0[0x113]=0x407fe
MRPS_EGR_ENG_IN_COLOR_MAP(0).MRPS0[0x123]=0x8421
MRPS_EGR_ENG_IN_COLOR_MAP(1).MRPS0[0x124]=0x8421
MRPS_EGR_ENG_OOP_FIFO_DATA(0).MRPS0[0x162]=0
MRPS_EGR_ENG_OOP_FIFO_DATA(1).MRPS0[0x163]=0
MRPS_EGR_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER.MRPS0[0x109]=0
MRPS_EGR_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_MASK.MRPS0[0x10a]=0
MRPS_EGR_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_TEST.MRPS0[0x10b]=0
MRPS_EGR_ENG_OOP_FIFO_SETTINGS(0).MRPS0[0x15e]=0
MRPS_EGR_ENG_OOP_FIFO_SETTINGS(1).MRPS0[0x15f]=0
MRPS_EGR_ENG_OOP_FIFO_WR_CTR(0).MRPS0[0x1b6]=0
MRPS_EGR_ENG_OOP_FIFO_WR_CTR(1).MRPS0[0x1b7]=0
MRPS_EGR_ENG_RND_SETTINGS(0).MRPS0[0x129]=0
MRPS_EGR_ENG_RND_SETTINGS(1).MRPS0[0x12a]=0
MRPS_EGR_ENG_STAT_CTR(0).MRPS0[0x18e]=0
MRPS_EGR_ENG_STAT_CTR(1).MRPS0[0x18f]=0
MRPS_EGR_ENG_STAT_CTR(2).MRPS0[0x190]=0
MRPS_EGR_ENG_STAT_SETTINGS.MRPS0[0x166]=0xfffff00000
MRPS_EGR_ENG_WRAP_INTERRUPT_REGISTER.MRPS0[0x103]=0
MRPS_EGR_ENG_WRAP_INTERRUPT_REGISTER_MASK.MRPS0[0x104]=0
MRPS_EGR_ENG_WRAP_INTERRUPT_REGISTER_TEST.MRPS0[0x105]=0
MRPS_EGR_GENERAL_SETTINGS.MRPS0[0x10d]=3
MRPS_EGR_IN_COLOR_CTR(0).MRPS0[0x17e]=0x4e126a4df
MRPS_EGR_IN_COLOR_CTR(1).MRPS0[0x17f]=0
MRPS_EGR_IN_COLOR_CTR(2).MRPS0[0x180]=0
MRPS_EGR_IN_COLOR_CTR(3).MRPS0[0x181]=0
MRPS_EGR_LAST_RX_CMD.MRPS0[0x1bc]=0xb2
MRPS_EGR_OUT_COLOR_CTR(0).MRPS0[0x186]=0x4e126a4e3
MRPS_EGR_OUT_COLOR_CTR(1).MRPS0[0x187]=0
MRPS_EGR_OUT_COLOR_CTR(2).MRPS0[0x188]=0
MRPS_EGR_OUT_COLOR_CTR(3).MRPS0[0x189]=0
MRPS_EGR_WRAP_ERR_INDEX.MRPS0[0x1c0]=0
MRPS_ENABLE_DYNAMIC_MEMORY_ACCESS.MRPS0[0x84]=0
MRPS_GTIMER_CONFIGURATION.MRPS0[0x89]=0
MRPS_GTIMER_CYCLE.MRPS0[0x88]=0x3b9aca00
MRPS_INDIRECT_COMMAND.MRPS0[0x80]=0xe000002
MRPS_INDIRECT_COMMAND_ADDRESS.MRPS0[0x81]=0x6025
MRPS_INDIRECT_COMMAND_RD_DATA.MRPS0[0x60]=0
MRPS_INDIRECT_COMMAND_WR_DATA.MRPS0[0x20]=0x9a48a079c69859449038c200000018
MRPS_INDIRECT_FORCE_BUBBLE.MRPS0[0x83]=0x20019
MRPS_ING_ENG_ADDR_MAP(0).MRPS0[0x130]=0x11c50c0fbceb8db4cb0bacaa89a48a079c69859449038c288184081
MRPS_ING_ENG_ADDR_MAP(1).MRPS0[0x131]=0x11c50c0fbceb8db4cb0bacaa89a48a079c69859449038c288184089
MRPS_ING_ENG_ADDR_MAP(2).MRPS0[0x132]=0x11c50c0fbceb8db4cb0bacaa89a48a079c69859449038c28818408d
MRPS_ING_ENG_ADDR_RANGE(0).MRPS0[0x12b]=0
MRPS_ING_ENG_ADDR_RANGE(1).MRPS0[0x12c]=1
MRPS_ING_ENG_ADDR_RANGE(2).MRPS0[0x12d]=1
MRPS_ING_ENG_EXP_SETTINGS(0).MRPS0[0x11c]=0xb
MRPS_ING_ENG_EXP_SETTINGS(1).MRPS0[0x11d]=8
MRPS_ING_ENG_EXP_SETTINGS(2).MRPS0[0x11e]=8
MRPS_ING_ENG_FILTER(0).MRPS0[0x117]=0xe1
MRPS_ING_ENG_FILTER(1).MRPS0[0x118]=0
MRPS_ING_ENG_FILTER(2).MRPS0[0x119]=0
MRPS_ING_ENG_GLOBAL_SETTINGS(0).MRPS0[0x10f]=0x6060d
MRPS_ING_ENG_GLOBAL_SETTINGS(1).MRPS0[0x110]=0x4060d
MRPS_ING_ENG_GLOBAL_SETTINGS(2).MRPS0[0x111]=0x4060d
MRPS_ING_ENG_IN_COLOR_MAP(0).MRPS0[0x120]=0x8421
MRPS_ING_ENG_IN_COLOR_MAP(1).MRPS0[0x121]=0x8421
MRPS_ING_ENG_IN_COLOR_MAP(2).MRPS0[0x122]=0x8421
MRPS_ING_ENG_OOP_FIFO_DATA(0).MRPS0[0x15b]=0
MRPS_ING_ENG_OOP_FIFO_DATA(1).MRPS0[0x15c]=0
MRPS_ING_ENG_OOP_FIFO_DATA(2).MRPS0[0x15d]=0
MRPS_ING_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER.MRPS0[0x106]=0
MRPS_ING_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_MASK.MRPS0[0x107]=0
MRPS_ING_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_TEST.MRPS0[0x108]=0
MRPS_ING_ENG_OOP_FIFO_SETTINGS(0).MRPS0[0x155]=0
MRPS_ING_ENG_OOP_FIFO_SETTINGS(1).MRPS0[0x156]=0
MRPS_ING_ENG_OOP_FIFO_SETTINGS(2).MRPS0[0x157]=0
MRPS_ING_ENG_OOP_FIFO_WR_CTR(0).MRPS0[0x1b2]=0
MRPS_ING_ENG_OOP_FIFO_WR_CTR(1).MRPS0[0x1b3]=0
MRPS_ING_ENG_OOP_FIFO_WR_CTR(2).MRPS0[0x1b4]=0
MRPS_ING_ENG_OOP_FIFO_WR_CTR(3).MRPS0[0x1b5]=0
MRPS_ING_ENG_RND_SETTINGS(0).MRPS0[0x126]=0
MRPS_ING_ENG_RND_SETTINGS(1).MRPS0[0x127]=0
MRPS_ING_ENG_RND_SETTINGS(2).MRPS0[0x128]=0
MRPS_ING_ENG_STAT_CTR(0).MRPS0[0x178]=0
MRPS_ING_ENG_STAT_CTR(1).MRPS0[0x179]=0
MRPS_ING_ENG_STAT_CTR(2).MRPS0[0x17a]=0
MRPS_ING_ENG_STAT_SETTINGS.MRPS0[0x164]=0xfffff00000
MRPS_ING_ENG_WRAP_INTERRUPT_REGISTER.MRPS0[0x100]=0
MRPS_ING_ENG_WRAP_INTERRUPT_REGISTER_MASK.MRPS0[0x101]=0
MRPS_ING_ENG_WRAP_INTERRUPT_REGISTER_TEST.MRPS0[0x102]=0
MRPS_ING_GENERAL_SETTINGS.MRPS0[0x10c]=0x33
MRPS_ING_GLBL_ENG_FILTER.MRPS0[0x115]=0xe1
MRPS_ING_GLBL_ENG_GLOBAL_SETTINGS.MRPS0[0x10e]=0x2060e
MRPS_ING_GLBL_ENG_IN_BLACK_COLOR_CTR(0).MRPS0[0x19e]=0
MRPS_ING_GLBL_ENG_IN_BLACK_COLOR_CTR(1).MRPS0[0x19f]=0
MRPS_ING_GLBL_ENG_IN_BLACK_COLOR_CTR(2).MRPS0[0x1a0]=0
MRPS_ING_GLBL_ENG_IN_BLACK_COLOR_CTR(3).MRPS0[0x1a1]=0
MRPS_ING_GLBL_ENG_IN_BLACK_COLOR_CTR(4).MRPS0[0x1a2]=0
MRPS_ING_GLBL_ENG_IN_COLOR_MAP.MRPS0[0x11f]=0x8421
MRPS_ING_GLBL_ENG_IN_RED_COLOR_CTR(0).MRPS0[0x194]=0
MRPS_ING_GLBL_ENG_IN_RED_COLOR_CTR(1).MRPS0[0x195]=0
MRPS_ING_GLBL_ENG_IN_RED_COLOR_CTR(2).MRPS0[0x196]=0
MRPS_ING_GLBL_ENG_IN_RED_COLOR_CTR(3).MRPS0[0x197]=0
MRPS_ING_GLBL_ENG_IN_RED_COLOR_CTR(4).MRPS0[0x198]=0
MRPS_ING_GLBL_ENG_OOP_FIFO_DATA.MRPS0[0x154]=0
MRPS_ING_GLBL_ENG_OOP_FIFO_SETTINGS.MRPS0[0x153]=0
MRPS_ING_GLBL_ENG_RJCT_CTR(0).MRPS0[0x1a8]=0
MRPS_ING_GLBL_ENG_RJCT_CTR(1).MRPS0[0x1a9]=0
MRPS_ING_GLBL_ENG_RJCT_CTR(2).MRPS0[0x1aa]=0
MRPS_ING_GLBL_ENG_RJCT_CTR(3).MRPS0[0x1ab]=0
MRPS_ING_GLBL_ENG_RJCT_CTR(4).MRPS0[0x1ac]=0
MRPS_ING_GLBL_ENG_RND_SETTINGS.MRPS0[0x125]=0
MRPS_ING_GLBL_PTR_MAP.MRPS0[0x116]=0x3440
MRPS_ING_IN_COLOR_CTR(0).MRPS0[0x168]=0x4e12d5929
MRPS_ING_IN_COLOR_CTR(1).MRPS0[0x169]=0
MRPS_ING_IN_COLOR_CTR(2).MRPS0[0x16a]=0
MRPS_ING_IN_COLOR_CTR(3).MRPS0[0x16b]=0
MRPS_ING_LAST_RX_CMD.MRPS0[0x1b8]=0xc94040000000000000000060006b
MRPS_ING_OUT_COLOR_CTR(0).MRPS0[0x170]=0x4e12d592d
MRPS_ING_OUT_COLOR_CTR(1).MRPS0[0x171]=0
MRPS_ING_OUT_COLOR_CTR(2).MRPS0[0x172]=0
MRPS_ING_OUT_COLOR_CTR(3).MRPS0[0x173]=0
MRPS_ING_TC_MAP.MRPS0[0x1c4]=0
MRPS_ING_WRAP_ERR_INDEX.MRPS0[0x1be]=0
MRPS_INIT_SEQ_ON_STATUS.MRPS0[0x114]=0x38
MRPS_INTERRUPT_MASK_REGISTER.MRPS0[0x10]=0
MRPS_INTERRUPT_REGISTER.MRPS0[0x0]=0
MRPS_INTERRUPT_REGISTER_TEST.MRPS0[0x18]=0
MRPS_REG_0041.MRPS0[0x41]=0
MRPS_REG_00C2.MRPS0[0xc2]=0x10
MRPS_RESERVED_MTCD.MRPS0[0xae]=0x30
MRPS_RESERVED_MTCP.MRPS0[0xad]=0x300000600000000
MRPS_RESERVED_SPARE_0.MRPS0[0x90]=0xffffffff
MRPS_RESERVED_SPARE_1.MRPS0[0x91]=0xffffffff
MRPS_RESERVED_SPARE_2.MRPS0[0x92]=0
MRPS_RESERVED_SPARE_3.MRPS0[0x93]=0
MRPS_SBUS_BROADCAST_ID.MRPS0[0x86]=0x7ff
MRPS_SBUS_LAST_IN_CHAIN.MRPS0[0x87]=0
MRPS_SPECIAL_CLOCK_CONTROLS.MRPS0[0xc1]=2
MTM_DBG_EGR_LAST_MCDB_ADDR.MTM0[0x13a]=0
MTM_DBG_ING_LAST_MCDB_ADDR.MTM0[0x139]=0x1a
MTM_ECC_1B_ERR_CNT.MTM0[0x94]=0
MTM_ECC_2B_ERR_CNT.MTM0[0x96]=0
MTM_ECC_ERR_1B_MONITOR_MEM_MASK.MTM0[0x9a]=0xffffff
MTM_ECC_ERR_2B_MONITOR_MEM_MASK.MTM0[0x9c]=0xffffff
MTM_ECC_INTERRUPT_REGISTER.MTM0[0x7]=0
MTM_ECC_INTERRUPT_REGISTER_MASK.MTM0[0x17]=0
MTM_ECC_INTERRUPT_REGISTER_TEST.MTM0[0x1f]=0
MTM_EGR_ENG_DISABLE.MTM0[0x103]=0
MTM_EGR_ERR_MAX_REPLICATION_MCID.MTM0[0x10f]=0
MTM_EGR_INVALID_CUD.MTM0[0x106]=0
MTM_EGR_MAX_REPLICATIONS.MTM0[0x101]=0x1000
MTM_EGR_MCDB_OFFSET.MTM0[0x108]=0x4000
MTM_EGR_MCH_MCDB_REQUESTS_CTR.MTM0[0x125]=0
MTM_EGR_MCH_REPLICATION_DISCARD_CTR.MTM0[0x119]=0
MTM_EGR_MCL_MCDB_REQUESTS_CTR.MTM0[0x127]=0
MTM_EGR_MCL_REPLICATION_DISCARD_CTR.MTM0[0x11b]=0
MTM_EGR_TDM_FULL_PACKET_MODE.MTM0[0x107]=1
MTM_EGR_TDM_MCDB_REQUESTS_CTR.MTM0[0x121]=0
MTM_EGR_TDM_REPLICATION_DISCARD_CTR.MTM0[0x115]=0
MTM_EGR_UC_MCDB_REQUESTS_CTR.MTM0[0x123]=0
MTM_EGR_UC_REPLICATION_DISCARD_CTR.MTM0[0x117]=0
MTM_EG_ERR_REPLICATION_EMPTY_MCID.MTM0[0x110]=0
MTM_ENABLE_DYNAMIC_MEMORY_ACCESS.MTM0[0x84]=0
MTM_GTIMER_CONFIGURATION.MTM0[0x89]=0
MTM_GTIMER_CYCLE.MTM0[0x88]=0x3b9aca00
MTM_INDIRECT_COMMAND.MTM0[0x80]=0xe000002
MTM_INDIRECT_COMMAND_ADDRESS.MTM0[0x81]=5
MTM_INDIRECT_COMMAND_RD_DATA.MTM0[0x60]=0x400020020008100000000402000000a20002a1021000814000000000400040081300406400
MTM_INDIRECT_COMMAND_WR_DATA.MTM0[0x20]=0xffffffff0002b01116ac00030ffff000003fffff0003201115ac00230000f0110d2c0001
MTM_INDIRECT_FORCE_BUBBLE.MTM0[0x83]=0x20019
MTM_ING_ENG_DISABLE.MTM0[0x102]=0
MTM_ING_ERR_MAX_REPLICATION_MCID.MTM0[0x10d]=0
MTM_ING_ERR_REPLICATION_EMPTY_MCID.MTM0[0x10e]=0
MTM_ING_INVALID_CUD.MTM0[0x105]=0
MTM_ING_MAX_REPLICATIONS.MTM0[0x100]=0x1000
MTM_ING_MCDB_OFFSET.MTM0[0x109]=0
MTM_ING_MCH_MCDB_REQUESTS_CTR.MTM0[0x11d]=0x11e99ba
MTM_ING_MCH_REPLICATION_DISCARD_CTR.MTM0[0x111]=0
MTM_ING_MCL_MCDB_REQUESTS_CTR.MTM0[0x11f]=0
MTM_ING_MCL_REPLICATION_DISCARD_CTR.MTM0[0x113]=0
MTM_INTERRUPT_MASK_REGISTER.MTM0[0x10]=0
MTM_INTERRUPT_REGISTER.MTM0[0x0]=0
MTM_INTERRUPT_REGISTER_TEST.MTM0[0x18]=0
MTM_J_2C_FORMATS_DISABLE.MTM0[0x10b]=0
MTM_MCDB_BANK_COLLISION_CTR(0).MTM0[0x129]=0
MTM_MCDB_BANK_COLLISION_CTR(1).MTM0[0x12a]=0
MTM_MCDB_BANK_COLLISION_CTR(2).MTM0[0x12b]=0
MTM_MCDB_BANK_COLLISION_CTR(3).MTM0[0x12c]=0
MTM_MCDB_BANK_COLLISION_CTR(4).MTM0[0x12d]=0
MTM_MCDB_BANK_COLLISION_CTR(5).MTM0[0x12e]=0
MTM_MCDB_BANK_COLLISION_CTR(6).MTM0[0x12f]=0
MTM_MCDB_BANK_COLLISION_CTR(7).MTM0[0x130]=0
MTM_MCDB_BANK_COLLISION_CTR(8).MTM0[0x131]=0
MTM_MCDB_BANK_COLLISION_CTR(9).MTM0[0x132]=0
MTM_MCDB_BANK_COLLISION_CTR(10).MTM0[0x133]=0
MTM_MCDB_BANK_COLLISION_CTR(11).MTM0[0x134]=0
MTM_MCDB_BANK_COLLISION_CTR(12).MTM0[0x135]=0
MTM_MCDB_BANK_COLLISION_CTR(13).MTM0[0x136]=0
MTM_MCDB_BANK_COLLISION_CTR(14).MTM0[0x137]=0
MTM_MCDB_BANK_COLLISION_CTR(15).MTM0[0x138]=0
MTM_PCMI_0.MTM0[0xb0]=0x3b9aca00
MTM_PCMI_1.MTM0[0xb3]=0x3b9aca00
MTM_PCMI_2.MTM0[0xb6]=0x3b9aca00
MTM_PCMI_3.MTM0[0xb9]=0x3b9aca00
MTM_PCMI_4.MTM0[0xbc]=0x3b9aca00
MTM_PCMI_0_S.MTM0[0xb1]=0
MTM_PCMI_0_T.MTM0[0xb2]=0
MTM_PCMI_1_S.MTM0[0xb4]=0
MTM_PCMI_1_T.MTM0[0xb5]=0
MTM_PCMI_2_S.MTM0[0xb7]=0
MTM_PCMI_2_T.MTM0[0xb8]=0
MTM_PCMI_3_S.MTM0[0xba]=0
MTM_PCMI_3_T.MTM0[0xbb]=0
MTM_PCMI_4_S.MTM0[0xbd]=0
MTM_PCMI_4_T.MTM0[0xbe]=0
MTM_REG_0041.MTM0[0x41]=0
MTM_REG_00C2.MTM0[0xc2]=0x10
MTM_REPLICATOR_DISABLE.MTM0[0x10c]=0
MTM_RESERVED_MTCD.MTM0[0xae]=0x30
MTM_RESERVED_MTCP.MTM0[0xad]=0x300000600000000
MTM_RESERVED_SPARE_0.MTM0[0x90]=0xffffffff
MTM_RESERVED_SPARE_1.MTM0[0x91]=0xffffffff
MTM_RESERVED_SPARE_2.MTM0[0x92]=0
MTM_RESERVED_SPARE_3.MTM0[0x93]=0
MTM_SBUS_BROADCAST_ID.MTM0[0x86]=0x7ff
MTM_SBUS_LAST_IN_CHAIN.MTM0[0x87]=0
MTM_SPECIAL_CLOCK_CONTROLS.MTM0[0xc1]=2
MTM_X_4_BITMAP_FORMAT.MTM0[0x10a]=0
NMG_ADDITIONAL_RESETS_AND_CONFIGS.NMG0[0x103]=0x4a7
NMG_BIST_CONTEXTS_MASK.NMG0[0x12f]=0xffffffff
NMG_BIST_CONTEXT_TO_NIF_PORT_MAP.NMG0[0x12e]=0x1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100
NMG_BIST_COUNTERS_OVF.NMG0[0x149]=0xf6
NMG_BIST_FLOW_FIRST_DESCRIPTOR(0).NMG0[0x134]=0xff00010
NMG_BIST_FLOW_FIRST_DESCRIPTOR(1).NMG0[0x136]=0xff00010
NMG_BIST_FLOW_FIRST_DESCRIPTOR(2).NMG0[0x138]=0xff00010
NMG_BIST_FLOW_FIRST_DESCRIPTOR(3).NMG0[0x13a]=0xff00010
NMG_BIST_FLOW_SECOND_DESCRIPTOR(0).NMG0[0x13c]=0xfc040
NMG_BIST_FLOW_SECOND_DESCRIPTOR(1).NMG0[0x13e]=0xfc040
NMG_BIST_FLOW_SECOND_DESCRIPTOR(2).NMG0[0x140]=0xfc040
NMG_BIST_FLOW_SECOND_DESCRIPTOR(3).NMG0[0x142]=0xfc040
NMG_BIST_GENERAL_CONFIGURATION.NMG0[0x12d]=0x1000000000ff0
NMG_BIST_RX_COUNTERS_1.NMG0[0x145]=0x999b999b
NMG_BIST_RX_COUNTERS_2.NMG0[0x146]=0x8a9d0000
NMG_BIST_RX_COUNTERS_3.NMG0[0x147]=0x999ebd85
NMG_BIST_RX_FLOW_CNT.NMG0[0x148]=0x999f
NMG_BIST_RX_OK_PKT_CNT.NMG0[0x144]=0
NMG_BIST_RX_SHAPER.NMG0[0x14b]=0
NMG_BIST_SEED.NMG0[0x133]=0x155a
NMG_BIST_STATUS.NMG0[0x14a]=0x31101100
NMG_BIST_TX_ADDITIONAL_COUNTER.NMG0[0x132]=0
NMG_BIST_TX_PKT_CNT.NMG0[0x131]=0
NMG_BIST_TX_PKT_TH.NMG0[0x130]=0x1000
NMG_ECC_2B_ERR_CNT.NMG0[0x96]=0
NMG_ECC_INTERRUPT_REGISTER.NMG0[0x7]=0
NMG_ECC_INTERRUPT_REGISTER_MASK.NMG0[0x17]=0
NMG_ECC_INTERRUPT_REGISTER_TEST.NMG0[0x1f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(0).NMG0[0x15f]=0x23
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(1).NMG0[0x160]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(2).NMG0[0x161]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(3).NMG0[0x162]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(4).NMG0[0x163]=0x2b4
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(5).NMG0[0x164]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(6).NMG0[0x165]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(7).NMG0[0x166]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(8).NMG0[0x167]=0x517
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(9).NMG0[0x168]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(10).NMG0[0x169]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(11).NMG0[0x16a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(12).NMG0[0x16b]=0xb24
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(13).NMG0[0x16c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(14).NMG0[0x16d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(15).NMG0[0x16e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(16).NMG0[0x16f]=0x20
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(17).NMG0[0x170]=0x20
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(18).NMG0[0x171]=0x1a6
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(19).NMG0[0x172]=0xfaf
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(20).NMG0[0x173]=0x20
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(21).NMG0[0x174]=0x20
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(22).NMG0[0x175]=0x2a3
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(23).NMG0[0x176]=0x327
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(24).NMG0[0x177]=0xe7c
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(25).NMG0[0x178]=0x64
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(26).NMG0[0x179]=0xf35
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(27).NMG0[0x17a]=0x79f
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(28).NMG0[0x17b]=0x3d4
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(29).NMG0[0x17c]=0x33c
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(30).NMG0[0x17d]=0xbe6
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(31).NMG0[0x17e]=0x42c
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(32).NMG0[0x17f]=0xe82
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(33).NMG0[0x180]=0xe5d
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(34).NMG0[0x181]=0x9b6
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(35).NMG0[0x182]=0xc86
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(36).NMG0[0x183]=0xe51
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(37).NMG0[0x184]=0xe08
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(38).NMG0[0x185]=0x837
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(39).NMG0[0x186]=0x930
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(40).NMG0[0x187]=0x2d9
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(41).NMG0[0x188]=0x2a3
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(42).NMG0[0x189]=0x11b
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(43).NMG0[0x18a]=0x355
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(44).NMG0[0x18b]=0xc46
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(45).NMG0[0x18c]=0x6f9
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(46).NMG0[0x18d]=0xfd3
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(47).NMG0[0x18e]=4
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(48).NMG0[0x18f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(49).NMG0[0x190]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(50).NMG0[0x191]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(51).NMG0[0x192]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(52).NMG0[0x193]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(53).NMG0[0x194]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(54).NMG0[0x195]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(55).NMG0[0x196]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(56).NMG0[0x197]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(57).NMG0[0x198]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(58).NMG0[0x199]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(59).NMG0[0x19a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(60).NMG0[0x19b]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(61).NMG0[0x19c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(62).NMG0[0x19d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(63).NMG0[0x19e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(64).NMG0[0x19f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(65).NMG0[0x1a0]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(66).NMG0[0x1a1]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(67).NMG0[0x1a2]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(68).NMG0[0x1a3]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(69).NMG0[0x1a4]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(70).NMG0[0x1a5]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(71).NMG0[0x1a6]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(72).NMG0[0x1a7]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(73).NMG0[0x1a8]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(74).NMG0[0x1a9]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(75).NMG0[0x1aa]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(76).NMG0[0x1ab]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(77).NMG0[0x1ac]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(78).NMG0[0x1ad]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(79).NMG0[0x1ae]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(80).NMG0[0x1af]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(81).NMG0[0x1b0]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(82).NMG0[0x1b1]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(83).NMG0[0x1b2]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(84).NMG0[0x1b3]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(85).NMG0[0x1b4]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(86).NMG0[0x1b5]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(87).NMG0[0x1b6]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(88).NMG0[0x1b7]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(89).NMG0[0x1b8]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(90).NMG0[0x1b9]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(91).NMG0[0x1ba]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(92).NMG0[0x1bb]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(93).NMG0[0x1bc]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(94).NMG0[0x1bd]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(95).NMG0[0x1be]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(96).NMG0[0x1bf]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(97).NMG0[0x1c0]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(98).NMG0[0x1c1]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(99).NMG0[0x1c2]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(100).NMG0[0x1c3]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(101).NMG0[0x1c4]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(102).NMG0[0x1c5]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(103).NMG0[0x1c6]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(104).NMG0[0x1c7]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(105).NMG0[0x1c8]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(106).NMG0[0x1c9]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(107).NMG0[0x1ca]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(108).NMG0[0x1cb]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(109).NMG0[0x1cc]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(110).NMG0[0x1cd]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(111).NMG0[0x1ce]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(112).NMG0[0x1cf]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(113).NMG0[0x1d0]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(114).NMG0[0x1d1]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(115).NMG0[0x1d2]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(116).NMG0[0x1d3]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(117).NMG0[0x1d4]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(118).NMG0[0x1d5]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(119).NMG0[0x1d6]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(120).NMG0[0x1d7]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(121).NMG0[0x1d8]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(122).NMG0[0x1d9]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(123).NMG0[0x1da]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(124).NMG0[0x1db]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(125).NMG0[0x1dc]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(126).NMG0[0x1dd]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(127).NMG0[0x1de]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(128).NMG0[0x1df]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(129).NMG0[0x1e0]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(130).NMG0[0x1e1]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(131).NMG0[0x1e2]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(132).NMG0[0x1e3]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(133).NMG0[0x1e4]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(134).NMG0[0x1e5]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(135).NMG0[0x1e6]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(136).NMG0[0x1e7]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT(137).NMG0[0x1e8]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(0).NMG0[0x1e9]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(1).NMG0[0x1ea]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(2).NMG0[0x1eb]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(3).NMG0[0x1ec]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(4).NMG0[0x1ed]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(5).NMG0[0x1ee]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(6).NMG0[0x1ef]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(7).NMG0[0x1f0]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(8).NMG0[0x1f1]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(9).NMG0[0x1f2]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(10).NMG0[0x1f3]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(11).NMG0[0x1f4]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(12).NMG0[0x1f5]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(13).NMG0[0x1f6]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(14).NMG0[0x1f7]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(15).NMG0[0x1f8]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(16).NMG0[0x1f9]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(17).NMG0[0x1fa]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(18).NMG0[0x1fb]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(19).NMG0[0x1fc]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(20).NMG0[0x1fd]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(21).NMG0[0x1fe]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(22).NMG0[0x1ff]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(23).NMG0[0x200]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(24).NMG0[0x201]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(25).NMG0[0x202]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(26).NMG0[0x203]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(27).NMG0[0x204]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(28).NMG0[0x205]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(29).NMG0[0x206]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(30).NMG0[0x207]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(31).NMG0[0x208]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(32).NMG0[0x209]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(33).NMG0[0x20a]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(34).NMG0[0x20b]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(35).NMG0[0x20c]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(36).NMG0[0x20d]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(37).NMG0[0x20e]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(38).NMG0[0x20f]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(39).NMG0[0x210]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(40).NMG0[0x211]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(41).NMG0[0x212]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(42).NMG0[0x213]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(43).NMG0[0x214]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(44).NMG0[0x215]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(45).NMG0[0x216]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(46).NMG0[0x217]=1
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(47).NMG0[0x218]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(48).NMG0[0x219]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(49).NMG0[0x21a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(50).NMG0[0x21b]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(51).NMG0[0x21c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(52).NMG0[0x21d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(53).NMG0[0x21e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(54).NMG0[0x21f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(55).NMG0[0x220]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(56).NMG0[0x221]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(57).NMG0[0x222]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(58).NMG0[0x223]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(59).NMG0[0x224]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(60).NMG0[0x225]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(61).NMG0[0x226]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(62).NMG0[0x227]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(63).NMG0[0x228]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(64).NMG0[0x229]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(65).NMG0[0x22a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(66).NMG0[0x22b]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(67).NMG0[0x22c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(68).NMG0[0x22d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(69).NMG0[0x22e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(70).NMG0[0x22f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(71).NMG0[0x230]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(72).NMG0[0x231]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(73).NMG0[0x232]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(74).NMG0[0x233]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(75).NMG0[0x234]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(76).NMG0[0x235]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(77).NMG0[0x236]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(78).NMG0[0x237]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(79).NMG0[0x238]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(80).NMG0[0x239]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(81).NMG0[0x23a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(82).NMG0[0x23b]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(83).NMG0[0x23c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(84).NMG0[0x23d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(85).NMG0[0x23e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(86).NMG0[0x23f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(87).NMG0[0x240]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(88).NMG0[0x241]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(89).NMG0[0x242]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(90).NMG0[0x243]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(91).NMG0[0x244]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(92).NMG0[0x245]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(93).NMG0[0x246]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(94).NMG0[0x247]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(95).NMG0[0x248]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(96).NMG0[0x249]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(97).NMG0[0x24a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(98).NMG0[0x24b]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(99).NMG0[0x24c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(100).NMG0[0x24d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(101).NMG0[0x24e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(102).NMG0[0x24f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(103).NMG0[0x250]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(104).NMG0[0x251]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(105).NMG0[0x252]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(106).NMG0[0x253]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(107).NMG0[0x254]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(108).NMG0[0x255]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(109).NMG0[0x256]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(110).NMG0[0x257]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(111).NMG0[0x258]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(112).NMG0[0x259]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(113).NMG0[0x25a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(114).NMG0[0x25b]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(115).NMG0[0x25c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(116).NMG0[0x25d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(117).NMG0[0x25e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(118).NMG0[0x25f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(119).NMG0[0x260]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(120).NMG0[0x261]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(121).NMG0[0x262]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(122).NMG0[0x263]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(123).NMG0[0x264]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(124).NMG0[0x265]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(125).NMG0[0x266]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(126).NMG0[0x267]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(127).NMG0[0x268]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(128).NMG0[0x269]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(129).NMG0[0x26a]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(130).NMG0[0x26b]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(131).NMG0[0x26c]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(132).NMG0[0x26d]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(133).NMG0[0x26e]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(134).NMG0[0x26f]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(135).NMG0[0x270]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(136).NMG0[0x271]=0
NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT_WRAP_AROUND(137).NMG0[0x272]=0
NMG_EGQ_CRDT_MASK_PER_NIF_PORT.NMG0[0x273]=0
NMG_EGQ_SEND_BICAST_WITH_NO_VALID.NMG0[0x275]=0
NMG_ENABLE_FEU_FROM_IRE_LB.NMG0[0x11f]=1
NMG_FC_CFG.NMG0[0x15d]=1
NMG_FC_CHAINS_SYNC_SAMP_CONFIG.NMG0[0x15e]=0x92
NMG_FEU_CRDT_MASK_PER_NIF_PORT.NMG0[0x274]=0xfffffffffffff
NMG_FEU_RD_EN_SAMP_CFG.NMG0[0x27d]=2
NMG_FEU_SHAPER_CFG.NMG0[0x27b]=0
NMG_FEU_SHAPER_DEBUG.NMG0[0x27c]=0
NMG_FEU_SHAPER_MASKS_SCH_CNT.NMG0[0x27a]=0
NMG_FORCE_FLUSH_OR_STOP_RX_FIFO.NMG0[0x123]=0
NMG_GTIMER_CONFIGURATION.NMG0[0x89]=2
NMG_GTIMER_CYCLE.NMG0[0x88]=0x2800
NMG_INTERRUPT_MASK_REGISTER.NMG0[0x10]=0
NMG_INTERRUPT_REGISTER.NMG0[0x0]=0
NMG_INTERRUPT_REGISTER_TEST.NMG0[0x18]=0
NMG_IRE_TXI_RXI_INDICATION.NMG0[0x276]=0x2448
NMG_LAST_RECEIVED_FROM_EGQ_CONTROLS.NMG0[0x119]=0x80201da000200001f
NMG_LAST_RECEIVED_FROM_EGQ_DATA.NMG0[0x11a]=0x8c0cd6655b0e8884bd549976b7b62d43d3ca4b1f3913bde7ebb690af648244bed62633da4b0405f43888865d2ec6028e09e341f954b43470d26e3b14ec6e6761
NMG_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP.NMG0[0x11b]=0xe48d8c5ad687de26794a6d19810000040800450005c8ce2b0000f40699ab6c9c696b0a0b794601bb8f2805857c53e4d1600e801003ba7a9700000101080a3061
NMG_LAST_SENT_TO_IRE_CONTROLS.NMG0[0x11c]=0x6139b1b46ed2f5
NMG_LAST_SENT_TO_IRE_DATA.NMG0[0x11d]=0x5890885ca11d121eebb909c88586f26ab4c438db9d134d9256c176807997c03bbe6ee2dfcb5991f73c0bacb6f3c2000031068f9b1b2f651c591b0011acbd73c1
NMG_LAST_SENT_TO_IRE_DATA_ON_SOP.NMG0[0x11e]=0x648f71a32aa83011b5550597dfcef4dd7dfbc82098d4f65d186d00cb513bf84ec22bacf4ffe8a19a40a056e47929247406aae420256ea3710b2bb7c3d72136b3
NMG_NMG_TO_FEU_DEBUG_COUNTERS.NMG0[0x27e]=0
NMG_REG_0094.NMG0[0x94]=0
NMG_REG_0098.NMG0[0x98]=0
NMG_REG_009A.NMG0[0x9a]=0
NMG_REG_009C.NMG0[0x9c]=0
NMG_REG_00A0.NMG0[0xa0]=0
NMG_REG_00C2.NMG0[0xc2]=0x10
NMG_REG_00C4.NMG0[0xc4]=0
NMG_RESERVED_MTCD.NMG0[0xae]=0x30
NMG_RESERVED_MTCP.NMG0[0xad]=0x300000600000000
NMG_RESERVED_SPARE_0.NMG0[0x90]=0xffffffff
NMG_RESERVED_SPARE_1.NMG0[0x91]=0xffffffff
NMG_RESERVED_SPARE_2.NMG0[0x92]=0
NMG_RESERVED_SPARE_3.NMG0[0x93]=0
NMG_RX_FLUSH_MODE.NMG0[0x124]=0x140000000000000000
NMG_RX_ILKN_VIRTUAL_TDM_MODE.NMG0[0x125]=0
NMG_RX_PORTS_SRSTN.NMG0[0x101]=0x140000
NMG_RX_REQ_HIGH_EN.NMG0[0x121]=0
NMG_RX_REQ_LOW_EN.NMG0[0x120]=0xf1f
NMG_RX_REQ_TDM_EN.NMG0[0x122]=0
NMG_RX_SCH_DEBUG_CONF.NMG0[0x126]=0
NMG_RX_WITH_ERR_COUNTER.NMG0[0x279]=0
NMG_SBUS_BROADCAST_ID.NMG0[0x86]=0x7ff
NMG_SBUS_LAST_IN_CHAIN.NMG0[0x87]=0
NMG_SIF_CFG(0).NMG0[0x106]=0
NMG_SIF_CFG(1).NMG0[0x107]=0
NMG_SIF_EGQ_DIS_SIF_FOR_N_CYCLES_COUNTER(0).NMG0[0x114]=0
NMG_SIF_EGQ_DIS_SIF_FOR_N_CYCLES_COUNTER(1).NMG0[0x115]=0
NMG_SIF_EGQ_DIS_SIF_REQ(0).NMG0[0x110]=0
NMG_SIF_EGQ_DIS_SIF_REQ(1).NMG0[0x111]=0
NMG_SIF_IF_STICKY_VALUES(0).NMG0[0x12b]=0
NMG_SIF_IF_STICKY_VALUES(1).NMG0[0x12c]=0
NMG_SIF_IF_TABLE_TO_WIN_MACHINE.NMG0[0x15c]=2
NMG_SIF_LAST_SENT_CONTROLS.NMG0[0x116]=0
NMG_SIF_LAST_SENT_DATA.NMG0[0x118]=0
NMG_SIF_LAST_SENT_DATA_ON_SOP.NMG0[0x117]=0
NMG_SIF_MAP_TABLE(0).NMG0[0x15a]=0x40
NMG_SIF_MAP_TABLE(1).NMG0[0x15b]=0x40
NMG_SIF_MISS_EOP_ERR_COUNTER(0).NMG0[0x10e]=0
NMG_SIF_MISS_EOP_ERR_COUNTER(1).NMG0[0x10f]=0
NMG_SIF_MISS_SOP_ERR_COUNTER(0).NMG0[0x10c]=0
NMG_SIF_MISS_SOP_ERR_COUNTER(1).NMG0[0x10d]=0
NMG_SIF_NO_TMC_CRDT_DIS_SIF_REQ(0).NMG0[0x112]=0
NMG_SIF_NO_TMC_CRDT_DIS_SIF_REQ(1).NMG0[0x113]=0
NMG_SIF_TOTAL_PACKETS_COUNTER(0).NMG0[0x108]=0
NMG_SIF_TOTAL_PACKETS_COUNTER(1).NMG0[0x109]=0
NMG_SIF_TOTAL_PACKETS_WITH_ERR_COUNTER(0).NMG0[0x10a]=0
NMG_SIF_TOTAL_PACKETS_WITH_ERR_COUNTER(1).NMG0[0x10b]=0
NMG_SPECIAL_CLOCK_CONTROLS.NMG0[0xc1]=2
NMG_STATS_BURSTS_CNT_PORT(0).NMG0[0x127]=0
NMG_STATS_BURSTS_CNT_PORT(1).NMG0[0x128]=0
NMG_STATS_OCTETS_CNT_PORT(0).NMG0[0x129]=0
NMG_STATS_OCTETS_CNT_PORT(1).NMG0[0x12a]=0
NMG_SYNC_ETH_CFG(0).NMG0[0x14c]=0x2c
NMG_SYNC_ETH_CFG(1).NMG0[0x14d]=0x2c
NMG_SYNC_ETH_CHAIN_SEL_FOR_CLOCK_VLD(0).NMG0[0x154]=0
NMG_SYNC_ETH_CHAIN_SEL_FOR_CLOCK_VLD(1).NMG0[0x155]=0
NMG_SYNC_ETH_CHAIN_SEL_FOR_LINK_STATUS(0).NMG0[0x156]=0
NMG_SYNC_ETH_CHAIN_SEL_FOR_LINK_STATUS(1).NMG0[0x157]=0
NMG_SYNC_ETH_CHAIN_SEL_FOR_SYNCE_CLK_WINNER(0).NMG0[0x158]=0
NMG_SYNC_ETH_CHAIN_SEL_FOR_SYNCE_CLK_WINNER(1).NMG0[0x159]=0
NMG_SYNC_ETH_COUNTER(0).NMG0[0x14e]=0x12a
NMG_SYNC_ETH_COUNTER(1).NMG0[0x14f]=0xfb0cfac7
NMG_SYNC_ETH_LINK_STATUS_CHANGES(0).NMG0[0x152]=0
NMG_SYNC_ETH_LINK_STATUS_CHANGES(1).NMG0[0x153]=0
NMG_SYNC_ETH_SQUELCH_DIS_TH_REG.NMG0[0x150]=0x2625a
NMG_SYNC_ETH_SQUELCH_EN_TH_REG.NMG0[0x151]=0x9c
NMG_TXI_NOT_READY.NMG0[0x104]=0
NMG_TXI_TDM_NOT_READY.NMG0[0x105]=0
NMG_TX_PORTS_SRSTN.NMG0[0x102]=0x3ffffffffffffffffffffffffffffffffff
NMG_TX_PORT_DEBUG_UNDERRUN.NMG0[0x278]=0x700
NMG_TX_WITH_ERR_COUNTER.NMG0[0x277]=0
NS_BROADSYNC0_CLK_EVENT_CTRL.CMIC0[0x35348]=0
NS_BROADSYNC1_CLK_EVENT_CTRL.CMIC0[0x3534c]=0
NS_BROADSYNC_REF_CLK_GEN_CTRL.CMIC0[0x35350]=0
NS_BROADSYNC_SYNC_MODE.CMIC0[0x35354]=0
NS_BS0_BS_CLK_CTRL.CMIC0[0x34004]=0x10101
NS_BS0_BS_CONFIG.CMIC0[0x34000]=0x78
NS_BS0_BS_HEARTBEAT_CTRL.CMIC0[0x34008]=1
NS_BS0_BS_HEARTBEAT_DOWN_DURATION.CMIC0[0x34010]=0x98961c
NS_BS0_BS_HEARTBEAT_UP_DURATION.CMIC0[0x3400c]=0x64
NS_BS0_BS_INITIAL_CRC.CMIC0[0x3402c]=0
NS_BS0_BS_INPUT_TIME_0.CMIC0[0x34020]=0
NS_BS0_BS_INPUT_TIME_1.CMIC0[0x34024]=0
NS_BS0_BS_INPUT_TIME_2.CMIC0[0x34028]=0
NS_BS0_BS_OUTPUT_TIME_0.CMIC0[0x34014]=0x1000000
NS_BS0_BS_OUTPUT_TIME_1.CMIC0[0x34018]=0
NS_BS0_BS_OUTPUT_TIME_2.CMIC0[0x3401c]=0
NS_BS0_BS_TC_CTRL.CMIC0[0x34030]=0
NS_BS1_BS_CLK_CTRL.CMIC0[0x34104]=0
NS_BS1_BS_CONFIG.CMIC0[0x34100]=0x40
NS_BS1_BS_HEARTBEAT_CTRL.CMIC0[0x34108]=0
NS_BS1_BS_HEARTBEAT_DOWN_DURATION.CMIC0[0x34110]=0x3ffffff
NS_BS1_BS_HEARTBEAT_UP_DURATION.CMIC0[0x3410c]=0x3ffffff
NS_BS1_BS_INITIAL_CRC.CMIC0[0x3412c]=0
NS_BS1_BS_INPUT_TIME_0.CMIC0[0x34120]=0
NS_BS1_BS_INPUT_TIME_1.CMIC0[0x34124]=0
NS_BS1_BS_INPUT_TIME_2.CMIC0[0x34128]=0
NS_BS1_BS_OUTPUT_TIME_0.CMIC0[0x34114]=0
NS_BS1_BS_OUTPUT_TIME_1.CMIC0[0x34118]=0
NS_BS1_BS_OUTPUT_TIME_2.CMIC0[0x3411c]=0
NS_BS1_BS_TC_CTRL.CMIC0[0x34130]=0
NS_COMMON_CTRL.CMIC0[0x35000]=3
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL0.CMIC0[0x358cc]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL1.CMIC0[0x358d0]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL2.CMIC0[0x358d4]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL3.CMIC0[0x358d8]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL4.CMIC0[0x358dc]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL5.CMIC0[0x358e0]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL6.CMIC0[0x358e4]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL7.CMIC0[0x358e8]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL8.CMIC0[0x358ec]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL9.CMIC0[0x358f0]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL10.CMIC0[0x358f4]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL11.CMIC0[0x358f8]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL12.CMIC0[0x358fc]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL13.CMIC0[0x35900]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL14.CMIC0[0x35904]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL15.CMIC0[0x35908]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION0.CMIC0[0x3590c]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION1.CMIC0[0x35910]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION2.CMIC0[0x35914]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION3.CMIC0[0x35918]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION4.CMIC0[0x3591c]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION5.CMIC0[0x35920]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION6.CMIC0[0x35924]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION7.CMIC0[0x35928]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION8.CMIC0[0x3592c]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION9.CMIC0[0x35930]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION10.CMIC0[0x35934]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION11.CMIC0[0x35938]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION12.CMIC0[0x3593c]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION13.CMIC0[0x35940]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION14.CMIC0[0x35944]=0
NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION15.CMIC0[0x35948]=0
NS_MISC_CLK_EVENT_CTRL.CMIC0[0x35358]=0x130002
NS_MISC_EVENT_OVRD_STATUS.CMIC0[0x35698]=0
NS_MISC_EVENT_STATUS.CMIC0[0x35684]=0x1db
NS_ROE_TS_INT_ENABLE.CMIC0[0x3595c]=0
NS_ROE_TS_INT_STATUS.CMIC0[0x35958]=0
NS_RX_CDR_EVENT_OVRD_STATUS0.CMIC0[0x35688]=0
NS_RX_CDR_EVENT_OVRD_STATUS1.CMIC0[0x3568c]=0
NS_RX_CDR_EVENT_STATUS0.CMIC0[0x35674]=0
NS_RX_CDR_EVENT_STATUS1.CMIC0[0x35678]=0
NS_TIMESYNC_COUNTER_CONFIG_SELECT.CMIC0[0x35004]=1
NS_TIMESYNC_GPIO_0_CTRL.CMIC0[0x350a8]=0
NS_TIMESYNC_GPIO_0_DOWN_EVENT_CTRL.CMIC0[0x350b4]=0
NS_TIMESYNC_GPIO_0_OUTPUT_ENABLE.CMIC0[0x350ac]=0
NS_TIMESYNC_GPIO_0_PHASE_ADJUST_LOWER.CMIC0[0x350b8]=0
NS_TIMESYNC_GPIO_0_PHASE_ADJUST_UPPER.CMIC0[0x350bc]=0
NS_TIMESYNC_GPIO_0_UP_EVENT_CTRL.CMIC0[0x350b0]=0
NS_TIMESYNC_GPIO_1_CTRL.CMIC0[0x350c0]=0
NS_TIMESYNC_GPIO_1_DOWN_EVENT_CTRL.CMIC0[0x350cc]=0
NS_TIMESYNC_GPIO_1_OUTPUT_ENABLE.CMIC0[0x350c4]=0
NS_TIMESYNC_GPIO_1_PHASE_ADJUST_LOWER.CMIC0[0x350d0]=0
NS_TIMESYNC_GPIO_1_PHASE_ADJUST_UPPER.CMIC0[0x350d4]=0
NS_TIMESYNC_GPIO_1_UP_EVENT_CTRL.CMIC0[0x350c8]=0
NS_TIMESYNC_GPIO_2_CTRL.CMIC0[0x350d8]=0
NS_TIMESYNC_GPIO_2_DOWN_EVENT_CTRL.CMIC0[0x350e4]=0
NS_TIMESYNC_GPIO_2_OUTPUT_ENABLE.CMIC0[0x350dc]=0
NS_TIMESYNC_GPIO_2_PHASE_ADJUST_LOWER.CMIC0[0x350e8]=0
NS_TIMESYNC_GPIO_2_PHASE_ADJUST_UPPER.CMIC0[0x350ec]=0
NS_TIMESYNC_GPIO_2_UP_EVENT_CTRL.CMIC0[0x350e0]=0
NS_TIMESYNC_GPIO_3_CTRL.CMIC0[0x350f0]=0
NS_TIMESYNC_GPIO_3_DOWN_EVENT_CTRL.CMIC0[0x350fc]=0
NS_TIMESYNC_GPIO_3_OUTPUT_ENABLE.CMIC0[0x350f4]=0
NS_TIMESYNC_GPIO_3_PHASE_ADJUST_LOWER.CMIC0[0x35100]=0
NS_TIMESYNC_GPIO_3_PHASE_ADJUST_UPPER.CMIC0[0x35104]=0
NS_TIMESYNC_GPIO_3_UP_EVENT_CTRL.CMIC0[0x350f8]=0
NS_TIMESYNC_GPIO_4_CTRL.CMIC0[0x35108]=0
NS_TIMESYNC_GPIO_4_DOWN_EVENT_CTRL.CMIC0[0x35114]=0
NS_TIMESYNC_GPIO_4_OUTPUT_ENABLE.CMIC0[0x3510c]=0
NS_TIMESYNC_GPIO_4_PHASE_ADJUST_LOWER.CMIC0[0x35118]=0
NS_TIMESYNC_GPIO_4_PHASE_ADJUST_UPPER.CMIC0[0x3511c]=0
NS_TIMESYNC_GPIO_4_UP_EVENT_CTRL.CMIC0[0x35110]=0
NS_TIMESYNC_GPIO_5_CTRL.CMIC0[0x35120]=0
NS_TIMESYNC_GPIO_5_DOWN_EVENT_CTRL.CMIC0[0x3512c]=0
NS_TIMESYNC_GPIO_5_OUTPUT_ENABLE.CMIC0[0x35124]=0
NS_TIMESYNC_GPIO_5_PHASE_ADJUST_LOWER.CMIC0[0x35130]=0
NS_TIMESYNC_GPIO_5_PHASE_ADJUST_UPPER.CMIC0[0x35134]=0
NS_TIMESYNC_GPIO_5_UP_EVENT_CTRL.CMIC0[0x35128]=0
NS_TIMESYNC_INPUT_TIME_FIFO_STATUS.CMIC0[0x3566c]=0xc1
NS_TIMESYNC_INPUT_TIME_FIFO_TS_0.CMIC0[0x3565c]=0x29c36f00
NS_TIMESYNC_INPUT_TIME_FIFO_TS_1.CMIC0[0x35660]=0xf000001d
NS_TIMESYNC_INPUT_TIME_FIFO_TS_2.CMIC0[0x35664]=0x1de3700
NS_TIMESYNC_INPUT_TIME_FIFO_TS_3.CMIC0[0x35668]=0x130400
NS_TIMESYNC_MAPPER_FWD_CFG0.CMIC0[0x356cc]=0
NS_TIMESYNC_MAPPER_FWD_CFG1.CMIC0[0x356d0]=0
NS_TIMESYNC_MAPPER_FWD_CFG2.CMIC0[0x356d4]=0
NS_TIMESYNC_MAPPER_FWD_CFG3.CMIC0[0x356d8]=0
NS_TIMESYNC_MAPPER_FWD_CFG4.CMIC0[0x356dc]=0
NS_TIMESYNC_MAPPER_FWD_CFG5.CMIC0[0x356e0]=0
NS_TIMESYNC_MAPPER_FWD_CFG6.CMIC0[0x356e4]=0
NS_TIMESYNC_MAPPER_FWD_CFG7.CMIC0[0x356e8]=0
NS_TIMESYNC_MAPPER_FWD_CFG8.CMIC0[0x356ec]=0
NS_TIMESYNC_MAPPER_FWD_CFG9.CMIC0[0x356f0]=0
NS_TIMESYNC_MAPPER_FWD_CFG10.CMIC0[0x356f4]=0
NS_TIMESYNC_MAPPER_FWD_CFG11.CMIC0[0x356f8]=0
NS_TIMESYNC_MAPPER_FWD_CFG12.CMIC0[0x356fc]=0
NS_TIMESYNC_MAPPER_FWD_CFG13.CMIC0[0x35700]=0
NS_TIMESYNC_MAPPER_FWD_CFG14.CMIC0[0x35704]=0
NS_TIMESYNC_MAPPER_FWD_CFG15.CMIC0[0x35708]=0
NS_TIMESYNC_MAPPER_FWD_CFG16.CMIC0[0x3570c]=0
NS_TIMESYNC_MAPPER_FWD_CFG17.CMIC0[0x35710]=0
NS_TIMESYNC_MAPPER_FWD_CFG18.CMIC0[0x35714]=0
NS_TIMESYNC_MAPPER_FWD_CFG19.CMIC0[0x35718]=0
NS_TIMESYNC_MAPPER_FWD_CFG20.CMIC0[0x3571c]=0
NS_TIMESYNC_MAPPER_FWD_CFG21.CMIC0[0x35720]=0
NS_TIMESYNC_MAPPER_FWD_CFG22.CMIC0[0x35724]=0
NS_TIMESYNC_MAPPER_FWD_CFG23.CMIC0[0x35728]=0
NS_TIMESYNC_MAPPER_FWD_CFG24.CMIC0[0x3572c]=0
NS_TIMESYNC_MAPPER_FWD_CFG25.CMIC0[0x35730]=0
NS_TIMESYNC_MAPPER_FWD_CFG26.CMIC0[0x35734]=0
NS_TIMESYNC_MAPPER_FWD_CFG27.CMIC0[0x35738]=0
NS_TIMESYNC_MAPPER_FWD_CFG28.CMIC0[0x3573c]=0
NS_TIMESYNC_MAPPER_FWD_CFG29.CMIC0[0x35740]=0
NS_TIMESYNC_MAPPER_FWD_CFG30.CMIC0[0x35744]=0
NS_TIMESYNC_MAPPER_FWD_CFG31.CMIC0[0x35748]=0
NS_TIMESYNC_MAPPER_FWD_CFG32.CMIC0[0x3574c]=0
NS_TIMESYNC_MAPPER_FWD_CFG33.CMIC0[0x35750]=0
NS_TIMESYNC_MAPPER_FWD_CFG34.CMIC0[0x35754]=0
NS_TIMESYNC_MAPPER_FWD_CFG35.CMIC0[0x35758]=0
NS_TIMESYNC_MAPPER_FWD_CFG36.CMIC0[0x3575c]=0
NS_TIMESYNC_MAPPER_FWD_CFG37.CMIC0[0x35760]=0
NS_TIMESYNC_MAPPER_FWD_CFG38.CMIC0[0x35764]=0
NS_TIMESYNC_MAPPER_FWD_CFG39.CMIC0[0x35768]=0
NS_TIMESYNC_MAPPER_FWD_CFG40.CMIC0[0x3576c]=0
NS_TIMESYNC_MAPPER_FWD_CFG41.CMIC0[0x35770]=0
NS_TIMESYNC_MAPPER_FWD_CFG42.CMIC0[0x35774]=0
NS_TIMESYNC_MAPPER_FWD_CFG43.CMIC0[0x35778]=0
NS_TIMESYNC_MAPPER_FWD_CFG44.CMIC0[0x3577c]=0
NS_TIMESYNC_MAPPER_FWD_CFG45.CMIC0[0x35780]=0
NS_TIMESYNC_MAPPER_FWD_CFG46.CMIC0[0x35784]=0
NS_TIMESYNC_MAPPER_FWD_CFG47.CMIC0[0x35788]=0
NS_TIMESYNC_MAPPER_FWD_CFG48.CMIC0[0x3578c]=0
NS_TIMESYNC_MAPPER_FWD_CFG49.CMIC0[0x35790]=0
NS_TIMESYNC_MAPPER_FWD_CFG50.CMIC0[0x35794]=0
NS_TIMESYNC_MAPPER_FWD_CFG51.CMIC0[0x35798]=0
NS_TIMESYNC_MAPPER_FWD_CFG52.CMIC0[0x3579c]=0
NS_TIMESYNC_MAPPER_FWD_CFG53.CMIC0[0x357a0]=0
NS_TIMESYNC_MAPPER_FWD_CFG54.CMIC0[0x357a4]=0
NS_TIMESYNC_MAPPER_FWD_CFG55.CMIC0[0x357a8]=0
NS_TIMESYNC_MAPPER_FWD_CFG56.CMIC0[0x357ac]=0
NS_TIMESYNC_MAPPER_FWD_CFG57.CMIC0[0x357b0]=0
NS_TIMESYNC_MAPPER_FWD_CFG58.CMIC0[0x357b4]=0
NS_TIMESYNC_MAPPER_FWD_CFG59.CMIC0[0x357b8]=0
NS_TIMESYNC_MAPPER_FWD_CFG60.CMIC0[0x357bc]=0
NS_TIMESYNC_MAPPER_FWD_CFG61.CMIC0[0x357c0]=0
NS_TIMESYNC_MAPPER_FWD_CFG62.CMIC0[0x357c4]=0
NS_TIMESYNC_MAPPER_FWD_CFG63.CMIC0[0x357c8]=0
NS_TIMESYNC_MAPPER_FWD_CFG64.CMIC0[0x357cc]=0
NS_TIMESYNC_MAPPER_FWD_CFG65.CMIC0[0x357d0]=0
NS_TIMESYNC_MAPPER_FWD_CFG66.CMIC0[0x357d4]=0
NS_TIMESYNC_MAPPER_FWD_CFG67.CMIC0[0x357d8]=0
NS_TIMESYNC_MAPPER_FWD_CFG68.CMIC0[0x357dc]=0
NS_TIMESYNC_MAPPER_FWD_CFG69.CMIC0[0x357e0]=0
NS_TIMESYNC_MAPPER_FWD_CFG70.CMIC0[0x357e4]=0
NS_TIMESYNC_MAPPER_FWD_CFG71.CMIC0[0x357e8]=0
NS_TIMESYNC_MAPPER_FWD_CFG72.CMIC0[0x357ec]=0
NS_TIMESYNC_MAPPER_FWD_CFG73.CMIC0[0x357f0]=0
NS_TIMESYNC_MAPPER_FWD_CFG74.CMIC0[0x357f4]=0
NS_TIMESYNC_MAPPER_FWD_CFG75.CMIC0[0x357f8]=0
NS_TIMESYNC_MAPPER_FWD_CFG76.CMIC0[0x357fc]=0
NS_TIMESYNC_MAPPER_FWD_CFG77.CMIC0[0x35800]=0
NS_TIMESYNC_MAPPER_FWD_CFG78.CMIC0[0x35804]=0
NS_TIMESYNC_MAPPER_FWD_CFG79.CMIC0[0x35808]=0
NS_TIMESYNC_MAPPER_FWD_CFG80.CMIC0[0x3580c]=0
NS_TIMESYNC_MAPPER_FWD_CFG81.CMIC0[0x35810]=0
NS_TIMESYNC_MAPPER_FWD_CFG82.CMIC0[0x35814]=0
NS_TIMESYNC_MAPPER_FWD_CFG83.CMIC0[0x35818]=0
NS_TIMESYNC_MAPPER_FWD_CFG84.CMIC0[0x3581c]=0
NS_TIMESYNC_MAPPER_FWD_CFG85.CMIC0[0x35820]=0
NS_TIMESYNC_MAPPER_FWD_CFG86.CMIC0[0x35824]=0
NS_TIMESYNC_MAPPER_FWD_CFG87.CMIC0[0x35828]=0
NS_TIMESYNC_MAPPER_FWD_CFG88.CMIC0[0x3582c]=0
NS_TIMESYNC_MAPPER_FWD_CFG89.CMIC0[0x35830]=0
NS_TIMESYNC_MAPPER_FWD_CFG90.CMIC0[0x35834]=0
NS_TIMESYNC_MAPPER_FWD_CFG91.CMIC0[0x35838]=0
NS_TIMESYNC_MAPPER_FWD_CFG92.CMIC0[0x3583c]=0
NS_TIMESYNC_MAPPER_FWD_CFG93.CMIC0[0x35840]=0
NS_TIMESYNC_MAPPER_FWD_CFG94.CMIC0[0x35844]=0
NS_TIMESYNC_MAPPER_FWD_CFG95.CMIC0[0x35848]=0
NS_TIMESYNC_MAPPER_FWD_CFG96.CMIC0[0x3584c]=0
NS_TIMESYNC_MAPPER_FWD_CFG97.CMIC0[0x35850]=0
NS_TIMESYNC_MAPPER_FWD_CFG98.CMIC0[0x35854]=0
NS_TIMESYNC_MAPPER_FWD_CFG99.CMIC0[0x35858]=0
NS_TIMESYNC_MAPPER_FWD_CFG100.CMIC0[0x3585c]=0
NS_TIMESYNC_MAPPER_FWD_CFG101.CMIC0[0x35860]=0
NS_TIMESYNC_MAPPER_FWD_CFG102.CMIC0[0x35864]=0
NS_TIMESYNC_MAPPER_FWD_CFG103.CMIC0[0x35868]=0
NS_TIMESYNC_MAPPER_FWD_CFG104.CMIC0[0x3586c]=0
NS_TIMESYNC_MAPPER_FWD_CFG105.CMIC0[0x35870]=0
NS_TIMESYNC_MAPPER_FWD_CFG106.CMIC0[0x35874]=0
NS_TIMESYNC_MAPPER_FWD_CFG107.CMIC0[0x35878]=0
NS_TIMESYNC_MAPPER_FWD_CFG108.CMIC0[0x3587c]=0
NS_TIMESYNC_MAPPER_FWD_CFG109.CMIC0[0x35880]=0
NS_TIMESYNC_MAPPER_FWD_CFG110.CMIC0[0x35884]=0
NS_TIMESYNC_MAPPER_FWD_CFG111.CMIC0[0x35888]=0
NS_TIMESYNC_MAPPER_FWD_CFG112.CMIC0[0x3588c]=0
NS_TIMESYNC_MAPPER_FWD_CFG113.CMIC0[0x35890]=0
NS_TIMESYNC_MAPPER_FWD_CFG114.CMIC0[0x35894]=0
NS_TIMESYNC_MAPPER_FWD_CFG115.CMIC0[0x35898]=0
NS_TIMESYNC_MAPPER_FWD_CFG116.CMIC0[0x3589c]=0
NS_TIMESYNC_MAPPER_FWD_CFG117.CMIC0[0x358a0]=0
NS_TIMESYNC_MAPPER_FWD_CFG118.CMIC0[0x358a4]=0
NS_TIMESYNC_MAPPER_FWD_CFG119.CMIC0[0x358a8]=0
NS_TIMESYNC_MAPPER_FWD_CFG120.CMIC0[0x358ac]=0
NS_TIMESYNC_MAPPER_FWD_CFG121.CMIC0[0x358b0]=0
NS_TIMESYNC_MAPPER_FWD_CFG122.CMIC0[0x358b4]=0
NS_TIMESYNC_MAPPER_FWD_CFG123.CMIC0[0x358b8]=0
NS_TIMESYNC_MAPPER_FWD_CFG124.CMIC0[0x358bc]=0
NS_TIMESYNC_MAPPER_FWD_CFG125.CMIC0[0x358c0]=0
NS_TIMESYNC_MAPPER_FWD_CFG126.CMIC0[0x358c4]=0
NS_TIMESYNC_MAPPER_FWD_CFG127.CMIC0[0x358c8]=0
NS_TIMESYNC_MAPPER_PORT_ENABLE_0.CMIC0[0x3569c]=0
NS_TIMESYNC_MAPPER_PORT_ENABLE_1.CMIC0[0x356a0]=0
NS_TIMESYNC_MAPPER_PORT_ENABLE_2.CMIC0[0x356a4]=0
NS_TIMESYNC_MAPPER_PORT_ENABLE_3.CMIC0[0x356a8]=0
NS_TIMESYNC_MAPPER_RX_TYPE0_OVRD_STATUS.CMIC0[0x356c0]=0
NS_TIMESYNC_MAPPER_RX_TYPE0_STATUS.CMIC0[0x356b4]=0
NS_TIMESYNC_MAPPER_RX_TYPE1_OVRD_STATUS.CMIC0[0x356c4]=0
NS_TIMESYNC_MAPPER_RX_TYPE1_STATUS.CMIC0[0x356b8]=0
NS_TIMESYNC_MAPPER_RX_TYPE2_OVRD_STATUS.CMIC0[0x356c8]=0
NS_TIMESYNC_MAPPER_RX_TYPE2_STATUS.CMIC0[0x356bc]=0
NS_TIMESYNC_MAPPER_TYPE2_FORMAT.CMIC0[0x356ac]=0
NS_TIMESYNC_ROE_MAX_DELTA.CMIC0[0x356b0]=0xfffffff
NS_TIMESYNC_RX_CDR_EVENT_CTRL0.CMIC0[0x35138]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL1.CMIC0[0x3513c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL2.CMIC0[0x35140]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL3.CMIC0[0x35144]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL4.CMIC0[0x35148]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL5.CMIC0[0x3514c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL6.CMIC0[0x35150]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL7.CMIC0[0x35154]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL8.CMIC0[0x35158]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL9.CMIC0[0x3515c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL10.CMIC0[0x35160]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL11.CMIC0[0x35164]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL12.CMIC0[0x35168]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL13.CMIC0[0x3516c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL14.CMIC0[0x35170]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL15.CMIC0[0x35174]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL16.CMIC0[0x35178]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL17.CMIC0[0x3517c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL18.CMIC0[0x35180]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL19.CMIC0[0x35184]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL20.CMIC0[0x35188]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL21.CMIC0[0x3518c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL22.CMIC0[0x35190]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL23.CMIC0[0x35194]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL24.CMIC0[0x35198]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL25.CMIC0[0x3519c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL26.CMIC0[0x351a0]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL27.CMIC0[0x351a4]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL28.CMIC0[0x351a8]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL29.CMIC0[0x351ac]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL30.CMIC0[0x351b0]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL31.CMIC0[0x351b4]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL32.CMIC0[0x351b8]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL33.CMIC0[0x351bc]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL34.CMIC0[0x351c0]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL35.CMIC0[0x351c4]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL36.CMIC0[0x351c8]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL37.CMIC0[0x351cc]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL38.CMIC0[0x351d0]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL39.CMIC0[0x351d4]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL40.CMIC0[0x351d8]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL41.CMIC0[0x351dc]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL42.CMIC0[0x351e0]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL43.CMIC0[0x351e4]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL44.CMIC0[0x351e8]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL45.CMIC0[0x351ec]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL46.CMIC0[0x351f0]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL47.CMIC0[0x351f4]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL48.CMIC0[0x351f8]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL49.CMIC0[0x351fc]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL50.CMIC0[0x35200]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL51.CMIC0[0x35204]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL52.CMIC0[0x35208]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL53.CMIC0[0x3520c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL54.CMIC0[0x35210]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL55.CMIC0[0x35214]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL56.CMIC0[0x35218]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL57.CMIC0[0x3521c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL58.CMIC0[0x35220]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL59.CMIC0[0x35224]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL60.CMIC0[0x35228]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL61.CMIC0[0x3522c]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL62.CMIC0[0x35230]=0
NS_TIMESYNC_RX_CDR_EVENT_CTRL63.CMIC0[0x35234]=0
NS_TIMESYNC_SERDES_LCPLL_EVENT_CTRL0.CMIC0[0x35338]=0
NS_TIMESYNC_SERDES_LCPLL_EVENT_CTRL1.CMIC0[0x3533c]=0
NS_TIMESYNC_SERDES_LCPLL_EVENT_CTRL2.CMIC0[0x35340]=0
NS_TIMESYNC_SERDES_LCPLL_EVENT_CTRL3.CMIC0[0x35344]=0
NS_TIMESYNC_TS0_ACCUMULATOR_0.CMIC0[0x35068]=0
NS_TIMESYNC_TS0_ACCUMULATOR_1.CMIC0[0x3506c]=0x76898000
NS_TIMESYNC_TS0_ACCUMULATOR_2.CMIC0[0x35070]=0xfa22c47
NS_TIMESYNC_TS0_BS_INIT_CTRL.CMIC0[0x35030]=0
NS_TIMESYNC_TS0_COUNTER_ENABLE.CMIC0[0x35020]=1
NS_TIMESYNC_TS0_CURRENT_FREQ_CTRL_LOWER.CMIC0[0x3507c]=0
NS_TIMESYNC_TS0_CURRENT_FREQ_CTRL_UPPER.CMIC0[0x35080]=0x2000
NS_TIMESYNC_TS0_FREQ_CTRL_FRAC_LOWER.CMIC0[0x35018]=0
NS_TIMESYNC_TS0_FREQ_CTRL_FRAC_UPPER.CMIC0[0x3501c]=0x2000
NS_TIMESYNC_TS0_FREQ_CTRL_OFFSET_LOWER.CMIC0[0x35010]=0
NS_TIMESYNC_TS0_FREQ_CTRL_OFFSET_UPPER.CMIC0[0x35014]=0
NS_TIMESYNC_TS0_FREQ_CTRL_UPDATE_LOWER.CMIC0[0x35008]=0
NS_TIMESYNC_TS0_FREQ_CTRL_UPDATE_UPPER.CMIC0[0x3500c]=0
NS_TIMESYNC_TS0_INIT_ACCUMULATOR_0.CMIC0[0x3502c]=0
NS_TIMESYNC_TS0_INIT_ACCUMULATOR_1.CMIC0[0x35028]=0
NS_TIMESYNC_TS0_INIT_ACCUMULATOR_2.CMIC0[0x35024]=0
NS_TIMESYNC_TS0_TIMESTAMP_LOWER_STATUS.CMIC0[0x35060]=0x300cd4a0
NS_TIMESYNC_TS0_TIMESTAMP_UPPER_STATUS.CMIC0[0x35064]=0xfa22c
NS_TIMESYNC_TS0_TS_OFFSET_LOWER_STATUS.CMIC0[0x35074]=0
NS_TIMESYNC_TS0_TS_OFFSET_UPPER_STATUS.CMIC0[0x35078]=0
NS_TIMESYNC_TS1_ACCUMULATOR_0.CMIC0[0x3508c]=0
NS_TIMESYNC_TS1_ACCUMULATOR_1.CMIC0[0x35090]=0x38748000
NS_TIMESYNC_TS1_ACCUMULATOR_2.CMIC0[0x35094]=0xfa22c48
NS_TIMESYNC_TS1_BS_INIT_CTRL.CMIC0[0x3505c]=0
NS_TIMESYNC_TS1_COUNTER_ENABLE.CMIC0[0x3504c]=1
NS_TIMESYNC_TS1_CURRENT_FREQ_CTRL_LOWER.CMIC0[0x350a0]=0
NS_TIMESYNC_TS1_CURRENT_FREQ_CTRL_UPPER.CMIC0[0x350a4]=0x2000
NS_TIMESYNC_TS1_FREQ_CTRL_FRAC_LOWER.CMIC0[0x35044]=0
NS_TIMESYNC_TS1_FREQ_CTRL_FRAC_UPPER.CMIC0[0x35048]=0x2000
NS_TIMESYNC_TS1_FREQ_CTRL_OFFSET_LOWER.CMIC0[0x3503c]=0
NS_TIMESYNC_TS1_FREQ_CTRL_OFFSET_UPPER.CMIC0[0x35040]=0
NS_TIMESYNC_TS1_FREQ_CTRL_UPDATE_LOWER.CMIC0[0x35034]=0
NS_TIMESYNC_TS1_FREQ_CTRL_UPDATE_UPPER.CMIC0[0x35038]=0
NS_TIMESYNC_TS1_INIT_ACCUMULATOR_0.CMIC0[0x35058]=0
NS_TIMESYNC_TS1_INIT_ACCUMULATOR_1.CMIC0[0x35054]=0
NS_TIMESYNC_TS1_INIT_ACCUMULATOR_2.CMIC0[0x35050]=0
NS_TIMESYNC_TS1_TIMESTAMP_LOWER_STATUS.CMIC0[0x35084]=0x30b9b4e0
NS_TIMESYNC_TS1_TIMESTAMP_UPPER_STATUS.CMIC0[0x35088]=0xfa22c
NS_TIMESYNC_TS1_TS_OFFSET_LOWER_STATUS.CMIC0[0x35098]=0
NS_TIMESYNC_TS1_TS_OFFSET_UPPER_STATUS.CMIC0[0x3509c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG0.CMIC0[0x3535c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG1.CMIC0[0x35360]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG2.CMIC0[0x35364]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG3.CMIC0[0x35368]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG4.CMIC0[0x3536c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG5.CMIC0[0x35370]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG6.CMIC0[0x35374]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG7.CMIC0[0x35378]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG8.CMIC0[0x3537c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG9.CMIC0[0x35380]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG10.CMIC0[0x35384]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG11.CMIC0[0x35388]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG12.CMIC0[0x3538c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG13.CMIC0[0x35390]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG14.CMIC0[0x35394]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG15.CMIC0[0x35398]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG16.CMIC0[0x3539c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG17.CMIC0[0x353a0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG18.CMIC0[0x353a4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG19.CMIC0[0x353a8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG20.CMIC0[0x353ac]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG21.CMIC0[0x353b0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG22.CMIC0[0x353b4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG23.CMIC0[0x353b8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG24.CMIC0[0x353bc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG25.CMIC0[0x353c0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG26.CMIC0[0x353c4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG27.CMIC0[0x353c8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG28.CMIC0[0x353cc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG29.CMIC0[0x353d0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG30.CMIC0[0x353d4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG31.CMIC0[0x353d8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG32.CMIC0[0x353dc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG33.CMIC0[0x353e0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG34.CMIC0[0x353e4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG35.CMIC0[0x353e8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG36.CMIC0[0x353ec]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG37.CMIC0[0x353f0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG38.CMIC0[0x353f4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG39.CMIC0[0x353f8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG40.CMIC0[0x353fc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG41.CMIC0[0x35400]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG42.CMIC0[0x35404]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG43.CMIC0[0x35408]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG44.CMIC0[0x3540c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG45.CMIC0[0x35410]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG46.CMIC0[0x35414]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG47.CMIC0[0x35418]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG48.CMIC0[0x3541c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG49.CMIC0[0x35420]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG50.CMIC0[0x35424]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG51.CMIC0[0x35428]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG52.CMIC0[0x3542c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG53.CMIC0[0x35430]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG54.CMIC0[0x35434]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG55.CMIC0[0x35438]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG56.CMIC0[0x3543c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG57.CMIC0[0x35440]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG58.CMIC0[0x35444]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG59.CMIC0[0x35448]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG60.CMIC0[0x3544c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG61.CMIC0[0x35450]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG62.CMIC0[0x35454]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG63.CMIC0[0x35458]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG64.CMIC0[0x3545c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG65.CMIC0[0x35460]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG66.CMIC0[0x35464]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG67.CMIC0[0x35468]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG68.CMIC0[0x3546c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG69.CMIC0[0x35470]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG70.CMIC0[0x35474]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG71.CMIC0[0x35478]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG72.CMIC0[0x3547c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG73.CMIC0[0x35480]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG74.CMIC0[0x35484]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG75.CMIC0[0x35488]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG76.CMIC0[0x3548c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG77.CMIC0[0x35490]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG78.CMIC0[0x35494]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG79.CMIC0[0x35498]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG80.CMIC0[0x3549c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG81.CMIC0[0x354a0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG82.CMIC0[0x354a4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG83.CMIC0[0x354a8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG84.CMIC0[0x354ac]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG85.CMIC0[0x354b0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG86.CMIC0[0x354b4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG87.CMIC0[0x354b8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG88.CMIC0[0x354bc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG89.CMIC0[0x354c0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG90.CMIC0[0x354c4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG91.CMIC0[0x354c8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG92.CMIC0[0x354cc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG93.CMIC0[0x354d0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG94.CMIC0[0x354d4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG95.CMIC0[0x354d8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG96.CMIC0[0x354dc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG97.CMIC0[0x354e0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG98.CMIC0[0x354e4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG99.CMIC0[0x354e8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG100.CMIC0[0x354ec]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG101.CMIC0[0x354f0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG102.CMIC0[0x354f4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG103.CMIC0[0x354f8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG104.CMIC0[0x354fc]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG105.CMIC0[0x35500]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG106.CMIC0[0x35504]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG107.CMIC0[0x35508]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG108.CMIC0[0x3550c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG109.CMIC0[0x35510]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG110.CMIC0[0x35514]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG111.CMIC0[0x35518]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG112.CMIC0[0x3551c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG113.CMIC0[0x35520]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG114.CMIC0[0x35524]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG115.CMIC0[0x35528]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG116.CMIC0[0x3552c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG117.CMIC0[0x35530]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG118.CMIC0[0x35534]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG119.CMIC0[0x35538]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG120.CMIC0[0x3553c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG121.CMIC0[0x35540]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG122.CMIC0[0x35544]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG123.CMIC0[0x35548]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG124.CMIC0[0x3554c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG125.CMIC0[0x35550]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG126.CMIC0[0x35554]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG127.CMIC0[0x35558]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG128.CMIC0[0x3555c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG129.CMIC0[0x35560]=0xc1
NS_TIMESYNC_TS_EVENT_FWD_CFG130.CMIC0[0x35564]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG131.CMIC0[0x35568]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG132.CMIC0[0x3556c]=0xc3
NS_TIMESYNC_TS_EVENT_FWD_CFG133.CMIC0[0x35570]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG134.CMIC0[0x35574]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG135.CMIC0[0x35578]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG136.CMIC0[0x3557c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG137.CMIC0[0x35580]=0xc9
NS_TIMESYNC_TS_EVENT_FWD_CFG138.CMIC0[0x35584]=0xca
NS_TIMESYNC_TS_EVENT_FWD_CFG139.CMIC0[0x35588]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG140.CMIC0[0x3558c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG141.CMIC0[0x35590]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG142.CMIC0[0x35594]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG143.CMIC0[0x35598]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG144.CMIC0[0x3559c]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG145.CMIC0[0x355a0]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG146.CMIC0[0x355a4]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG147.CMIC0[0x355a8]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG148.CMIC0[0x355ac]=0
NS_TIMESYNC_TS_EVENT_FWD_CFG149.CMIC0[0x355b0]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL0.CMIC0[0x35238]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL1.CMIC0[0x3523c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL2.CMIC0[0x35240]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL3.CMIC0[0x35244]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL4.CMIC0[0x35248]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL5.CMIC0[0x3524c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL6.CMIC0[0x35250]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL7.CMIC0[0x35254]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL8.CMIC0[0x35258]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL9.CMIC0[0x3525c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL10.CMIC0[0x35260]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL11.CMIC0[0x35264]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL12.CMIC0[0x35268]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL13.CMIC0[0x3526c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL14.CMIC0[0x35270]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL15.CMIC0[0x35274]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL16.CMIC0[0x35278]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL17.CMIC0[0x3527c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL18.CMIC0[0x35280]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL19.CMIC0[0x35284]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL20.CMIC0[0x35288]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL21.CMIC0[0x3528c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL22.CMIC0[0x35290]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL23.CMIC0[0x35294]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL24.CMIC0[0x35298]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL25.CMIC0[0x3529c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL26.CMIC0[0x352a0]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL27.CMIC0[0x352a4]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL28.CMIC0[0x352a8]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL29.CMIC0[0x352ac]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL30.CMIC0[0x352b0]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL31.CMIC0[0x352b4]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL32.CMIC0[0x352b8]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL33.CMIC0[0x352bc]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL34.CMIC0[0x352c0]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL35.CMIC0[0x352c4]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL36.CMIC0[0x352c8]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL37.CMIC0[0x352cc]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL38.CMIC0[0x352d0]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL39.CMIC0[0x352d4]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL40.CMIC0[0x352d8]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL41.CMIC0[0x352dc]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL42.CMIC0[0x352e0]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL43.CMIC0[0x352e4]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL44.CMIC0[0x352e8]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL45.CMIC0[0x352ec]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL46.CMIC0[0x352f0]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL47.CMIC0[0x352f4]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL48.CMIC0[0x352f8]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL49.CMIC0[0x352fc]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL50.CMIC0[0x35300]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL51.CMIC0[0x35304]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL52.CMIC0[0x35308]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL53.CMIC0[0x3530c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL54.CMIC0[0x35310]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL55.CMIC0[0x35314]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL56.CMIC0[0x35318]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL57.CMIC0[0x3531c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL58.CMIC0[0x35320]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL59.CMIC0[0x35324]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL60.CMIC0[0x35328]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL61.CMIC0[0x3532c]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL62.CMIC0[0x35330]=0
NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL63.CMIC0[0x35334]=0
NS_TS_CAPTURE_STATUS.CMIC0[0x35670]=0xa00
NS_TS_CPU_FIFO_ECC_CONTROL.CMIC0[0x35950]=0
NS_TS_CPU_FIFO_ECC_STATUS.CMIC0[0x3594c]=0
NS_TS_CPU_FIFO_TM_CONTROL.CMIC0[0x35954]=0
NS_TS_INT_ENABLE.CMIC0[0x35964]=0
NS_TS_INT_STATUS.CMIC0[0x35960]=3
NS_TX_PI_EVENT_OVRD_STATUS0.CMIC0[0x35690]=0
NS_TX_PI_EVENT_OVRD_STATUS1.CMIC0[0x35694]=0
NS_TX_PI_EVENT_STATUS0.CMIC0[0x3567c]=0
NS_TX_PI_EVENT_STATUS1.CMIC0[0x35680]=0
OAMP_ARBITER_CONTROL.OAMP0[0x66b]=0
OAMP_ARBITER_WEIGHT.OAMP0[0x66c]=1
OAMP_BFD_DIAG_PROFILE.OAMP0[0x538]=0x7b9ac5a928398a418820
OAMP_BFD_EMC_CONST.OAMP0[0x193]=0x200010000
OAMP_BFD_FLAGS_PROFILE.OAMP0[0x53b]=0xeb8cb0aa88a0698490288080
OAMP_BFD_IPV4_ONE_HOP_TOS.OAMP0[0xb2f]=0
OAMP_BFD_IPV4_STATIC_REGISTER.OAMP0[0x415]=0
OAMP_BFD_IPV4_UDP_SPORT.OAMP0[0x51e]=0x1001
OAMP_BFD_MPLS_UDP_SPORT.OAMP0[0x51f]=0x1002
OAMP_BFD_MY_DISCRIMINATOR_RANGE_START.OAMP0[0x181]=0
OAMP_BFD_PDU_STATIC_REGISTER.OAMP0[0x413]=0xc1
OAMP_BFD_PWE_CW_0.OAMP0[0x520]=0x10000007
OAMP_BFD_PWE_CW_1.OAMP0[0x521]=0x10000022
OAMP_BFD_PWE_CW_2.OAMP0[0x522]=0x12345678
OAMP_BFD_PWE_CW_3.OAMP0[0x523]=0x12345678
OAMP_BFD_PWE_ROUTER_ALERT.OAMP0[0x524]=0x1040
OAMP_BFD_REQ_INTERVAL_POINTER.OAMP0[0x528]=0x700000006000000050000000400000003000000020000000100000000
OAMP_BFD_TX_RATE.OAMP0[0x405]=0
OAMP_BFM_UDP_SRC_PORT.OAMP0[0xb28]=0x12b00ec8
OAMP_CCM_MAC_SA.OAMP0[0x108]=0
OAMP_CCM_TPID_MAP.OAMP0[0x10b]=0
OAMP_CCM_TX_RATE.OAMP0[0x400]=0x15f8fc464f8176f004ae000ec000280001
OAMP_CFG_SAT_TX_WRAP_AROUND_NUM.OAMP0[0xb17]=0
OAMP_CPUPORT.OAMP0[0x111]=0x2f1c3c3c3834302c2824201c181410100c08043c000200000f0000700003400019008080000540202000011008080000300001400008000040000180000800002c0042
OAMP_DMA_ARBITER_WEIGHT.OAMP0[0x66d]=0
OAMP_DMA_COS_MAP.OAMP0[0x66e]=0xe4
OAMP_DMA_TX_CONTROL.OAMP0[0x66f]=0
OAMP_DOWN_PTCH.OAMP0[0x408]=0x1800
OAMP_DROPPED_EVENTS_COUNT.OAMP0[0x669]=0
OAMP_ECC_1B_ERR_CNT.OAMP0[0x94]=0
OAMP_ECC_2B_ERR_CNT.OAMP0[0x96]=0
OAMP_ECC_ERR_1B_MONITOR_MEM_MASK.OAMP0[0x9a]=0x7fffffffffffffffff
OAMP_ECC_ERR_2B_MONITOR_MEM_MASK.OAMP0[0x9c]=0x7fffffffffffffffff
OAMP_ECC_INTERRUPT_REGISTER.OAMP0[0x7]=0
OAMP_ECC_INTERRUPT_REGISTER_MASK.OAMP0[0x17]=0
OAMP_ECC_INTERRUPT_REGISTER_TEST.OAMP0[0x1f]=0
OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS.OAMP0[0x84]=0x7ffffffffff
OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT.OAMP0[0x169]=0x1d
OAMP_ETH_MAID_MISS_INFO.OAMP0[0xb00]=0
OAMP_ETH_MDL_MISS_INFO.OAMP0[0xb09]=0
OAMP_ETH_OAM_CONTROL.OAMP0[0x192]=1
OAMP_ETH_PERIOD_MISS_INFO.OAMP0[0xb0b]=0
OAMP_FLEX_CRC_MISS_INFO.OAMP0[0xb0a]=0
OAMP_GACH_CHAN_TYPES.OAMP0[0x196]=0xb000a000c0022
OAMP_GTIMER_CONFIGURATION.OAMP0[0x89]=0
OAMP_GTIMER_CYCLE.OAMP0[0x88]=0x3b9aca00
OAMP_HEADER_CONFIG.OAMP0[0x123]=0x248248248248258d31
OAMP_ICC_MAP_REG_1.OAMP0[0x16a]=0x9000000000008000000000007000000000006000000000005000000000004000000000003000000000002000000000001000000000000
OAMP_ICC_MAP_REG_2.OAMP0[0x179]=0xe00000000000d00000000000c00000000000b00000000000a
OAMP_INDIRECT_COMMAND.OAMP0[0x80]=0xe000002
OAMP_INDIRECT_COMMAND_ADDRESS.OAMP0[0x81]=0x43000a
OAMP_INDIRECT_COMMAND_RD_DATA.OAMP0[0x60]=0
OAMP_INDIRECT_COMMAND_WIDE_MEM.OAMP0[0x41]=0
OAMP_INDIRECT_COMMAND_WR_DATA.OAMP0[0x20]=0x4000000430001
OAMP_INDIRECT_FORCE_BUBBLE.OAMP0[0x83]=0x20019
OAMP_INTERFACE_STAT_TLV.OAMP0[0x531]=0x40001
OAMP_INTERRUPT_MASK_REGISTER.OAMP0[0x10]=4
OAMP_INTERRUPT_MESSAGE.OAMP0[0x13d]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
OAMP_INTERRUPT_REGISTER.OAMP0[0x0]=0
OAMP_INTERRUPT_REGISTER_TEST.OAMP0[0x18]=0
OAMP_IPV4_SRC_ADDR_SELECT(0).OAMP0[0x416]=0
OAMP_IPV4_SRC_ADDR_SELECT(1).OAMP0[0x417]=0
OAMP_IPV4_SRC_ADDR_SELECT(2).OAMP0[0x418]=0
OAMP_IPV4_SRC_ADDR_SELECT(3).OAMP0[0x419]=0
OAMP_IPV4_SRC_ADDR_SELECT(4).OAMP0[0x41a]=0
OAMP_IPV4_SRC_ADDR_SELECT(5).OAMP0[0x41b]=0
OAMP_IPV4_SRC_ADDR_SELECT(6).OAMP0[0x41c]=0
OAMP_IPV4_SRC_ADDR_SELECT(7).OAMP0[0x41d]=0
OAMP_IPV4_SRC_ADDR_SELECT(8).OAMP0[0x41e]=0
OAMP_IPV4_SRC_ADDR_SELECT(9).OAMP0[0x41f]=0
OAMP_IPV4_SRC_ADDR_SELECT(10).OAMP0[0x420]=0
OAMP_IPV4_SRC_ADDR_SELECT(11).OAMP0[0x421]=0
OAMP_IPV4_SRC_ADDR_SELECT(12).OAMP0[0x422]=0
OAMP_IPV4_SRC_ADDR_SELECT(13).OAMP0[0x423]=0
OAMP_IPV4_SRC_ADDR_SELECT(14).OAMP0[0x424]=0
OAMP_IPV4_SRC_ADDR_SELECT(15).OAMP0[0x425]=0
OAMP_IPV4_SRC_ADDR_SELECT(16).OAMP0[0x426]=0
OAMP_IPV4_SRC_ADDR_SELECT(17).OAMP0[0x427]=0
OAMP_IPV4_SRC_ADDR_SELECT(18).OAMP0[0x428]=0
OAMP_IPV4_SRC_ADDR_SELECT(19).OAMP0[0x429]=0
OAMP_IPV4_SRC_ADDR_SELECT(20).OAMP0[0x42a]=0
OAMP_IPV4_SRC_ADDR_SELECT(21).OAMP0[0x42b]=0
OAMP_IPV4_SRC_ADDR_SELECT(22).OAMP0[0x42c]=0
OAMP_IPV4_SRC_ADDR_SELECT(23).OAMP0[0x42d]=0
OAMP_IPV4_SRC_ADDR_SELECT(24).OAMP0[0x42e]=0
OAMP_IPV4_SRC_ADDR_SELECT(25).OAMP0[0x42f]=0
OAMP_IPV4_SRC_ADDR_SELECT(26).OAMP0[0x430]=0
OAMP_IPV4_SRC_ADDR_SELECT(27).OAMP0[0x431]=0
OAMP_IPV4_SRC_ADDR_SELECT(28).OAMP0[0x432]=0
OAMP_IPV4_SRC_ADDR_SELECT(29).OAMP0[0x433]=0
OAMP_IPV4_SRC_ADDR_SELECT(30).OAMP0[0x434]=0
OAMP_IPV4_SRC_ADDR_SELECT(31).OAMP0[0x435]=0
OAMP_IPV4_SRC_ADDR_SELECT(32).OAMP0[0x436]=0
OAMP_IPV4_SRC_ADDR_SELECT(33).OAMP0[0x437]=0
OAMP_IPV4_SRC_ADDR_SELECT(34).OAMP0[0x438]=0
OAMP_IPV4_SRC_ADDR_SELECT(35).OAMP0[0x439]=0
OAMP_IPV4_SRC_ADDR_SELECT(36).OAMP0[0x43a]=0
OAMP_IPV4_SRC_ADDR_SELECT(37).OAMP0[0x43b]=0
OAMP_IPV4_SRC_ADDR_SELECT(38).OAMP0[0x43c]=0
OAMP_IPV4_SRC_ADDR_SELECT(39).OAMP0[0x43d]=0
OAMP_IPV4_SRC_ADDR_SELECT(40).OAMP0[0x43e]=0
OAMP_IPV4_SRC_ADDR_SELECT(41).OAMP0[0x43f]=0
OAMP_IPV4_SRC_ADDR_SELECT(42).OAMP0[0x440]=0
OAMP_IPV4_SRC_ADDR_SELECT(43).OAMP0[0x441]=0
OAMP_IPV4_SRC_ADDR_SELECT(44).OAMP0[0x442]=0
OAMP_IPV4_SRC_ADDR_SELECT(45).OAMP0[0x443]=0
OAMP_IPV4_SRC_ADDR_SELECT(46).OAMP0[0x444]=0
OAMP_IPV4_SRC_ADDR_SELECT(47).OAMP0[0x445]=0
OAMP_IPV4_SRC_ADDR_SELECT(48).OAMP0[0x446]=0
OAMP_IPV4_SRC_ADDR_SELECT(49).OAMP0[0x447]=0
OAMP_IPV4_SRC_ADDR_SELECT(50).OAMP0[0x448]=0
OAMP_IPV4_SRC_ADDR_SELECT(51).OAMP0[0x449]=0
OAMP_IPV4_SRC_ADDR_SELECT(52).OAMP0[0x44a]=0
OAMP_IPV4_SRC_ADDR_SELECT(53).OAMP0[0x44b]=0
OAMP_IPV4_SRC_ADDR_SELECT(54).OAMP0[0x44c]=0
OAMP_IPV4_SRC_ADDR_SELECT(55).OAMP0[0x44d]=0
OAMP_IPV4_SRC_ADDR_SELECT(56).OAMP0[0x44e]=0
OAMP_IPV4_SRC_ADDR_SELECT(57).OAMP0[0x44f]=0
OAMP_IPV4_SRC_ADDR_SELECT(58).OAMP0[0x450]=0
OAMP_IPV4_SRC_ADDR_SELECT(59).OAMP0[0x451]=0
OAMP_IPV4_SRC_ADDR_SELECT(60).OAMP0[0x452]=0
OAMP_IPV4_SRC_ADDR_SELECT(61).OAMP0[0x453]=0
OAMP_IPV4_SRC_ADDR_SELECT(62).OAMP0[0x454]=0
OAMP_IPV4_SRC_ADDR_SELECT(63).OAMP0[0x455]=0
OAMP_IPV4_SRC_ADDR_SELECT(64).OAMP0[0x456]=0
OAMP_IPV4_SRC_ADDR_SELECT(65).OAMP0[0x457]=0
OAMP_IPV4_SRC_ADDR_SELECT(66).OAMP0[0x458]=0
OAMP_IPV4_SRC_ADDR_SELECT(67).OAMP0[0x459]=0
OAMP_IPV4_SRC_ADDR_SELECT(68).OAMP0[0x45a]=0
OAMP_IPV4_SRC_ADDR_SELECT(69).OAMP0[0x45b]=0
OAMP_IPV4_SRC_ADDR_SELECT(70).OAMP0[0x45c]=0
OAMP_IPV4_SRC_ADDR_SELECT(71).OAMP0[0x45d]=0
OAMP_IPV4_SRC_ADDR_SELECT(72).OAMP0[0x45e]=0
OAMP_IPV4_SRC_ADDR_SELECT(73).OAMP0[0x45f]=0
OAMP_IPV4_SRC_ADDR_SELECT(74).OAMP0[0x460]=0
OAMP_IPV4_SRC_ADDR_SELECT(75).OAMP0[0x461]=0
OAMP_IPV4_SRC_ADDR_SELECT(76).OAMP0[0x462]=0
OAMP_IPV4_SRC_ADDR_SELECT(77).OAMP0[0x463]=0
OAMP_IPV4_SRC_ADDR_SELECT(78).OAMP0[0x464]=0
OAMP_IPV4_SRC_ADDR_SELECT(79).OAMP0[0x465]=0
OAMP_IPV4_SRC_ADDR_SELECT(80).OAMP0[0x466]=0
OAMP_IPV4_SRC_ADDR_SELECT(81).OAMP0[0x467]=0
OAMP_IPV4_SRC_ADDR_SELECT(82).OAMP0[0x468]=0
OAMP_IPV4_SRC_ADDR_SELECT(83).OAMP0[0x469]=0
OAMP_IPV4_SRC_ADDR_SELECT(84).OAMP0[0x46a]=0
OAMP_IPV4_SRC_ADDR_SELECT(85).OAMP0[0x46b]=0
OAMP_IPV4_SRC_ADDR_SELECT(86).OAMP0[0x46c]=0
OAMP_IPV4_SRC_ADDR_SELECT(87).OAMP0[0x46d]=0
OAMP_IPV4_SRC_ADDR_SELECT(88).OAMP0[0x46e]=0
OAMP_IPV4_SRC_ADDR_SELECT(89).OAMP0[0x46f]=0
OAMP_IPV4_SRC_ADDR_SELECT(90).OAMP0[0x470]=0
OAMP_IPV4_SRC_ADDR_SELECT(91).OAMP0[0x471]=0
OAMP_IPV4_SRC_ADDR_SELECT(92).OAMP0[0x472]=0
OAMP_IPV4_SRC_ADDR_SELECT(93).OAMP0[0x473]=0
OAMP_IPV4_SRC_ADDR_SELECT(94).OAMP0[0x474]=0
OAMP_IPV4_SRC_ADDR_SELECT(95).OAMP0[0x475]=0
OAMP_IPV4_SRC_ADDR_SELECT(96).OAMP0[0x476]=0
OAMP_IPV4_SRC_ADDR_SELECT(97).OAMP0[0x477]=0
OAMP_IPV4_SRC_ADDR_SELECT(98).OAMP0[0x478]=0
OAMP_IPV4_SRC_ADDR_SELECT(99).OAMP0[0x479]=0
OAMP_IPV4_SRC_ADDR_SELECT(100).OAMP0[0x47a]=0
OAMP_IPV4_SRC_ADDR_SELECT(101).OAMP0[0x47b]=0
OAMP_IPV4_SRC_ADDR_SELECT(102).OAMP0[0x47c]=0
OAMP_IPV4_SRC_ADDR_SELECT(103).OAMP0[0x47d]=0
OAMP_IPV4_SRC_ADDR_SELECT(104).OAMP0[0x47e]=0
OAMP_IPV4_SRC_ADDR_SELECT(105).OAMP0[0x47f]=0
OAMP_IPV4_SRC_ADDR_SELECT(106).OAMP0[0x480]=0
OAMP_IPV4_SRC_ADDR_SELECT(107).OAMP0[0x481]=0
OAMP_IPV4_SRC_ADDR_SELECT(108).OAMP0[0x482]=0
OAMP_IPV4_SRC_ADDR_SELECT(109).OAMP0[0x483]=0
OAMP_IPV4_SRC_ADDR_SELECT(110).OAMP0[0x484]=0
OAMP_IPV4_SRC_ADDR_SELECT(111).OAMP0[0x485]=0
OAMP_IPV4_SRC_ADDR_SELECT(112).OAMP0[0x486]=0
OAMP_IPV4_SRC_ADDR_SELECT(113).OAMP0[0x487]=0
OAMP_IPV4_SRC_ADDR_SELECT(114).OAMP0[0x488]=0
OAMP_IPV4_SRC_ADDR_SELECT(115).OAMP0[0x489]=0
OAMP_IPV4_SRC_ADDR_SELECT(116).OAMP0[0x48a]=0
OAMP_IPV4_SRC_ADDR_SELECT(117).OAMP0[0x48b]=0
OAMP_IPV4_SRC_ADDR_SELECT(118).OAMP0[0x48c]=0
OAMP_IPV4_SRC_ADDR_SELECT(119).OAMP0[0x48d]=0
OAMP_IPV4_SRC_ADDR_SELECT(120).OAMP0[0x48e]=0
OAMP_IPV4_SRC_ADDR_SELECT(121).OAMP0[0x48f]=0
OAMP_IPV4_SRC_ADDR_SELECT(122).OAMP0[0x490]=0
OAMP_IPV4_SRC_ADDR_SELECT(123).OAMP0[0x491]=0
OAMP_IPV4_SRC_ADDR_SELECT(124).OAMP0[0x492]=0
OAMP_IPV4_SRC_ADDR_SELECT(125).OAMP0[0x493]=0
OAMP_IPV4_SRC_ADDR_SELECT(126).OAMP0[0x494]=0
OAMP_IPV4_SRC_ADDR_SELECT(127).OAMP0[0x495]=0
OAMP_IPV4_SRC_ADDR_SELECT(128).OAMP0[0x496]=0
OAMP_IPV4_SRC_ADDR_SELECT(129).OAMP0[0x497]=0
OAMP_IPV4_SRC_ADDR_SELECT(130).OAMP0[0x498]=0
OAMP_IPV4_SRC_ADDR_SELECT(131).OAMP0[0x499]=0
OAMP_IPV4_SRC_ADDR_SELECT(132).OAMP0[0x49a]=0
OAMP_IPV4_SRC_ADDR_SELECT(133).OAMP0[0x49b]=0
OAMP_IPV4_SRC_ADDR_SELECT(134).OAMP0[0x49c]=0
OAMP_IPV4_SRC_ADDR_SELECT(135).OAMP0[0x49d]=0
OAMP_IPV4_SRC_ADDR_SELECT(136).OAMP0[0x49e]=0
OAMP_IPV4_SRC_ADDR_SELECT(137).OAMP0[0x49f]=0
OAMP_IPV4_SRC_ADDR_SELECT(138).OAMP0[0x4a0]=0
OAMP_IPV4_SRC_ADDR_SELECT(139).OAMP0[0x4a1]=0
OAMP_IPV4_SRC_ADDR_SELECT(140).OAMP0[0x4a2]=0
OAMP_IPV4_SRC_ADDR_SELECT(141).OAMP0[0x4a3]=0
OAMP_IPV4_SRC_ADDR_SELECT(142).OAMP0[0x4a4]=0
OAMP_IPV4_SRC_ADDR_SELECT(143).OAMP0[0x4a5]=0
OAMP_IPV4_SRC_ADDR_SELECT(144).OAMP0[0x4a6]=0
OAMP_IPV4_SRC_ADDR_SELECT(145).OAMP0[0x4a7]=0
OAMP_IPV4_SRC_ADDR_SELECT(146).OAMP0[0x4a8]=0
OAMP_IPV4_SRC_ADDR_SELECT(147).OAMP0[0x4a9]=0
OAMP_IPV4_SRC_ADDR_SELECT(148).OAMP0[0x4aa]=0
OAMP_IPV4_SRC_ADDR_SELECT(149).OAMP0[0x4ab]=0
OAMP_IPV4_SRC_ADDR_SELECT(150).OAMP0[0x4ac]=0
OAMP_IPV4_SRC_ADDR_SELECT(151).OAMP0[0x4ad]=0
OAMP_IPV4_SRC_ADDR_SELECT(152).OAMP0[0x4ae]=0
OAMP_IPV4_SRC_ADDR_SELECT(153).OAMP0[0x4af]=0
OAMP_IPV4_SRC_ADDR_SELECT(154).OAMP0[0x4b0]=0
OAMP_IPV4_SRC_ADDR_SELECT(155).OAMP0[0x4b1]=0
OAMP_IPV4_SRC_ADDR_SELECT(156).OAMP0[0x4b2]=0
OAMP_IPV4_SRC_ADDR_SELECT(157).OAMP0[0x4b3]=0
OAMP_IPV4_SRC_ADDR_SELECT(158).OAMP0[0x4b4]=0
OAMP_IPV4_SRC_ADDR_SELECT(159).OAMP0[0x4b5]=0
OAMP_IPV4_SRC_ADDR_SELECT(160).OAMP0[0x4b6]=0
OAMP_IPV4_SRC_ADDR_SELECT(161).OAMP0[0x4b7]=0
OAMP_IPV4_SRC_ADDR_SELECT(162).OAMP0[0x4b8]=0
OAMP_IPV4_SRC_ADDR_SELECT(163).OAMP0[0x4b9]=0
OAMP_IPV4_SRC_ADDR_SELECT(164).OAMP0[0x4ba]=0
OAMP_IPV4_SRC_ADDR_SELECT(165).OAMP0[0x4bb]=0
OAMP_IPV4_SRC_ADDR_SELECT(166).OAMP0[0x4bc]=0
OAMP_IPV4_SRC_ADDR_SELECT(167).OAMP0[0x4bd]=0
OAMP_IPV4_SRC_ADDR_SELECT(168).OAMP0[0x4be]=0
OAMP_IPV4_SRC_ADDR_SELECT(169).OAMP0[0x4bf]=0
OAMP_IPV4_SRC_ADDR_SELECT(170).OAMP0[0x4c0]=0
OAMP_IPV4_SRC_ADDR_SELECT(171).OAMP0[0x4c1]=0
OAMP_IPV4_SRC_ADDR_SELECT(172).OAMP0[0x4c2]=0
OAMP_IPV4_SRC_ADDR_SELECT(173).OAMP0[0x4c3]=0
OAMP_IPV4_SRC_ADDR_SELECT(174).OAMP0[0x4c4]=0
OAMP_IPV4_SRC_ADDR_SELECT(175).OAMP0[0x4c5]=0
OAMP_IPV4_SRC_ADDR_SELECT(176).OAMP0[0x4c6]=0
OAMP_IPV4_SRC_ADDR_SELECT(177).OAMP0[0x4c7]=0
OAMP_IPV4_SRC_ADDR_SELECT(178).OAMP0[0x4c8]=0
OAMP_IPV4_SRC_ADDR_SELECT(179).OAMP0[0x4c9]=0
OAMP_IPV4_SRC_ADDR_SELECT(180).OAMP0[0x4ca]=0
OAMP_IPV4_SRC_ADDR_SELECT(181).OAMP0[0x4cb]=0
OAMP_IPV4_SRC_ADDR_SELECT(182).OAMP0[0x4cc]=0
OAMP_IPV4_SRC_ADDR_SELECT(183).OAMP0[0x4cd]=0
OAMP_IPV4_SRC_ADDR_SELECT(184).OAMP0[0x4ce]=0
OAMP_IPV4_SRC_ADDR_SELECT(185).OAMP0[0x4cf]=0
OAMP_IPV4_SRC_ADDR_SELECT(186).OAMP0[0x4d0]=0
OAMP_IPV4_SRC_ADDR_SELECT(187).OAMP0[0x4d1]=0
OAMP_IPV4_SRC_ADDR_SELECT(188).OAMP0[0x4d2]=0
OAMP_IPV4_SRC_ADDR_SELECT(189).OAMP0[0x4d3]=0
OAMP_IPV4_SRC_ADDR_SELECT(190).OAMP0[0x4d4]=0
OAMP_IPV4_SRC_ADDR_SELECT(191).OAMP0[0x4d5]=0
OAMP_IPV4_SRC_ADDR_SELECT(192).OAMP0[0x4d6]=0
OAMP_IPV4_SRC_ADDR_SELECT(193).OAMP0[0x4d7]=0
OAMP_IPV4_SRC_ADDR_SELECT(194).OAMP0[0x4d8]=0
OAMP_IPV4_SRC_ADDR_SELECT(195).OAMP0[0x4d9]=0
OAMP_IPV4_SRC_ADDR_SELECT(196).OAMP0[0x4da]=0
OAMP_IPV4_SRC_ADDR_SELECT(197).OAMP0[0x4db]=0
OAMP_IPV4_SRC_ADDR_SELECT(198).OAMP0[0x4dc]=0
OAMP_IPV4_SRC_ADDR_SELECT(199).OAMP0[0x4dd]=0
OAMP_IPV4_SRC_ADDR_SELECT(200).OAMP0[0x4de]=0
OAMP_IPV4_SRC_ADDR_SELECT(201).OAMP0[0x4df]=0
OAMP_IPV4_SRC_ADDR_SELECT(202).OAMP0[0x4e0]=0
OAMP_IPV4_SRC_ADDR_SELECT(203).OAMP0[0x4e1]=0
OAMP_IPV4_SRC_ADDR_SELECT(204).OAMP0[0x4e2]=0
OAMP_IPV4_SRC_ADDR_SELECT(205).OAMP0[0x4e3]=0
OAMP_IPV4_SRC_ADDR_SELECT(206).OAMP0[0x4e4]=0
OAMP_IPV4_SRC_ADDR_SELECT(207).OAMP0[0x4e5]=0
OAMP_IPV4_SRC_ADDR_SELECT(208).OAMP0[0x4e6]=0
OAMP_IPV4_SRC_ADDR_SELECT(209).OAMP0[0x4e7]=0
OAMP_IPV4_SRC_ADDR_SELECT(210).OAMP0[0x4e8]=0
OAMP_IPV4_SRC_ADDR_SELECT(211).OAMP0[0x4e9]=0
OAMP_IPV4_SRC_ADDR_SELECT(212).OAMP0[0x4ea]=0
OAMP_IPV4_SRC_ADDR_SELECT(213).OAMP0[0x4eb]=0
OAMP_IPV4_SRC_ADDR_SELECT(214).OAMP0[0x4ec]=0
OAMP_IPV4_SRC_ADDR_SELECT(215).OAMP0[0x4ed]=0
OAMP_IPV4_SRC_ADDR_SELECT(216).OAMP0[0x4ee]=0
OAMP_IPV4_SRC_ADDR_SELECT(217).OAMP0[0x4ef]=0
OAMP_IPV4_SRC_ADDR_SELECT(218).OAMP0[0x4f0]=0
OAMP_IPV4_SRC_ADDR_SELECT(219).OAMP0[0x4f1]=0
OAMP_IPV4_SRC_ADDR_SELECT(220).OAMP0[0x4f2]=0
OAMP_IPV4_SRC_ADDR_SELECT(221).OAMP0[0x4f3]=0
OAMP_IPV4_SRC_ADDR_SELECT(222).OAMP0[0x4f4]=0
OAMP_IPV4_SRC_ADDR_SELECT(223).OAMP0[0x4f5]=0
OAMP_IPV4_SRC_ADDR_SELECT(224).OAMP0[0x4f6]=0
OAMP_IPV4_SRC_ADDR_SELECT(225).OAMP0[0x4f7]=0
OAMP_IPV4_SRC_ADDR_SELECT(226).OAMP0[0x4f8]=0
OAMP_IPV4_SRC_ADDR_SELECT(227).OAMP0[0x4f9]=0
OAMP_IPV4_SRC_ADDR_SELECT(228).OAMP0[0x4fa]=0
OAMP_IPV4_SRC_ADDR_SELECT(229).OAMP0[0x4fb]=0
OAMP_IPV4_SRC_ADDR_SELECT(230).OAMP0[0x4fc]=0
OAMP_IPV4_SRC_ADDR_SELECT(231).OAMP0[0x4fd]=0
OAMP_IPV4_SRC_ADDR_SELECT(232).OAMP0[0x4fe]=0
OAMP_IPV4_SRC_ADDR_SELECT(233).OAMP0[0x4ff]=0
OAMP_IPV4_SRC_ADDR_SELECT(234).OAMP0[0x500]=0
OAMP_IPV4_SRC_ADDR_SELECT(235).OAMP0[0x501]=0
OAMP_IPV4_SRC_ADDR_SELECT(236).OAMP0[0x502]=0
OAMP_IPV4_SRC_ADDR_SELECT(237).OAMP0[0x503]=0
OAMP_IPV4_SRC_ADDR_SELECT(238).OAMP0[0x504]=0
OAMP_IPV4_SRC_ADDR_SELECT(239).OAMP0[0x505]=0
OAMP_IPV4_SRC_ADDR_SELECT(240).OAMP0[0x506]=0
OAMP_IPV4_SRC_ADDR_SELECT(241).OAMP0[0x507]=0
OAMP_IPV4_SRC_ADDR_SELECT(242).OAMP0[0x508]=0
OAMP_IPV4_SRC_ADDR_SELECT(243).OAMP0[0x509]=0
OAMP_IPV4_SRC_ADDR_SELECT(244).OAMP0[0x50a]=0
OAMP_IPV4_SRC_ADDR_SELECT(245).OAMP0[0x50b]=0
OAMP_IPV4_SRC_ADDR_SELECT(246).OAMP0[0x50c]=0
OAMP_IPV4_SRC_ADDR_SELECT(247).OAMP0[0x50d]=0
OAMP_IPV4_SRC_ADDR_SELECT(248).OAMP0[0x50e]=0
OAMP_IPV4_SRC_ADDR_SELECT(249).OAMP0[0x50f]=0
OAMP_IPV4_SRC_ADDR_SELECT(250).OAMP0[0x510]=0
OAMP_IPV4_SRC_ADDR_SELECT(251).OAMP0[0x511]=0
OAMP_IPV4_SRC_ADDR_SELECT(252).OAMP0[0x512]=0
OAMP_IPV4_SRC_ADDR_SELECT(253).OAMP0[0x513]=0
OAMP_IPV4_SRC_ADDR_SELECT(254).OAMP0[0x514]=0
OAMP_IPV4_SRC_ADDR_SELECT(255).OAMP0[0x515]=0
OAMP_IPV4_TOS_TTL_SELECT.OAMP0[0x516]=0x1016101510141013101210111010100910081007100610051004100310021001
OAMP_LMM_DA_OUI.OAMP0[0x532]=0x7000006000005000004000003000002000001000000
OAMP_MAP_OAM_ID.OAMP0[0xb18]=0xe000000000000000000000000000000000000000000
OAMP_MDB_APP_DB.OAMP0[0xb29]=0x53
OAMP_MEMORY_HAZARD_PROTECTION_EN.OAMP0[0xb4b]=3
OAMP_MEP_DB_FULL_ENTRY_THRESHOLD.OAMP0[0xb2a]=0
OAMP_MIN_NET_PKT_SIZE.OAMP0[0x547]=0x2c
OAMP_MODE_REGISTER.OAMP0[0x100]=0x31b
OAMP_MPLS_PWE_PROFILE.OAMP0[0x40a]=0
OAMP_MY_DISC_MISS_INFO.OAMP0[0xb0d]=0
OAMP_NUMBER_OF_RMEPS.OAMP0[0x66a]=0x10000
OAMP_NUMBER_OF_SDSF_ENTRIES.OAMP0[0xb4a]=0x2000
OAMP_NUM_ENTRIES_SAT_2_IRE_CRDT_CNT_CORE_0.OAMP0[0xb4d]=0x102040
OAMP_NUM_ENTRIES_SAT_2_IRE_CRDT_CNT_CORE_1.OAMP0[0xb4e]=0
OAMP_OPCODE_CONFIG.OAMP0[0x546]=0
OAMP_OPCODE_FOR_COUNT(0).OAMP0[0xb30]=0x18
OAMP_OPCODE_FOR_COUNT(1).OAMP0[0xb31]=1
OAMP_OPCODE_FOR_COUNT(2).OAMP0[0xb32]=2
OAMP_OPCODE_FOR_COUNT(3).OAMP0[0xb33]=3
OAMP_OPCODE_FOR_COUNT(4).OAMP0[0xb34]=4
OAMP_OPCODE_FOR_COUNT(5).OAMP0[0xb35]=5
OAMP_OPCODE_INFO(0).OAMP0[0x548]=0
OAMP_OPCODE_INFO(1).OAMP0[0x54b]=0
OAMP_OPCODE_INFO(2).OAMP0[0x54e]=0
OAMP_OPCODE_INFO(3).OAMP0[0x551]=0
OAMP_OPCODE_INFO(4).OAMP0[0x554]=0
OAMP_OPCODE_INFO(5).OAMP0[0x557]=0
OAMP_OPCODE_INFO(6).OAMP0[0x55a]=0
OAMP_OPCODE_INFO(7).OAMP0[0x55d]=0
OAMP_PER_MEP_PROFILE_RX_COUNTER_CFG.OAMP0[0xb2c]=0xe1
OAMP_PER_MEP_PROFILE_TX_COUNTER_CFG.OAMP0[0xb2d]=0xe0
OAMP_PE_CONST(0).OAMP0[0x5ac]=0
OAMP_PE_CONST(1).OAMP0[0x5ad]=0x10000021
OAMP_PE_CONST(2).OAMP0[0x5ae]=0xd140fffc
OAMP_PE_CONST(3).OAMP0[0x5af]=0xd0fffc
OAMP_PE_CONST(4).OAMP0[0x5b0]=0xd0fffc
OAMP_PE_CONST(5).OAMP0[0x5b1]=0xd0fffc
OAMP_PE_CONST(6).OAMP0[0x5b2]=0
OAMP_PE_CONST(7).OAMP0[0x5b3]=0xe0fffc
OAMP_PE_CONST(8).OAMP0[0x5b4]=0x10000021
OAMP_PE_CONST(9).OAMP0[0x5b5]=0
OAMP_PE_CONST(10).OAMP0[0x5b6]=0xec90000
OAMP_PE_CONST(11).OAMP0[0x5b7]=0x1e68
OAMP_PE_CONST(12).OAMP0[0x5b8]=2
OAMP_PE_CONST(13).OAMP0[0x5b9]=2
OAMP_PE_CONST(14).OAMP0[0x5ba]=0
OAMP_PE_CONST(15).OAMP0[0x5bb]=0
OAMP_PE_CONST(16).OAMP0[0x5bc]=0
OAMP_PE_CONST(17).OAMP0[0x5bd]=0
OAMP_PE_CONST(18).OAMP0[0x5be]=0
OAMP_PE_CONST(19).OAMP0[0x5bf]=0xec90000
OAMP_PE_CONST(20).OAMP0[0x5c0]=0xec90000
OAMP_PE_CONST(21).OAMP0[0x5c1]=0x7f0000ff
OAMP_PE_CONST(22).OAMP0[0x5c2]=0
OAMP_PE_CONST(23).OAMP0[0x5c3]=1
OAMP_PE_CONST(24).OAMP0[0x5c4]=0
OAMP_PE_CONST(25).OAMP0[0x5c5]=0
OAMP_PE_CONST(26).OAMP0[0x5c6]=0
OAMP_PE_CONST(27).OAMP0[0x5c7]=0
OAMP_PE_CONST(28).OAMP0[0x5c8]=0
OAMP_PE_CONST(29).OAMP0[0x5c9]=0
OAMP_PE_CONST(30).OAMP0[0x5ca]=0
OAMP_PE_CONST(31).OAMP0[0x5cb]=0
OAMP_PE_FEM_MAP(0).OAMP0[0x5ed]=0x8208208165548204df79d71b
OAMP_PE_FEM_MAP(1).OAMP0[0x5f0]=0x8208208207de82082082075c
OAMP_PE_FEM_MAP(2).OAMP0[0x5f3]=0x3ce34c2ca8481c61440c2040
OAMP_PE_FEM_MAP(3).OAMP0[0x5f6]=0x3e134c2ca2481c61440c2040
OAMP_PE_FEM_MAP(4).OAMP0[0x5f9]=0x82038d30b289207185103081
OAMP_PE_FEM_MAP(5).OAMP0[0x5fc]=0x7de75c6da6585d65544d2460
OAMP_PE_FEM_MAP(6).OAMP0[0x5ff]=0x6da820820820820820820820
OAMP_PE_FEM_MAP(7).OAMP0[0x602]=0x82081b6a0820820820820820
OAMP_PE_FEM_MAP(8).OAMP0[0x605]=0x82082082082082082079d720
OAMP_PE_FEM_MAP(9).OAMP0[0x608]=0x7de75c6da6585e15544d2450
OAMP_PE_FEM_MAP(10).OAMP0[0x60b]=0x82082081f79d71b699617595
OAMP_PE_FEM_MAP(11).OAMP0[0x60e]=0x82082082081f79d71b699617
OAMP_PE_FEM_MAP(12).OAMP0[0x611]=0x3ce34c2ca8218211440c2040
OAMP_PE_FEM_MAP(13).OAMP0[0x614]=0x79d71b699617595513491420
OAMP_PE_FEM_MAP(14).OAMP0[0x617]=0x3ce34c2ca2481c61440c2060
OAMP_PE_FEM_MAP(15).OAMP0[0x61a]=0
OAMP_PE_FEM_MAP(16).OAMP0[0x61d]=0
OAMP_PE_FEM_MAP(17).OAMP0[0x620]=0
OAMP_PE_FEM_MAP(18).OAMP0[0x623]=0
OAMP_PE_FEM_MAP(19).OAMP0[0x626]=0
OAMP_PE_FEM_MAP(20).OAMP0[0x629]=0
OAMP_PE_FEM_MAP(21).OAMP0[0x62c]=0
OAMP_PE_FEM_MAP(22).OAMP0[0x62f]=0
OAMP_PE_FEM_MAP(23).OAMP0[0x632]=0
OAMP_PE_FEM_MAP(24).OAMP0[0x635]=0
OAMP_PE_FEM_MAP(25).OAMP0[0x638]=0
OAMP_PE_FEM_MAP(26).OAMP0[0x63b]=0
OAMP_PE_FEM_MAP(27).OAMP0[0x63e]=0
OAMP_PE_FEM_MAP(28).OAMP0[0x641]=0
OAMP_PE_FEM_MAP(29).OAMP0[0x644]=0
OAMP_PE_FEM_MAP(30).OAMP0[0x647]=0
OAMP_PE_INST.OAMP0[0x5ec]=0x800000
OAMP_PE_PROF(0).OAMP0[0x561]=0
OAMP_PE_PROF(1).OAMP0[0x562]=0x32031
OAMP_PE_PROF(2).OAMP0[0x563]=0xc9dc1b
OAMP_PE_PROF(3).OAMP0[0x564]=0xc9dc1b
OAMP_PE_PROF(4).OAMP0[0x565]=0
OAMP_PE_PROF(5).OAMP0[0x566]=0x32031
OAMP_PE_PROF(6).OAMP0[0x567]=0x32031
OAMP_PE_PROF(7).OAMP0[0x568]=0x400
OAMP_PE_PROF(8).OAMP0[0x569]=0x32031
OAMP_PE_PROF(9).OAMP0[0x56a]=0x400
OAMP_PE_PROF(10).OAMP0[0x56b]=0
OAMP_PE_PROF(11).OAMP0[0x56c]=0
OAMP_PE_PROF(12).OAMP0[0x56d]=0xc9d000
OAMP_PE_PROF(13).OAMP0[0x56e]=0xc9d000
OAMP_PE_PROF(14).OAMP0[0x56f]=0
OAMP_PE_PROF(15).OAMP0[0x570]=0
OAMP_PE_PROF(16).OAMP0[0x571]=0xc9d000
OAMP_PE_PROF(17).OAMP0[0x572]=0xc9d000
OAMP_PE_PROF(18).OAMP0[0x573]=0x30
OAMP_PE_PROF(19).OAMP0[0x574]=0x30
OAMP_PE_PROF(20).OAMP0[0x575]=0xcb6000
OAMP_PE_PROF(21).OAMP0[0x576]=0xcb6000
OAMP_PE_PROF(22).OAMP0[0x577]=0x32031
OAMP_PE_PROF(23).OAMP0[0x578]=0x32031
OAMP_PE_PROF(24).OAMP0[0x579]=0x32031
OAMP_PE_PROF(25).OAMP0[0x57a]=0x32031
OAMP_PE_PROF(26).OAMP0[0x57b]=0
OAMP_PE_PROF(27).OAMP0[0x57c]=0
OAMP_PE_PROF(28).OAMP0[0x57d]=0x24
OAMP_PE_PROF(29).OAMP0[0x57e]=0x24
OAMP_PE_PROF(30).OAMP0[0x57f]=0x117000
OAMP_PE_PROF(31).OAMP0[0x580]=0x117000
OAMP_PE_PROF(32).OAMP0[0x581]=0xcb6024
OAMP_PE_PROF(33).OAMP0[0x582]=0xcb6024
OAMP_PE_PROF(34).OAMP0[0x583]=0
OAMP_PE_PROF(35).OAMP0[0x584]=0x400
OAMP_PE_PROF(36).OAMP0[0x585]=0x400
OAMP_PE_PROF(37).OAMP0[0x586]=0x400
OAMP_PE_PROF(38).OAMP0[0x587]=0x400
OAMP_PE_PROF(39).OAMP0[0x588]=0x400
OAMP_PE_PROF(40).OAMP0[0x589]=0x400
OAMP_PE_PROF(41).OAMP0[0x58a]=0x400
OAMP_PE_PROF(42).OAMP0[0x58b]=0x400
OAMP_PE_PROF(43).OAMP0[0x58c]=0x400
OAMP_PE_PROF(44).OAMP0[0x58d]=0x400
OAMP_PE_PROF(45).OAMP0[0x58e]=0x400
OAMP_PE_PROF(46).OAMP0[0x58f]=0x400
OAMP_PE_PROF(47).OAMP0[0x590]=0x400
OAMP_PE_PROF(48).OAMP0[0x591]=0x400
OAMP_PE_PROF(49).OAMP0[0x592]=0x400
OAMP_PE_PROF(50).OAMP0[0x593]=0x400
OAMP_PE_PROF(51).OAMP0[0x594]=0x400
OAMP_PE_PROF(52).OAMP0[0x595]=0x400
OAMP_PE_PROF(53).OAMP0[0x596]=0x400
OAMP_PE_PROF(54).OAMP0[0x597]=0x400
OAMP_PE_PROF(55).OAMP0[0x598]=0x400
OAMP_PE_PROF(56).OAMP0[0x599]=0x400
OAMP_PE_PROF(57).OAMP0[0x59a]=0x400
OAMP_PE_PROF(58).OAMP0[0x59b]=0x400
OAMP_PE_PROF(59).OAMP0[0x59c]=0x400
OAMP_PE_PROF(60).OAMP0[0x59d]=0x400
OAMP_PE_PROF(61).OAMP0[0x59e]=0x400
OAMP_PE_PROF(62).OAMP0[0x59f]=0x400
OAMP_PE_PROF(63).OAMP0[0x5a0]=0x400
OAMP_PE_PTR(0).OAMP0[0x5cc]=0
OAMP_PE_PTR(1).OAMP0[0x5cd]=1
OAMP_PE_PTR(2).OAMP0[0x5ce]=0xb
OAMP_PE_PTR(3).OAMP0[0x5cf]=0x64
OAMP_PE_PTR(4).OAMP0[0x5d0]=0xa9
OAMP_PE_PTR(5).OAMP0[0x5d1]=0xe9
OAMP_PE_PTR(6).OAMP0[0x5d2]=0x12b
OAMP_PE_PTR(7).OAMP0[0x5d3]=0x131
OAMP_PE_PTR(8).OAMP0[0x5d4]=0x1bc
OAMP_PE_PTR(9).OAMP0[0x5d5]=0x1ed
OAMP_PE_PTR(10).OAMP0[0x5d6]=0x1fe
OAMP_PE_PTR(11).OAMP0[0x5d7]=0x231
OAMP_PE_PTR(12).OAMP0[0x5d8]=0x245
OAMP_PE_PTR(13).OAMP0[0x5d9]=0x24f
OAMP_PE_PTR(14).OAMP0[0x5da]=0x256
OAMP_PE_PTR(15).OAMP0[0x5db]=0x25e
OAMP_PE_PTR(16).OAMP0[0x5dc]=0x275
OAMP_PE_PTR(17).OAMP0[0x5dd]=0x27e
OAMP_PE_PTR(18).OAMP0[0x5de]=0x282
OAMP_PE_PTR(19).OAMP0[0x5df]=0x298
OAMP_PE_PTR(20).OAMP0[0x5e0]=0x2aa
OAMP_PE_PTR(21).OAMP0[0x5e1]=0x2dd
OAMP_PE_PTR(22).OAMP0[0x5e2]=0x30f
OAMP_PE_PTR(23).OAMP0[0x5e3]=0x361
OAMP_PE_PTR(24).OAMP0[0x5e4]=0
OAMP_PE_PTR(25).OAMP0[0x5e5]=0
OAMP_PE_PTR(26).OAMP0[0x5e6]=0
OAMP_PE_PTR(27).OAMP0[0x5e7]=0
OAMP_PE_PTR(28).OAMP0[0x5e8]=0
OAMP_PE_PTR(29).OAMP0[0x5e9]=0
OAMP_PE_PTR(30).OAMP0[0x5ea]=0
OAMP_PE_PTR(31).OAMP0[0x5eb]=0
OAMP_PE_STATUS_1.OAMP0[0x64a]=0
OAMP_PE_STATUS_2.OAMP0[0x64f]=0
OAMP_PORT_STAT_TLV.OAMP0[0x530]=0x20001
OAMP_PROTECTION_PACKET_CONF.OAMP0[0x668]=0x18
OAMP_PROTECTION_PACKET_HEADER.OAMP0[0x654]=0x12345678
OAMP_PR_2_FWDDP.OAMP0[0x10f]=0
OAMP_PR_2_FW_DTC.OAMP0[0x10e]=0
OAMP_PUNT_EVENT_HENDLING(0).OAMP0[0x182]=0xa8
OAMP_PUNT_EVENT_HENDLING(1).OAMP0[0x183]=0xa8
OAMP_PUNT_EVENT_HENDLING(2).OAMP0[0x184]=0xa8
OAMP_PUNT_EVENT_HENDLING(3).OAMP0[0x185]=0xa8
OAMP_PUNT_EVENT_HENDLING(4).OAMP0[0x186]=0xa8
OAMP_PUNT_EVENT_HENDLING(5).OAMP0[0x187]=0xa8
OAMP_PUNT_EVENT_HENDLING(6).OAMP0[0x188]=0xa8
OAMP_PUNT_EVENT_HENDLING(7).OAMP0[0x189]=0xa8
OAMP_PUNT_EVENT_HENDLING(8).OAMP0[0x18a]=0xa8
OAMP_PUNT_EVENT_HENDLING(9).OAMP0[0x18b]=0xa8
OAMP_PUNT_EVENT_HENDLING(10).OAMP0[0x18c]=0xa8
OAMP_PUNT_EVENT_HENDLING(11).OAMP0[0x18d]=0xa8
OAMP_PUNT_EVENT_HENDLING(12).OAMP0[0x18e]=0xa8
OAMP_PUNT_EVENT_HENDLING(13).OAMP0[0x18f]=0xa8
OAMP_PUNT_EVENT_HENDLING(14).OAMP0[0x190]=0xa8
OAMP_PUNT_EVENT_HENDLING(15).OAMP0[0x191]=0xa8
OAMP_PUNT_PKT_SYS_HDR.OAMP0[0x110]=0x1380001
OAMP_REG_0098.OAMP0[0x98]=0
OAMP_REG_0127.OAMP0[0x127]=0x20
OAMP_REG_0129.OAMP0[0x129]=0xc4f060300000800000c0e227d
OAMP_REG_0165.OAMP0[0x165]=0
OAMP_REG_0167.OAMP0[0x167]=0
OAMP_REG_0199.OAMP0[0x199]=0
OAMP_REG_00A0.OAMP0[0xa0]=0
OAMP_REG_00C2.OAMP0[0xc2]=0x10
OAMP_REG_00C6.OAMP0[0xc6]=0x53
OAMP_RESERVED_MIRROR_ADDR.OAMP0[0x85]=0
OAMP_RESERVED_MTCD.OAMP0[0xae]=0x30
OAMP_RESERVED_MTCP.OAMP0[0xad]=0x300000600000000
OAMP_RESERVED_SPARE_0.OAMP0[0x90]=0xffffffff
OAMP_RESERVED_SPARE_1.OAMP0[0x91]=0xffffffff
OAMP_RESERVED_SPARE_2.OAMP0[0x92]=0
OAMP_RESERVED_SPARE_3.OAMP0[0x93]=0
OAMP_RFC_6374_DM_PDU_HEADER.OAMP0[0x542]=0x333000000801002c333000000000002c
OAMP_RFC_6374_DM_PWE_CW.OAMP0[0x525]=0xc
OAMP_RFC_6374_IGNORED.OAMP0[0x198]=0
OAMP_RFC_6374_LM_PDU_HEADER.OAMP0[0x53e]=0x80100340000000000000034
OAMP_RFC_6374_LM_PWE_CW_0.OAMP0[0x526]=0xa
OAMP_RFC_6374_LM_PWE_CW_1.OAMP0[0x527]=0x1000000b
OAMP_RMEP_PUNT_GOOD_TIMER(1).OAMP0[0xb36]=0
OAMP_RMEP_PUNT_GOOD_TIMER(2).OAMP0[0xb37]=0
OAMP_RMEP_PUNT_GOOD_TIMER(3).OAMP0[0xb38]=0
OAMP_RMEP_PUNT_GOOD_TIMER(4).OAMP0[0xb39]=0
OAMP_RMEP_PUNT_GOOD_TIMER(5).OAMP0[0xb3a]=0
OAMP_RMEP_PUNT_GOOD_TIMER(6).OAMP0[0xb3b]=0
OAMP_RMEP_PUNT_GOOD_TIMER(7).OAMP0[0xb3c]=0
OAMP_RSP_PKT_COUNTER.OAMP0[0x5a3]=0
OAMP_RXB_DEBUG.OAMP0[0x195]=0
OAMP_RXB_PKT_COUNTER.OAMP0[0x5a5]=0
OAMP_RX_PKT_COUNTER.OAMP0[0x19a]=0
OAMP_RX_STATS_DATA_0.OAMP0[0x67f]=0
OAMP_RX_STATS_DATA_1.OAMP0[0x693]=0
OAMP_RX_STATS_DATA_2.OAMP0[0x6a7]=0
OAMP_RX_STATS_DATA_3.OAMP0[0x6bb]=0
OAMP_R_MEP_DB_FULL_ENTRY_THRESHOLD.OAMP0[0xb2b]=0
OAMP_SAT_EVC_RATE_CONTROL(0).OAMP0[0x6cf]=0
OAMP_SAT_EVC_RATE_CONTROL(1).OAMP0[0x6d3]=0
OAMP_SAT_EVC_RATE_CONTROL(2).OAMP0[0x6d7]=0
OAMP_SAT_EVC_RATE_CONTROL(3).OAMP0[0x6db]=0
OAMP_SAT_EVC_RATE_CONTROL(4).OAMP0[0x6df]=0
OAMP_SAT_EVC_RATE_CONTROL(5).OAMP0[0x6e3]=0
OAMP_SAT_EVC_RATE_CONTROL(6).OAMP0[0x6e7]=0
OAMP_SAT_EVC_RATE_CONTROL(7).OAMP0[0x6eb]=0
OAMP_SAT_GEN_CONFIG.OAMP0[0x670]=0x124f8f
OAMP_SAT_RX_CONFIG.OAMP0[0x673]=0
OAMP_SAT_RX_STAT.OAMP0[0x67d]=0x1400
OAMP_SAT_TX_CONFIG.OAMP0[0x672]=0x1020408
OAMP_SAT_TX_EVC_CNTR(0).OAMP0[0x8ef]=0
OAMP_SAT_TX_EVC_CNTR(1).OAMP0[0x8f1]=0
OAMP_SAT_TX_EVC_CNTR(2).OAMP0[0x8f3]=0
OAMP_SAT_TX_EVC_CNTR(3).OAMP0[0x8f5]=0
OAMP_SAT_TX_EVC_CNTR(4).OAMP0[0x8f7]=0
OAMP_SAT_TX_EVC_CNTR(5).OAMP0[0x8f9]=0
OAMP_SAT_TX_EVC_CNTR(6).OAMP0[0x8fb]=0
OAMP_SAT_TX_EVC_CNTR(7).OAMP0[0x8fd]=0
OAMP_SAT_TX_GEN_CNTR(0).OAMP0[0x6ef]=0
OAMP_SAT_TX_GEN_CNTR(1).OAMP0[0x6f7]=0
OAMP_SAT_TX_GEN_CNTR(2).OAMP0[0x6ff]=0
OAMP_SAT_TX_GEN_CNTR(3).OAMP0[0x707]=0
OAMP_SAT_TX_GEN_CNTR(4).OAMP0[0x70f]=0
OAMP_SAT_TX_GEN_CNTR(5).OAMP0[0x717]=0
OAMP_SAT_TX_GEN_CNTR(6).OAMP0[0x71f]=0
OAMP_SAT_TX_GEN_CNTR(7).OAMP0[0x727]=0
OAMP_SAT_TX_GEN_CNTR(8).OAMP0[0x72f]=0
OAMP_SAT_TX_GEN_CNTR(9).OAMP0[0x737]=0
OAMP_SAT_TX_GEN_CNTR(10).OAMP0[0x73f]=0
OAMP_SAT_TX_GEN_CNTR(11).OAMP0[0x747]=0
OAMP_SAT_TX_GEN_CNTR(12).OAMP0[0x74f]=0
OAMP_SAT_TX_GEN_CNTR(13).OAMP0[0x757]=0
OAMP_SAT_TX_GEN_CNTR(14).OAMP0[0x75f]=0
OAMP_SAT_TX_GEN_CNTR(15).OAMP0[0x767]=0
OAMP_SAT_TX_GEN_CNTR(16).OAMP0[0x76f]=0
OAMP_SAT_TX_GEN_CNTR(17).OAMP0[0x777]=0
OAMP_SAT_TX_GEN_CNTR(18).OAMP0[0x77f]=0
OAMP_SAT_TX_GEN_CNTR(19).OAMP0[0x787]=0
OAMP_SAT_TX_GEN_CNTR(20).OAMP0[0x78f]=0
OAMP_SAT_TX_GEN_CNTR(21).OAMP0[0x797]=0
OAMP_SAT_TX_GEN_CNTR(22).OAMP0[0x79f]=0
OAMP_SAT_TX_GEN_CNTR(23).OAMP0[0x7a7]=0
OAMP_SAT_TX_GEN_CNTR(24).OAMP0[0x7af]=0
OAMP_SAT_TX_GEN_CNTR(25).OAMP0[0x7b7]=0
OAMP_SAT_TX_GEN_CNTR(26).OAMP0[0x7bf]=0
OAMP_SAT_TX_GEN_CNTR(27).OAMP0[0x7c7]=0
OAMP_SAT_TX_GEN_CNTR(28).OAMP0[0x7cf]=0
OAMP_SAT_TX_GEN_CNTR(29).OAMP0[0x7d7]=0
OAMP_SAT_TX_GEN_CNTR(30).OAMP0[0x7df]=0
OAMP_SAT_TX_GEN_CNTR(31).OAMP0[0x7e7]=0
OAMP_SAT_TX_GEN_CNTR(32).OAMP0[0x7ef]=0
OAMP_SAT_TX_GEN_CNTR(33).OAMP0[0x7f7]=0
OAMP_SAT_TX_GEN_CNTR(34).OAMP0[0x7ff]=0
OAMP_SAT_TX_GEN_CNTR(35).OAMP0[0x807]=0
OAMP_SAT_TX_GEN_CNTR(36).OAMP0[0x80f]=0
OAMP_SAT_TX_GEN_CNTR(37).OAMP0[0x817]=0
OAMP_SAT_TX_GEN_CNTR(38).OAMP0[0x81f]=0
OAMP_SAT_TX_GEN_CNTR(39).OAMP0[0x827]=0
OAMP_SAT_TX_GEN_CNTR(40).OAMP0[0x82f]=0
OAMP_SAT_TX_GEN_CNTR(41).OAMP0[0x837]=0
OAMP_SAT_TX_GEN_CNTR(42).OAMP0[0x83f]=0
OAMP_SAT_TX_GEN_CNTR(43).OAMP0[0x847]=0
OAMP_SAT_TX_GEN_CNTR(44).OAMP0[0x84f]=0
OAMP_SAT_TX_GEN_CNTR(45).OAMP0[0x857]=0
OAMP_SAT_TX_GEN_CNTR(46).OAMP0[0x85f]=0
OAMP_SAT_TX_GEN_CNTR(47).OAMP0[0x867]=0
OAMP_SAT_TX_GEN_CNTR(48).OAMP0[0x86f]=0
OAMP_SAT_TX_GEN_CNTR(49).OAMP0[0x877]=0
OAMP_SAT_TX_GEN_CNTR(50).OAMP0[0x87f]=0
OAMP_SAT_TX_GEN_CNTR(51).OAMP0[0x887]=0
OAMP_SAT_TX_GEN_CNTR(52).OAMP0[0x88f]=0
OAMP_SAT_TX_GEN_CNTR(53).OAMP0[0x897]=0
OAMP_SAT_TX_GEN_CNTR(54).OAMP0[0x89f]=0
OAMP_SAT_TX_GEN_CNTR(55).OAMP0[0x8a7]=0
OAMP_SAT_TX_GEN_CNTR(56).OAMP0[0x8af]=0
OAMP_SAT_TX_GEN_CNTR(57).OAMP0[0x8b7]=0
OAMP_SAT_TX_GEN_CNTR(58).OAMP0[0x8bf]=0
OAMP_SAT_TX_GEN_CNTR(59).OAMP0[0x8c7]=0
OAMP_SAT_TX_GEN_CNTR(60).OAMP0[0x8cf]=0
OAMP_SAT_TX_GEN_CNTR(61).OAMP0[0x8d7]=0
OAMP_SAT_TX_GEN_CNTR(62).OAMP0[0x8df]=0
OAMP_SAT_TX_GEN_CNTR(63).OAMP0[0x8e7]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(0).OAMP0[0x900]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(1).OAMP0[0x908]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(2).OAMP0[0x910]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(3).OAMP0[0x918]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(4).OAMP0[0x920]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(5).OAMP0[0x928]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(6).OAMP0[0x930]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(7).OAMP0[0x938]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(8).OAMP0[0x940]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(9).OAMP0[0x948]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(10).OAMP0[0x950]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(11).OAMP0[0x958]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(12).OAMP0[0x960]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(13).OAMP0[0x968]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(14).OAMP0[0x970]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(15).OAMP0[0x978]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(16).OAMP0[0x980]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(17).OAMP0[0x988]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(18).OAMP0[0x990]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(19).OAMP0[0x998]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(20).OAMP0[0x9a0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(21).OAMP0[0x9a8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(22).OAMP0[0x9b0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(23).OAMP0[0x9b8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(24).OAMP0[0x9c0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(25).OAMP0[0x9c8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(26).OAMP0[0x9d0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(27).OAMP0[0x9d8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(28).OAMP0[0x9e0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(29).OAMP0[0x9e8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(30).OAMP0[0x9f0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(31).OAMP0[0x9f8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(32).OAMP0[0xa00]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(33).OAMP0[0xa08]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(34).OAMP0[0xa10]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(35).OAMP0[0xa18]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(36).OAMP0[0xa20]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(37).OAMP0[0xa28]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(38).OAMP0[0xa30]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(39).OAMP0[0xa38]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(40).OAMP0[0xa40]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(41).OAMP0[0xa48]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(42).OAMP0[0xa50]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(43).OAMP0[0xa58]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(44).OAMP0[0xa60]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(45).OAMP0[0xa68]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(46).OAMP0[0xa70]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(47).OAMP0[0xa78]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(48).OAMP0[0xa80]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(49).OAMP0[0xa88]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(50).OAMP0[0xa90]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(51).OAMP0[0xa98]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(52).OAMP0[0xaa0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(53).OAMP0[0xaa8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(54).OAMP0[0xab0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(55).OAMP0[0xab8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(56).OAMP0[0xac0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(57).OAMP0[0xac8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(58).OAMP0[0xad0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(59).OAMP0[0xad8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(60).OAMP0[0xae0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(61).OAMP0[0xae8]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(62).OAMP0[0xaf0]=0
OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL(63).OAMP0[0xaf8]=0
OAMP_SBUS_BROADCAST_ID.OAMP0[0x86]=0x7ff
OAMP_SBUS_LAST_IN_CHAIN.OAMP0[0x87]=0
OAMP_SD_SF_SCANNER_CFG.OAMP0[0xb45]=0x79f2c0000000000000000000000000000000000
OAMP_SD_SF_SHARE_CFG.OAMP0[0x8ff]=0
OAMP_SKIP_NEXT_BANK.OAMP0[0xb4c]=0
OAMP_SLM_CONFIG.OAMP0[0x560]=0
OAMP_SLM_MEASUREMENT_PERIOD_TIMER.OAMP0[0xb2e]=0
OAMP_SPECIAL_CLOCK_CONTROLS.OAMP0[0xc1]=2
OAMP_SRC_IP_MISS_INFO.OAMP0[0xb11]=0
OAMP_SRC_PORT_MISS_INFO.OAMP0[0xb15]=0
OAMP_STATUS_1_REG.OAMP0[0x12d]=0
OAMP_STATUS_2_REG.OAMP0[0x12e]=0
OAMP_STAT_INTERRUPT_MESSAGE.OAMP0[0x151]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
OAMP_TIMER_CONFIG.OAMP0[0x12f]=0x323c34600
OAMP_TRAP_CODE_MISS_INFO.OAMP0[0xb0c]=0
OAMP_TXM_BANK_SCAN_CONFIG(0).OAMP0[0x131]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(1).OAMP0[0x132]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(2).OAMP0[0x133]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(3).OAMP0[0x134]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(4).OAMP0[0x135]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(5).OAMP0[0x136]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(6).OAMP0[0x137]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(7).OAMP0[0x138]=0x1e942002
OAMP_TXM_BANK_SCAN_CONFIG(8).OAMP0[0x139]=0x1e942020
OAMP_TXM_BANK_SCAN_CONFIG(9).OAMP0[0x13a]=0x1e942020
OAMP_TXM_BANK_SCAN_CONFIG(10).OAMP0[0x13b]=0x1e942020
OAMP_TXM_BANK_SCAN_CONFIG(11).OAMP0[0x13c]=0x1e942020
0:_soc_cmicx_schan_err_handle:   NACK received in CMIC_SCHAN_ERR.
0:_soc_cmicx_schan_err_handle: CMIC_SCHAN_ERR data dump: err_code=0, data_len=0, src_port=32, dst_port=3, op_code=12 Full reg value=0x30380001
0:soc_reg_get: soc_reg_get failed for OAMP_TXM_DISABLE_DROP_FIX
ERROR: read from register OAMP_TXM_DISABLE_DROP_FIX.OAMP0 failed: Operation failed
OAMP_TXM_DISABLE_INVALID_MEPS.OAMP0[0xb4f]=0
OAMP_TXM_PKT_COUNTER.OAMP0[0x5a1]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(0).OAMP0[0xb3d]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(1).OAMP0[0xb3e]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(2).OAMP0[0xb3f]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(3).OAMP0[0xb40]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(4).OAMP0[0xb41]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(5).OAMP0[0xb42]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(6).OAMP0[0xb43]=0
OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER(7).OAMP0[0xb44]=0
OAMP_TXO_PKT_COUNTER.OAMP0[0x5aa]=0
OAMP_TXO_REQ_FIFO_DATA.OAMP0[0x5a7]=0
OAMP_TXO_REQ_STATUS.OAMP0[0x5a9]=0
OAMP_TX_JR_2_AS_OAM.OAMP0[0x126]=0
OAMP_UDH.OAMP0[0xb16]=1
OAMP_UP_PTCH.OAMP0[0x409]=0x3f
OAMP_VALIDITY_CHECK_STICKY.OAMP0[0x122]=0
OAMP_YOUR_DISC_MISS_INFO.OAMP0[0xb0f]=0
OAMP_Y_1731O_MPLSTP_GACH.OAMP0[0x411]=0x10000027
OAMP_Y_1731O_MPLSTP_GAL.OAMP0[0x410]=0xd140
OAMP_Y_1731O_PWE_GACH.OAMP0[0x412]=0x10008902
OCB_BANKS_FULL_TH_REGISTER.OCB0[0x105]=0x6190
OCB_DISABLE_BANK_DBG.OCB0[0x141]=0
OCB_DISABLE_REQ_DBG.OCB0[0x142]=0
OCB_DYNAMIC_CONFIGURATION.OCB0[0x103]=0
OCB_ECC_1B_ERR_CNT.OCB0[0x94]=0
OCB_ECC_2B_ERR_CNT.OCB0[0x96]=0
OCB_ECC_ERR_1B_MONITOR_MEM_MASK.OCB0[0x9a]=0x1ffffffffffffffffffffffffffffffffffffffffffff
OCB_ECC_ERR_2B_MONITOR_MEM_MASK.OCB0[0x9c]=0x1ffffffffffffffffffffffffffffffffffffffffffff
OCB_ECC_INTERRUPT_REGISTER.OCB0[0x7]=0
OCB_ECC_INTERRUPT_REGISTER_MASK.OCB0[0x17]=0
OCB_ECC_INTERRUPT_REGISTER_TEST.OCB0[0x1f]=0
OCB_ENABLE_DYNAMIC_MEMORY_ACCESS.OCB0[0x84]=0
OCB_FBC_BANK_CFG(0).OCB0[0x107]=0x3ff800
OCB_FBC_BANK_CFG(1).OCB0[0x108]=0x3ff800
OCB_FBC_BANK_CFG(2).OCB0[0x109]=0x3ff800
OCB_FBC_BANK_CFG(3).OCB0[0x10a]=0x3ff800
OCB_FBC_BANK_CFG(4).OCB0[0x10b]=0x3ff800
OCB_FBC_BANK_CFG(5).OCB0[0x10c]=0x3ff800
OCB_FBC_BANK_CFG(6).OCB0[0x10d]=0x3ff800
OCB_FBC_BANK_CFG(7).OCB0[0x10e]=0x3ff800
OCB_FBC_BANK_CFG(8).OCB0[0x10f]=0x3ff800
OCB_FBC_BANK_CFG(9).OCB0[0x110]=0x3ff800
OCB_FBC_BANK_CFG(10).OCB0[0x111]=0x3ff800
OCB_FBC_BANK_CFG(11).OCB0[0x112]=0x3ff800
OCB_FBC_BANK_CFG(12).OCB0[0x113]=0x3ff800
OCB_FBC_BANK_CFG(13).OCB0[0x114]=0x3ff800
OCB_FBC_BANK_CFG(14).OCB0[0x115]=0x3ff800
OCB_FBC_BANK_CFG(15).OCB0[0x116]=0x3ff800
OCB_FBC_BANK_INTERRUPT_REGISTER.OCB0[0x100]=0
OCB_FBC_BANK_INTERRUPT_REGISTER_MASK.OCB0[0x101]=0
OCB_FBC_BANK_INTERRUPT_REGISTER_TEST.OCB0[0x102]=0
OCB_FPC_DELETE.OCB0[0x106]=0
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(0).OCB0[0x121]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(1).OCB0[0x122]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(2).OCB0[0x123]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(3).OCB0[0x124]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(4).OCB0[0x125]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(5).OCB0[0x126]=0x7f2800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(6).OCB0[0x127]=0x7ef800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(7).OCB0[0x128]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(8).OCB0[0x129]=0x7ef800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(9).OCB0[0x12a]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(10).OCB0[0x12b]=0x7ef800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(11).OCB0[0x12c]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(12).OCB0[0x12d]=0x7ef800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(13).OCB0[0x12e]=0x7ef800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(14).OCB0[0x12f]=0x7f0800800
OCB_FREE_BUFFERS_BANK_STATUS_REGISTER(15).OCB0[0x130]=0x7f0800800
OCB_FREE_BUFFERS_STATUS_REGISTER.OCB0[0x11f]=0x7efe80008000
OCB_FREE_ERROR.OCB0[0x143]=0xffe2
OCB_GTIMER_CONFIGURATION.OCB0[0x89]=0
OCB_GTIMER_CYCLE.OCB0[0x88]=0x3b9aca00
OCB_INDIRECT_COMMAND.OCB0[0x80]=0xe000002
OCB_INDIRECT_COMMAND_ADDRESS.OCB0[0x81]=0x8000
OCB_INDIRECT_COMMAND_RD_DATA.OCB0[0x60]=0
OCB_INDIRECT_COMMAND_WIDE_MEM.OCB0[0x41]=0
OCB_INDIRECT_COMMAND_WR_DATA.OCB0[0x20]=0
OCB_INDIRECT_FORCE_BUBBLE.OCB0[0x83]=0x20019
OCB_INTERRUPT_MASK_REGISTER.OCB0[0x10]=0
OCB_INTERRUPT_REGISTER.OCB0[0x0]=0
OCB_INTERRUPT_REGISTER_TEST.OCB0[0x18]=0
OCB_PCMI_0.OCB0[0xb0]=0x3b9aca00
OCB_PCMI_1.OCB0[0xb3]=0x3b9aca00
OCB_PCMI_2.OCB0[0xb6]=0x3b9aca00
OCB_PCMI_3.OCB0[0xb9]=0x3b9aca00
OCB_PCMI_4.OCB0[0xbc]=0x3b9aca00
OCB_PCMI_0_S.OCB0[0xb1]=0
OCB_PCMI_0_T.OCB0[0xb2]=0
OCB_PCMI_1_S.OCB0[0xb4]=0
OCB_PCMI_1_T.OCB0[0xb5]=0
OCB_PCMI_2_S.OCB0[0xb7]=0
OCB_PCMI_2_T.OCB0[0xb8]=0
OCB_PCMI_3_S.OCB0[0xba]=0
OCB_PCMI_3_T.OCB0[0xbb]=0
OCB_PCMI_4_S.OCB0[0xbd]=0
OCB_PCMI_4_T.OCB0[0xbe]=0
OCB_REG_00C2.OCB0[0xc2]=0x10
OCB_RESERVED_MTCD.OCB0[0xae]=0x30
OCB_RESERVED_MTCP.OCB0[0xad]=0x300000600000000
OCB_RESERVED_SPARE_0.OCB0[0x90]=0xffffffff
OCB_RESERVED_SPARE_1.OCB0[0x91]=0xffffffff
OCB_RESERVED_SPARE_2.OCB0[0x92]=0
OCB_RESERVED_SPARE_3.OCB0[0x93]=0
OCB_RESET_STATUS_REGISTER.OCB0[0x104]=0
OCB_SBUS_BROADCAST_ID.OCB0[0x86]=0x7ff
OCB_SBUS_LAST_IN_CHAIN.OCB0[0x87]=0
OCB_SPECIAL_CLOCK_CONTROLS.OCB0[0xc1]=2
OCB_STATISTICS_COUNTERS.OCB0[0x117]=0x158ecf737e
OLP_APP_DB_TO_APP_DB_INDEX_MAP.OLP0[0x120]=0
OLP_APP_DB_TO_APP_DB_INDEX_MAP_FOR_ROUTING.OLP0[0x15a]=0
OLP_AUTO_DOC_NAME_0(0).OLP0[0x12c]=0
OLP_AUTO_DOC_NAME_0(1).OLP0[0x12e]=0
OLP_AUTO_DOC_NAME_1(0).OLP0[0x130]=2
OLP_AUTO_DOC_NAME_1(1).OLP0[0x132]=0
OLP_AUTO_DOC_NAME_2.OLP0[0x134]=0
OLP_AUTO_DOC_NAME_3.OLP0[0x135]=0
OLP_CFG_JR_2_CMD_TO_JR_CMD_MAP.OLP0[0x12b]=0xfeb433
OLP_CFG_JR_CMD_TO_JR_2_CMD_MAP.OLP0[0x12a]=0xe6f8c2
OLP_CFG_JR_LOGICAL_DB_TYPE.OLP0[0x129]=0
OLP_CFG_JR_TO_JR_2_AGE.OLP0[0x126]=0
OLP_CFG_JR_TO_JR_2_APP_DB.OLP0[0x127]=2
OLP_CFG_JR_TO_JR_2_KEY_MASK.OLP0[0x128]=0
OLP_CFG_JR_TO_JR_2_VMV.OLP0[0x125]=0x18
OLP_DSP_ENGINE_CONFIGURATION(0).OLP0[0x136]=0xaa07807
OLP_DSP_ENGINE_CONFIGURATION(1).OLP0[0x137]=0xaa07807
OLP_DSP_HEADER(0).OLP0[0x138]=0x5f001801e0000200000000ff020000000000ab000000000000000000000000
OLP_DSP_HEADER(1).OLP0[0x140]=0x5f0030000e000200000000ff020000000000ab000000000000000000000000
OLP_ECC_1B_ERR_CNT.OLP0[0x94]=0x7f0000
OLP_ECC_2B_ERR_CNT.OLP0[0x96]=0xa90000
OLP_ECC_ERR_1B_MONITOR_MEM_MASK.OLP0[0x9a]=0x3f
OLP_ECC_ERR_2B_MONITOR_MEM_MASK.OLP0[0x9c]=0x3f
OLP_ECC_INTERRUPT_REGISTER.OLP0[0x7]=0
OLP_ECC_INTERRUPT_REGISTER_MASK.OLP0[0x17]=0
OLP_ECC_INTERRUPT_REGISTER_TEST.OLP0[0x1f]=0
OLP_ENABLE_DYNAMIC_MEMORY_ACCESS.OLP0[0x84]=0x1f
OLP_EP_TRANSACTION_COUNTER.OLP0[0x14f]=0x18ba
OLP_FIFO_0_EVENT_COUNTER.OLP0[0x14a]=0x1d0
OLP_FIFO_1_EVENT_COUNTER.OLP0[0x14b]=0
OLP_FIFO_DMA_EVENT_COUNTER.OLP0[0x14c]=0
OLP_GTIMER_CONFIGURATION.OLP0[0x89]=0
OLP_GTIMER_CYCLE.OLP0[0x88]=0x3b9aca00
OLP_HEAD_OF_CPU_DSPG_CMD_FIFO.OLP0[0x154]=0x1fffffffffffffffffffffffffffffffffffffffffffff
OLP_INCOMING_BAD_PACKET_COUNTER.OLP0[0x151]=0
OLP_INCOMING_EVENT_COUNTER.OLP0[0x148]=0xdde2
OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER.OLP0[0x152]=0x1d0
OLP_INCOMING_VALID_PACKET_COUNTER.OLP0[0x150]=0x1a6
OLP_INDIRECT_COMMAND.OLP0[0x80]=0xe000002
OLP_INDIRECT_COMMAND_ADDRESS.OLP0[0x81]=0x6e
OLP_INDIRECT_COMMAND_RD_DATA.OLP0[0x60]=0
OLP_INDIRECT_COMMAND_WR_DATA.OLP0[0x20]=2
OLP_INDIRECT_FORCE_BUBBLE.OLP0[0x83]=0x20019
OLP_INTERRUPT_MASK_REGISTER.OLP0[0x10]=0
OLP_INTERRUPT_REGISTER.OLP0[0x0]=0
OLP_INTERRUPT_REGISTER_TEST.OLP0[0x18]=0
OLP_IP_TRANSACTION_COUNTER.OLP0[0x14e]=0x1a8a
OLP_LARGE_EM_MRQ_CONFIGURATION.OLP0[0x124]=2
OLP_LEARN_CMD_DESTINATION_OFFSET.OLP0[0x11c]=0x1f
OLP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUE.OLP0[0x118]=0xa010000000000000
OLP_LEARN_CMD_EEI_OFFSET.OLP0[0x11e]=7
OLP_LEARN_CMD_FEC_OFFSET.OLP0[0x11f]=0x1f
OLP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUE.OLP0[0x11a]=0xc010000000000000
OLP_LEARN_CMD_OUT_LIF_OFFSET.OLP0[0x11d]=9
OLP_LPBK_EVENT_COUNTER.OLP0[0x149]=0
OLP_OLP_GENERAL_CFG.OLP0[0x10f]=1
OLP_OLP_LEARN_PAYLOAD_STRENGTH_SIZE.OLP0[0x15e]=0
OLP_OUTGOING_PACKET_COUNTER.OLP0[0x14d]=0x1a6
OLP_OUTGOING_REQUEST_COUNTER.OLP0[0x153]=0x1d0
OLP_PIPE_SELECT.OLP0[0x110]=0
OLP_REG_0041.OLP0[0x41]=0
OLP_REG_0098.OLP0[0x98]=0
OLP_REG_00A0.OLP0[0xa0]=0
OLP_REG_00C2.OLP0[0xc2]=0x10
OLP_REG_00C3.OLP0[0xc3]=1
OLP_RESERVED_MTCD.OLP0[0xae]=0x30
OLP_RESERVED_MTCP.OLP0[0xad]=0x300000600000000
OLP_RESERVED_SPARE_0.OLP0[0x90]=0xffffffff
OLP_RESERVED_SPARE_1.OLP0[0x91]=0xffffffff
OLP_RESERVED_SPARE_2.OLP0[0x92]=0
OLP_RESERVED_SPARE_3.OLP0[0x93]=0
OLP_RX_CONFIGS_BCM_86650_DSP_SOURCE_DEVICE.OLP0[0x113]=0xe
OLP_RX_CONFIGS_DSP_IDENTIFIER.OLP0[0x111]=0x7fffeac00c
OLP_RX_CONFIGS_GENERAL.OLP0[0x115]=0xe
OLP_SBUS_BROADCAST_ID.OLP0[0x86]=0x7ff
OLP_SBUS_LAST_IN_CHAIN.OLP0[0x87]=0
OLP_SPECIAL_CLOCK_CONTROLS.OLP0[0xc1]=2
OLP_TX_CONFIGS.OLP0[0x117]=1
OLP_TX_CONFIGS_BCM_86650.OLP0[0x116]=0
PDM_ECC_1B_ERR_CNT.PDM0[0x94]=0
PDM_ECC_2B_ERR_CNT.PDM0[0x96]=0
PDM_ECC_ERR_1B_MONITOR_MEM_MASK.PDM0[0x9a]=3
PDM_ECC_ERR_2B_MONITOR_MEM_MASK.PDM0[0x9c]=3
PDM_ECC_INTERRUPT_REGISTER.PDM0[0x7]=0
PDM_ECC_INTERRUPT_REGISTER_MASK.PDM0[0x17]=0
PDM_ECC_INTERRUPT_REGISTER_TEST.PDM0[0x1f]=0
PDM_FPC_CONTROL.PDM0[0x104]=0x3fff8000
PDM_FPC_STATUS.PDM0[0x105]=0x3aa1d92200003aa1d9223551dfecbfa37fb2
PDM_GTIMER_CONFIGURATION.PDM0[0x89]=0
PDM_GTIMER_CYCLE.PDM0[0x88]=0x3b9aca00
PDM_INTERRUPT_MASK_REGISTER.PDM0[0x10]=0
PDM_INTERRUPT_REGISTER.PDM0[0x0]=0
PDM_INTERRUPT_REGISTER_TEST.PDM0[0x18]=0
PDM_PDM_CONTROL.PDM0[0x10a]=0
PDM_PDM_STATUS.PDM0[0x10b]=0
PDM_REG_00C2.PDM0[0xc2]=0x10
PDM_RESERVED_MTCD.PDM0[0xae]=0x30
PDM_RESERVED_MTCP.PDM0[0xad]=0x300000600000000
PDM_RESERVED_SPARE_0.PDM0[0x90]=0xffffffff
PDM_RESERVED_SPARE_1.PDM0[0x91]=0xffffffff
PDM_RESERVED_SPARE_2.PDM0[0x92]=0
PDM_RESERVED_SPARE_3.PDM0[0x93]=0
PDM_SBUS_BROADCAST_ID.PDM0[0x86]=0x7ff
PDM_SBUS_LAST_IN_CHAIN.PDM0[0x87]=0
PDM_SPECIAL_CLOCK_CONTROLS.PDM0[0xc1]=2
PEM_ALU_CONFIG(0).PEM0[0x305]=2
PEM_ALU_CONFIG(1).PEM0[0x306]=2
PEM_ALU_CONFIG(2).PEM0[0x307]=2
PEM_ALU_CONFIG(3).PEM0[0x308]=2
PEM_ALU_CONFIG(0).PEM1[0x305]=2
PEM_ALU_CONFIG(1).PEM1[0x306]=2
PEM_ALU_CONFIG(2).PEM1[0x307]=2
PEM_ALU_CONFIG(3).PEM1[0x308]=2
PEM_ALU_CONFIG(0).PEM2[0x305]=0
PEM_ALU_CONFIG(1).PEM2[0x306]=2
PEM_ALU_CONFIG(2).PEM2[0x307]=2
PEM_ALU_CONFIG(3).PEM2[0x308]=4
PEM_ALU_CONFIG(0).PEM3[0x305]=2
PEM_ALU_CONFIG(1).PEM3[0x306]=6
PEM_ALU_CONFIG(2).PEM3[0x307]=6
PEM_ALU_CONFIG(3).PEM3[0x308]=2
PEM_CAM_CONFIG(0).PEM0[0x405]=0x4e
PEM_CAM_CONFIG(1).PEM0[0x406]=0x4e
PEM_CAM_CONFIG(2).PEM0[0x407]=0xa
PEM_CAM_CONFIG(3).PEM0[0x408]=0xa
PEM_CAM_CONFIG(0).PEM1[0x405]=0xa
PEM_CAM_CONFIG(1).PEM1[0x406]=0x4e
PEM_CAM_CONFIG(2).PEM1[0x407]=0xa
PEM_CAM_CONFIG(3).PEM1[0x408]=8
PEM_CAM_CONFIG(0).PEM2[0x405]=0x4e
PEM_CAM_CONFIG(1).PEM2[0x406]=0xa
PEM_CAM_CONFIG(2).PEM2[0x407]=0x4c
PEM_CAM_CONFIG(3).PEM2[0x408]=0x4e
PEM_CAM_CONFIG(0).PEM3[0x405]=0x4e
PEM_CAM_CONFIG(1).PEM3[0x406]=0x4e
PEM_CAM_CONFIG(2).PEM3[0x407]=0x4e
PEM_CAM_CONFIG(3).PEM3[0x408]=0x4e
PEM_ECC_1B_ERR_CNT.PEM0[0x94]=0
PEM_ECC_1B_ERR_CNT.PEM1[0x94]=0
PEM_ECC_1B_ERR_CNT.PEM2[0x94]=0
PEM_ECC_1B_ERR_CNT.PEM3[0x94]=0
PEM_ECC_2B_ERR_CNT.PEM0[0x96]=0
PEM_ECC_2B_ERR_CNT.PEM1[0x96]=0
PEM_ECC_2B_ERR_CNT.PEM2[0x96]=0
PEM_ECC_2B_ERR_CNT.PEM3[0x96]=0
PEM_ECC_ERR_1B_MONITOR_MEM_MASK.PEM0[0x9a]=0xffffffffffffffff
PEM_ECC_ERR_1B_MONITOR_MEM_MASK.PEM1[0x9a]=0xffffffffffffffff
PEM_ECC_ERR_1B_MONITOR_MEM_MASK.PEM2[0x9a]=0xffffffffffffffff
PEM_ECC_ERR_1B_MONITOR_MEM_MASK.PEM3[0x9a]=0xffffffffffffffff
PEM_ECC_ERR_2B_MONITOR_MEM_MASK.PEM0[0x9c]=0xffffffffffffffff
PEM_ECC_ERR_2B_MONITOR_MEM_MASK.PEM1[0x9c]=0xffffffffffffffff
PEM_ECC_ERR_2B_MONITOR_MEM_MASK.PEM2[0x9c]=0xffffffffffffffff
PEM_ECC_ERR_2B_MONITOR_MEM_MASK.PEM3[0x9c]=0xffffffffffffffff
PEM_ECC_INTERRUPT_REGISTER.PEM0[0x7]=0
PEM_ECC_INTERRUPT_REGISTER.PEM1[0x7]=0
PEM_ECC_INTERRUPT_REGISTER.PEM2[0x7]=0
PEM_ECC_INTERRUPT_REGISTER.PEM3[0x7]=0
PEM_ECC_INTERRUPT_REGISTER_MASK.PEM0[0x17]=0
PEM_ECC_INTERRUPT_REGISTER_MASK.PEM1[0x17]=0
PEM_ECC_INTERRUPT_REGISTER_MASK.PEM2[0x17]=0
PEM_ECC_INTERRUPT_REGISTER_MASK.PEM3[0x17]=0
PEM_ECC_INTERRUPT_REGISTER_TEST.PEM0[0x1f]=0
PEM_ECC_INTERRUPT_REGISTER_TEST.PEM1[0x1f]=0
PEM_ECC_INTERRUPT_REGISTER_TEST.PEM2[0x1f]=0
PEM_ECC_INTERRUPT_REGISTER_TEST.PEM3[0x1f]=0
PEM_ENABLE_DYNAMIC_MEMORY_ACCESS.PEM0[0x84]=1
PEM_ENABLE_DYNAMIC_MEMORY_ACCESS.PEM1[0x84]=1
PEM_ENABLE_DYNAMIC_MEMORY_ACCESS.PEM2[0x84]=1
PEM_ENABLE_DYNAMIC_MEMORY_ACCESS.PEM3[0x84]=1
PEM_GTIMER_CONFIGURATION.PEM0[0x89]=0
PEM_GTIMER_CONFIGURATION.PEM1[0x89]=0
PEM_GTIMER_CONFIGURATION.PEM2[0x89]=0
PEM_GTIMER_CONFIGURATION.PEM3[0x89]=0
PEM_GTIMER_CYCLE.PEM0[0x88]=0x3b9aca00
PEM_GTIMER_CYCLE.PEM1[0x88]=0x3b9aca00
PEM_GTIMER_CYCLE.PEM2[0x88]=0x3b9aca00
PEM_GTIMER_CYCLE.PEM3[0x88]=0x3b9aca00
PEM_INDIRECT_COMMAND.PEM0[0x80]=0xe000002
PEM_INDIRECT_COMMAND.PEM1[0x80]=0xe000002
PEM_INDIRECT_COMMAND.PEM2[0x80]=0xe000002
PEM_INDIRECT_COMMAND.PEM3[0x80]=0xe000002
PEM_INDIRECT_COMMAND_ADDRESS.PEM0[0x81]=0x10c00e7
PEM_INDIRECT_COMMAND_ADDRESS.PEM1[0x81]=0x80840022
PEM_INDIRECT_COMMAND_ADDRESS.PEM2[0x81]=0x82080018
PEM_INDIRECT_COMMAND_ADDRESS.PEM3[0x81]=0x10c002a
PEM_INDIRECT_COMMAND_RD_DATA.PEM0[0x60]=0xffffffffffffff330000000000000000000000000000000000000000000000000000000000000000
PEM_INDIRECT_COMMAND_RD_DATA.PEM1[0x60]=0x1d00000000000000000001f043ffe1fff0fff87ffc3ffe268d
PEM_INDIRECT_COMMAND_RD_DATA.PEM2[0x60]=0xc80f300f301ff71fff000000000000000000000000000000000000000000000000
PEM_INDIRECT_COMMAND_RD_DATA.PEM3[0x60]=0xffffffffffffff330000000000000000000000000000000000000000000000000000000000000000
PEM_INDIRECT_COMMAND_WR_DATA.PEM0[0x20]=0xfff807ffc03fffffffffffffff330000000000000000000000000000000000000000000000000000000000000010
PEM_INDIRECT_COMMAND_WR_DATA.PEM1[0x20]=0xfff807ffc03fffffffffffff3a43000000000000000000000000000000000001f043ffe1fff0fff87ffc3ffe268d
PEM_INDIRECT_COMMAND_WR_DATA.PEM2[0x20]=0xfff807ffc03fffffffff11f622110f300f301ff71fff000000000000000000000000000000000000000000000000
PEM_INDIRECT_COMMAND_WR_DATA.PEM3[0x20]=0xfff807ffc03fffffffffffffff330000000000000000000000000000000000000000000000000000000000000010
PEM_INDIRECT_FORCE_BUBBLE.PEM0[0x83]=0x20019
PEM_INDIRECT_FORCE_BUBBLE.PEM1[0x83]=0x20019
PEM_INDIRECT_FORCE_BUBBLE.PEM2[0x83]=0x20019
PEM_INDIRECT_FORCE_BUBBLE.PEM3[0x83]=0x20019
PEM_INTERRUPT_MASK_REGISTER.PEM0[0x10]=0
PEM_INTERRUPT_MASK_REGISTER.PEM1[0x10]=0
PEM_INTERRUPT_MASK_REGISTER.PEM2[0x10]=0
PEM_INTERRUPT_MASK_REGISTER.PEM3[0x10]=0
PEM_INTERRUPT_REGISTER.PEM0[0x0]=0
PEM_INTERRUPT_REGISTER.PEM1[0x0]=0
PEM_INTERRUPT_REGISTER.PEM2[0x0]=0
PEM_INTERRUPT_REGISTER.PEM3[0x0]=0
PEM_INTERRUPT_REGISTER_TEST.PEM0[0x18]=0
PEM_INTERRUPT_REGISTER_TEST.PEM1[0x18]=0
PEM_INTERRUPT_REGISTER_TEST.PEM2[0x18]=0
PEM_INTERRUPT_REGISTER_TEST.PEM3[0x18]=0
PEM_MAP_CONFIG(0).PEM0[0x205]=6
PEM_MAP_CONFIG(1).PEM0[0x206]=6
PEM_MAP_CONFIG(2).PEM0[0x207]=6
PEM_MAP_CONFIG(3).PEM0[0x208]=6
PEM_MAP_CONFIG(0).PEM1[0x205]=2
PEM_MAP_CONFIG(1).PEM1[0x206]=6
PEM_MAP_CONFIG(2).PEM1[0x207]=6
PEM_MAP_CONFIG(3).PEM1[0x208]=6
PEM_MAP_CONFIG(0).PEM2[0x205]=6
PEM_MAP_CONFIG(1).PEM2[0x206]=4
PEM_MAP_CONFIG(2).PEM2[0x207]=6
PEM_MAP_CONFIG(3).PEM2[0x208]=6
PEM_MAP_CONFIG(0).PEM3[0x205]=4
PEM_MAP_CONFIG(1).PEM3[0x206]=6
PEM_MAP_CONFIG(2).PEM3[0x207]=6
PEM_MAP_CONFIG(3).PEM3[0x208]=6
PEM_PCMI_0.PEM0[0xb0]=0x3b9aca00
PEM_PCMI_0.PEM1[0xb0]=0x3b9aca00
PEM_PCMI_0.PEM2[0xb0]=0x3b9aca00
PEM_PCMI_0.PEM3[0xb0]=0x3b9aca00
PEM_PCMI_1.PEM0[0xb3]=0x3b9aca00
PEM_PCMI_1.PEM1[0xb3]=0x3b9aca00
PEM_PCMI_1.PEM2[0xb3]=0x3b9aca00
PEM_PCMI_1.PEM3[0xb3]=0x3b9aca00
PEM_PCMI_2.PEM0[0xb6]=0x3b9aca00
PEM_PCMI_2.PEM1[0xb6]=0x3b9aca00
PEM_PCMI_2.PEM2[0xb6]=0x3b9aca00
PEM_PCMI_2.PEM3[0xb6]=0x3b9aca00
PEM_PCMI_3.PEM0[0xb9]=0x3b9aca00
PEM_PCMI_3.PEM1[0xb9]=0x3b9aca00
PEM_PCMI_3.PEM2[0xb9]=0x3b9aca00
PEM_PCMI_3.PEM3[0xb9]=0x3b9aca00
PEM_PCMI_4.PEM0[0xbc]=0x3b9aca00
PEM_PCMI_4.PEM1[0xbc]=0x3b9aca00
PEM_PCMI_4.PEM2[0xbc]=0x3b9aca00
PEM_PCMI_4.PEM3[0xbc]=0x3b9aca00
PEM_PCMI_0_S.PEM0[0xb1]=0
PEM_PCMI_0_S.PEM1[0xb1]=0
PEM_PCMI_0_S.PEM2[0xb1]=0
PEM_PCMI_0_S.PEM3[0xb1]=0
PEM_PCMI_0_T.PEM0[0xb2]=0
PEM_PCMI_0_T.PEM1[0xb2]=0
PEM_PCMI_0_T.PEM2[0xb2]=0
PEM_PCMI_0_T.PEM3[0xb2]=0
PEM_PCMI_1_S.PEM0[0xb4]=0
PEM_PCMI_1_S.PEM1[0xb4]=0
PEM_PCMI_1_S.PEM2[0xb4]=0
PEM_PCMI_1_S.PEM3[0xb4]=0
PEM_PCMI_1_T.PEM0[0xb5]=0
PEM_PCMI_1_T.PEM1[0xb5]=0
PEM_PCMI_1_T.PEM2[0xb5]=0
PEM_PCMI_1_T.PEM3[0xb5]=0
PEM_PCMI_2_S.PEM0[0xb7]=0
PEM_PCMI_2_S.PEM1[0xb7]=0
PEM_PCMI_2_S.PEM2[0xb7]=0
PEM_PCMI_2_S.PEM3[0xb7]=0
PEM_PCMI_2_T.PEM0[0xb8]=0
PEM_PCMI_2_T.PEM1[0xb8]=0
PEM_PCMI_2_T.PEM2[0xb8]=0
PEM_PCMI_2_T.PEM3[0xb8]=0
PEM_PCMI_3_S.PEM0[0xba]=0
PEM_PCMI_3_S.PEM1[0xba]=0
PEM_PCMI_3_S.PEM2[0xba]=0
PEM_PCMI_3_S.PEM3[0xba]=0
PEM_PCMI_3_T.PEM0[0xbb]=0
PEM_PCMI_3_T.PEM1[0xbb]=0
PEM_PCMI_3_T.PEM2[0xbb]=0
PEM_PCMI_3_T.PEM3[0xbb]=0
PEM_PCMI_4_S.PEM0[0xbd]=0
PEM_PCMI_4_S.PEM1[0xbd]=0
PEM_PCMI_4_S.PEM2[0xbd]=0
PEM_PCMI_4_S.PEM3[0xbd]=0
PEM_PCMI_4_T.PEM0[0xbe]=0
PEM_PCMI_4_T.PEM1[0xbe]=0
PEM_PCMI_4_T.PEM2[0xbe]=0
PEM_PCMI_4_T.PEM3[0xbe]=0
PEM_PRIO_CONFIG(0).PEM0[0x505]=6
PEM_PRIO_CONFIG(1).PEM0[0x506]=2
PEM_PRIO_CONFIG(2).PEM0[0x507]=2
PEM_PRIO_CONFIG(3).PEM0[0x508]=2
PEM_PRIO_CONFIG(0).PEM1[0x505]=2
PEM_PRIO_CONFIG(1).PEM1[0x506]=2
PEM_PRIO_CONFIG(2).PEM1[0x507]=1
PEM_PRIO_CONFIG(3).PEM1[0x508]=2
PEM_PRIO_CONFIG(0).PEM2[0x505]=2
PEM_PRIO_CONFIG(1).PEM2[0x506]=1
PEM_PRIO_CONFIG(2).PEM2[0x507]=2
PEM_PRIO_CONFIG(3).PEM2[0x508]=2
PEM_PRIO_CONFIG(0).PEM3[0x505]=6
PEM_PRIO_CONFIG(1).PEM3[0x506]=6
PEM_PRIO_CONFIG(2).PEM3[0x507]=6
PEM_PRIO_CONFIG(3).PEM3[0x508]=2
PEM_REG_0041.PEM0[0x41]=0
PEM_REG_0041.PEM1[0x41]=0
PEM_REG_0041.PEM2[0x41]=0
PEM_REG_0041.PEM3[0x41]=0
PEM_REG_0098.PEM0[0x98]=0
PEM_REG_0098.PEM1[0x98]=0
PEM_REG_0098.PEM2[0x98]=0
PEM_REG_0098.PEM3[0x98]=0
PEM_REG_00A0.PEM0[0xa0]=0
PEM_REG_00A0.PEM1[0xa0]=0
PEM_REG_00A0.PEM2[0xa0]=0
PEM_REG_00A0.PEM3[0xa0]=0
PEM_REG_00C2.PEM0[0xc2]=0x10
PEM_REG_00C2.PEM1[0xc2]=0x10
PEM_REG_00C2.PEM2[0xc2]=0x10
PEM_REG_00C2.PEM3[0xc2]=0x10
PEM_RESERVED_MTCD.PEM0[0xae]=0x30
PEM_RESERVED_MTCD.PEM1[0xae]=0x30
PEM_RESERVED_MTCD.PEM2[0xae]=0x30
PEM_RESERVED_MTCD.PEM3[0xae]=0x30
PEM_RESERVED_MTCP.PEM0[0xad]=0x300000600000000
PEM_RESERVED_MTCP.PEM1[0xad]=0x300000600000000
PEM_RESERVED_MTCP.PEM2[0xad]=0x300000600000000
PEM_RESERVED_MTCP.PEM3[0xad]=0x300000600000000
PEM_RESERVED_SPARE_0.PEM0[0x90]=0xe1ce40cb
PEM_RESERVED_SPARE_0.PEM1[0x90]=0x2120b0
PEM_RESERVED_SPARE_0.PEM2[0x90]=0xffffffff
PEM_RESERVED_SPARE_0.PEM3[0x90]=0xffffffff
PEM_RESERVED_SPARE_1.PEM0[0x91]=0x6cc2bf86
PEM_RESERVED_SPARE_1.PEM1[0x91]=0x1437e5
PEM_RESERVED_SPARE_1.PEM2[0x91]=0xffffffff
PEM_RESERVED_SPARE_1.PEM3[0x91]=0xffffffff
PEM_RESERVED_SPARE_2.PEM0[0x92]=0x12ed0ad9
PEM_RESERVED_SPARE_2.PEM1[0x92]=0x1437e5
PEM_RESERVED_SPARE_2.PEM2[0x92]=0
PEM_RESERVED_SPARE_2.PEM3[0x92]=0
PEM_RESERVED_SPARE_3.PEM0[0x93]=0x65308f41
PEM_RESERVED_SPARE_3.PEM1[0x93]=0x10
PEM_RESERVED_SPARE_3.PEM2[0x93]=0
PEM_RESERVED_SPARE_3.PEM3[0x93]=0
PEM_ROUTER_INPUT_SELECT.PEM0[0x100]=0xaaaaaa69a69a
PEM_ROUTER_INPUT_SELECT.PEM1[0x100]=0x5aaaaa69a69a
PEM_ROUTER_INPUT_SELECT.PEM2[0x100]=0xa45589212a9a
PEM_ROUTER_INPUT_SELECT.PEM3[0x100]=0xaaaaaa6aaaaa
PEM_SBUS_BROADCAST_ID.PEM0[0x86]=0x7ff
PEM_SBUS_BROADCAST_ID.PEM1[0x86]=0x7ff
PEM_SBUS_BROADCAST_ID.PEM2[0x86]=0x7ff
PEM_SBUS_BROADCAST_ID.PEM3[0x86]=0x7ff
PEM_SBUS_LAST_IN_CHAIN.PEM0[0x87]=0
PEM_SBUS_LAST_IN_CHAIN.PEM1[0x87]=0
PEM_SBUS_LAST_IN_CHAIN.PEM2[0x87]=0
PEM_SBUS_LAST_IN_CHAIN.PEM3[0x87]=0
PEM_SPECIAL_CLOCK_CONTROLS.PEM0[0xc1]=2
PEM_SPECIAL_CLOCK_CONTROLS.PEM1[0xc1]=2
PEM_SPECIAL_CLOCK_CONTROLS.PEM2[0xc1]=2
PEM_SPECIAL_CLOCK_CONTROLS.PEM3[0xc1]=2
PQP_CAPTURE_ALL_PACKETS.PQP0[0x16a]=1
PQP_DELETE_FBC_FIFO_IRDY_STATUS.PQP0[0x140]=0
PQP_DELETE_FIFO_CONFIGURATION.PQP0[0x102]=0x4b2bd90c825896320fa3e9
PQP_DELETE_FIFO_STATUS.PQP0[0x144]=0
PQP_DELETE_FIFO_WATERMARK.PQP0[0x142]=0x801
PQP_DEQ_COUNTERS_CONFIG.PQP0[0x15b]=0
PQP_EBTR_ILLEGAL_TH.PQP0[0x109]=0x1be
PQP_ECC_1B_ERR_CNT.PQP0[0x94]=0x8000
PQP_ECC_2B_ERR_CNT.PQP0[0x96]=0x8000
PQP_ECC_ERR_1B_MONITOR_MEM_MASK.PQP0[0x9a]=0xfff
PQP_ECC_ERR_2B_MONITOR_MEM_MASK.PQP0[0x9c]=0xfff
PQP_ECC_INTERRUPT_REGISTER.PQP0[0x7]=0
PQP_ECC_INTERRUPT_REGISTER_MASK.PQP0[0x17]=0
PQP_ECC_INTERRUPT_REGISTER_TEST.PQP0[0x1f]=0
PQP_EGQ_BLOCK_INIT_STATUS.PQP0[0x100]=8
PQP_EGRESS_QUEUES_EMPTY.PQP0[0x146]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
PQP_ENABLE_DYNAMIC_MEMORY_ACCESS.PQP0[0x84]=0
PQP_ENQ_COUNTERS_CONFIG.PQP0[0x156]=0
PQP_FDC_LEVEL.PQP0[0x13f]=0x114000
PQP_GTIMER_CONFIGURATION.PQP0[0x89]=2
PQP_GTIMER_CYCLE.PQP0[0x88]=0x23c34600
PQP_INDIRECT_COMMAND.PQP0[0x80]=0xe000002
PQP_INDIRECT_COMMAND_ADDRESS.PQP0[0x81]=0xa0140
PQP_INDIRECT_COMMAND_RD_DATA.PQP0[0x60]=0x19
PQP_INDIRECT_COMMAND_WR_DATA.PQP0[0x20]=0x100000000000000000000000000000019
PQP_INDIRECT_FORCE_BUBBLE.PQP0[0x83]=0x20019
PQP_INTERRUPT_MASK_REGISTER.PQP0[0x10]=0
PQP_INTERRUPT_REGISTER.PQP0[0x0]=0
PQP_INTERRUPT_REGISTER_TEST.PQP0[0x18]=0
PQP_INVALID_OTM.PQP0[0x101]=0x1ff
PQP_LCD_FBC_FIFO_IRDY_STATUS.PQP0[0x141]=0
PQP_LCD_FIFO_CONFIGURATION.PQP0[0x105]=0x100003212c4b1907d1f4
PQP_LCD_FIFO_STATUS.PQP0[0x145]=0
PQP_PACKET_SIZES_BINS_COUNTER(0).PQP0[0x11f]=0
PQP_PACKET_SIZES_BINS_COUNTER(1).PQP0[0x120]=0
PQP_PACKET_SIZES_BINS_COUNTER(2).PQP0[0x121]=0
PQP_PACKET_SIZES_BINS_COUNTER(3).PQP0[0x122]=0
PQP_PACKET_SIZES_BINS_COUNTER(4).PQP0[0x123]=0
PQP_PACKET_SIZES_BINS_COUNTER(5).PQP0[0x124]=0
PQP_PACKET_SIZES_BINS_COUNTER(6).PQP0[0x125]=0
PQP_PACKET_SIZES_BINS_COUNTER(7).PQP0[0x126]=0
PQP_PACKET_SIZES_BINS_COUNTER(8).PQP0[0x127]=0
PQP_PACKET_SIZES_BINS_COUNTER(9).PQP0[0x128]=0
PQP_PACKET_SIZES_BINS_COUNTER(10).PQP0[0x129]=0
PQP_PACKET_SIZES_BINS_COUNTER(11).PQP0[0x12a]=0
PQP_PACKET_SIZES_BINS_COUNTER(12).PQP0[0x12b]=0
PQP_PACKET_SIZES_BINS_COUNTER(13).PQP0[0x12c]=0
PQP_PACKET_SIZES_BINS_COUNTER(14).PQP0[0x12d]=0
PQP_PACKET_SIZES_BINS_COUNTER(15).PQP0[0x12e]=0x4e1dded0e
PQP_PACKET_SIZE_BINNING_CONFIGURATION.PQP0[0x10f]=0
PQP_PACKET_SIZE_BINNING_RANGE(0).PQP0[0x110]=0
PQP_PACKET_SIZE_BINNING_RANGE(1).PQP0[0x111]=0
PQP_PACKET_SIZE_BINNING_RANGE(2).PQP0[0x112]=0
PQP_PACKET_SIZE_BINNING_RANGE(3).PQP0[0x113]=0
PQP_PACKET_SIZE_BINNING_RANGE(4).PQP0[0x114]=0
PQP_PACKET_SIZE_BINNING_RANGE(5).PQP0[0x115]=0
PQP_PACKET_SIZE_BINNING_RANGE(6).PQP0[0x116]=0
PQP_PACKET_SIZE_BINNING_RANGE(7).PQP0[0x117]=0
PQP_PACKET_SIZE_BINNING_RANGE(8).PQP0[0x118]=0
PQP_PACKET_SIZE_BINNING_RANGE(9).PQP0[0x119]=0
PQP_PACKET_SIZE_BINNING_RANGE(10).PQP0[0x11a]=0
PQP_PACKET_SIZE_BINNING_RANGE(11).PQP0[0x11b]=0
PQP_PACKET_SIZE_BINNING_RANGE(12).PQP0[0x11c]=0
PQP_PACKET_SIZE_BINNING_RANGE(13).PQP0[0x11d]=0
PQP_PACKET_SIZE_BINNING_RANGE(14).PQP0[0x11e]=0
PQP_PD_SP_MAPPING.PQP0[0x10a]=0x1000000000000000000000000f0020200
PQP_PER_TXQ_MAX_BURST_FIX_ENABLE.PQP0[0x16f]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
PQP_PQP_DISCARD_MULTICAST_PACKET_COUNTER.PQP0[0x166]=0
PQP_PQP_DISCARD_UNICAST_PACKET_COUNTER.PQP0[0x164]=0x7fd02c
PQP_PQP_ENQ_BYTES_COUNTER.PQP0[0x159]=0x12e7fed61b44
PQP_PQP_ENQ_PACKET_COUNTER.PQP0[0x157]=0x1e1a68e08
PQP_PQP_LCD_MULTICAST_PACKET_COUNTER.PQP0[0x168]=0
PQP_PQP_MULTICAST_BYTES_COUNTER.PQP0[0x162]=0
PQP_PQP_MULTICAST_PACKET_COUNTER.PQP0[0x15e]=0
PQP_PQP_UNICAST_BYTES_COUNTER.PQP0[0x160]=0x12e7a2db789b
PQP_PQP_UNICAST_PACKET_COUNTER.PQP0[0x15c]=0x1e126bde3
PQP_REG_0041.PQP0[0x41]=0
PQP_REG_0098.PQP0[0x98]=0
PQP_REG_0108.PQP0[0x108]=0x2dace
PQP_REG_00A0.PQP0[0xa0]=0
PQP_REG_00C2.PQP0[0xc2]=0x10
PQP_REG_00C5.PQP0[0xc5]=0x78401
PQP_RESERVED_MTCD.PQP0[0xae]=0x30
PQP_RESERVED_MTCP.PQP0[0xad]=0x300000600000000
PQP_RESERVED_SPARE_0.PQP0[0x90]=0xffffffff
PQP_RESERVED_SPARE_1.PQP0[0x91]=0xffffffff
PQP_RESERVED_SPARE_2.PQP0[0x92]=0
PQP_RESERVED_SPARE_3.PQP0[0x93]=0
PQP_SBUS_BROADCAST_ID.PQP0[0x86]=0x7ff
PQP_SBUS_LAST_IN_CHAIN.PQP0[0x87]=0
PQP_SPECIAL_CLOCK_CONTROLS.PQP0[0xc1]=2
PQP_TXQ_MAX_BURST_THRESHOLD.PQP0[0x178]=0x400
PQP_VISIBILITY_PACKET_COUNTER.PQP0[0x16d]=0x1e1a68af3
PQP_VISIBILITY_PACKET_DEBUG.PQP0[0x16b]=0x942300800901
RQP_BUBBLE_TRIGGER.RQP0[0x13b]=0
RQP_CRPS_BUBBLE_REQ_CNTR.RQP0[0x13a]=0
RQP_DBG_PRP_SOP_DISCARD_MASK_DIS_CNT.RQP0[0x105]=0
RQP_DBG_SOURCE_MASK_DIS_CNT.RQP0[0x106]=0
RQP_ECC_1B_ERR_CNT.RQP0[0x94]=0x8000
RQP_ECC_2B_ERR_CNT.RQP0[0x96]=0x8000
RQP_ECC_ERR_1B_MONITOR_MEM_MASK.RQP0[0x9a]=0x3f
RQP_ECC_ERR_2B_MONITOR_MEM_MASK.RQP0[0x9c]=0x3f
RQP_ECC_INTERRUPT_REGISTER.RQP0[0x7]=0
RQP_ECC_INTERRUPT_REGISTER_MASK.RQP0[0x17]=0
RQP_ECC_INTERRUPT_REGISTER_TEST.RQP0[0x1f]=0
RQP_EMR_BUBBLE_CONFIGURATION.RQP0[0x137]=0x12c600020
RQP_EMR_DISCARDS_PACKET_COUNTER.RQP0[0x144]=0
RQP_EMR_GENERAL_CONFIGURATION.RQP0[0x130]=0
RQP_EMR_MC_HIGH_DISCARDS_COUNTER.RQP0[0x146]=0
RQP_EMR_MC_HIGH_PACKET_COUNTER.RQP0[0x140]=0
RQP_EMR_MC_LOW_DISCARDS_COUNTER.RQP0[0x148]=0
RQP_EMR_MC_LOW_PACKET_COUNTER.RQP0[0x142]=0
RQP_EMR_TDM_PACKET_COUNTER.RQP0[0x13c]=0
RQP_EMR_UNICAST_PACKET_COUNTER.RQP0[0x13e]=0x1e1a68e36
RQP_ENABLE_DYNAMIC_MEMORY_ACCESS.RQP0[0x84]=0
RQP_ERPP_BUBBLE_REQ_CNTR.RQP0[0x139]=0
RQP_GENERAL_RQP_CONFIG.RQP0[0x102]=1
RQP_GENERAL_RQP_DEBUG_CONFIG.RQP0[0x103]=0x4408050010
RQP_GTIMER_CONFIGURATION.RQP0[0x89]=2
RQP_GTIMER_CYCLE.RQP0[0x88]=0x23c34600
RQP_INDIRECT_COMMAND.RQP0[0x80]=0xe000002
RQP_INDIRECT_COMMAND_ADDRESS.RQP0[0x81]=0x50020
RQP_INDIRECT_COMMAND_RD_DATA.RQP0[0x60]=0x18
RQP_INDIRECT_COMMAND_WR_DATA.RQP0[0x20]=0x18
RQP_INDIRECT_FORCE_BUBBLE.RQP0[0x83]=0x20019
RQP_INTERRUPT_MASK_REGISTER.RQP0[0x10]=0
RQP_INTERRUPT_REGISTER.RQP0[0x0]=0
RQP_INTERRUPT_REGISTER_TEST.RQP0[0x18]=0
RQP_LAST_PRP_SOP_HEADER.RQP0[0x10a]=0x52001ac000190000445f0e0
RQP_LAST_PRP_TDM_HEADER.RQP0[0x107]=0
RQP_MC_PRIORITY_LOOKUP_TABLE.RQP0[0x12f]=0xffffffff
RQP_MULTICAST_FIFOS_ALMOST_FULL_CONFIG.RQP0[0x133]=0x50140280a05000
RQP_MULTICAST_FIFOS_CURR_LEVEL.RQP0[0x14a]=0
RQP_MULTICAST_FIFOS_DEPTH.RQP0[0x131]=0x3fd0000001
RQP_MULTICAST_FIFOS_FULL_CONFIG.RQP0[0x135]=0xc0305000
RQP_MULTICAST_FIFOS_MAX_LEVEL.RQP0[0x14c]=0x400
RQP_PCMI_0.RQP0[0xb0]=0x3b9aca00
RQP_PCMI_1.RQP0[0xb3]=0x3b9aca00
RQP_PCMI_2.RQP0[0xb6]=0x3b9aca00
RQP_PCMI_3.RQP0[0xb9]=0x3b9aca00
RQP_PCMI_4.RQP0[0xbc]=0x3b9aca00
RQP_PCMI_0_S.RQP0[0xb1]=0
RQP_PCMI_0_T.RQP0[0xb2]=0
RQP_PCMI_1_S.RQP0[0xb4]=0
RQP_PCMI_1_T.RQP0[0xb5]=0
RQP_PCMI_2_S.RQP0[0xb7]=0
RQP_PCMI_2_T.RQP0[0xb8]=0
RQP_PCMI_3_S.RQP0[0xba]=0
RQP_PCMI_3_T.RQP0[0xbb]=0
RQP_PCMI_4_S.RQP0[0xbd]=0
RQP_PCMI_4_T.RQP0[0xbe]=0
RQP_PRP_DEBUG_COUNTERS.RQP0[0x10d]=0x4e1a68e8900000004e1a68e89
RQP_PRP_DEBUG_INPUT_COUNTERS.RQP0[0x11d]=0x4e1a68e8a0000000000000000000000158f62ce1d0000000000000000
RQP_REG_0041.RQP0[0x41]=0
RQP_REG_0098.RQP0[0x98]=0
RQP_REG_00A0.RQP0[0xa0]=0
RQP_REG_00C2.RQP0[0xc2]=0x10
RQP_REG_00C3.RQP0[0xc3]=0
RQP_REG_00C5.RQP0[0xc5]=0x78001
RQP_REG_00C6.RQP0[0xc6]=0x13
RQP_RESERVED_MTCD.RQP0[0xae]=0x30
RQP_RESERVED_MTCP.RQP0[0xad]=0x300000600000000
RQP_RESERVED_SPARE_0.RQP0[0x90]=0xffffffff
RQP_RESERVED_SPARE_1.RQP0[0x91]=0xffffffff
RQP_RESERVED_SPARE_2.RQP0[0x92]=0
RQP_RESERVED_SPARE_3.RQP0[0x93]=0
RQP_RQP_BLOCK_INIT_STATUS.RQP0[0x100]=0
RQP_SBUS_BROADCAST_ID.RQP0[0x86]=0x7ff
RQP_SBUS_LAST_IN_CHAIN.RQP0[0x87]=0
RQP_SPECIAL_CLOCK_CONTROLS.RQP0[0xc1]=2
RQP_TDM_GENERAL_CONFIGURATION.RQP0[0x101]=0
SCH_ASSIGNED_CREDIT_CONFIGURATION.SCH0[0x123]=0x4a
SCH_ASSIGNED_CREDIT_CONFIGURATION_1.SCH0[0x127]=0x20
SCH_ATTEMPTTO_ACTIVATE_ASHAPERWITH_BAD_PARAMETERS.SCH0[0x192]=0x38
SCH_ATTEMPT_TO_ACTIVATE_BAD_FLOW_PARAMS.SCH0[0x191]=0x38
SCH_BFC_PARAMS.SCH0[0x15b]=0x30
SCH_CIR_SHAPERS_CONFIGURATION.SCH0[0x124]=0x1ff0030
SCH_CIR_SHAPERS_CONFIGURATION_1.SCH0[0x128]=0
SCH_CREDIT_COUNTER_CONFIGURATION_REG_1.SCH0[0x108]=0
SCH_CREDIT_COUNTER_CONFIGURATION_REG_2.SCH0[0x109]=0
SCH_DBG_CML_CREDIT_SCHEDULER_COUNTER_CONFIGURRATION.SCH0[0x10a]=0
SCH_DBG_CML_SCHEDULER_COUNTER.SCH0[0x18b]=0x505
SCH_DBG_CREDIT_COUNTER.SCH0[0x18a]=0xd511ef6b
SCH_DBG_DVS_CREDIT_COUNTER_CONFIGURATION.SCH0[0x13a]=0
SCH_DBG_DVS_FC_COUNTERS_CONFIGURATION.SCH0[0x13c]=0
SCH_DBG_DVS_FLOW_CONTROL_COUNTER.SCH0[0x19c]=0
SCH_DBG_DVS_LINK_STATUS.SCH0[0x19d]=0
SCH_DBG_DVS_RCI_COUNTER.SCH0[0x19b]=0xcaf12dc3
SCH_DBG_DVS_RCI_COUNTERS_CONFIGURATION.SCH0[0x13d]=0
SCH_DBG_SMP_MESSAGE_COUNTER.SCH0[0x18f]=0x94b6ea0d
SCH_DBG_SMP_MESSAGE_COUNTER_CONFIGURATION.SCH0[0x10b]=0
SCH_DELETE_MECHANISM_CONFIGURATION_REGISTER.SCH0[0x10d]=0x111f3ff7
SCH_DUMMY_REGISTER.SCH0[0x189]=0
SCH_DVS_CONFIG.SCH0[0x119]=0x40c00
SCH_DVS_CONFIG_2.SCH0[0x11a]=0x74
SCH_DVS_CREDIT_COUNTER.SCH0[0x19a]=0xd58c7b82
SCH_DVS_CREDIT_SHARE_CONFIGURATION.SCH0[0x131]=0x100400
SCH_DVS_NIF_CONFIG(0).SCH0[0x114]=0
SCH_DVS_NIF_CONFIG(1).SCH0[0x115]=0
SCH_DVS_NIF_CONFIG(2).SCH0[0x116]=0
SCH_DVS_NIF_CONFIG(3).SCH0[0x117]=0
SCH_DVS_NIF_CONFIG(4).SCH0[0x118]=0
SCH_DVS_WEIGHT_CONFIG(0).SCH0[0x11c]=0x10001
SCH_DVS_WEIGHT_CONFIG(1).SCH0[0x11d]=0x10001
SCH_DVS_WEIGHT_CONFIG(2).SCH0[0x11e]=0x10001
SCH_DVS_WEIGHT_CONFIG(3).SCH0[0x11f]=0x10001
SCH_DVS_WEIGHT_ENABLE.SCH0[0x120]=0xff
SCH_ECC_1B_ERR_CNT.SCH0[0x94]=0x8000
SCH_ECC_2B_ERR_CNT.SCH0[0x96]=0x8000
SCH_ECC_ERR_1B_MONITOR_MEM_MASK.SCH0[0x9a]=0x1fffffffffffff
SCH_ECC_ERR_2B_MONITOR_MEM_MASK.SCH0[0x9c]=0x1fffffffffffff
SCH_ECC_INTERRUPT_REGISTER.SCH0[0x7]=0
SCH_ECC_INTERRUPT_REGISTER_MASK.SCH0[0x17]=0
SCH_ECC_INTERRUPT_REGISTER_TEST.SCH0[0x1f]=0
SCH_ENABLE_DYNAMIC_MEMORY_ACCESS.SCH0[0x84]=0xff
SCH_FC_ENABLERS.SCH0[0x162]=0x1f
SCH_FORCE_PORT_FC_REGISTER(0).SCH0[0x146]=0
SCH_FORCE_PORT_FC_REGISTER(1).SCH0[0x147]=0
SCH_FORCE_PORT_FC_REGISTER(2).SCH0[0x148]=0
SCH_FORCE_PORT_FC_REGISTER(3).SCH0[0x149]=0
SCH_FORCE_PORT_FC_REGISTER(4).SCH0[0x14a]=0
SCH_FORCE_PORT_FC_REGISTER(5).SCH0[0x14b]=0
SCH_FORCE_PORT_FC_REGISTER(6).SCH0[0x14c]=0
SCH_FORCE_PORT_FC_REGISTER(7).SCH0[0x14d]=0
SCH_FORCE_PORT_FC_REGISTER(8).SCH0[0x14e]=0
SCH_FORCE_PORT_FC_REGISTER(9).SCH0[0x14f]=0
SCH_FORCE_PORT_FC_REGISTER(10).SCH0[0x150]=0
SCH_FORCE_PORT_FC_REGISTER(11).SCH0[0x151]=0
SCH_FORCE_PORT_FC_REGISTER(12).SCH0[0x152]=0
SCH_FORCE_PORT_FC_REGISTER(13).SCH0[0x153]=0
SCH_FORCE_PORT_FC_REGISTER(14).SCH0[0x154]=0
SCH_FORCE_PORT_FC_REGISTER(15).SCH0[0x155]=0
SCH_FSF_COMPOSITE_CONFIGURATION(0).SCH0[0x110]=0x3fff
SCH_GTIMER_CONFIGURATION.SCH0[0x89]=2
SCH_GTIMER_CYCLE.SCH0[0x88]=0x23c34600
SCH_HR_PRIORITY_MASK(0).SCH0[0x136]=0
SCH_HR_PRIORITY_MASK(1).SCH0[0x137]=0
SCH_HR_PRIORITY_MASK(2).SCH0[0x138]=0
SCH_HR_PRIORITY_MASK(3).SCH0[0x139]=0
SCH_INCORRECT_STATUS_MESSAGE.SCH0[0x18c]=0x100000000000e0008537
SCH_INDIRECT_COMMAND.SCH0[0x80]=0xe000002
SCH_INDIRECT_COMMAND_ADDRESS.SCH0[0x81]=0x104c09
SCH_INDIRECT_COMMAND_RD_DATA.SCH0[0x60]=0x1c8c1cf00
SCH_INDIRECT_COMMAND_WR_DATA.SCH0[0x20]=0xffff81effffe07bffff81effffe07bffff81effffe07bffff81effffe07b
SCH_INDIRECT_FORCE_BUBBLE.SCH0[0x83]=0x20019
SCH_INDIRECT_WR_MASK.SCH0[0x40]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
SCH_INGRESS_SHAPING_PORT_CONFIGURATION.SCH0[0x140]=0
SCH_INTERFACE_FC_MASK.SCH0[0x163]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
SCH_INTERRUPT_MASK_REGISTER.SCH0[0x10]=0
SCH_INTERRUPT_REGISTER.SCH0[0x0]=0x40
SCH_INTERRUPT_REGISTER_TEST.SCH0[0x18]=0
SCH_LAST_FLOW_RESTART_EVENT.SCH0[0x193]=0
SCH_LINKS_MASK(0).SCH0[0x134]=0xffffff
SCH_LINKS_MASK(1).SCH0[0x135]=0xffffff
SCH_LOW_RATE_FLOW_CONFIG_RANGE(0).SCH0[0x15f]=0
SCH_LOW_RATE_FLOW_CONFIG_RANGE(1).SCH0[0x160]=0
SCH_LOW_RATE_FLOW_CONFIG_RANGE(2).SCH0[0x161]=0
SCH_LOW_RATE_FLOW_EN_MASK(0).SCH0[0x15c]=0
SCH_LOW_RATE_FLOW_EN_MASK(1).SCH0[0x15d]=0
SCH_LOW_RATE_FLOW_EN_MASK(2).SCH0[0x15e]=0
SCH_MAX_PORT_QUEUE_SIZECOUNTER.SCH0[0x1a7]=0xc0038f
SCH_NIF_1P_PRIORITY_MODE_REGISTER.SCH0[0x16c]=0x1ffff
SCH_NIF_2P_PRIORITY_MODE_REGISTER.SCH0[0x16d]=0
SCH_NIF_4P_PRIORITY_MODE_REGISTER.SCH0[0x16e]=0
SCH_OOB_FC_CONFIGURATION_REGISTER.SCH0[0x156]=0x20fff0
SCH_OOB_FC_STATUS_REGISTER.SCH0[0x157]=0
SCH_PARITY_ERR_CNT.SCH0[0x98]=0x8000
SCH_PAR_ERR_MEM_MASK.SCH0[0xa0]=0x7ff
SCH_PCMI_0.SCH0[0xb0]=0x3b9aca00
SCH_PCMI_1.SCH0[0xb3]=0x3b9aca00
SCH_PCMI_2.SCH0[0xb6]=0x3b9aca00
SCH_PCMI_3.SCH0[0xb9]=0x3b9aca00
SCH_PCMI_4.SCH0[0xbc]=0x3b9aca00
SCH_PCMI_0_S.SCH0[0xb1]=0
SCH_PCMI_0_T.SCH0[0xb2]=0
SCH_PCMI_1_S.SCH0[0xb4]=0
SCH_PCMI_1_T.SCH0[0xb5]=0
SCH_PCMI_2_S.SCH0[0xb7]=0
SCH_PCMI_2_T.SCH0[0xb8]=0
SCH_PCMI_3_S.SCH0[0xba]=0
SCH_PCMI_3_T.SCH0[0xbb]=0
SCH_PCMI_4_S.SCH0[0xbd]=0
SCH_PCMI_4_T.SCH0[0xbe]=0
SCH_PIR_SHAPERS_CONFIGURATION.SCH0[0x125]=0x1ff0030
SCH_PIR_SHAPERS_CONFIGURATION_1.SCH0[0x129]=0
SCH_PS_1P_PRIORITY_MODE_REGISTER(0).SCH0[0x12b]=0
SCH_PS_1P_PRIORITY_MODE_REGISTER(1).SCH0[0x12c]=0
SCH_PS_2P_PRIORITY_MODE_REGISTER(0).SCH0[0x12d]=0x3bff
SCH_PS_2P_PRIORITY_MODE_REGISTER(1).SCH0[0x12e]=0
SCH_PS_4P_PRIORITY_MODE_REGISTER(0).SCH0[0x12f]=0
SCH_PS_4P_PRIORITY_MODE_REGISTER(1).SCH0[0x130]=0
SCH_PS_CALENDAR_SELECT.SCH0[0x121]=0x10
SCH_PS_PRIORITY_PROPAGATION_ENABLE(0).SCH0[0x16f]=0
SCH_PS_PRIORITY_PROPAGATION_ENABLE(1).SCH0[0x170]=0
SCH_RCI_BFC_PARAMS.SCH0[0x159]=0x77770
SCH_RCI_CREDIT_JITTER.SCH0[0x15a]=0
SCH_RCI_PARAMS.SCH0[0x158]=0x2b
SCH_REBOUNDED_CREDIT_CONFIGURATION.SCH0[0x122]=0x4a
SCH_REBOUNDED_CREDIT_CONFIGURATION_1.SCH0[0x126]=0x20
SCH_REG_0041.SCH0[0x41]=0
SCH_REG_00C2.SCH0[0xc2]=0x10
SCH_RESERVED_1.SCH0[0x102]=0xffff
SCH_RESERVED_2.SCH0[0x107]=0xc0d33a5
SCH_RESERVED_3.SCH0[0x10c]=0x26
SCH_RESERVED_4.SCH0[0x112]=0
SCH_RESERVED_5.SCH0[0x113]=0
SCH_RESERVED_6.SCH0[0x11b]=0x50000884
SCH_RESERVED_7.SCH0[0x12a]=0x3bf
SCH_RESERVED_8(0).SCH0[0x132]=0xffffff
SCH_RESERVED_8(1).SCH0[0x133]=0xffffff
SCH_RESERVED_9.SCH0[0x141]=0x3073b3c3
SCH_RESERVED_10.SCH0[0x142]=0x13f3f3f
SCH_RESERVED_11.SCH0[0x144]=0
SCH_RESERVED_12.SCH0[0x190]=0
SCH_RESERVED_13.SCH0[0x194]=0
SCH_RESERVED_14.SCH0[0x196]=0
SCH_RESERVED_15.SCH0[0x197]=0x96e000
SCH_RESERVED_16.SCH0[0x198]=1
SCH_RESERVED_17.SCH0[0x19f]=0
SCH_RESERVED_18.SCH0[0x1a0]=0
SCH_RESERVED_19.SCH0[0x1a1]=0
SCH_RESERVED_20.SCH0[0x1a2]=0
SCH_RESERVED_21.SCH0[0x1a3]=0
SCH_RESERVED_22.SCH0[0x1a4]=0
SCH_RESERVED_23.SCH0[0x1a5]=0
SCH_RESERVED_24.SCH0[0x1a8]=0xf63ff242
SCH_RESERVED_25.SCH0[0x1a9]=0x100281e08000707
SCH_RESERVED_MAX_PA.SCH0[0x104]=0
SCH_RESERVED_MAX_PB.SCH0[0x105]=0
SCH_RESERVED_MAX_PC.SCH0[0x106]=0
SCH_RESERVED_MTCD.SCH0[0xae]=0x30
SCH_RESERVED_MTCP.SCH0[0xad]=0x300000600000000
SCH_RESERVED_SHAPER_3.SCH0[0x103]=0x1f8
SCH_RESERVED_SPARE_0.SCH0[0x90]=0xffffffff
SCH_RESERVED_SPARE_1.SCH0[0x91]=0xffffffff
SCH_RESERVED_SPARE_2.SCH0[0x92]=0
SCH_RESERVED_SPARE_3.SCH0[0x93]=0
SCH_RETURNED_CREDITS_CFG_REGISTER.SCH0[0x145]=0x4000
SCH_SBUS_BROADCAST_ID.SCH0[0x86]=0x7ff
SCH_SBUS_LAST_IN_CHAIN.SCH0[0x87]=0
SCH_SCHEDULER_CONFIGURATION_REGISTER.SCH0[0x100]=0x2450420
SCH_SCHEDULER_NOT_VALID.SCH0[0x1a6]=0
SCH_SCH_FABRIC_MULTICAST_PORT_CONFIGURATION_REGISTER_0.SCH0[0x13e]=0
SCH_SCH_FABRIC_MULTICAST_PORT_CONFIGURATION_REGISTER_1.SCH0[0x13f]=0
SCH_SCL_SMP_MESSAGES.SCH0[0x195]=0xb831
SCH_SELECT_FLOW_TO_QUEUE_MAPPING(0).SCH0[0x111]=0x800
SCH_SHAPER_CONFIGURATION_REGISTER_1.SCH0[0x101]=0x180
SCH_SHARED_BUCKET_2_ACT_BITMAP.SCH0[0x171]=0x80c02030080c0203
SCH_SHARED_BUCKET_2_ACT_BITMAP_SWITCHED.SCH0[0x173]=0xc04030100c040301
SCH_SHARED_BUCKET_2_INC_BITMAP.SCH0[0x17d]=0xc04030100c040301
SCH_SHARED_BUCKET_2_INC_BITMAP_SWITCHED.SCH0[0x17f]=0x80c02030080c0203
SCH_SHARED_BUCKET_4_ACT_BITMAP.SCH0[0x175]=0x80c0e0f0080c0e0f
SCH_SHARED_BUCKET_4_ACT_BITMAP_SWITCHED.SCH0[0x177]=0xf07030100f070301
SCH_SHARED_BUCKET_4_INC_BITMAP.SCH0[0x181]=0xf07030100f070301
SCH_SHARED_BUCKET_4_INC_BITMAP_SWITCHED.SCH0[0x183]=0x80c0e0f0080c0e0f
SCH_SHARED_BUCKET_8_ACT_BITMAP.SCH0[0x179]=0x80c0e0f0f8fcfeff
SCH_SHARED_BUCKET_8_ACT_BITMAP_SWITCHED.SCH0[0x17b]=0xff7f3f1f0f070301
SCH_SHARED_BUCKET_8_INC_BITMAP.SCH0[0x185]=0xff7f3f1f0f070301
SCH_SHARED_BUCKET_8_INC_BITMAP_SWITCHED.SCH0[0x187]=0x80c0e0f0f8fcfeff
SCH_SMP_BACK_UP_MESSAGES.SCH0[0x143]=0x10ff
SCH_SPECIAL_CLOCK_CONTROLS.SCH0[0xc1]=2
SCH_SWITCH_CIR_EIR_IN_DUAL_SHAPERS(0).SCH0[0x10e]=0x35ff
SCH_SYSTEM_RED_CONFIGURATION.SCH0[0x10f]=0
SIF_AUTO_DOC_NAME_0(0).SIF0[0x122]=0
SIF_AUTO_DOC_NAME_1(0).SIF0[0x123]=0
SIF_AUTO_DOC_NAME_2(0).SIF0[0x124]=0
SIF_AUTO_DOC_NAME_3(0).SIF0[0x125]=0
SIF_AUTO_DOC_NAME_3(1).SIF0[0x126]=0
SIF_AUTO_DOC_NAME_4(0).SIF0[0x127]=0
SIF_AUTO_DOC_NAME_4(1).SIF0[0x128]=0
SIF_AUTO_DOC_NAME_5(0).SIF0[0x12b]=0xc
SIF_AUTO_DOC_NAME_5(1).SIF0[0x12c]=0xc
SIF_AUTO_DOC_NAME_7(0).SIF0[0x137]=0x200000000
SIF_AUTO_DOC_NAME_7(1).SIF0[0x138]=0x200000000
SIF_AUTO_DOC_NAME_7(2).SIF0[0x139]=0x200000000
SIF_AUTO_DOC_NAME_8(0).SIF0[0x13a]=0x18000000
SIF_AUTO_DOC_NAME_8(1).SIF0[0x13b]=0x18000000
SIF_AUTO_DOC_NAME_9(0).SIF0[0x13c]=0x107
SIF_AUTO_DOC_NAME_9(1).SIF0[0x13d]=0x107
SIF_BILLING_INPUT_FC_CTR(0).SIF0[0x134]=0
SIF_BILLING_INPUT_FC_CTR(1).SIF0[0x135]=0
SIF_BILLING_INPUT_FC_CTR(2).SIF0[0x136]=0
SIF_BILLING_OUTPUT_FC_CTR(0).SIF0[0x131]=0
SIF_BILLING_OUTPUT_FC_CTR(1).SIF0[0x132]=0
SIF_BILLING_OUTPUT_FC_CTR(2).SIF0[0x133]=0
SIF_ECC_1B_ERR_CNT.SIF0[0x94]=0
SIF_ECC_2B_ERR_CNT.SIF0[0x96]=0
SIF_ECC_ERR_1B_MONITOR_MEM_MASK.SIF0[0x9a]=0x3fff
SIF_ECC_ERR_2B_MONITOR_MEM_MASK.SIF0[0x9c]=0x3fff
SIF_ECC_INTERRUPT_REGISTER.SIF0[0x7]=0
SIF_ECC_INTERRUPT_REGISTER_MASK.SIF0[0x17]=0
SIF_ECC_INTERRUPT_REGISTER_TEST.SIF0[0x1f]=0
SIF_ENABLERS.SIF0[0x12a]=0
SIF_GTIMER_CONFIGURATION.SIF0[0x89]=0
SIF_GTIMER_CYCLE.SIF0[0x88]=0x3b9aca00
SIF_INIT.SIF0[0x109]=0x1fd
SIF_INTERRUPT_MASK_REGISTER.SIF0[0x10]=0
SIF_INTERRUPT_REGISTER.SIF0[0x0]=0
SIF_INTERRUPT_REGISTER_TEST.SIF0[0x18]=0
SIF_QSIZE_INPUT_FC_CTR(0).SIF0[0x12f]=0
SIF_QSIZE_INPUT_FC_CTR(1).SIF0[0x130]=0
SIF_QSIZE_OUTPUT_FC_CTR(0).SIF0[0x12d]=0
SIF_QSIZE_OUTPUT_FC_CTR(1).SIF0[0x12e]=0
SIF_REG_00C2.SIF0[0xc2]=0x10
SIF_RESERVED_MTCD.SIF0[0xae]=0x30
SIF_RESERVED_MTCP.SIF0[0xad]=0x300000600000000
SIF_RESERVED_SPARE_0.SIF0[0x90]=0xffffffff
SIF_RESERVED_SPARE_1.SIF0[0x91]=0xffffffff
SIF_RESERVED_SPARE_2.SIF0[0x92]=0
SIF_RESERVED_SPARE_3.SIF0[0x93]=0
SIF_SBUS_BROADCAST_ID.SIF0[0x86]=0x7ff
SIF_SBUS_LAST_IN_CHAIN.SIF0[0x87]=0
SIF_SPECIAL_CLOCK_CONTROLS.SIF0[0xc1]=2
SIF_ST_BILL_INPUT_PORT_SETTINGS(0).SIF0[0x10a]=0x400000
SIF_ST_BILL_INPUT_PORT_SETTINGS(1).SIF0[0x10b]=0x400000
SIF_ST_BILL_INPUT_PORT_SETTINGS(2).SIF0[0x10c]=0x400000
SIF_ST_BILL_OPCODE_ERR_INTERRUPT_REGISTER.SIF0[0x106]=0
SIF_ST_BILL_OPCODE_ERR_INTERRUPT_REGISTER_MASK.SIF0[0x107]=0
SIF_ST_BILL_OPCODE_ERR_INTERRUPT_REGISTER_TEST.SIF0[0x108]=0
SIF_ST_BILL_RPRT_CTR(0).SIF0[0x113]=0
SIF_ST_BILL_RPRT_CTR(1).SIF0[0x114]=0
SIF_ST_BILL_RPRT_CTR(2).SIF0[0x115]=0
SIF_ST_BILL_RPRT_DROP_CTR(0).SIF0[0x116]=0
SIF_ST_BILL_RPRT_DROP_CTR(1).SIF0[0x117]=0
SIF_ST_BILL_RPRT_DROP_CTR(2).SIF0[0x118]=0
SIF_ST_BILL_RPRT_DROP_ECC_CTR(0).SIF0[0x119]=0
SIF_ST_BILL_RPRT_DROP_ECC_CTR(1).SIF0[0x11a]=0
SIF_ST_BILL_RPRT_DROP_ECC_CTR(2).SIF0[0x11b]=0
SIF_ST_PORT_FC_SETTINGS(0).SIF0[0x111]=0
SIF_ST_PORT_FC_SETTINGS(1).SIF0[0x112]=0
SIF_ST_PORT_SETTINGS(0).SIF0[0x10f]=0xffff0f50030000000000000000000000000000000
SIF_ST_PORT_SETTINGS(1).SIF0[0x110]=0xffff0f50030000000000000000000000000000000
SIF_ST_QSIZE_RPRT_CTR(0).SIF0[0x11c]=0
SIF_ST_QSIZE_RPRT_CTR(1).SIF0[0x11d]=0
SIF_ST_QSIZE_RPRT_DROP_CTR(0).SIF0[0x11e]=0
SIF_ST_QSIZE_RPRT_DROP_CTR(1).SIF0[0x11f]=0
SIF_ST_QSIZE_RPRT_DROP_ECC_CTR(0).SIF0[0x120]=0
SIF_ST_QSIZE_RPRT_DROP_ECC_CTR(1).SIF0[0x121]=0
SIF_ST_QSIZE_SETTINGS.SIF0[0x129]=0
SIF_ST_Q_SIZE_INPUT_PORT_FC_SETTINGS(0).SIF0[0x10d]=0
SIF_ST_Q_SIZE_INPUT_PORT_FC_SETTINGS(1).SIF0[0x10e]=0
SIF_ST_RPRT_BILLING_RX_FIFO_ERR_INTERRUPT_REGISTER.SIF0[0x100]=0
SIF_ST_RPRT_BILLING_RX_FIFO_ERR_INTERRUPT_REGISTER_MASK.SIF0[0x101]=0
SIF_ST_RPRT_BILLING_RX_FIFO_ERR_INTERRUPT_REGISTER_TEST.SIF0[0x102]=0
SIF_ST_RPRT_QSIZE_RX_FIFO_ERR_INTERRUPT_REGISTER.SIF0[0x103]=0
SIF_ST_RPRT_QSIZE_RX_FIFO_ERR_INTERRUPT_REGISTER_MASK.SIF0[0x104]=0
SIF_ST_RPRT_QSIZE_RX_FIFO_ERR_INTERRUPT_REGISTER_TEST.SIF0[0x105]=0
SPB_ALMOST_FULL_SRAM_REJECT_COUNTER(0).SPB0[0x137]=0
SPB_ALMOST_FULL_SRAM_REJECT_COUNTER(1).SPB0[0x13b]=0
SPB_ALMOST_FULL_SRAM_REJECT_COUNTER(2).SPB0[0x13f]=0
SPB_ALMOST_FULL_SRAM_REJECT_GLB_COUNTER.SPB0[0x143]=0
SPB_AUTO_DOC_NAME_19.SPB0[0x10c]=0
SPB_BRC_DEBUG.SPB0[0x14a]=0xc208595f6300000004009547200000e93500400
SPB_BRC_DEBUG_2.SPB0[0x14b]=0x3e0000000000880000
SPB_BRC_S_2D_DEBUG.SPB0[0x14d]=0
SPB_BRC_S_2F_DEBUG.SPB0[0x14c]=0xe22c9353f17c0000580
SPB_COUNTERS_REASSEMBLYCONTEXTS.SPB0[0x115]=0x3020100
SPB_CPU_REQUEST_REGISTER.SPB0[0x110]=0
SPB_DISCARDED_BYTES_CNT(0).SPB0[0x12e]=0
SPB_DISCARDED_BYTES_CNT(1).SPB0[0x130]=0
SPB_DISCARDED_BYTES_CNT(2).SPB0[0x132]=0
SPB_DISCARDED_BYTES_CNT(3).SPB0[0x134]=0
SPB_DISCARDED_PACKETS_CNT(0).SPB0[0x11e]=0
SPB_DISCARDED_PACKETS_CNT(1).SPB0[0x120]=0
SPB_DISCARDED_PACKETS_CNT(2).SPB0[0x122]=0
SPB_DISCARDED_PACKETS_CNT(3).SPB0[0x124]=0
SPB_DROP_DESTINATION_CONFIGURATION.SPB0[0x10f]=0x1fffff
SPB_DYNAMIC_CONFIGURATION.SPB0[0x109]=0x61
SPB_ECC_1B_ERR_CNT.SPB0[0x94]=0
SPB_ECC_2B_ERR_CNT.SPB0[0x96]=0
SPB_ECC_ERR_1B_MONITOR_MEM_MASK.SPB0[0x9a]=0x3ffffffffff
SPB_ECC_ERR_2B_MONITOR_MEM_MASK.SPB0[0x9c]=0x3ffffffffff
SPB_ECC_INTERRUPT_REGISTER.SPB0[0x7]=0
SPB_ECC_INTERRUPT_REGISTER_MASK.SPB0[0x17]=0
SPB_ECC_INTERRUPT_REGISTER_TEST.SPB0[0x1f]=0
SPB_ENABLE_DYNAMIC_MEMORY_ACCESS.SPB0[0x84]=0x1fffff
SPB_FIFO_INTERRUPT_REGISTER.SPB0[0x104]=0
SPB_FIFO_INTERRUPT_REGISTER_MASK.SPB0[0x105]=0
SPB_FIFO_INTERRUPT_REGISTER_TEST.SPB0[0x106]=0
SPB_FORCE_CRC_ERROR.SPB0[0x10e]=0
SPB_FULL_SRAM_REJECT_COUNTER.SPB0[0x136]=0
SPB_GTIMER_CONFIGURATION.SPB0[0x89]=0
SPB_GTIMER_CYCLE.SPB0[0x88]=0x3b9aca00
SPB_INDIRECT_COMMAND.SPB0[0x80]=0xe000002
SPB_INDIRECT_COMMAND_ADDRESS.SPB0[0x81]=0x100
SPB_INDIRECT_COMMAND_RD_DATA.SPB0[0x60]=0x2420000000000000000000000000000008000000
SPB_INDIRECT_COMMAND_WR_DATA.SPB0[0x20]=0
SPB_INDIRECT_FORCE_BUBBLE.SPB0[0x83]=0x20019
SPB_INTERRUPT_MASK_REGISTER.SPB0[0x10]=0
SPB_INTERRUPT_REGISTER.SPB0[0x0]=0
SPB_INTERRUPT_REGISTER_TEST.SPB0[0x18]=0
SPB_LAST_LEARN_INFO_RPRT.SPB0[0x14f]=0x29895a68031c24600b000040445c001
SPB_LAST_REAS_REPORT.SPB0[0x145]=0x94808000002e4fd1800000003c0090000001000000638020000000000000000000000000000000000000000000000000000001000000000000000000000006c00010307a740
SPB_LAST_TX_RPRT.SPB0[0x14e]=0x1148e010000030
SPB_LEARN_INFO_COUNTER.SPB0[0x144]=0xec000000ec
SPB_OCB_STATUS.SPB0[0x114]=0x80007efe7ffa
SPB_OW_PP_PORT_WITH_RSM_CONTEXT.SPB0[0x111]=0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
SPB_PACKET_REJECT_TH.SPB0[0x10a]=0x190064012c
SPB_PARITY_ERR_CNT.SPB0[0x98]=0
SPB_PAR_ERR_MEM_MASK.SPB0[0xa0]=1
SPB_PEC_DEBUG.SPB0[0x146]=0x76740
SPB_PEC_DEBUG_2.SPB0[0x147]=0xd75339474287a9d0000d7533d7533
SPB_PEC_STATUS.SPB0[0x113]=0x3400000000100000
SPB_PTC_S_2D_DEBUG.SPB0[0x149]=0
SPB_PTC_S_2F_DEBUG.SPB0[0x148]=0x24000000000000000003a4e4ba4e4ab8e1c0000000000300000007ffffc00010000030148fe60b9fa200
SPB_REASSEMBLY_ERRORS.SPB0[0x112]=0x7ff
SPB_REASSEMBLY_INTERRUPT_REGISTER.SPB0[0x101]=0x100
SPB_REASSEMBLY_INTERRUPT_REGISTER_MASK.SPB0[0x102]=0
SPB_REASSEMBLY_INTERRUPT_REGISTER_TEST.SPB0[0x103]=0
SPB_REASSEMBLY_TIMEOUT.SPB0[0x10b]=0x2000
SPB_RECEIVED_BYTES_CNT(0).SPB0[0x126]=0x15f6673fc
SPB_RECEIVED_BYTES_CNT(1).SPB0[0x128]=0xe5abc2c73b
SPB_RECEIVED_BYTES_CNT(2).SPB0[0x12a]=0x413a55b476
SPB_RECEIVED_BYTES_CNT(3).SPB0[0x12c]=0x10ad33e0d1a
SPB_RECEIVED_PACKETS_CNT(0).SPB0[0x116]=0x3013811
SPB_RECEIVED_PACKETS_CNT(1).SPB0[0x118]=0xa2878667
SPB_RECEIVED_PACKETS_CNT(2).SPB0[0x11a]=0x29ad33ab
SPB_RECEIVED_PACKETS_CNT(3).SPB0[0x11c]=0x907d7aa8
SPB_REG_0041.SPB0[0x41]=0
SPB_REG_00C2.SPB0[0xc2]=0x10
SPB_REG_00C5.SPB0[0xc5]=0x786df
SPB_RESERVED_MTCD.SPB0[0xae]=0x30
SPB_RESERVED_MTCP.SPB0[0xad]=0x300000600000000
SPB_RESERVED_SPARE_0.SPB0[0x90]=0xffffffff
SPB_RESERVED_SPARE_1.SPB0[0x91]=0xffffffff
SPB_RESERVED_SPARE_2.SPB0[0x92]=0
SPB_RESERVED_SPARE_3.SPB0[0x93]=0
SPB_RESET_STATUS_REGISTER.SPB0[0x107]=0
SPB_SBUS_BROADCAST_ID.SPB0[0x86]=0x7ff
SPB_SBUS_LAST_IN_CHAIN.SPB0[0x87]=0
SPB_SPECIAL_CLOCK_CONTROLS.SPB0[0xc1]=2
SPB_STATIC_CONFIGURATION.SPB0[0x108]=0x1c080a1
SPB_S_2D_RPC_CFG(0).SPB0[0x153]=0
SPB_S_2D_RPC_CFG(1).SPB0[0x154]=0
SPB_S_2F_RPC_CFG(0).SPB0[0x150]=0
SPB_S_2F_RPC_CFG(1).SPB0[0x151]=0
SPB_S_2F_RPC_CFG(2).SPB0[0x152]=0x2800
SPB_TIMEOUT_REG.SPB0[0x10d]=0
SQM_BUNDLE_DEQ_CTR.SQM0[0x207]=0x4e1a693cb
SQM_DCC_NO_ACTIVE_READS_CTR.SQM0[0x212]=0xe60d1ed1
SQM_DCC_READ_ACTIVE_CTR_STATUS.SQM0[0x211]=0
SQM_DEQ_DRAM_BUNDLE_SETTINGS.SQM0[0x202]=0x18102f0bc20080180400c0
SQM_ECC_1B_ERR_CNT.SQM0[0x94]=0x8000
SQM_ECC_2B_ERR_CNT.SQM0[0x96]=0x8000
SQM_ECC_ERR_1B_MONITOR_MEM_MASK.SQM0[0x9a]=0xff
SQM_ECC_ERR_2B_MONITOR_MEM_MASK.SQM0[0x9c]=0xff
SQM_ECC_INTERRUPT_REGISTER.SQM0[0x7]=0
SQM_ECC_INTERRUPT_REGISTER_MASK.SQM0[0x17]=0
SQM_ECC_INTERRUPT_REGISTER_TEST.SQM0[0x1f]=0
SQM_ENABLERS.SQM0[0x201]=3
SQM_ENABLE_DYNAMIC_MEMORY_ACCESS.SQM0[0x84]=0
SQM_GTIMER_CONFIGURATION.SQM0[0x89]=2
SQM_GTIMER_CYCLE.SQM0[0x88]=0x23c34600
SQM_INDIRECT_COMMAND.SQM0[0x80]=0xe000002
SQM_INDIRECT_COMMAND_ADDRESS.SQM0[0x81]=0x81000
SQM_INDIRECT_COMMAND_RD_DATA.SQM0[0x60]=0x2786bff0bf4de7ffff2afefeff2be7bbcf8effefafeefabfb3ff7fffffd
SQM_INDIRECT_COMMAND_WR_DATA.SQM0[0x20]=0
SQM_INDIRECT_FORCE_BUBBLE.SQM0[0x83]=0x20019
SQM_INIT_ON.SQM0[0x200]=0
SQM_INTERNAL_SETTINGS.SQM0[0x204]=0x30084c0212810
SQM_INTERRUPT_MASK_REGISTER.SQM0[0x10]=0
SQM_INTERRUPT_REGISTER.SQM0[0x0]=0
SQM_INTERRUPT_REGISTER_TEST.SQM0[0x18]=0
SQM_LAST_DEQ_CMD.SQM0[0x20c]=0x7200000000000462
SQM_LAST_ENQ_CMD.SQM0[0x20b]=0x100798003ffffe00d6410408c0
SQM_PDB_ALLOCATE_NRDY_CTR.SQM0[0x215]=0
SQM_PDB_RELEASE_NRDY_CTR.SQM0[0x216]=0
SQM_PDM_RD_ACCESS_DROP_CTR.SQM0[0x20a]=0x4a57b
SQM_PDM_RD_ACCESS_VALID_CTR.SQM0[0x209]=0x4e1a693f5
SQM_PDM_WR_ACCESS_VALID_CTR.SQM0[0x208]=0x4e1a693f6
SQM_PKT_DEQ_CTR.SQM0[0x206]=0x4e1a693f8
SQM_PKT_ENQ_CTR.SQM0[0x205]=0x4e1a693f8
SQM_REG_0041.SQM0[0x41]=0
SQM_REG_0203.SQM0[0x203]=0
SQM_REG_0217.SQM0[0x217]=0
SQM_REG_0218.SQM0[0x218]=0x80000
SQM_REG_0219.SQM0[0x219]=0x80000
SQM_REG_0220.SQM0[0x220]=0
SQM_REG_00C2.SQM0[0xc2]=0x10
SQM_REG_00C7.SQM0[0xc7]=3
SQM_REG_021A.SQM0[0x21a]=0
SQM_REG_021B.SQM0[0x21b]=0
SQM_REG_021C.SQM0[0x21c]=0
SQM_REG_021D.SQM0[0x21d]=0
SQM_REG_021E.SQM0[0x21e]=0
SQM_REG_021F.SQM0[0x21f]=0
SQM_RESERVED_MTCD.SQM0[0xae]=0x30
SQM_RESERVED_MTCP.SQM0[0xad]=0x300000600000000
SQM_RESERVED_SPARE_0.SQM0[0x90]=0xffffffff
SQM_RESERVED_SPARE_1.SQM0[0x91]=0xffffffff
SQM_RESERVED_SPARE_2.SQM0[0x92]=0
SQM_RESERVED_SPARE_3.SQM0[0x93]=0
SQM_SBUS_BROADCAST_ID.SQM0[0x86]=0x7ff
SQM_SBUS_LAST_IN_CHAIN.SQM0[0x87]=0
SQM_SPECIAL_CLOCK_CONTROLS.SQM0[0xc1]=2
SQM_TO_DRAM_IQM_PKT_TX_NRDY_CTR.SQM0[0x213]=0
SQM_TO_DRAM_TX_BUNDLE_FIFO_MAX_STATUS.SQM0[0x210]=0
SQM_TO_DRAM_TX_PD_FIFO_MAX_STATUS.SQM0[0x20d]=0
SQM_TO_FABRIC_IQM_PKT_TX_NRDY_CTR.SQM0[0x214]=0
SQM_TO_FABRIC_TX_BUNDLE_FIFO_MAX_STATUS.SQM0[0x20f]=5
SQM_TO_FABRIC_TX_PD_FIFO_MAX_STATUS.SQM0[0x20e]=5
SQM_TX_FIFO_ERR_INTERRUPT_MASK_REGISTER.SQM0[0x111]=0
SQM_TX_FIFO_ERR_INTERRUPT_REGISTER.SQM0[0x110]=0
SQM_TX_FIFO_ERR_INTERRUPT_REGISTER_TEST.SQM0[0x112]=0
TCAM_ECC_1B_ERR_CNT.TCAM0[0x94]=0
TCAM_ECC_2B_ERR_CNT.TCAM0[0x96]=0
TCAM_ECC_ERR_1B_MONITOR_MEM_MASK.TCAM0[0x9a]=0xffffffff
TCAM_ECC_ERR_2B_MONITOR_MEM_MASK.TCAM0[0x9c]=0xffffffff
TCAM_ECC_INTERRUPT_REGISTER.TCAM0[0x7]=0
TCAM_ECC_INTERRUPT_REGISTER_MASK.TCAM0[0x17]=0
TCAM_ECC_INTERRUPT_REGISTER_TEST.TCAM0[0x1f]=0
TCAM_ENABLE_DYNAMIC_MEMORY_ACCESS.TCAM0[0x84]=0xffffffffffff
TCAM_GTIMER_CONFIGURATION.TCAM0[0x89]=0
TCAM_GTIMER_CYCLE.TCAM0[0x88]=0x3b9aca00
TCAM_INDIRECT_COMMAND.TCAM0[0x80]=0xe000002
TCAM_INDIRECT_COMMAND_ADDRESS.TCAM0[0x81]=0x1002847
TCAM_INDIRECT_COMMAND_RD_DATA.TCAM0[0x60]=0
TCAM_INDIRECT_COMMAND_WR_DATA.TCAM0[0x20]=0x3eef3c0003fc000002f6f9fcff007ff9fcf7fffffe110c00000000000010906030000000603080000013
TCAM_INDIRECT_FORCE_BUBBLE.TCAM0[0x83]=0x20019
TCAM_INDIRECT_WR_MASK.TCAM0[0x40]=0xff
TCAM_INTERRUPT_MASK_REGISTER.TCAM0[0x10]=0
TCAM_INTERRUPT_REGISTER.TCAM0[0x0]=8
TCAM_INTERRUPT_REGISTER_TEST.TCAM0[0x18]=0
TCAM_PCMI_0.TCAM0[0xb0]=0x3b9aca00
TCAM_PCMI_1.TCAM0[0xb3]=0x3b9aca00
TCAM_PCMI_2.TCAM0[0xb6]=0x3b9aca00
TCAM_PCMI_3.TCAM0[0xb9]=0x3b9aca00
TCAM_PCMI_4.TCAM0[0xbc]=0x3b9aca00
TCAM_PCMI_0_S.TCAM0[0xb1]=0
TCAM_PCMI_0_T.TCAM0[0xb2]=0
TCAM_PCMI_1_S.TCAM0[0xb4]=0
TCAM_PCMI_1_T.TCAM0[0xb5]=0
TCAM_PCMI_2_S.TCAM0[0xb7]=0
TCAM_PCMI_2_T.TCAM0[0xb8]=0
TCAM_PCMI_3_S.TCAM0[0xba]=0
TCAM_PCMI_3_T.TCAM0[0xbb]=0
TCAM_PCMI_4_S.TCAM0[0xbd]=0
TCAM_PCMI_4_T.TCAM0[0xbe]=0
TCAM_REG_0041.TCAM0[0x41]=0
TCAM_REG_0207.TCAM0[0x207]=0
TCAM_REG_0211.TCAM0[0x211]=0
TCAM_REG_00C2.TCAM0[0xc2]=0x10
TCAM_REG_020A.TCAM0[0x20a]=0
TCAM_REG_020C.TCAM0[0x20c]=0
TCAM_REG_020F.TCAM0[0x20f]=0
TCAM_RESERVED_MTCD.TCAM0[0xae]=0x30
TCAM_RESERVED_MTCP.TCAM0[0xad]=0x300000600000000
TCAM_RESERVED_SPARE_0.TCAM0[0x90]=0xffffffff
TCAM_RESERVED_SPARE_1.TCAM0[0x91]=0xffffffff
TCAM_RESERVED_SPARE_2.TCAM0[0x92]=0
TCAM_RESERVED_SPARE_3.TCAM0[0x93]=0
TCAM_SBUS_BROADCAST_ID.TCAM0[0x86]=0x7ff
TCAM_SBUS_LAST_IN_CHAIN.TCAM0[0x87]=0
TCAM_SPECIAL_CLOCK_CONTROLS.TCAM0[0xc1]=2
TCAM_TCAM_ACCESS_COUNTER.TCAM0[0x219]=0
TCAM_TCAM_ACCESS_COUNTER_SELECTOR.TCAM0[0x218]=0
TCAM_TCAM_BANK_BLOCK_OWNER.TCAM0[0x205]=0
TCAM_TCAM_ECC_FIX_EN.TCAM0[0x214]=1
TCAM_TCAM_INTERFACE_ACCESS_BITMAP.TCAM0[0x217]=0x14c3f
TCAM_TCAM_MANAGER_0.TCAM0[0x200]=0
TCAM_TCAM_MANAGER_1.TCAM0[0x201]=0
TCAM_TCAM_MATCH_BITMAP.TCAM0[0x216]=0x33
TCAM_TCAM_MOVE_ECC_FAILURE.TCAM0[0x21e]=0
TCAM_TCAM_PROTECTION_ERROR.TCAM0[0x206]=0
TCAM_TCAM_PROTECTION_MACHINE_CONFIGURATION.TCAM0[0x212]=0x1fffe000002
TCAM_TCAM_PROTECTION_TRIGGER.TCAM0[0x203]=0
TCAM_TCAM_QUERY_FAILURE.TCAM0[0x21a]=0x30000000000000000000000003
TCAM_TCAM_RESET_BLOCK_BITMAP.TCAM0[0x204]=0
TCAM_TCAM_VTT_IF_SELECT.TCAM0[0x215]=0
TDU_ADDRESS_TRANSLATION_CONFIG.TDU0[0x15e]=0
TDU_ADDRESS_TRANSLATION_MATRIX(0).TDU0[0x15f]=0x800000
TDU_ADDRESS_TRANSLATION_MATRIX(1).TDU0[0x160]=0x21
TDU_ADDRESS_TRANSLATION_MATRIX(2).TDU0[0x161]=0x200002
TDU_ADDRESS_TRANSLATION_MATRIX(3).TDU0[0x162]=0x400004
TDU_ADDRESS_TRANSLATION_MATRIX(4).TDU0[0x163]=0x4008
TDU_ADDRESS_TRANSLATION_MATRIX(5).TDU0[0x164]=0x41
TDU_ADDRESS_TRANSLATION_MATRIX(6).TDU0[0x165]=0x8008
TDU_ADDRESS_TRANSLATION_MATRIX(7).TDU0[0x166]=0x10004
TDU_ADDRESS_TRANSLATION_MATRIX(8).TDU0[0x167]=0x20002
TDU_ADDRESS_TRANSLATION_MATRIX(9).TDU0[0x168]=0x11
TDU_ADDRESS_TRANSLATION_MATRIX(10).TDU0[0x169]=0x80
TDU_ADDRESS_TRANSLATION_MATRIX(11).TDU0[0x16a]=0x100
TDU_ADDRESS_TRANSLATION_MATRIX(12).TDU0[0x16b]=0x200
TDU_ADDRESS_TRANSLATION_MATRIX(13).TDU0[0x16c]=0x400
TDU_ADDRESS_TRANSLATION_MATRIX(14).TDU0[0x16d]=0x800
TDU_ADDRESS_TRANSLATION_MATRIX(15).TDU0[0x16e]=0x1000
TDU_ADDRESS_TRANSLATION_MATRIX(16).TDU0[0x16f]=0x2000
TDU_ADDRESS_TRANSLATION_MATRIX(17).TDU0[0x170]=1
TDU_ADDRESS_TRANSLATION_MATRIX(18).TDU0[0x171]=2
TDU_ADDRESS_TRANSLATION_MATRIX(19).TDU0[0x172]=4
TDU_ADDRESS_TRANSLATION_MATRIX(20).TDU0[0x173]=8
TDU_ADDRESS_TRANSLATION_MATRIX(21).TDU0[0x174]=0
TDU_ADDRESS_TRANSLATION_MATRIX(22).TDU0[0x175]=0
TDU_ADDRESS_TRANSLATION_MATRIX(23).TDU0[0x176]=0
TDU_ADDRESS_TRANSLATION_MATRIX(24).TDU0[0x177]=0
TDU_ADDRESS_TRANSLATION_MATRIX(25).TDU0[0x178]=0
TDU_ADDRESS_TRANSLATION_MATRIX(26).TDU0[0x179]=0x80000
TDU_ADDRESS_TRANSLATION_MATRIX(27).TDU0[0x17a]=0x100000
TDU_ADDRESS_TRANSLATION_MATRIX(28).TDU0[0x17b]=0x40000
TDU_ADDRESS_TRANSLATION_MATRIX(29).TDU0[0x17c]=0
TDU_DRAM_BLOCKED_CONFIG.TDU0[0x17d]=0x600010006000a010080400578006400070820100800898007d00070a0000000000640000000170a00b840000008040201f4000fa000001000400100032010403020dae00d6450d1a9010007
TDU_DRAM_BLOCKED_STATUS.TDU0[0x17e]=0
TDU_ECC_1B_ERR_CNT.TDU0[0x94]=0
TDU_ECC_2B_ERR_CNT.TDU0[0x96]=0
TDU_ECC_ERR_1B_MONITOR_MEM_MASK.TDU0[0x9a]=0xf
TDU_ECC_ERR_2B_MONITOR_MEM_MASK.TDU0[0x9c]=0xf
TDU_ECC_INTERRUPT_REGISTER.TDU0[0x7]=0
TDU_ECC_INTERRUPT_REGISTER_MASK.TDU0[0x17]=0
TDU_ECC_INTERRUPT_REGISTER_TEST.TDU0[0x1f]=0
TDU_GTIMER_CONFIGURATION.TDU0[0x89]=0
TDU_GTIMER_CYCLE.TDU0[0x88]=0x3b9aca00
TDU_INTERRUPT_MASK_REGISTER.TDU0[0x10]=0
TDU_INTERRUPT_REGISTER.TDU0[0x0]=0
TDU_INTERRUPT_REGISTER_TEST.TDU0[0x18]=0
TDU_PCMI_0.TDU0[0xb0]=0x3b9aca00
TDU_PCMI_1.TDU0[0xb3]=0x3b9aca00
TDU_PCMI_2.TDU0[0xb6]=0x3b9aca00
TDU_PCMI_3.TDU0[0xb9]=0x3b9aca00
TDU_PCMI_4.TDU0[0xbc]=0x3b9aca00
TDU_PCMI_0_S.TDU0[0xb1]=0
TDU_PCMI_0_T.TDU0[0xb2]=0
TDU_PCMI_1_S.TDU0[0xb4]=0
TDU_PCMI_1_T.TDU0[0xb5]=0
TDU_PCMI_2_S.TDU0[0xb7]=0
TDU_PCMI_2_T.TDU0[0xb8]=0
TDU_PCMI_3_S.TDU0[0xba]=0
TDU_PCMI_3_T.TDU0[0xbb]=0
TDU_PCMI_4_S.TDU0[0xbd]=0
TDU_PCMI_4_T.TDU0[0xbe]=0
TDU_READ_DATA_PATH_CONFIG.TDU0[0x15c]=0x6000003
TDU_READ_DATA_PATH_COUNTERS.TDU0[0x15d]=0x20000000000000000000000000000000000000
TDU_READ_REQUEST_PATH_CONFIG.TDU0[0x12e]=0x600000101
TDU_READ_REQUEST_PATH_COUNTERS.TDU0[0x12f]=0
TDU_READ_REQUEST_PER_BANK_COUNT(0).TDU0[0x14c]=0
TDU_READ_REQUEST_PER_BANK_COUNT(1).TDU0[0x14d]=0
TDU_READ_REQUEST_PER_BANK_COUNT(2).TDU0[0x14e]=0
TDU_READ_REQUEST_PER_BANK_COUNT(3).TDU0[0x14f]=0
TDU_READ_REQUEST_PER_BANK_COUNT(4).TDU0[0x150]=0
TDU_READ_REQUEST_PER_BANK_COUNT(5).TDU0[0x151]=0
TDU_READ_REQUEST_PER_BANK_COUNT(6).TDU0[0x152]=0
TDU_READ_REQUEST_PER_BANK_COUNT(7).TDU0[0x153]=0
TDU_READ_REQUEST_PER_BANK_COUNT(8).TDU0[0x154]=0
TDU_READ_REQUEST_PER_BANK_COUNT(9).TDU0[0x155]=0
TDU_READ_REQUEST_PER_BANK_COUNT(10).TDU0[0x156]=0
TDU_READ_REQUEST_PER_BANK_COUNT(11).TDU0[0x157]=0
TDU_READ_REQUEST_PER_BANK_COUNT(12).TDU0[0x158]=0
TDU_READ_REQUEST_PER_BANK_COUNT(13).TDU0[0x159]=0
TDU_READ_REQUEST_PER_BANK_COUNT(14).TDU0[0x15a]=0
TDU_READ_REQUEST_PER_BANK_COUNT(15).TDU0[0x15b]=0
TDU_READ_REQUEST_PER_CHANNEL_COUNT(0).TDU0[0x148]=0
TDU_READ_REQUEST_PER_CHANNEL_COUNT(1).TDU0[0x149]=0
TDU_READ_REQUEST_PER_CHANNEL_COUNT(2).TDU0[0x14a]=0
TDU_READ_REQUEST_PER_CHANNEL_COUNT(3).TDU0[0x14b]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(0).TDU0[0x130]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(1).TDU0[0x131]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(2).TDU0[0x132]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(3).TDU0[0x133]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(4).TDU0[0x134]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(5).TDU0[0x135]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(6).TDU0[0x136]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(7).TDU0[0x137]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(8).TDU0[0x138]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(9).TDU0[0x139]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(10).TDU0[0x13a]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(11).TDU0[0x13b]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(12).TDU0[0x13c]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(13).TDU0[0x13d]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(14).TDU0[0x13e]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(15).TDU0[0x13f]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(16).TDU0[0x140]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(17).TDU0[0x141]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(18).TDU0[0x142]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(19).TDU0[0x143]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(20).TDU0[0x144]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(21).TDU0[0x145]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(22).TDU0[0x146]=0
TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(23).TDU0[0x147]=0
TDU_REG_00C2.TDU0[0xc2]=0x10
TDU_RESERVED_MTCD.TDU0[0xae]=0x30
TDU_RESERVED_MTCP.TDU0[0xad]=0x300000600000000
TDU_RESERVED_SPARE_0.TDU0[0x90]=0xffffffff
TDU_RESERVED_SPARE_1.TDU0[0x91]=0xffffffff
TDU_RESERVED_SPARE_2.TDU0[0x92]=0
TDU_RESERVED_SPARE_3.TDU0[0x93]=0
TDU_SBUS_BROADCAST_ID.TDU0[0x86]=0x7ff
TDU_SBUS_LAST_IN_CHAIN.TDU0[0x87]=0
TDU_SPECIAL_CLOCK_CONTROLS.TDU0[0xc1]=2
TDU_WRITE_REQUEST_PATH_CONFIG.TDU0[0x100]=0x101
TDU_WRITE_REQUEST_PATH_COUNTERS.TDU0[0x101]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(0).TDU0[0x11e]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(1).TDU0[0x11f]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(2).TDU0[0x120]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(3).TDU0[0x121]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(4).TDU0[0x122]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(5).TDU0[0x123]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(6).TDU0[0x124]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(7).TDU0[0x125]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(8).TDU0[0x126]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(9).TDU0[0x127]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(10).TDU0[0x128]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(11).TDU0[0x129]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(12).TDU0[0x12a]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(13).TDU0[0x12b]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(14).TDU0[0x12c]=0
TDU_WRITE_REQUEST_PER_BANK_COUNT(15).TDU0[0x12d]=0
TDU_WRITE_REQUEST_PER_CHANNEL_COUNT(0).TDU0[0x11a]=0
TDU_WRITE_REQUEST_PER_CHANNEL_COUNT(1).TDU0[0x11b]=0
TDU_WRITE_REQUEST_PER_CHANNEL_COUNT(2).TDU0[0x11c]=0
TDU_WRITE_REQUEST_PER_CHANNEL_COUNT(3).TDU0[0x11d]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(0).TDU0[0x102]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(1).TDU0[0x103]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(2).TDU0[0x104]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(3).TDU0[0x105]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(4).TDU0[0x106]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(5).TDU0[0x107]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(6).TDU0[0x108]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(7).TDU0[0x109]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(8).TDU0[0x10a]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(9).TDU0[0x10b]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(10).TDU0[0x10c]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(11).TDU0[0x10d]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(12).TDU0[0x10e]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(13).TDU0[0x10f]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(14).TDU0[0x110]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(15).TDU0[0x111]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(16).TDU0[0x112]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(17).TDU0[0x113]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(18).TDU0[0x114]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(19).TDU0[0x115]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(20).TDU0[0x116]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(21).TDU0[0x117]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(22).TDU0[0x118]=0
TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT(23).TDU0[0x119]=0
>/usr/bin/bcmcmd config
    port_init_speed_32=1000
    default_trap_strength=4
    port_init_speed_24=1000
    port_init_speed_16=1000
    ucode_port_10=XE33:core_0.10
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit5.0=0x00000016
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram1_byte0.0=0x00000014
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit7.0=0x00000001
    ext_ram_dq_swap_dram0_byte1_bit3=5
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram0_byte0.0=0x00000017
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram0_byte3.0=0x00000011
    phy_tx_polarity_flip_phy31=1
    phy_tx_polarity_flip_phy23=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit1.0=0x0000000E
    dtm_flow_nof_remote_cores_region_32=1
    oamp_fifo_dma_event_interface_buffer_size=327680
    mdb_profile=custom
    dtm_flow_nof_remote_cores_region_24=1
    lane_to_serdes_map_nif_lane5=rx4:tx5
    dtm_flow_nof_remote_cores_region_16=1
    phy_rx_polarity_flip_phy1=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit7.0=0x00000014
    rate_ext_mdio_divisor=0x9A
    pmf_vsi_profile_full_range=1
    oam_maid_11_bytes_enable=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit2.0=0x00000012
    port_init_speed_33=100000
    port_init_speed_25=1000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit0.0=0x0000000B
    port_init_speed_17=1000
    ucode_port_11=XE36:core_0.11
    custom_feature_enhanced_mux_cal=1
    phy_tx_polarity_flip_phy40=1
    ext_ram_dq_swap_dram0_byte1_bit4=2
    phy_tx_polarity_flip_phy32=1
    tslam_timeout_usec=5000000
    phy_tx_polarity_flip_phy24=1
    phy_tx_polarity_flip_phy16=1
    ext_ram_t_rtw=14000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit4.0=0x00000008
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit2.0=0x00000000
    dtm_flow_nof_remote_cores_region_25=1
    lane_to_serdes_map_nif_lane6=rx7:tx7
    dtm_flow_nof_remote_cores_region_17=1
    phy_rx_polarity_flip_phy2=1
    ext_ram_t_wr=30000
    port_init_speed_34=100000
    port_init_speed_26=1000
    ucode_port_20=XE23:core_0.20
    port_init_speed_18=1000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit3.0=0x00000012
    ucode_port_12=XE37:core_0.12
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit5.0=0x0000000F
    ext_ram_dq_swap_dram0_byte1_bit5=3
    phy_tx_polarity_flip_phy33=1
    phy_tx_polarity_flip_phy25=1
    phy_tx_polarity_flip_phy17=1
    dtm_flow_nof_remote_cores_region_26=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit5.0=0x00000006
    lane_to_serdes_map_nif_lane7=rx5:tx4
    dtm_flow_nof_remote_cores_region_18=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit7.0=0x00000011
    lane_to_serdes_map_nif_lane10=rx10:tx11
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit0.0=0x00000005
    polled_irq_mode=0
    port_init_speed_35=100000
    port_init_speed_27=1000
    ucode_port_21=XE26:core_0.21
    port_init_speed_19=1000
    ext_ram_dq_swap_dram1_byte0_bit0=7
    ucode_port_13=XE40:core_0.13
    ext_ram_dq_swap_dram0_byte2_bit0=7
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit6.0=0x00000010
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram1_byte1.0=0x00000013
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram0_byte1.0=0x00000016
    ext_ram_dq_swap_dram0_byte1_bit6=0
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit0.0=0x0000001F
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit2.0=0x00000000
    port_egress_recycling_scheduler_configuration=0
    dtm_flow_nof_remote_cores_region_27=1
    lane_to_serdes_map_nif_lane8=rx11:tx10
    dtm_flow_nof_remote_cores_region_19=1
    ext_ram_t_wtr_l=7000
    pci_cmcs_num=2
    lane_to_serdes_map_nif_lane11=rx8:tx8
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit3.0=0x0000001B
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit1.0=0x0000000B
    port_init_speed_36=100000
    ucode_port_30=XE43:core_0.30
    port_init_speed_28=1000
    ucode_port_22=XE27:core_0.22
    ext_ram_dq_swap_dram1_byte0_bit1=6
    ucode_port_14=XE41:core_0.14
    ext_ram_dq_swap_dram0_byte2_bit1=6
    custom_feature_dynamic_port=1
    ext_ram_dq_swap_dram0_byte1_bit7=1
    phy_tx_polarity_flip_phy35=1
    learning_fifo_dma_threshold=4
    phy_tx_polarity_flip_phy27=1
    phy_tx_polarity_flip_phy19=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit5.0=0x00000007
    ucode_port_0=CPU.0:core_0.0
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit3.0=0x0000000B
    ext_ram_t_rtp_l=3c
    dtm_flow_nof_remote_cores_region_28=1
    lane_to_serdes_map_nif_lane9=rx9:tx9
    outlif_physical_phase_data_granularity_XL=60
    serdes_lane_config_media_type=optics
    oam_rcy_port=-1
    lane_to_serdes_map_nif_lane20=rx21:tx20
    lane_to_serdes_map_nif_lane12=rx13:tx13
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit4.0=0x0000000B
    ucode_port_31=XE46:core_0.31
    port_init_speed_29=1000
    ucode_port_23=XE30:core_0.23
    ext_ram_dq_swap_dram1_byte0_bit2=5
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit6.0=0x0000000D
    ucode_port_15=XE44:core_0.15
    ext_ram_dq_swap_dram0_byte2_bit2=5
    fabric_connect_mode=SINGLE_FAP
    ext_ram_t_crc_wr_latency=14c
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit0.0=0x00000015
    phy_tx_polarity_flip_phy36=1
    phy_tx_polarity_flip_phy28=1
    ucode_port_1=XE16:core_0.1
    itmh_programmable_mode_enable=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit6.0=0x00000000
    dtm_flow_nof_remote_cores_region_29=1
    bcm88xxx_system_resource_management=1
    phy_rx_polarity_flip_phy6=1
    custom_feature_kbp_recovery_enable=0
    field_presel_mgmt_advanced_mode=1
    oamp_fifo_dma_event_interface_timeout=500
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit1.0=0x0000000B
    lane_to_serdes_map_nif_lane21=rx23:tx22
    lane_to_serdes_map_nif_lane13=rx14:tx14
    ext_ram_t_rcdrtr=1c
    ucode_port_32=XE47:core_0.32
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit7.0=0x00000011
    ucode_port_24=XE31:core_0.24
    ext_ram_dq_swap_dram1_byte0_bit3=4
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram1_byte2.0=0x00000010
    ucode_port_16=XE45:core_0.16
    ext_ram_dq_swap_dram0_byte2_bit3=4
    itmh_arad_mode_enable=0
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram0_byte2.0=0x0000000A
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit1.0=0x00000020
    phy_tx_polarity_flip_phy37=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit3.0=0x00000010
    phy_tx_polarity_flip_phy29=1
    ucode_port_2=XE17:core_0.2
    synth_dram_freq=25
    phy_rx_polarity_flip_phy7=1
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram0_byte0.0=0x00000018
    lane_to_serdes_map_nif_lane30=rx28:tx29
    lane_to_serdes_map_nif_lane22=rx20:tx21
    custom_feature_oam_mip_snoop_multicast_ltm=0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit4.0=0x00000009
    lane_to_serdes_map_nif_lane14=rx12:tx12
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit2.0=0x00000000
    ucode_port_33=CCGE0:core_0.33
    ucode_port_25=XE34:core_0.25
    ext_ram_dq_swap_dram1_byte0_bit4=2
    dma_desc_aggregator_timeout_usec=1000
    ucode_port_17=XE18:core_0.17
    ext_ram_dq_swap_dram0_byte2_bit4=2
    g6phy16_tune_dq_byte_macro_reserved_reg_dram0_byte0.0=0x0000002F
    phy_tx_polarity_flip_phy46=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit6.0=0x0000000A
    is_dual_mode=0
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit4.0=0x00000012
    ucode_port_3=XE20:core_0.3
    phy_rx_polarity_flip_phy8=1
    system_ref_core_clock_khz=1200000
    lane_to_serdes_map_nif_lane31=rx31:tx31
    stable_size=420000000
    lane_to_serdes_map_nif_lane23=rx22:tx23
    lane_to_serdes_map_nif_lane15=rx15:tx15
    stable_location=3
    ext_ram_t_rc=45000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit5.0=0x00000005
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit7.0=0x0000000F
    ucode_port_34=CCGE1:core_0.34
    ucode_port_26=XE35:core_0.26
    ext_ram_dq_swap_dram1_byte0_bit5=0
    ucode_port_18=XE19:core_0.18
    ext_ram_dq_swap_dram0_byte2_bit5=1
    g6phy16_tune_dq_byte_vref_dac_config_dram0_byte0.0=0x00900000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit1.0=0x00000016
    phy_tx_polarity_flip_phy39=1
    ucode_port_4=XE21:core_0.4
    tm_port_header_type_in_240=INJECTED_2
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit7.0=0x00000001
    tm_port_header_type_in_232=INJECTED_2_PP
    broadsync_enable_clk=1
    phy_rx_polarity_flip_phy9=1
    discard_mtu_size=0
    port_init_speed_sfi=10312
    serdes_qrtt_active=0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit0.0=0x00000018
    serdes_lane_config_dfe=on
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit2.0=0x00000000
    lane_to_serdes_map_nif_lane40=rx43:tx40
    lane_to_serdes_map_nif_lane32=rx33:tx32
    lane_to_serdes_map_nif_lane24=rx25:tx24
    lane_to_serdes_map_nif_lane16=rx18:tx16
    ext_ram_dq_swap_dram1_byte1_bit0=2
    bcm886xx_ocb_databuffer_size=256
    ext_ram_dq_swap_dram0_byte3_bit0=2
    phy_1588_dpll_frequency_lock=1
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram1_byte0.0=0x0000001B
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram1_byte3.0=0x00000010
    ucode_port_35=CCGE3:core_0.35
    ucode_port_27=XE38:core_0.27
    ext_ram_dq_swap_dram1_byte0_bit6=3
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram0_byte3.0=0x0000000C
    ucode_port_19=XE22:core_0.19
    ext_ram_dq_swap_dram0_byte2_bit6=3
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit2.0=0x00000019
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit4.0=0x00000015
    oam_maid_48_bytes_external_enable=1
    ucode_port_5=XE24:core_0.5
    fap_tdm_bypass=0
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram0_byte1.0=0x00000012
    lane_to_serdes_map_nif_lane41=rx41:tx42
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit5.0=0x00000007
    phy_1588_dpll_phase_initial_lo=0x00000000
    lane_to_serdes_map_nif_lane33=rx34:tx34
    lane_to_serdes_map_nif_lane25=rx27:tx26
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit3.0=0x0000000D
    lane_to_serdes_map_nif_lane17=rx19:tx18
    ext_ram_channel_swap_en_dram0=1
    ext_ram_dq_swap_dram1_byte1_bit1=1
    ext_ram_dq_swap_dram0_byte3_bit1=1
    ucode_port_36=CCGE2:core_0.36
    ucode_port_28=XE39:core_0.28
    ext_ram_dq_swap_dram1_byte0_bit7=1
    ext_ram_dq_swap_dram0_byte2_bit7=0
    custom_feature_flexe_std_driver=1
    g6phy16_tune_dq_byte_macro_reserved_reg_dram0_byte1.0=0x0000002F
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit7.0=0x00000000
    ucode_port_100=RCY_MIRROR.0:core_0.100
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit5.0=0x00000010
    phy_tx_polarity_flip_phy1=1
    ucode_port_6=XE25:core_0.6
    tm_port_header_type_in_218=INJECTED_2_PP
    sat_enable=1
    custom_feature_oam_lm_enable=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit0.0=0x00000015
    ext_ram_t_wtr_s=6000
    lane_to_serdes_map_nif_lane50=rx50:tx50
    lane_to_serdes_map_nif_lane42=rx40:tx41
    lane_to_serdes_map_nif_lane34=rx32:tx33
    ext_ram_t_ltltr=4c
    lane_to_serdes_map_nif_lane26=rx24:tx25
    lane_to_serdes_map_nif_lane18=rx16:tx17
    ext_ram_channel_swap_en_dram1=0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit6.0=0x00000000
    ext_ram_dq_swap_dram1_byte1_bit2=0
    ext_ram_dq_swap_dram0_byte3_bit2=0
    dma_desc_aggregator_enable_specific_MDB_FEC=1
    system_ftmh_load_balancing_ext_mode=ENABLED
    port_init_speed_1=1000
    ucode_port_29=XE42:core_0.29
    g6phy16_tune_dq_byte_vref_dac_config_dram0_byte1.0=0x008C0000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit0.0=0x00000005
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit2.0=0x00000012
    ucode_port_101=RCY_MIRROR.1:core_0.101
    phy_tx_polarity_flip_phy2=1
    ucode_port_7=XE28:core_0.7
    ext_ram_t_rtp_s=2c
    packet_padding_size=64
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit1.0=0x00000019
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit3.0=0x0000000D
    lane_to_serdes_map_nif_lane43=rx42:tx43
    lane_to_serdes_map_nif_lane35=rx35:tx35
    lane_to_serdes_map_nif_lane27=rx26:tx27
    lane_to_serdes_map_nif_lane19=rx17:tx19
    ucode_port_70=CPU.24:core_0.70
    ext_ram_dq_swap_dram1_byte1_bit3=3
    ext_ram_dq_swap_dram0_byte3_bit3=3
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram1_byte1.0=0x00000015
    port_init_speed_2=1000
    ha_hw_journal_size=15728640
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit3.0=0x0000001F
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit5.0=0x00000018
    ucode_port_110=RCY_MIRROR.10:core_0.110
    ucode_port_102=RCY_MIRROR.2:core_0.102
    schan_timeout_usec=300000
    bcm886xx_ocb_enable=1
    ucode_port_8=XE29:core_0.8
    in_lif_profile_egress_allocate_same_interface_mode=2
    dtm_flow_nof_remote_cores_region_1=1
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram0_byte2.0=0x0000000B
    trunk_resolve_use_lb_key_msb_smooth_division = 0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit6.0=0x00000009
    lane_to_serdes_map_nif_lane44=rx44:tx44
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit4.0=0x00000013
    lane_to_serdes_map_nif_lane36=rx38:tx36
    lane_to_serdes_map_nif_lane28=rx29:tx28
    ucode_port_71=RCY.2:core_0.71
    ext_ram_dq_swap_dram1_byte1_bit4=6
    ext_ram_dq_swap_dram0_byte3_bit4=6
    port_init_speed_3=1000
    pmf_maps_payload_size=60
    tdma_timeout_usec=5000000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit0.0=0x0000000B
    outlif_logical_to_physical_phase_map_1=L1
    g6phy16_tune_dq_byte_macro_reserved_reg_dram0_byte2.0=0x0000002E
    miim_timeout_usec.0=300000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit6.0=0x00000011
    ucode_port_111=RCY_MIRROR.11:core_0.111
    tm_port_header_type_out_240=ETH
    ucode_port_103=RCY_MIRROR.3:core_0.103
    tm_port_header_type_out_232=CPU
    ucode_port_9=XE32:core_0.9
    dtm_flow_nof_remote_cores_region_2=1
    fabric_ftmh_outlif_extension=IF_MC
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit1.0=0x00000016
    lane_to_serdes_map_nif_lane45=rx46:tx46
    oamp_fifo_dma_event_interface_threshold=32
    lane_to_serdes_map_nif_lane37=rx39:tx38
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit7.0=0x00000002
    lane_to_serdes_map_nif_lane29=rx30:tx30
    ext_ram_dq_swap_dram1_byte1_bit5=7
    polled_irq_delay=50000
    ext_ram_dq_swap_dram0_byte3_bit5=7
    port_init_speed_4=1000
    g6phy16_tune_dq_byte_vref_dac_config_dram0_byte2.0=0x00900000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit1.0=0x0000000D
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit3.0=0x00000012
    outlif_logical_to_physical_phase_map_2=L2
    pmf_in_lif_profile_nof_bits=1
    ucode_port_120=RCY_MIRROR.20:core_0.120
    ucode_port_112=RCY_MIRROR.12:core_0.112
    oversubscribe_mode = 1
    ucode_port_104=RCY_MIRROR.4:core_0.104
    phy_tx_polarity_flip_phy5=1
    dtm_flow_nof_remote_cores_region_3=1
    port_init_cl72=0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit2.0=0x00000012
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit4.0=0x00000012
    os=unix
    ext_ram_dq_swap_dram1_byte2_bit0=1
    lane_to_serdes_map_nif_lane46=rx45:tx45
    lane_to_serdes_map_nif_lane38=rx36:tx37
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram1_byte2.0=0x0000000C
    ext_ram_dq_swap_dram1_byte1_bit6=5
    port_priorities_66=8
    phy_rx_polarity_flip=0
    ext_ram_dq_swap_dram0_byte3_bit6=5
    port_init_speed_5=1000
    phy_tx_polarity_flip=0
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit4.0=0x00000008
    outlif_logical_to_physical_phase_map_3=M1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit6.0=0x00000011
    ucode_port_121=RCY_MIRROR.21:core_0.121
    ucode_port_113=RCY_MIRROR.13:core_0.113
    ucode_port_105=RCY_MIRROR.5:core_0.105
    phy_tx_polarity_flip_phy6=1
    ha_crash_recovery=1
    tm_port_header_type_out_218=CPU
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram1_byte0.0=0x00000015
    dtm_flow_nof_remote_cores_region_4=1
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram0_byte3.0=0x0000000E
    oam_rcy_port_up_core_0=-1
    g6phy16_tune_aq_l_max_vdl_ctrl_dram0.0=0x00000037
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit7.0=0x00000000
    tm_port_header_type_in_71=RAW
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit5.0=0x00000010
    ext_ram_dq_swap_dram1_byte2_bit1=0
    ext_ram_t_ccd_l=3c
    lane_to_serdes_map_nif_lane47=rx47:tx47
    lane_to_serdes_map_nif_lane39=rx37:tx39
    ext_ram_t_rfc=110000
    ext_ram_dq_swap_dram1_byte1_bit7=4
    ucode_port_66=CPU.8:core_0.66
    ext_ram_dq_swap_dram0_byte3_bit7=4
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit1.0=0x0000000A
    g6phy16_tune_dq_byte_macro_reserved_reg_dram1_byte0.0=0x00000030
    port_init_speed_6=1000
    outlif_physical_phase_data_granularity_L1=60
    g6phy16_tune_dq_byte_macro_reserved_reg_dram0_byte3.0=0x0000002D
    outlif_logical_to_physical_phase_map_4=M2
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit7.0=0x0000000D
    ucode_port_130=RCY_MIRROR.30:core_0.130
    ucode_port_122=RCY_MIRROR.22:core_0.122
    ucode_port_114=RCY_MIRROR.14:core_0.114
    ucode_port_106=RCY_MIRROR.6:core_0.106
    dtm_flow_nof_remote_cores_region_5=1
    port_priorities=2
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit0.0=0x00000006
    system_is_dual_mode_in_system=0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit2.0=0x00000014
    g6phy16_tune_aq_l_max_vdl_addr_dram0.0=0x00000037
    ext_ram_dq_swap_dram1_byte2_bit2=3
    lane_to_serdes_map_nif_lane48=rx48:tx48
    g6phy16_tune_dq_byte_vref_dac_config_dram1_byte0.0=0x008C0000
    g6phy16_tune_dq_byte_vref_dac_config_dram0_byte3.0=0x008E0000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit2.0=0x00000000
    port_init_speed_7=1000
    outlif_physical_phase_data_granularity_L2=60
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit4.0=0x0000000A
    dtm_flow_mapping_mode_region_40=3
    outlif_logical_to_physical_phase_map_5=M3
    ucode_port_131=RCY_MIRROR.31:core_0.131
    ucode_port_123=RCY_MIRROR.23:core_0.123
    ucode_port_115=RCY_MIRROR.15:core_0.115
    ha_sw_journal_size=15728640
    custom_feature_flexe_disable_l1_mismatch_rate_checking=1
    ucode_port_107=RCY_MIRROR.7:core_0.107
    dtm_flow_nof_remote_cores_region_6=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit3.0=0x00000017
    in_lif_profile_egress_allocate_orientation=4
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit5.0=0x00000015
    phy_rx_polarity_flip_phy13=1
    ext_ram_dq_swap_dram1_byte2_bit3=2
    lane_to_serdes_map_nif_lane49=rx49:tx49
    g6phy16_tune_dq_byte_rd_min_vdl_dbi_dram1_byte3.0=0x0000000E
    ucode_port_76=RCY.0:core_0.76
    outlif_physical_phase_data_granularity_M1=60
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit5.0=0x00000000
    port_init_speed_8=1000
    dtm_flow_mapping_mode_region_41=3
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit7.0=0x00000013
    dtm_flow_mapping_mode_region_33=3
    ext_ram_t_rcd_wr=11000
    outlif_logical_to_physical_phase_map_6=S2
    fabric_segmentation_enable=1
    ucode_port_140=RCY_MIRROR.40:core_0.140
    ucode_port_132=RCY_MIRROR.32:core_0.132
    ucode_port_124=RCY_MIRROR.24:core_0.124
    custom_feature_nif_recovery_enable=1
    ucode_port_116=RCY_MIRROR.16:core_0.116
    ucode_port_108=RCY_MIRROR.8:core_0.108
    phy_tx_polarity_flip_phy9=1
    ext_ram_t_rdtlt=16c
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram1_byte1.0=0x00000015
    dtm_flow_nof_remote_cores_region_7=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit0.0=0x0000000D
    g6phy16_tune_aq_l_max_vdl_ctrl_dram1.0=0x00000039
    phy_rx_polarity_flip_phy22=1
    phy_rx_polarity_flip_phy14=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit6.0=0x00000013
    tm_port_header_type_in_66=INJECTED_2_PP
    ext_ram_dq_swap_dram1_byte2_bit4=5
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit0.0=0x0000001A
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit2.0=0x00000000
    g6phy16_tune_dq_byte_macro_reserved_reg_dram1_byte1.0=0x0000002F
    ucode_port_69=CPU.16:core_0.69
    outlif_physical_phase_data_granularity_M2=60
    port_init_speed_9=1000
    dtm_flow_mapping_mode_region_42=7
    dtm_flow_mapping_mode_region_34=3
    outlif_logical_to_physical_phase_map_7=S1
    ucode_port_141=RCY_MIRROR.41:core_0.141
    system_headers_mode=1
    ucode_port_133=RCY_MIRROR.33:core_0.133
    ucode_port_125=RCY_MIRROR.25:core_0.125
    ucode_port_117=RCY_MIRROR.17:core_0.117
    serdes_firmware_mode=2
    ucode_port_109=RCY_MIRROR.9:core_0.109
    oamp_fifo_dma_event_interface_enable=1
    ext_ram_t_rcdltr=6000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit1.0=0x0000000D
    dtm_flow_nof_remote_cores_region_8=1
    fap_tdm_packet=0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit3.0=0x00000010
    custom_feature_skip_before_traffic_validation=0
    phy_rx_polarity_flip_phy23=1
    tm_port_header_type_out_71=ETH
    g6phy16_tune_aq_l_max_vdl_addr_dram1.0=0x00000039
    ext_ram_dq_swap_dram1_byte2_bit5=6
    g6phy16_tune_dq_byte_vref_dac_config_dram1_byte1.0=0x008C0000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit3.0=0x00000011
    ucode_port_78=RCY.1:core_0.78
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit5.0=0x00000004
    outlif_physical_phase_data_granularity_M3=60
    fabric_tdm_over_primary_pipe=0
    dtm_flow_mapping_mode_region_43=3
    system_is_fe600_in_system=0
    ext_ram_t_wtrtr=6c
    dtm_flow_mapping_mode_region_35=3
    tslam_intr_enable=1
    outlif_logical_to_physical_phase_map_8=XL
    ext_ram_t_crc_rd_latency=2c
    ucode_port_142=RCY_MIRROR.42:core_0.142
    ucode_port_134=RCY_MIRROR.34:core_0.134
    ucode_port_126=RCY_MIRROR.26:core_0.126
    ucode_port_118=RCY_MIRROR.18:core_0.118
    ext_ram_write_latency=6c
    dtm_flow_nof_remote_cores_region_9=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit4.0=0x00000009
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit6.0=0x0000000E
    phy_rx_polarity_flip_phy40=1
    ext_ram_dq_swap_dram1_byte3_bit0=7
    ext_ram_t_rcdwtr=11000
    tm_port_header_type_in_76=TM
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit0.0=0x0000001C
    ext_ram_dq_swap_dram1_byte2_bit6=4
    ext_ram_t_rp=17000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit6.0=0x00000009
    dtm_flow_mapping_mode_region_44=1
    dtm_flow_mapping_mode_region_36=3
    ucode_port_240=OLP.0:core_0.240
    ucode_port_232=OAMP:core_0.232
    ucode_port_143=RCY_MIRROR.43:core_0.143
    ucode_port_135=RCY_MIRROR.35:core_0.135
    ucode_port_127=RCY_MIRROR.27:core_0.127
    ucode_port_119=RCY_MIRROR.19:core_0.119
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram1_byte2.0=0x0000000C
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit1.0=0x0000000C
    port_init_cl72_sfi=1
    phy_rx_polarity_flip_phy41=1
    phy_rx_polarity_flip_phy33=1
    ext_ram_dq_swap_dram1_byte3_bit1=6
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte3_bit7.0=0x0000000D
    phy_rx_polarity_flip_phy25=1
    g6phy16_tune_aq_u_max_vdl_ctrl_dram0.0=0x00000027
    ext_ram_dq_swap_dram1_byte2_bit7=7
    ext_ram_t_faw=16000
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit1.0=0x00000015
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit3.0=0x0000000B
    g6phy16_tune_dq_byte_macro_reserved_reg_dram1_byte2.0=0x0000002F
    ext_ram_t_ras=28000
    dtm_flow_mapping_mode_region_45=3
    dtm_flow_mapping_mode_region_37=3
    ucode_port_144=RCY_MIRROR.44:core_0.144
    ucode_port_136=RCY_MIRROR.36:core_0.136
    ucode_port_128=RCY_MIRROR.28:core_0.128
    serdes_firmware_mode_sfi=4
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit2.0=0x00000000
    num_oamp_ports=1
    ext_ram_dq_swap_dram0_byte0_bit0=0
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit4.0=0x0000000A
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram0_byte0.0=0x00000015
    srd_tx_drv_hv_disable=1
    field_key_allocation_msb_balance_enable=1
    phy_rx_polarity_flip_phy42=1
    phy_rx_polarity_flip_phy34=1
    ext_ram_dq_swap_dram1_byte3_bit2=4
    phy_rx_polarity_flip_phy18=1
    tm_port_header_type_out_66=CPU
    tm_port_header_type_in_78=INJECTED_2_PP
    tm_port_header_type_in_0=INJECTED_2_PP
    ext_ram_t_ccd_s=2c
    g6phy16_tune_dq_byte_vref_dac_config_dram1_byte2.0=0x008C0000
    g6phy16_tune_aq_u_max_vdl_addr_dram0.0=0x00000027
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit4.0=0x00000016
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit6.0=0x00000000
    dtm_flow_mapping_mode_region_46=3
    dtm_flow_mapping_mode_region_38=3
    flexe_device_mode=centralized
    ucode_port_145=RCY_MIRROR.45:core_0.145
    ucode_port_218=SAT:core_0.218
    ucode_port_137=RCY_MIRROR.37:core_0.137
    ucode_port_129=RCY_MIRROR.29:core_0.129
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit5.0=0x00000000
    ext_ram_dq_swap_dram0_byte0_bit1=1
    learning_fifo_dma_timeout=32767
    ext_ram_t_rrd_l=4000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte1_bit7.0=0x0000000E
    phy_rx_polarity_flip_phy43=1
    ext_ram_dq_swap_dram1_byte3_bit3=5
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit1.0=0x0000001E
    bist_enable_dram=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte0_bit7.0=0x00000009
    dtm_flow_mapping_mode_region_47=3
    dtm_flow_mapping_mode_region_39=3
    sw_state_max_size=350000000
    ucode_port_146=RCY_MIRROR.46:core_0.146
    ucode_port_138=RCY_MIRROR.38:core_0.138
    g6phy16_tune_dq_byte_wr_min_vdl_dbi_dram1_byte3.0=0x0000000E
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit0.0=0x00000019
    custom_feature_no_backdoor=1
    num_olp_tm_ports=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit2.0=0x00000000
    bcm886xx_ocb_repartition=0
    ext_ram_dq_swap_dram0_byte0_bit2=2
    phy_rx_polarity_flip_phy36=1
    ext_ram_dq_swap_dram1_byte3_bit4=3
    g6phy16_tune_aq_u_max_vdl_ctrl_dram1.0=0x00000029
    tm_port_header_type_out_76=ETH
    custom_feature_optimized_de_allocation=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit2.0=0x00000014
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit4.0=0x00000013
    g6phy16_tune_dq_byte_macro_reserved_reg_dram1_byte3.0=0x0000002D
    serdes_firmware_mode_il=4
    ha_hw_journal_mode=0
    port_init_speed_10=1000
    egress_multicast_direct_bitmap_max=0
    ucode_port_147=RCY_MIRROR.47:core_0.147
    ucode_port_139=RCY_MIRROR.39:core_0.139
    ext_ram_t_rcd_rd=18000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit3.0=0x0000000E
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit5.0=0x00000004
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram0_byte1.0=0x00000014
    ext_ram_dq_swap_dram0_byte0_bit3=3
    mem_cache_enable_parity=1
    phy_rx_polarity_flip_phy45=1
    dtm_flow_nof_remote_cores_region_10=1
    stable_filename=/tmp/warmboot_data
    phy_rx_polarity_flip_phy37=1
    ext_ram_dq_swap_dram1_byte3_bit5=2
    phy_rx_polarity_flip_phy29=1
    ext_ram_enabled_bitmap=3
    tm_port_header_type_out_0=CPU
    g6phy16_tune_dq_byte_vref_dac_config_dram1_byte3.0=0x008C0000
    g6phy16_tune_aq_u_max_vdl_addr_dram1.0=0x00000029
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit5.0=0x00000016
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte2_bit7.0=0x00000000
    ext_ram_t_reftr=11000
    learning_fifo_dma_buffer_size=200000
    dma_desc_aggregator_buff_size_kb=100
    port_init_speed_11=1000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit0.0=0x0000001D
    ucode_port_148=RCY_MIRROR.48:core_0.148
    use_trunk_as_ingress_mc_destination=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit6.0=0x00000008
    phy_tx_polarity_flip_phy10=1
    ext_ram_dq_swap_dram0_byte0_bit4=5
    phy_rx_polarity_flip_phy46=1
    lane_to_serdes_map_nif_lane0=rx1:tx1
    dtm_flow_nof_remote_cores_region_11=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit2.0=0x00000010
    ext_ram_dq_swap_dram1_byte3_bit6=1
    tm_port_header_type_out_78=ETH
    ext_ram_t_abref_in_ns=1000000
    trunk_resolve_use_lb_key_msb_stack = 0
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit0.0=0x00000009
    stable_flags=0
    bfd_extended_ipv4_src_ip=1
    ext_ram_t_wrwtr=4c
    phy_1588_dpll_phase_initial_hi=0x2000
    tdma_intr_enable=1
    port_init_speed_20=1000
    port_init_speed_12=1000
    pbmp_oversubscribe=0x1fffffffffffe222222
    dma_desc_aggregator_chain_length_max=1000
    ucode_port_149=RCY_MIRROR.49:core_0.149
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit1.0=0x00000013
    mem_nocache_IHB_CPU_TRAP_CODE_CTR=1
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit3.0=0x0000000C
    ext_ram_dq_swap_dram0_byte0_bit5=6
    ext_ram_t_refi_sb_in_ns=118
    dtm_flow_nof_remote_cores_region_20=1
    lane_to_serdes_map_nif_lane1=rx2:tx2
    dtm_flow_nof_remote_cores_region_12=1
    phy_rx_polarity_flip_phy39=1
    ext_ram_dq_swap_dram1_byte3_bit7=0
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit3.0=0x00000012
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit5.0=0x00000013
    port_init_speed_21=1000
    port_init_speed_13=1000
    bcm886xx_pdm_mode=0
    credit_size=2048
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte1_bit4.0=0x00000015
    ext_ram_dq_swap_dram0_byte1_bit0=7
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte2_bit6.0=0x00000000
    phy_tx_polarity_flip_phy20=1
    g6phy16_tune_dq_byte_rd_min_vdl_edc_dram0_byte2.0=0x0000000E
    ext_ram_dq_swap_dram0_byte0_bit6=4
    ext_ram_t_ltrtr=4c
    ext_ram_freq=900
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte1_bit0.0=0x00000006
    dtm_flow_nof_remote_cores_region_21=1
    lane_to_serdes_map_nif_lane2=rx0:tx0
    dtm_flow_nof_remote_cores_region_13=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte1_bit6.0=0x00000012
    first_header_size=0
    port_init_speed_30=1000
    port_init_speed_22=1000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte0_bit1.0=0x0000001E
    port_init_speed_14=1000
    bfd_ipv4_single_hop_extended=2
    dma_desc_aggregator_enable_specific_MDB_LPM=1
    ext_ram_dq_swap_dram0_byte1_bit1=6
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte0_bit7.0=0x00000009
    phy_tx_polarity_flip_phy21=1
    phy_tx_polarity_flip_phy13=1
    ext_ram_dq_swap_dram0_byte0_bit7=7
    dtm_flow_nof_remote_cores_region_30=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte0_bit3.0=0x0000001C
    dtm_flow_nof_remote_cores_region_22=1
    lane_to_serdes_map_nif_lane3=rx3:tx3
    ext_ram_read_latency=16c
    dtm_flow_nof_remote_cores_region_14=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte3_bit1.0=0x00000009
    outlif_physical_phase_data_granularity_S1=60
    default_snoop_strength=1
    dram_phy_tune_mode_on_init=RESTORE_TUNE_PARAMETERS_FROM_SOC_PROPERTIES
    port_init_speed_31=1000
    port_init_speed_23=1000
    port_init_speed_15=1000
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram1_byte2_bit2.0=0x00000013
    g6phy16_tune_dq_byte_wr_min_vdl_bit_dram0_byte3_bit4.0=0x00000010
    ext_ram_dq_swap_dram0_byte1_bit2=4
    phy_tx_polarity_flip_phy14=1
    ext_ram_t_rrd_s=4000
    dtm_flow_nof_remote_cores_region_31=1
    dtm_flow_nof_remote_cores_region_23=1
    lane_to_serdes_map_nif_lane4=rx6:tx6
    dtm_flow_nof_remote_cores_region_15=1
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram1_byte2_bit4.0=0x0000000A
    g6phy16_tune_dq_byte_rd_min_vdl_bit_dram0_byte3_bit6.0=0x00000010
    number_of_trunks=256
    outlif_physical_phase_data_granularity_S2=60
    trill_mc_prune_mode=0
    host_memory_address_remap_entries_reserved_cmc_1=0xc003
>/usr/bin/bcmcmd show counter full
==========================================================================================================
|                                                 Full counters                                          |
==========================================================================================================
| Port  | Counter Name                           | Counter Value      | Diff from last call | Rate       |
==========================================================================================================
| eth1  | RX 64-byte frame                       | 34,789,404         | 34,789,404          | 3          |
| eth1  | RX 65 to 127 byte frame                | 8,124,192,061      | 8,124,192,061       | 1,091      |
| eth1  | RX 128 to 255 byte frame               | 811,510,677        | 811,510,677         | 135        |
| eth1  | RX 256 to 511 byte frame               | 782,375,759        | 782,375,759         | 86         |
| eth1  | RX 512 to 1023 byte frame              | 340,931,420        | 340,931,420         | 88         |
| eth1  | RX 1024 to 1518 byte frame             | 1,776,575,599      | 1,776,575,599       | 260        |
| eth1  | RX 1519 to 1522 byte frame             | 530,465,482        | 530,465,482         | 24         |
| eth1  | RX 1519 to 2047 byte frame             | 530,465,482        | 530,465,482         | 24         |
| eth1  | RX BC frame                            | 5,927,926          | 5,927,926           | 1          |
| eth1  | RX RPROG0 frame                        | 6,390,049,023      | 6,390,049,023       | 633        |
| eth1  | RX RPROG1 frame                        | 1,018,091,555      | 1,018,091,555       | 391        |
| eth1  | RX RPROG2 frame                        | 598,749,908        | 598,749,908         | 42         |
| eth1  | RX RPROG3 frame                        | 152,090,979        | 152,090,979         | 28         |
| eth1  | RX all packets frame                   | 12,400,840,402     | 12,400,840,402      | 1,686      |
| eth1  | RX good frame                          | 12,400,829,547     | 12,400,829,547      | 1,686      |
| eth1  | RX UC frame                            | 12,383,485,295     | 12,383,485,295      | 1,685      |
| eth1  | RX MC frame                            | 11,416,326         | 11,416,326          | 1          |
| eth1  | RX out-of-range length frame           | 10,855             | 10,855              | 0          |
| eth1  | RX single and double VLAN tagged frame | 12,400,840,402     | 12,400,840,402      | 1,686      |
| eth1  | RX promiscuous frame                   | 11,853,019,822     | 11,853,019,822      | 1,661      |
| eth1  | TX 64-byte frame                       | 357,337,366        | 357,337,366         | 17         |
| eth1  | TX 65 to 127 byte frame                | 3,465,035,014      | 3,465,035,014       | 704        |
| eth1  | TX 128 to 255 byte frame               | 364,712,917        | 364,712,917         | 178        |
| eth1  | TX 256 to 511 byte frame               | 279,238,820        | 279,238,820         | 138        |
| eth1  | TX 512 to 1023 byte frame              | 397,247,755        | 397,247,755         | 338        |
| eth1  | TX 1024 to 1518 byte frame             | 11,760,008,831     | 11,760,008,831      | 2,223      |
| eth1  | TX 1519 to 1522 byte frame             | 8,534,358,406      | 8,534,358,406       | 717        |
| eth1  | TX 1519 to 2047 byte frame             | 8,534,358,406      | 8,534,358,406       | 717        |
| eth1  | TX Broadcast frame                     | 2,680,421          | 2,680,421           | 0          |
| eth1  | TX all packets frame                   | 25,157,939,116     | 25,157,939,116      | 4,321      |
| eth1  | TX good frame                          | 25,157,939,116     | 25,157,939,116      | 4,321      |
| eth1  | TX UC frame                            | 25,153,699,373     | 25,153,699,373      | 4,321      |
| eth1  | TX MC frame                            | 1,559,322          | 1,559,322           | 0          |
| eth1  | TX single and double VLAN tagged frame | 25,157,375,476     | 25,157,375,476      | 4,321      |
| eth1  | RX Byte frame                          | 4,663,678,119,648  | 4,663,678,119,648   | 605,552    |
| eth1  | TX Byte frame                          | 30,900,005,368,776 | 30,900,005,368,776  | 4,726,369  |
| eth2  | RX 64-byte frame                       | 30,293,473         | 30,293,473          | 0          |
| eth2  | RX 65 to 127 byte frame                | 3,590,412,284      | 3,590,412,284       | 443        |
| eth2  | RX 128 to 255 byte frame               | 360,573,193        | 360,573,193         | 113        |
| eth2  | RX 256 to 511 byte frame               | 127,433,118        | 127,433,118         | 6          |
| eth2  | RX 512 to 1023 byte frame              | 147,789,074        | 147,789,074         | 34         |
| eth2  | RX 1024 to 1518 byte frame             | 541,669,814        | 541,669,814         | 1,632      |
| eth2  | RX 1519 to 1522 byte frame             | 388,834,976        | 388,834,976         | 0          |
| eth2  | RX 1519 to 2047 byte frame             | 388,834,976        | 388,834,976         | 0          |
| eth2  | RX BC frame                            | 3,515,032          | 3,515,032           | 0          |
| eth2  | RX RPROG0 frame                        | 2,580,877,336      | 2,580,877,336       | 351        |
| eth2  | RX RPROG1 frame                        | 607,282,731        | 607,282,731         | 49         |
| eth2  | RX RPROG2 frame                        | 324,112,824        | 324,112,824         | 27         |
| eth2  | RX RPROG3 frame                        | 108,432,866        | 108,432,866         | 17         |
| eth2  | RX all packets frame                   | 5,187,005,932      | 5,187,005,932       | 2,229      |
| eth2  | RX good frame                          | 5,187,005,599      | 5,187,005,599       | 2,229      |
| eth2  | RX UC frame                            | 5,178,810,222      | 5,178,810,222       | 2,229      |
| eth2  | RX MC frame                            | 4,680,345          | 4,680,345           | 0          |
| eth2  | RX out-of-range length frame           | 333                | 333                 | 0          |
| eth2  | RX single and double VLAN tagged frame | 5,187,005,932      | 5,187,005,932       | 2,228      |
| eth2  | RX promiscuous frame                   | 4,789,975,246      | 4,789,975,246       | 2,228      |
| eth2  | TX 64-byte frame                       | 276,211,888        | 276,211,888         | 23         |
| eth2  | TX 65 to 127 byte frame                | 1,308,233,082      | 1,308,233,082       | 1,129      |
| eth2  | TX 128 to 255 byte frame               | 266,392,850        | 266,392,850         | 71         |
| eth2  | TX 256 to 511 byte frame               | 164,759,698        | 164,759,698         | 20         |
| eth2  | TX 512 to 1023 byte frame              | 205,260,107        | 205,260,107         | 12         |
| eth2  | TX 1024 to 1518 byte frame             | 5,718,184,103      | 5,718,184,103       | 255        |
| eth2  | TX 1519 to 1522 byte frame             | 3,781,866,329      | 3,781,866,329       | 69         |
| eth2  | TX 1519 to 2047 byte frame             | 3,781,866,329      | 3,781,866,329       | 69         |
| eth2  | TX Broadcast frame                     | 2,161,794          | 2,161,794           | 0          |
| eth2  | TX all packets frame                   | 11,720,908,059     | 11,720,908,059      | 1,579      |
| eth2  | TX good frame                          | 11,720,908,059     | 11,720,908,059      | 1,579      |
| eth2  | TX UC frame                            | 11,717,187,110     | 11,717,187,110      | 1,579      |
| eth2  | TX MC frame                            | 1,559,155          | 1,559,155           | 0          |
| eth2  | TX single and double VLAN tagged frame | 11,720,344,419     | 11,720,344,419      | 1,578      |
| eth2  | RX Byte frame                          | 1,823,748,165,504  | 1,823,748,165,504   | 2,516,332  |
| eth2  | TX Byte frame                          | 14,268,536,596,284 | 14,268,536,596,284  | 612,522    |
| eth3  | RX 64-byte frame                       | 64,321,759         | 64,321,759          | 0          |
| eth3  | RX 65 to 127 byte frame                | 8,762,392,368      | 8,762,392,368       | 2,567      |
| eth3  | RX 128 to 255 byte frame               | 805,135,339        | 805,135,339         | 129        |
| eth3  | RX 256 to 511 byte frame               | 616,233,040        | 616,233,040         | 98         |
| eth3  | RX 512 to 1023 byte frame              | 365,296,751        | 365,296,751         | 51         |
| eth3  | RX 1024 to 1518 byte frame             | 2,401,406,305      | 2,401,406,305       | 131        |
| eth3  | RX 1519 to 1522 byte frame             | 807,599,709        | 807,599,709         | 6          |
| eth3  | RX 1519 to 2047 byte frame             | 807,599,709        | 807,599,709         | 6          |
| eth3  | RX BC frame                            | 7,212,417          | 7,212,417           | 0          |
| eth3  | RX RPROG0 frame                        | 6,302,107,627      | 6,302,107,627       | 1,479      |
| eth3  | RX RPROG1 frame                        | 1,576,009,560      | 1,576,009,560       | 812        |
| eth3  | RX RPROG2 frame                        | 767,139,059        | 767,139,059         | 247        |
| eth3  | RX RPROG3 frame                        | 181,457,881        | 181,457,881         | 29         |
| eth3  | RX all packets frame                   | 13,822,385,271     | 13,822,385,271      | 2,981      |
| eth3  | RX good frame                          | 13,821,472,244     | 13,821,472,244      | 2,981      |
| eth3  | RX UC frame                            | 13,804,763,542     | 13,804,763,542      | 2,981      |
| eth3  | RX MC frame                            | 9,496,285          | 9,496,285           | 0          |
| eth3  | RX out-of-range length frame           | 913,027            | 913,027             | 0          |
| eth3  | RX single and double VLAN tagged frame | 13,822,385,271     | 13,822,385,271      | 2,981      |
| eth3  | RX promiscuous frame                   | 12,997,163,923     | 12,997,163,923      | 2,975      |
| eth3  | TX 64-byte frame                       | 632,235,963        | 632,235,963         | 32         |
| eth3  | TX 65 to 127 byte frame                | 3,747,934,802      | 3,747,934,802       | 537        |
| eth3  | TX 128 to 255 byte frame               | 652,637,477        | 652,637,477         | 84         |
| eth3  | TX 256 to 511 byte frame               | 445,416,563        | 445,416,563         | 63         |
| eth3  | TX 512 to 1023 byte frame              | 564,383,336        | 564,383,336         | 56         |
| eth3  | TX 1024 to 1518 byte frame             | 11,559,386,570     | 11,559,386,570      | 4,552      |
| eth3  | TX 1519 to 1522 byte frame             | 12,234,752,510     | 12,234,752,510      | 1,593      |
| eth3  | TX 1519 to 2047 byte frame             | 12,234,752,510     | 12,234,752,510      | 1,593      |
| eth3  | TX Broadcast frame                     | 2,590,169          | 2,590,169           | 0          |
| eth3  | TX all packets frame                   | 29,836,747,223     | 29,836,747,223      | 6,915      |
| eth3  | TX good frame                          | 29,836,747,223     | 29,836,747,223      | 6,914      |
| eth3  | TX UC frame                            | 29,832,597,784     | 29,832,597,784      | 6,914      |
| eth3  | TX MC frame                            | 1,559,270          | 1,559,270           | 0          |
| eth3  | TX single and double VLAN tagged frame | 29,836,183,581     | 29,836,183,581      | 6,906      |
| eth3  | RX Byte frame                          | 5,952,304,945,939  | 5,952,304,945,939   | 503,313    |
| eth3  | TX Byte frame                          | 36,190,445,783,979 | 36,190,445,783,979  | 8,933,907  |
| eth4  | RX 64-byte frame                       | 35,688,751         | 35,688,751          | 0          |
| eth4  | RX 65 to 127 byte frame                | 4,318,054,682      | 4,318,054,682       | 423        |
| eth4  | RX 128 to 255 byte frame               | 813,044,493        | 813,044,493         | 158        |
| eth4  | RX 256 to 511 byte frame               | 139,951,530        | 139,951,530         | 21         |
| eth4  | RX 512 to 1023 byte frame              | 173,952,344        | 173,952,344         | 33         |
| eth4  | RX 1024 to 1518 byte frame             | 1,808,216,323      | 1,808,216,323       | 163        |
| eth4  | RX 1519 to 1522 byte frame             | 290,162,217        | 290,162,217         | 1          |
| eth4  | RX 1519 to 2047 byte frame             | 290,162,217        | 290,162,217         | 1          |
| eth4  | RX BC frame                            | 4,657,101          | 4,657,101           | 0          |
| eth4  | RX RPROG0 frame                        | 2,977,695,026      | 2,977,695,026       | 312        |
| eth4  | RX RPROG1 frame                        | 643,266,425        | 643,266,425         | 67         |
| eth4  | RX RPROG2 frame                        | 348,326,225        | 348,326,225         | 27         |
| eth4  | RX RPROG3 frame                        | 384,455,757        | 384,455,757         | 18         |
| eth4  | RX all packets frame                   | 7,579,070,341      | 7,579,070,341       | 801        |
| eth4  | RX good frame                          | 7,576,226,282      | 7,576,226,282       | 801        |
| eth4  | RX UC frame                            | 7,566,402,985      | 7,566,402,985       | 801        |
| eth4  | RX MC frame                            | 5,166,196          | 5,166,196           | 0          |
| eth4  | RX out-of-range length frame           | 2,844,059          | 2,844,059           | 0          |
| eth4  | RX single and double VLAN tagged frame | 7,579,070,343      | 7,579,070,343       | 803        |
| eth4  | RX promiscuous frame                   | 7,276,240,770      | 7,276,240,770       | 802        |
| eth4  | TX 64-byte frame                       | 314,710,883        | 314,710,883         | 46         |
| eth4  | TX 65 to 127 byte frame                | 2,015,529,589      | 2,015,529,589       | 219        |
| eth4  | TX 128 to 255 byte frame               | 540,859,021        | 540,859,021         | 138        |
| eth4  | TX 256 to 511 byte frame               | 315,344,471        | 315,344,471         | 67         |
| eth4  | TX 512 to 1023 byte frame              | 501,848,529        | 501,848,529         | 85         |
| eth4  | TX 1024 to 1518 byte frame             | 4,950,740,538      | 4,950,740,538       | 178        |
| eth4  | TX 1519 to 1522 byte frame             | 5,276,592,391      | 5,276,592,391       | 748        |
| eth4  | TX 1519 to 2047 byte frame             | 5,276,592,391      | 5,276,592,391       | 748        |
| eth4  | TX Broadcast frame                     | 3,408,316          | 3,408,316           | 0          |
| eth4  | TX all packets frame                   | 13,915,625,422     | 13,915,625,422      | 1,473      |
| eth4  | TX good frame                          | 13,915,625,422     | 13,915,625,422      | 1,473      |
| eth4  | TX UC frame                            | 13,910,657,887     | 13,910,657,887      | 1,473      |
| eth4  | TX MC frame                            | 1,559,219          | 1,559,219           | 0          |
| eth4  | TX single and double VLAN tagged frame | 13,915,061,781     | 13,915,061,781      | 1,473      |
| eth4  | RX Byte frame                          | 3,733,527,594,617  | 3,733,527,594,617   | 326,085    |
| eth4  | TX Byte frame                          | 15,943,303,949,451 | 15,943,303,949,451  | 1,521,484  |
| eth32 | RX NIF BIP error count                 | 191                | 191                 | 0          |
| eth32 | RX 64-byte frame                       | 1,602,866,306      | 1,602,866,306       | 78         |
| eth32 | RX 65 to 127 byte frame                | 10,107,196,845     | 10,107,196,845      | 1,678      |
| eth32 | RX 128 to 255 byte frame               | 1,824,057,367      | 1,824,057,367       | 312        |
| eth32 | RX 256 to 511 byte frame               | 1,203,756,105      | 1,203,756,105       | 186        |
| eth32 | RX 512 to 1023 byte frame              | 1,668,739,918      | 1,668,739,918       | 295        |
| eth32 | RX 1024 to 1518 byte frame             | 33,988,319,425     | 33,988,319,425      | 7,064      |
| eth32 | RX 1519 to 1522 byte frame             | 29,827,569,714     | 29,827,569,714      | 770        |
| eth32 | RX 1519 to 2047 byte frame             | 29,827,570,935     | 29,827,570,935      | 770        |
| eth32 | RX BC frame                            | 25,915,962         | 25,915,962          | 1          |
| eth32 | RX RPROG0 frame                        | 8,566,848,958      | 8,566,848,958       | 1,094      |
| eth32 | RX RPROG1 frame                        | 875,073,369        | 875,073,369         | 393        |
| eth32 | RX RPROG2 frame                        | 762,347,053        | 762,347,053         | 133        |
| eth32 | RX RPROG3 frame                        | 1,505,793,771      | 1,505,793,771       | 133        |
| eth32 | RX all packets frame                   | 80,222,506,903     | 80,222,506,903      | 10,378     |
| eth32 | RX good frame                          | 80,222,503,927     | 80,222,503,927      | 10,379     |
| eth32 | RX UC frame                            | 80,191,001,758     | 80,191,001,758      | 10,364     |
| eth32 | RX MC frame                            | 5,586,207          | 5,586,207           | 0          |
| eth32 | RX FCS error frame                     | 2,969              | 2,969               | 0          |
| eth32 | RX code error frame                    | 210                | 210                 | 0          |
| eth32 | RX jabber frame                        | 8                  | 8                   | 0          |
| eth32 | RX single and double VLAN tagged frame | 80,198,588,035     | 80,198,588,035      | 10,368     |
| eth32 | RX promiscuous frame                   | 50,363,432,051     | 50,363,432,051      | 9,597      |
| eth32 | RX fragment frame                      | 2                  | 2                   | 0          |
| eth32 | RX RUNT frame                          | 6                  | 6                   | 0          |
| eth32 | TX 65 to 127 byte frame                | 24,678,302,428     | 24,678,302,428      | 4,019      |
| eth32 | TX 128 to 255 byte frame               | 2,592,667,076      | 2,592,667,076       | 363        |
| eth32 | TX 256 to 511 byte frame               | 1,662,024,285      | 1,662,024,285       | 159        |
| eth32 | TX 512 to 1023 byte frame              | 1,026,951,823      | 1,026,951,823       | 119        |
| eth32 | TX 1024 to 1518 byte frame             | 6,527,868,065      | 6,527,868,065       | 1,183      |
| eth32 | TX 1519 to 1522 byte frame             | 2,017,062,382      | 2,017,062,382       | 23         |
| eth32 | TX 1519 to 2047 byte frame             | 2,017,062,382      | 2,017,062,382       | 23         |
| eth32 | TX Broadcast frame                     | 21,562,761         | 21,562,761          | 1          |
| eth32 | TX all packets frame                   | 38,504,876,059     | 38,504,876,059      | 5,847      |
| eth32 | TX good frame                          | 38,504,876,059     | 38,504,876,059      | 5,845      |
| eth32 | TX UC frame                            | 38,448,151,855     | 38,448,151,855      | 5,842      |
| eth32 | TX MC frame                            | 35,161,443         | 35,161,443          | 2          |
| eth32 | TX single and double VLAN tagged frame | 38,504,312,353     | 38,504,312,353      | 5,844      |
| eth32 | RX Byte frame                          | 97,269,775,461,289 | 97,269,775,461,289  | 11,805,438 |
| eth32 | RX Runt Byte frame                     | 208                | 208                 | 0          |
| eth32 | TX Byte frame                          | 16,124,428,120,862 | 16,124,428,120,862  | 2,306,952  |
==========================================================================================================
>/usr/bin/bcmcmd show counter nz
#############
# NIF Ports #
#############
===============================================================================================
|                                             RX COUNTERS                                     |
===============================================================================================
| Port | snmpIfHCInUcastPkts | snmpIfInNUcastPkts | snmpIfInErrors | snmpEtherStatsRXNoErrors |
===============================================================================================
| 1    | 12,383,486,760      | 17,344,254         | 0              | 12,400,841,869           |
-----------------------------------------------------------------------------------------------
| 2    | 5,178,810,941       | 8,195,377          | 0              | 5,187,006,651            |
-----------------------------------------------------------------------------------------------
| 3    | 13,804,765,527      | 16,708,705         | 0              | 13,822,387,259           |
-----------------------------------------------------------------------------------------------
| 4    | 7,566,403,913       | 9,823,297          | 0              | 7,579,071,269            |
-----------------------------------------------------------------------------------------------
| 32   | 80,191,008,712      | 31,502,169         | 2,983          | 80,222,510,881           |
===============================================================================================
==================================================================================================
|                                               TX COUNTERS                                      |
==================================================================================================
| Port | snmpIfHCOutUcastPkts | snmpIfOutNUcastPkts | snmpIfOutErrors | snmpEtherStatsTXNoErrors |
==================================================================================================
| 1    | 25,153,702,227       | 4,239,743           | 0               | 25,157,941,970           |
--------------------------------------------------------------------------------------------------
| 2    | 11,717,188,931       | 3,720,949           | 0               | 11,720,909,880           |
--------------------------------------------------------------------------------------------------
| 3    | 29,832,600,607       | 4,149,439           | 0               | 29,836,750,046           |
--------------------------------------------------------------------------------------------------
| 4    | 13,910,659,665       | 4,967,535           | 0               | 13,915,627,200           |
--------------------------------------------------------------------------------------------------
| 32   | 38,448,155,623       | 56,724,206          | 0               | 38,504,879,829           |
==================================================================================================
>/usr/bin/bcmcmd vis status
==================================
| Debug Memory Status            |
|     Visibility Mode - "Select" |
==================================
| Core | Block    | NoF | Status |
==================================
| 0    | IPPA(0)  | 10  | Ready  |
| 0    | IPPB(1)  | 43  | Ready  |
| 0    | IPPC(2)  | 5   | Ready  |
| 0    | IPPD(3)  | 18  | Ready  |
| 0    | IPPE(4)  | 4   | Ready  |
| 0    | IPPF(5)  | 21  | Ready  |
| 0    | ERPP(6)  | 17  | Ready  |
| 0    | ETPPA(7) | 6   | Ready  |
| 0    | ETPPB(8) | 8   | Ready  |
| 0    | ETPPC(9) | 10  | Ready  |
==================================
>/usr/bin/bcmcmd vis global mode=always
>/usr/bin/bcmcmd vis resume
>/usr/bin/bcmcmd port status
=======================================================================
|                                 Port status                         |
=======================================================================
| Port      | Ena/Link | Speed | Linkscan | Autoneg | FEC  | Loopback |
=======================================================================
| eth1(1)   | up       |  10G  | HW       | No      | NONE | NONE     |
| eth2(2)   | up       |  10G  | HW       | No      | NONE | NONE     |
| eth3(3)   | up       |  10G  | HW       | No      | NONE | NONE     |
| eth4(4)   | up       |  10G  | HW       | No      | NONE | NONE     |
| eth5(5)   | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth6(6)   | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth7(7)   | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth8(8)   | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth9(9)   | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth10(10) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth11(11) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth12(12) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth13(13) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth14(14) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth15(15) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth16(16) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth17(17) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth18(18) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth19(19) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth20(20) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth21(21) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth22(22) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth23(23) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth24(24) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth25(25) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth26(26) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth27(27) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth28(28) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth29(29) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth30(30) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth31(31) | !ena     |  10G  | None     | No      | NONE | NONE     |
| eth32(32) | up       |  10G  | HW       | No      | NONE | NONE     |
| eth33(33) | !ena     | 100G  | None     | No      | NONE | NONE     |
| eth34(34) | !ena     | 100G  | None     | No      | NONE | NONE     |
| eth35(35) | !ena     | 100G  | None     | No      | NONE | NONE     |
| eth36(36) | !ena     | 100G  | None     | No      | NONE | NONE     |
=======================================================================
>/usr/bin/bcmcmd vis lag
==================================================
|                              LAGs              |
==================================================
| Pool | Group | Core | PP Port | Enable | Force |
==================================================
| 0    | 1     | 0    | 96      | 1      | 0     |
| 0    | 2     | 0    | 97      | 1      | 0     |
| 0    | 3     | 0    | 98      | 1      | 0     |
| 0    | 4     | 0    | 99      | 1      | 0     |
| 0    | 5     | 0    | 100     | 1      | 0     |
| 0    | 6     | 0    | 101     | 1      | 0     |
| 0    | 7     | 0    | 102     | 1      | 0     |
| 0    | 8     | 0    | 103     | 1      | 0     |
| 0    | 9     | 0    | 104     | 1      | 0     |
| 0    | 10    | 0    | 105     | 1      | 0     |
| 0    | 11    | 0    | 106     | 1      | 0     |
| 0    | 12    | 0    | 107     | 1      | 0     |
| 0    | 13    | 0    | 108     | 1      | 0     |
| 0    | 14    | 0    | 109     | 1      | 0     |
| 0    | 15    | 0    | 110     | 1      | 0     |
| 0    | 16    | 0    | 111     | 1      | 0     |
| 0    | 17    | 0    | 112     | 1      | 0     |
| 0    | 18    | 0    | 113     | 1      | 0     |
| 0    | 19    | 0    | 114     | 1      | 0     |
| 0    | 20    | 0    | 115     | 1      | 0     |
| 0    | 21    | 0    | 116     | 1      | 0     |
| 0    | 22    | 0    | 117     | 1      | 0     |
| 0    | 23    | 0    | 118     | 1      | 0     |
| 0    | 24    | 0    | 119     | 1      | 0     |
| 0    | 25    | 0    | 120     | 1      | 0     |
| 0    | 26    | 0    | 121     | 1      | 0     |
| 0    | 27    | 0    | 122     | 1      | 0     |
| 0    | 28    | 0    | 123     | 1      | 0     |
| 0    | 29    | 0    | 124     | 1      | 0     |
| 0    | 30    | 0    | 125     | 1      | 0     |
| 0    | 31    | 0    | 126     | 1      | 0     |
| 0    | 32    | 0    | 127     | 1      | 0     |
| 0    | 33    | 0    | 128     | 1      | 0     |
| 0    | 34    | 0    | 129     | 1      | 0     |
| 0    | 35    | 0    | 130     | 1      | 0     |
| 0    | 36    | 0    | 131     | 1      | 0     |
==================================================
>/usr/bin/bcmcmd vis port
========================================================================================
|                              Visibility Status Per Port                              |
========================================================================================
| Name          | PP   | PP  | Type       | Core | Ingress | Ingress | Egress | Egress |
|               | Port | DSP |            |      | Enable  | Force   | Enable | Force  |
========================================================================================
| cpu0          | 0    | 0   | CPU        | 0    | 0       | 1       | 0      | 1      |
| eth1          | 1    | 1   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth2          | 2    | 2   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth3          | 3    | 3   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth4          | 4    | 4   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth5          | 5    | 5   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth6          | 6    | 6   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth7          | 7    | 7   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth8          | 8    | 8   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth9          | 9    | 9   | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth10         | 10   | 10  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth11         | 11   | 11  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth12         | 12   | 12  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth13         | 13   | 13  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth14         | 14   | 14  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth15         | 15   | 15  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth16         | 16   | 16  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth17         | 17   | 17  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth18         | 18   | 18  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth19         | 19   | 19  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth20         | 20   | 20  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth21         | 21   | 21  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth22         | 22   | 22  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth23         | 23   | 23  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth24         | 24   | 24  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth25         | 25   | 25  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth26         | 26   | 26  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth27         | 27   | 27  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth28         | 28   | 28  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth29         | 29   | 29  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth30         | 30   | 30  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth31         | 31   | 31  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth32         | 32   | 32  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth33         | 33   | 33  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth34         | 34   | 34  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth35         | 35   | 35  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| eth36         | 36   | 36  | NIF_ETH    | 0    | 0       | 1       | 0      | 1      |
| cpu66         | 37   | 66  | CPU        | 0    | 0       | 1       | 0      | 1      |
| cpu69         | 38   | 69  | CPU        | 0    | 0       | 1       | 0      | 1      |
| cpu70         | 39   | 70  | CPU        | 0    | 0       | 1       | 0      | 1      |
| rcy71         | 40   | 71  | RCY        | 0    | 0       | 1       | 0      | 1      |
| rcy76         | 41   | 76  | RCY        | 0    | 0       | 1       | 0      | 1      |
| rcy78         | 42   | 78  | RCY        | 0    | 0       | 1       | 0      | 1      |
| rcy_mirror100 | 43   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror101 | 44   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror102 | 45   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror103 | 46   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror104 | 47   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror105 | 48   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror106 | 49   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror107 | 50   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror108 | 51   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror109 | 52   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror110 | 53   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror111 | 54   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror112 | 55   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror113 | 56   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror114 | 57   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror115 | 58   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror116 | 59   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror117 | 60   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror118 | 61   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror119 | 62   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror120 | 63   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror121 | 64   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror122 | 65   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror123 | 66   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror124 | 67   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror125 | 68   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror126 | 69   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror127 | 70   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror128 | 71   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror129 | 72   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror130 | 73   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror131 | 74   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror132 | 75   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror133 | 76   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror134 | 77   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror135 | 78   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror136 | 79   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror137 | 80   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror138 | 81   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror139 | 82   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror140 | 83   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror141 | 84   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror142 | 85   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror143 | 86   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror144 | 87   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror145 | 88   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror146 | 89   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror147 | 90   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror148 | 91   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| rcy_mirror149 | 92   | -1  | RCY_MIRROR | 0    | 0       | 1       | -1     | -1     |
| sat218        | 93   | 218 | SAT        | 0    | 0       | 1       | 0      | 1      |
| oamp232       | 94   | 232 | OAMP       | 0    | 0       | 1       | 0      | 1      |
| olp240        | 95   | 240 | OLP        | 0    | 0       | 1       | 0      | 1      |
========================================================================================
>/usr/bin/bcmcmd pbmp
===========================================================
|                       Current Bitmaps                   |
===========================================================
| Ports | Bit(s)                                          |
===========================================================
| XE    | 1-32                                            |
-----------------------------------------------------------
| CE    | 33-36                                           |
-----------------------------------------------------------
| E     | 0-36, 66, 69-70, 78, 218, 232                   |
-----------------------------------------------------------
| RCY   | 71, 76, 78                                      |
-----------------------------------------------------------
| PORT  | 1-36                                            |
-----------------------------------------------------------
| CPU   | 0, 66, 69-70                                    |
-----------------------------------------------------------
| SAT   | 218                                             |
-----------------------------------------------------------
| OLP   | 240                                             |
-----------------------------------------------------------
| OAMP  | 232                                             |
-----------------------------------------------------------
| NIF   | 1-36                                            |
-----------------------------------------------------------
| ALL   | 0-36, 66, 69-71, 76, 78, 100-149, 218, 232, 240 |
===========================================================
>/usr/bin/bcmcmd port mgmt dump
==================================================================
|                                 PORT MGMT                      |
==================================================================
| Port | Type       | Core | First | IN   | PP  | OUT  | Channel |
|      |            |      | PHY   | TM   | DSP | TM   |         |
|      |            |      |       | Port |     | Port |         |
==================================================================
| 0    | CPU        | 0    | -1    | 0    | 0   | 0    | 0       |
| 1    | NIF_ETH    | 0    | 16    | 1    | 1   | 1    | 0       |
| 2    | NIF_ETH    | 0    | 17    | 2    | 2   | 2    | 0       |
| 3    | NIF_ETH    | 0    | 20    | 3    | 3   | 3    | 0       |
| 4    | NIF_ETH    | 0    | 21    | 4    | 4   | 4    | 0       |
| 5    | NIF_ETH    | 0    | 24    | 5    | 5   | 5    | 0       |
| 6    | NIF_ETH    | 0    | 25    | 6    | 6   | 6    | 0       |
| 7    | NIF_ETH    | 0    | 28    | 7    | 7   | 7    | 0       |
| 8    | NIF_ETH    | 0    | 29    | 8    | 8   | 8    | 0       |
| 9    | NIF_ETH    | 0    | 32    | 9    | 9   | 9    | 0       |
| 10   | NIF_ETH    | 0    | 33    | 10   | 10  | 10   | 0       |
| 11   | NIF_ETH    | 0    | 36    | 11   | 11  | 11   | 0       |
| 12   | NIF_ETH    | 0    | 37    | 12   | 12  | 12   | 0       |
| 13   | NIF_ETH    | 0    | 40    | 13   | 13  | 13   | 0       |
| 14   | NIF_ETH    | 0    | 41    | 14   | 14  | 14   | 0       |
| 15   | NIF_ETH    | 0    | 44    | 15   | 15  | 15   | 0       |
| 16   | NIF_ETH    | 0    | 45    | 16   | 16  | 16   | 0       |
| 17   | NIF_ETH    | 0    | 18    | 17   | 17  | 17   | 0       |
| 18   | NIF_ETH    | 0    | 19    | 18   | 18  | 18   | 0       |
| 19   | NIF_ETH    | 0    | 22    | 19   | 19  | 19   | 0       |
| 20   | NIF_ETH    | 0    | 23    | 20   | 20  | 20   | 0       |
| 21   | NIF_ETH    | 0    | 26    | 21   | 21  | 21   | 0       |
| 22   | NIF_ETH    | 0    | 27    | 22   | 22  | 22   | 0       |
| 23   | NIF_ETH    | 0    | 30    | 23   | 23  | 23   | 0       |
| 24   | NIF_ETH    | 0    | 31    | 24   | 24  | 24   | 0       |
| 25   | NIF_ETH    | 0    | 34    | 25   | 25  | 25   | 0       |
| 26   | NIF_ETH    | 0    | 35    | 26   | 26  | 26   | 0       |
| 27   | NIF_ETH    | 0    | 38    | 27   | 27  | 27   | 0       |
| 28   | NIF_ETH    | 0    | 39    | 28   | 28  | 28   | 0       |
| 29   | NIF_ETH    | 0    | 42    | 29   | 29  | 29   | 0       |
| 30   | NIF_ETH    | 0    | 43    | 30   | 30  | 30   | 0       |
| 31   | NIF_ETH    | 0    | 46    | 31   | 31  | 31   | 0       |
| 32   | NIF_ETH    | 0    | 47    | 32   | 32  | 32   | 0       |
| 33   | NIF_ETH    | 0    | 0     | 33   | 33  | 33   | 0       |
| 34   | NIF_ETH    | 0    | 4     | 34   | 34  | 34   | 0       |
| 35   | NIF_ETH    | 0    | 12    | 35   | 35  | 35   | 0       |
| 36   | NIF_ETH    | 0    | 8     | 36   | 36  | 36   | 0       |
| 66   | CPU        | 0    | -1    | 66   | 66  | 66   | 8       |
| 69   | CPU        | 0    | -1    | 69   | 69  | 69   | 16      |
| 70   | CPU        | 0    | -1    | 70   | 70  | 70   | 24      |
| 71   | RCY        | 0    | -1    | 71   | 71  | 71   | 2       |
| 76   | RCY        | 0    | -1    | 76   | 76  | 76   | 0       |
| 78   | RCY        | 0    | -1    | 78   | 78  | 78   | 1       |
| 100  | RCY_MIRROR | 0    | -1    | 100  | -1  | -1   | 0       |
| 101  | RCY_MIRROR | 0    | -1    | 101  | -1  | -1   | 1       |
| 102  | RCY_MIRROR | 0    | -1    | 102  | -1  | -1   | 2       |
| 103  | RCY_MIRROR | 0    | -1    | 103  | -1  | -1   | 3       |
| 104  | RCY_MIRROR | 0    | -1    | 104  | -1  | -1   | 4       |
| 105  | RCY_MIRROR | 0    | -1    | 105  | -1  | -1   | 5       |
| 106  | RCY_MIRROR | 0    | -1    | 106  | -1  | -1   | 6       |
| 107  | RCY_MIRROR | 0    | -1    | 107  | -1  | -1   | 7       |
| 108  | RCY_MIRROR | 0    | -1    | 108  | -1  | -1   | 8       |
| 109  | RCY_MIRROR | 0    | -1    | 109  | -1  | -1   | 9       |
| 110  | RCY_MIRROR | 0    | -1    | 110  | -1  | -1   | 10      |
| 111  | RCY_MIRROR | 0    | -1    | 111  | -1  | -1   | 11      |
| 112  | RCY_MIRROR | 0    | -1    | 112  | -1  | -1   | 12      |
| 113  | RCY_MIRROR | 0    | -1    | 113  | -1  | -1   | 13      |
| 114  | RCY_MIRROR | 0    | -1    | 114  | -1  | -1   | 14      |
| 115  | RCY_MIRROR | 0    | -1    | 115  | -1  | -1   | 15      |
| 116  | RCY_MIRROR | 0    | -1    | 116  | -1  | -1   | 16      |
| 117  | RCY_MIRROR | 0    | -1    | 117  | -1  | -1   | 17      |
| 118  | RCY_MIRROR | 0    | -1    | 118  | -1  | -1   | 18      |
| 119  | RCY_MIRROR | 0    | -1    | 119  | -1  | -1   | 19      |
| 120  | RCY_MIRROR | 0    | -1    | 120  | -1  | -1   | 20      |
| 121  | RCY_MIRROR | 0    | -1    | 121  | -1  | -1   | 21      |
| 122  | RCY_MIRROR | 0    | -1    | 122  | -1  | -1   | 22      |
| 123  | RCY_MIRROR | 0    | -1    | 123  | -1  | -1   | 23      |
| 124  | RCY_MIRROR | 0    | -1    | 124  | -1  | -1   | 24      |
| 125  | RCY_MIRROR | 0    | -1    | 125  | -1  | -1   | 25      |
| 126  | RCY_MIRROR | 0    | -1    | 126  | -1  | -1   | 26      |
| 127  | RCY_MIRROR | 0    | -1    | 127  | -1  | -1   | 27      |
| 128  | RCY_MIRROR | 0    | -1    | 128  | -1  | -1   | 28      |
| 129  | RCY_MIRROR | 0    | -1    | 129  | -1  | -1   | 29      |
| 130  | RCY_MIRROR | 0    | -1    | 130  | -1  | -1   | 30      |
| 131  | RCY_MIRROR | 0    | -1    | 131  | -1  | -1   | 31      |
| 132  | RCY_MIRROR | 0    | -1    | 132  | -1  | -1   | 32      |
| 133  | RCY_MIRROR | 0    | -1    | 133  | -1  | -1   | 33      |
| 134  | RCY_MIRROR | 0    | -1    | 134  | -1  | -1   | 34      |
| 135  | RCY_MIRROR | 0    | -1    | 135  | -1  | -1   | 35      |
| 136  | RCY_MIRROR | 0    | -1    | 136  | -1  | -1   | 36      |
| 137  | RCY_MIRROR | 0    | -1    | 137  | -1  | -1   | 37      |
| 138  | RCY_MIRROR | 0    | -1    | 138  | -1  | -1   | 38      |
| 139  | RCY_MIRROR | 0    | -1    | 139  | -1  | -1   | 39      |
| 140  | RCY_MIRROR | 0    | -1    | 140  | -1  | -1   | 40      |
| 141  | RCY_MIRROR | 0    | -1    | 141  | -1  | -1   | 41      |
| 142  | RCY_MIRROR | 0    | -1    | 142  | -1  | -1   | 42      |
| 143  | RCY_MIRROR | 0    | -1    | 143  | -1  | -1   | 43      |
| 144  | RCY_MIRROR | 0    | -1    | 144  | -1  | -1   | 44      |
| 145  | RCY_MIRROR | 0    | -1    | 145  | -1  | -1   | 45      |
| 146  | RCY_MIRROR | 0    | -1    | 146  | -1  | -1   | 46      |
| 147  | RCY_MIRROR | 0    | -1    | 147  | -1  | -1   | 47      |
| 148  | RCY_MIRROR | 0    | -1    | 148  | -1  | -1   | 48      |
| 149  | RCY_MIRROR | 0    | -1    | 149  | -1  | -1   | 49      |
| 218  | SAT        | 0    | -1    | 218  | 218 | 218  | 0       |
| 232  | OAMP       | 0    | -1    | 232  | 232 | 232  | 0       |
| 240  | OLP        | 0    | -1    | 240  | 240 | 240  | 0       |
==================================================================
>/usr/bin/bcmcmd port mgmt dump full
==================================================================
|                            PORT MGMT FULL                      |
==================================================================
| Port | Module    | Property                     | Value        |
==================================================================
| 0    | LOGICAL   | type                         | CPU          |
|      |           | if offset                    | -1           |
|      |           | master                       | 0            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 0            |
|      |           | pp dsp                       | 0            |
|      |           | out tm port                  | 0            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 0            |
|      |           | channels                     | 0, 66, 69-70 |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 0            |
|      |           | egress interface             | 0            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 0            |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 8            |
|      |           | base_hr                      | 0            |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 0            |
==================================================================
| 1    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 16           |
|      |           | master                       | 1            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 16           |
|      |           | phys                         | 16           |
|      |           | logical fifos                | 0            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 1            |
|      |           | pp dsp                       | 1            |
|      |           | out tm port                  | 1            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 1            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 1            |
|      |           | egress interface             | 32           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 8            |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 32           |
|      |           | base_hr                      | 8            |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 1            |
==================================================================
| 2    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 17           |
|      |           | master                       | 2            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 17           |
|      |           | phys                         | 17           |
|      |           | logical fifos                | 1            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 2            |
|      |           | pp dsp                       | 2            |
|      |           | out tm port                  | 2            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 2            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 2            |
|      |           | egress interface             | 33           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 10           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 33           |
|      |           | base_hr                      | 10           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 2            |
==================================================================
| 3    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 20           |
|      |           | master                       | 3            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 20           |
|      |           | phys                         | 20           |
|      |           | logical fifos                | 2            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 3            |
|      |           | pp dsp                       | 3            |
|      |           | out tm port                  | 3            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 3            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 3            |
|      |           | egress interface             | 34           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 12           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 34           |
|      |           | base_hr                      | 12           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 3            |
==================================================================
| 4    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 21           |
|      |           | master                       | 4            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 21           |
|      |           | phys                         | 21           |
|      |           | logical fifos                | 3            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 4            |
|      |           | pp dsp                       | 4            |
|      |           | out tm port                  | 4            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 4            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 4            |
|      |           | egress interface             | 35           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 14           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 35           |
|      |           | base_hr                      | 14           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 4            |
==================================================================
| 5    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 24           |
|      |           | master                       | 5            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 24           |
|      |           | phys                         | 24           |
|      |           | logical fifos                | 4            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 5            |
|      |           | pp dsp                       | 5            |
|      |           | out tm port                  | 5            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 5            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 5            |
|      |           | egress interface             | 36           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 16           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 36           |
|      |           | base_hr                      | 16           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 5            |
==================================================================
| 6    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 25           |
|      |           | master                       | 6            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 25           |
|      |           | phys                         | 25           |
|      |           | logical fifos                | 5            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 6            |
|      |           | pp dsp                       | 6            |
|      |           | out tm port                  | 6            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 6            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 6            |
|      |           | egress interface             | 37           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 18           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 37           |
|      |           | base_hr                      | 18           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 6            |
==================================================================
| 7    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 28           |
|      |           | master                       | 7            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 28           |
|      |           | phys                         | 28           |
|      |           | logical fifos                | 0            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 7            |
|      |           | pp dsp                       | 7            |
|      |           | out tm port                  | 7            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 7            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 7            |
|      |           | egress interface             | 38           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 20           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 38           |
|      |           | base_hr                      | 20           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 7            |
==================================================================
| 8    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 29           |
|      |           | master                       | 8            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 29           |
|      |           | phys                         | 29           |
|      |           | logical fifos                | 1            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 8            |
|      |           | pp dsp                       | 8            |
|      |           | out tm port                  | 8            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 8            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 8            |
|      |           | egress interface             | 39           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 22           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 39           |
|      |           | base_hr                      | 22           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 8            |
==================================================================
| 9    | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 32           |
|      |           | master                       | 9            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 32           |
|      |           | phys                         | 32           |
|      |           | logical fifos                | 2            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 9            |
|      |           | pp dsp                       | 9            |
|      |           | out tm port                  | 9            |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 9            |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 9            |
|      |           | egress interface             | 40           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 24           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 40           |
|      |           | base_hr                      | 24           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 9            |
==================================================================
| 10   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 33           |
|      |           | master                       | 10           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 33           |
|      |           | phys                         | 33           |
|      |           | logical fifos                | 3            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 10           |
|      |           | pp dsp                       | 10           |
|      |           | out tm port                  | 10           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 10           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 10           |
|      |           | egress interface             | 41           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 26           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 41           |
|      |           | base_hr                      | 26           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 10           |
==================================================================
| 11   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 36           |
|      |           | master                       | 11           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 36           |
|      |           | phys                         | 36           |
|      |           | logical fifos                | 4            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 11           |
|      |           | pp dsp                       | 11           |
|      |           | out tm port                  | 11           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 11           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 11           |
|      |           | egress interface             | 42           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 28           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 42           |
|      |           | base_hr                      | 28           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 11           |
==================================================================
| 12   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 37           |
|      |           | master                       | 12           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 37           |
|      |           | phys                         | 37           |
|      |           | logical fifos                | 5            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 12           |
|      |           | pp dsp                       | 12           |
|      |           | out tm port                  | 12           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 12           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 12           |
|      |           | egress interface             | 43           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 30           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 43           |
|      |           | base_hr                      | 30           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 12           |
==================================================================
| 13   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 40           |
|      |           | master                       | 13           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 40           |
|      |           | phys                         | 40           |
|      |           | logical fifos                | 0            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 13           |
|      |           | pp dsp                       | 13           |
|      |           | out tm port                  | 13           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 13           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 13           |
|      |           | egress interface             | 44           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 32           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 44           |
|      |           | base_hr                      | 32           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 13           |
==================================================================
| 14   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 41           |
|      |           | master                       | 14           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 41           |
|      |           | phys                         | 41           |
|      |           | logical fifos                | 1            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 14           |
|      |           | pp dsp                       | 14           |
|      |           | out tm port                  | 14           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 14           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 14           |
|      |           | egress interface             | 45           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 34           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 45           |
|      |           | base_hr                      | 34           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 14           |
==================================================================
| 15   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 44           |
|      |           | master                       | 15           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 44           |
|      |           | phys                         | 44           |
|      |           | logical fifos                | 2            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 15           |
|      |           | pp dsp                       | 15           |
|      |           | out tm port                  | 15           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 15           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 15           |
|      |           | egress interface             | 46           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 36           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 46           |
|      |           | base_hr                      | 36           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 15           |
==================================================================
| 16   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 45           |
|      |           | master                       | 16           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 45           |
|      |           | phys                         | 45           |
|      |           | logical fifos                | 3            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 16           |
|      |           | pp dsp                       | 16           |
|      |           | out tm port                  | 16           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 16           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 16           |
|      |           | egress interface             | 47           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 38           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 47           |
|      |           | base_hr                      | 38           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 16           |
==================================================================
| 17   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 18           |
|      |           | master                       | 17           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 18           |
|      |           | phys                         | 18           |
|      |           | logical fifos                | 6            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 17           |
|      |           | pp dsp                       | 17           |
|      |           | out tm port                  | 17           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 17           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 17           |
|      |           | egress interface             | 48           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 40           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 48           |
|      |           | base_hr                      | 40           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 17           |
==================================================================
| 18   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 19           |
|      |           | master                       | 18           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 19           |
|      |           | phys                         | 19           |
|      |           | logical fifos                | 7            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 18           |
|      |           | pp dsp                       | 18           |
|      |           | out tm port                  | 18           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 18           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 18           |
|      |           | egress interface             | 49           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 42           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 49           |
|      |           | base_hr                      | 42           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 18           |
==================================================================
| 19   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 22           |
|      |           | master                       | 19           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 22           |
|      |           | phys                         | 22           |
|      |           | logical fifos                | 8            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 19           |
|      |           | pp dsp                       | 19           |
|      |           | out tm port                  | 19           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 19           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 19           |
|      |           | egress interface             | 50           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 44           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 50           |
|      |           | base_hr                      | 44           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 19           |
==================================================================
| 20   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 23           |
|      |           | master                       | 20           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 23           |
|      |           | phys                         | 23           |
|      |           | logical fifos                | 9            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 20           |
|      |           | pp dsp                       | 20           |
|      |           | out tm port                  | 20           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 20           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 20           |
|      |           | egress interface             | 51           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 46           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 51           |
|      |           | base_hr                      | 46           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 20           |
==================================================================
| 21   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 26           |
|      |           | master                       | 21           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 26           |
|      |           | phys                         | 26           |
|      |           | logical fifos                | 10           |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 21           |
|      |           | pp dsp                       | 21           |
|      |           | out tm port                  | 21           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 21           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 21           |
|      |           | egress interface             | 52           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 48           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 52           |
|      |           | base_hr                      | 48           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 21           |
==================================================================
| 22   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 27           |
|      |           | master                       | 22           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 27           |
|      |           | phys                         | 27           |
|      |           | logical fifos                | 11           |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 22           |
|      |           | pp dsp                       | 22           |
|      |           | out tm port                  | 22           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 22           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 22           |
|      |           | egress interface             | 53           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 50           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 53           |
|      |           | base_hr                      | 50           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 22           |
==================================================================
| 23   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 30           |
|      |           | master                       | 23           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 30           |
|      |           | phys                         | 30           |
|      |           | logical fifos                | 6            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 23           |
|      |           | pp dsp                       | 23           |
|      |           | out tm port                  | 23           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 23           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 23           |
|      |           | egress interface             | 54           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 52           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 54           |
|      |           | base_hr                      | 52           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 23           |
==================================================================
| 24   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 31           |
|      |           | master                       | 24           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 31           |
|      |           | phys                         | 31           |
|      |           | logical fifos                | 7            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 24           |
|      |           | pp dsp                       | 24           |
|      |           | out tm port                  | 24           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 24           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 24           |
|      |           | egress interface             | 55           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 54           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 55           |
|      |           | base_hr                      | 54           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 24           |
==================================================================
| 25   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 34           |
|      |           | master                       | 25           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 34           |
|      |           | phys                         | 34           |
|      |           | logical fifos                | 8            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 25           |
|      |           | pp dsp                       | 25           |
|      |           | out tm port                  | 25           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 25           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 25           |
|      |           | egress interface             | 56           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 56           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 56           |
|      |           | base_hr                      | 56           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 25           |
==================================================================
| 26   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 35           |
|      |           | master                       | 26           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 35           |
|      |           | phys                         | 35           |
|      |           | logical fifos                | 9            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 26           |
|      |           | pp dsp                       | 26           |
|      |           | out tm port                  | 26           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 26           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 26           |
|      |           | egress interface             | 57           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 58           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 57           |
|      |           | base_hr                      | 58           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 26           |
==================================================================
| 27   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 38           |
|      |           | master                       | 27           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 38           |
|      |           | phys                         | 38           |
|      |           | logical fifos                | 10           |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 27           |
|      |           | pp dsp                       | 27           |
|      |           | out tm port                  | 27           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 27           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 27           |
|      |           | egress interface             | 58           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 60           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 58           |
|      |           | base_hr                      | 60           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 27           |
==================================================================
| 28   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 39           |
|      |           | master                       | 28           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 39           |
|      |           | phys                         | 39           |
|      |           | logical fifos                | 11           |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 28           |
|      |           | pp dsp                       | 28           |
|      |           | out tm port                  | 28           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 28           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 28           |
|      |           | egress interface             | 59           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 62           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 59           |
|      |           | base_hr                      | 62           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 28           |
==================================================================
| 29   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 42           |
|      |           | master                       | 29           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 42           |
|      |           | phys                         | 42           |
|      |           | logical fifos                | 4            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 29           |
|      |           | pp dsp                       | 29           |
|      |           | out tm port                  | 29           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 29           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 29           |
|      |           | egress interface             | 60           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 64           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 60           |
|      |           | base_hr                      | 64           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 29           |
==================================================================
| 30   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 43           |
|      |           | master                       | 30           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 43           |
|      |           | phys                         | 43           |
|      |           | logical fifos                | 5            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 30           |
|      |           | pp dsp                       | 30           |
|      |           | out tm port                  | 30           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 30           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 30           |
|      |           | egress interface             | 61           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 66           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 61           |
|      |           | base_hr                      | 66           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 30           |
==================================================================
| 31   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 46           |
|      |           | master                       | 31           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 46           |
|      |           | phys                         | 46           |
|      |           | logical fifos                | 6            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 31           |
|      |           | pp dsp                       | 31           |
|      |           | out tm port                  | 31           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 31           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 31           |
|      |           | egress interface             | 62           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 68           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 62           |
|      |           | base_hr                      | 68           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 31           |
==================================================================
| 32   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 47           |
|      |           | master                       | 32           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | NIF       | first phy                    | 47           |
|      |           | phys                         | 47           |
|      |           | logical fifos                | 7            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 32           |
|      |           | pp dsp                       | 32           |
|      |           | out tm port                  | 32           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 32           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 32           |
|      |           | egress interface             | 63           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 70           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 63           |
|      |           | base_hr                      | 70           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 32           |
==================================================================
| 33   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 0            |
|      |           | master                       | 33           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:100000    |
|      |           |                              | Tx:100000    |
------------------------------------------------------------------
|      | NIF       | first phy                    | 0            |
|      |           | phys                         | 0-3          |
|      |           | logical fifos                | 0            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 33           |
|      |           | pp dsp                       | 33           |
|      |           | out tm port                  | 33           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 33           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 33           |
|      |           | egress interface             | 64           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 72           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 64           |
|      |           | base_hr                      | 72           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 33           |
==================================================================
| 34   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 1            |
|      |           | master                       | 34           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:100000    |
|      |           |                              | Tx:100000    |
------------------------------------------------------------------
|      | NIF       | first phy                    | 4            |
|      |           | phys                         | 4-7          |
|      |           | logical fifos                | 1            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 34           |
|      |           | pp dsp                       | 34           |
|      |           | out tm port                  | 34           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 34           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 34           |
|      |           | egress interface             | 65           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 74           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 65           |
|      |           | base_hr                      | 74           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 34           |
==================================================================
| 35   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 3            |
|      |           | master                       | 35           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:100000    |
|      |           |                              | Tx:100000    |
------------------------------------------------------------------
|      | NIF       | first phy                    | 12           |
|      |           | phys                         | 12-15        |
|      |           | logical fifos                | 0            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 35           |
|      |           | pp dsp                       | 35           |
|      |           | out tm port                  | 35           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 35           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 35           |
|      |           | egress interface             | 66           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 76           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 66           |
|      |           | base_hr                      | 76           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 35           |
==================================================================
| 36   | LOGICAL   | type                         | NIF_ETH      |
|      |           | if offset                    | 2            |
|      |           | master                       | 36           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:100000    |
|      |           |                              | Tx:100000    |
------------------------------------------------------------------
|      | NIF       | first phy                    | 8            |
|      |           | phys                         | 8-11         |
|      |           | logical fifos                | 1            |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 36           |
|      |           | pp dsp                       | 36           |
|      |           | out tm port                  | 36           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 36           |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 36           |
|      |           | egress interface             | 67           |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 78           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 67           |
|      |           | base_hr                      | 78           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 36           |
==================================================================
| 66   | LOGICAL   | type                         | CPU          |
|      |           | if offset                    | -1           |
|      |           | master                       | 0            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 66           |
|      |           | pp dsp                       | 66           |
|      |           | out tm port                  | 66           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 8            |
|      |           | channels                     | 0, 66, 69-70 |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 0            |
|      |           | egress interface             | 0            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 80           |
|      |           | nof priorities               | 8            |
|      |           | scheduler interface          | 8            |
|      |           | base_hr                      | 80           |
|      |           | sch priorities               | 8            |
|      |           | pp port                      | 37           |
==================================================================
| 69   | LOGICAL   | type                         | CPU          |
|      |           | if offset                    | -1           |
|      |           | master                       | 0            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 69           |
|      |           | pp dsp                       | 69           |
|      |           | out tm port                  | 69           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 16           |
|      |           | channels                     | 0, 66, 69-70 |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 0            |
|      |           | egress interface             | 0            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 2            |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 8            |
|      |           | base_hr                      | 2            |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 38           |
==================================================================
| 70   | LOGICAL   | type                         | CPU          |
|      |           | if offset                    | -1           |
|      |           | master                       | 0            |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 70           |
|      |           | pp dsp                       | 70           |
|      |           | out tm port                  | 70           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 24           |
|      |           | channels                     | 0, 66, 69-70 |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 0            |
|      |           | egress interface             | 0            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 4            |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 8            |
|      |           | base_hr                      | 4            |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 39           |
==================================================================
| 71   | LOGICAL   | type                         | RCY          |
|      |           | if offset                    | 0            |
|      |           | master                       | 71           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 71           |
|      |           | pp dsp                       | 71           |
|      |           | out tm port                  | 71           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 2            |
|      |           | channels                     | 71, 76, 78   |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 71           |
|      |           | egress interface             | 4            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 88           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 9            |
|      |           | base_hr                      | 88           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 40           |
==================================================================
| 76   | LOGICAL   | type                         | RCY          |
|      |           | if offset                    | 0            |
|      |           | master                       | 71           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 76           |
|      |           | pp dsp                       | 76           |
|      |           | out tm port                  | 76           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 0            |
|      |           | channels                     | 71, 76, 78   |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 71           |
|      |           | egress interface             | 4            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 90           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 9            |
|      |           | base_hr                      | 90           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 41           |
==================================================================
| 78   | LOGICAL   | type                         | RCY          |
|      |           | if offset                    | 0            |
|      |           | master                       | 71           |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 78           |
|      |           | pp dsp                       | 78           |
|      |           | out tm port                  | 78           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 1            |
|      |           | channels                     | 71, 76, 78   |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 71           |
|      |           | egress interface             | 4            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 92           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 9            |
|      |           | base_hr                      | 92           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 42           |
==================================================================
| 100  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 100          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 0            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 43           |
==================================================================
| 101  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 101          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 1            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 44           |
==================================================================
| 102  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 102          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 2            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 45           |
==================================================================
| 103  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 103          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 3            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 46           |
==================================================================
| 104  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 104          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 4            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 47           |
==================================================================
| 105  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 105          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 5            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 48           |
==================================================================
| 106  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 106          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 6            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 49           |
==================================================================
| 107  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 107          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 7            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 50           |
==================================================================
| 108  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 108          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 8            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 51           |
==================================================================
| 109  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 109          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 9            |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 52           |
==================================================================
| 110  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 110          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 10           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 53           |
==================================================================
| 111  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 111          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 11           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 54           |
==================================================================
| 112  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 112          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 12           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 55           |
==================================================================
| 113  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 113          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 13           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 56           |
==================================================================
| 114  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 114          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 14           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 57           |
==================================================================
| 115  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 115          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 15           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 58           |
==================================================================
| 116  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 116          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 16           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 59           |
==================================================================
| 117  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 117          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 17           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 60           |
==================================================================
| 118  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 118          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 18           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 61           |
==================================================================
| 119  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 119          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 19           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 62           |
==================================================================
| 120  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 120          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 20           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 63           |
==================================================================
| 121  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 121          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 21           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 64           |
==================================================================
| 122  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 122          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 22           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 65           |
==================================================================
| 123  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 123          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 23           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 66           |
==================================================================
| 124  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 124          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 24           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 67           |
==================================================================
| 125  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 125          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 25           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 68           |
==================================================================
| 126  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 126          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 26           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 69           |
==================================================================
| 127  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 127          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 27           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 70           |
==================================================================
| 128  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 128          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 28           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 71           |
==================================================================
| 129  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 129          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 29           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 72           |
==================================================================
| 130  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 130          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 30           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 73           |
==================================================================
| 131  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 131          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 31           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 74           |
==================================================================
| 132  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 132          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 32           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 75           |
==================================================================
| 133  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 133          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 33           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 76           |
==================================================================
| 134  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 134          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 34           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 77           |
==================================================================
| 135  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 135          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 35           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 78           |
==================================================================
| 136  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 136          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 36           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 79           |
==================================================================
| 137  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 137          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 37           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 80           |
==================================================================
| 138  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 138          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 38           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 81           |
==================================================================
| 139  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 139          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 39           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 82           |
==================================================================
| 140  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 140          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 40           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 83           |
==================================================================
| 141  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 141          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 41           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 84           |
==================================================================
| 142  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 142          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 42           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 85           |
==================================================================
| 143  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 143          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 43           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 86           |
==================================================================
| 144  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 144          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 44           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 87           |
==================================================================
| 145  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 145          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 45           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 88           |
==================================================================
| 146  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 146          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 46           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 89           |
==================================================================
| 147  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 147          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 47           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 90           |
==================================================================
| 148  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 148          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 48           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 91           |
==================================================================
| 149  | LOGICAL   | type                         | RCY_MIRROR   |
|      |           | if offset                    | -1           |
|      |           | master                       | 100          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:-1        |
|      |           |                              | Tx:-1        |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 149          |
|      |           | pp dsp                       | -1           |
|      |           | out tm port                  | -1           |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 49           |
|      |           | channels                     | 100-149      |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 100          |
|      |           | pp port                      | 92           |
==================================================================
| 218  | LOGICAL   | type                         | SAT          |
|      |           | if offset                    | -1           |
|      |           | master                       | 218          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 218          |
|      |           | pp dsp                       | 218          |
|      |           | out tm port                  | 218          |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 218          |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 218          |
|      |           | egress interface             | 1            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 96           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 68           |
|      |           | base_hr                      | 96           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 93           |
==================================================================
| 232  | LOGICAL   | type                         | OAMP         |
|      |           | if offset                    | -1           |
|      |           | master                       | 232          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 232          |
|      |           | pp dsp                       | 232          |
|      |           | out tm port                  | 232          |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 0            |
|      |           | channel                      | 0            |
|      |           | channels                     | 232          |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 232          |
|      |           | egress interface             | 2            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 98           |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 69           |
|      |           | base_hr                      | 98           |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 94           |
==================================================================
| 240  | LOGICAL   | type                         | OLP          |
|      |           | if offset                    | -1           |
|      |           | master                       | 240          |
|      |           | core                         | 0            |
|      |           | interface speed              | Rx:10000     |
|      |           |                              | Tx:10000     |
------------------------------------------------------------------
|      | TM AND PP | in tm port                   | 240          |
|      |           | pp dsp                       | 240          |
|      |           | out tm port                  | 240          |
|      |           | tdm mode                     | NONE         |
|      |           | if_tdm mode                  | NO_TDM       |
|      |           | is channelized               | 1            |
|      |           | channel                      | 0            |
|      |           | channels                     | 240          |
|      |           | tdm-bypass master            | -1           |
|      |           | non tdm-bypass master        | 240          |
|      |           | egress interface             | 3            |
|      |           | egress interface interleaved | 0            |
|      |           | base_q_pair                  | 104          |
|      |           | nof priorities               | 2            |
|      |           | scheduler interface          | 10           |
|      |           | base_hr                      | 104          |
|      |           | sch priorities               | 2            |
|      |           | pp port                      | 95           |
==================================================================
>/usr/bin/bcmcmd nif status
=================================================================================================================
|                                                      NIF Status:                                              |
=================================================================================================================
| Port | Port Type | Lanes | PLL Lock | Link up (Signal Lock) | SerDes Rate [GBps] | Ref Clock [Mhz] | Comments |
=================================================================================================================
| 1    | ETH 10G   | 16    | 0x1      | +                     | 10.288             | 156.25          |          |
| 2    | ETH 10G   | 17    | 0x1      | +                     | 10.288             | 156.25          |          |
| 3    | ETH 10G   | 20    | 0x1      | +                     | 10.288             | 156.25          |          |
| 4    | ETH 10G   | 21    | 0x1      | +                     | 10.288             | 156.25          |          |
| 5    | ETH 10G   | 24    | 0x0      | -                     | N/A                | 156.25          |          |
| 6    | ETH 10G   | 25    | 0x0      | -                     | N/A                | 156.25          |          |
| 7    | ETH 10G   | 28    | 0x0      | -                     | N/A                | 156.25          |          |
| 8    | ETH 10G   | 29    | 0x0      | -                     | N/A                | 156.25          |          |
| 9    | ETH 10G   | 32    | 0x0      | -                     | N/A                | 156.25          |          |
| 10   | ETH 10G   | 33    | 0x0      | -                     | N/A                | 156.25          |          |
| 11   | ETH 10G   | 36    | 0x0      | -                     | N/A                | 156.25          |          |
| 12   | ETH 10G   | 37    | 0x0      | -                     | N/A                | 156.25          |          |
| 13   | ETH 10G   | 40    | 0x0      | -                     | N/A                | 156.25          |          |
| 14   | ETH 10G   | 41    | 0x0      | -                     | N/A                | 156.25          |          |
| 15   | ETH 10G   | 44    | 0x0      | -                     | N/A                | 156.25          |          |
| 16   | ETH 10G   | 45    | 0x0      | -                     | N/A                | 156.25          |          |
| 17   | ETH 10G   | 18    | 0x0      | -                     | N/A                | 156.25          |          |
| 18   | ETH 10G   | 19    | 0x0      | -                     | N/A                | 156.25          |          |
| 19   | ETH 10G   | 22    | 0x0      | -                     | N/A                | 156.25          |          |
| 20   | ETH 10G   | 23    | 0x0      | -                     | N/A                | 156.25          |          |
| 21   | ETH 10G   | 26    | 0x0      | -                     | N/A                | 156.25          |          |
| 22   | ETH 10G   | 27    | 0x0      | -                     | N/A                | 156.25          |          |
| 23   | ETH 10G   | 30    | 0x0      | -                     | N/A                | 156.25          |          |
| 24   | ETH 10G   | 31    | 0x0      | -                     | N/A                | 156.25          |          |
| 25   | ETH 10G   | 34    | 0x0      | -                     | N/A                | 156.25          |          |
| 26   | ETH 10G   | 35    | 0x0      | -                     | N/A                | 156.25          |          |
| 27   | ETH 10G   | 38    | 0x0      | -                     | N/A                | 156.25          |          |
| 28   | ETH 10G   | 39    | 0x0      | -                     | N/A                | 156.25          |          |
| 29   | ETH 10G   | 42    | 0x0      | -                     | N/A                | 156.25          |          |
| 30   | ETH 10G   | 43    | 0x0      | -                     | N/A                | 156.25          |          |
| 31   | ETH 10G   | 46    | 0x0      | -                     | N/A                | 156.25          |          |
| 32   | ETH 10G   | 47    | 0x1      | +                     | 10.288             | 156.25          |          |
| 33   | ETH 100G  | 00-03 | 0x0      | -                     | N/A                | 156.25          |          |
| 34   | ETH 100G  | 04-07 | 0x0      | -                     | N/A                | 156.25          |          |
| 35   | ETH 100G  | 12-15 | 0x0      | -                     | N/A                | 156.25          |          |
| 36   | ETH 100G  | 08-11 | 0x0      | -                     | N/A                | 156.25          |          |
=================================================================================================================
>/usr/bin/bcmcmd nif lane_map
=================================================================
|                             NIF Lane Map                      |
=================================================================
| Lane# | SRD_RX# | SRD_TX# | PM ID | Logical | Port     | ILKN |
|       |         |         |       | Port    | Internal | Lane |
|       |         |         |       |         | Lane     | ID   |
=================================================================
| 0     | 1       | 1       | 00    | 33      | 0        | N/A  |
| 1     | 2       | 2       | 00    | 33      | 1        | N/A  |
| 2     | 0       | 0       | 00    | 33      | 2        | N/A  |
| 3     | 3       | 3       | 00    | 33      | 3        | N/A  |
| 4     | 6       | 6       | 00    | 34      | 0        | N/A  |
| 5     | 4       | 5       | 00    | 34      | 1        | N/A  |
| 6     | 7       | 7       | 00    | 34      | 2        | N/A  |
| 7     | 5       | 4       | 00    | 34      | 3        | N/A  |
| 8     | 11      | 10      | 01    | 36      | 0        | N/A  |
| 9     | 9       | 9       | 01    | 36      | 1        | N/A  |
| 10    | 10      | 11      | 01    | 36      | 2        | N/A  |
| 11    | 8       | 8       | 01    | 36      | 3        | N/A  |
| 12    | 13      | 13      | 01    | 35      | 0        | N/A  |
| 13    | 14      | 14      | 01    | 35      | 1        | N/A  |
| 14    | 12      | 12      | 01    | 35      | 2        | N/A  |
| 15    | 15      | 15      | 01    | 35      | 3        | N/A  |
| 16    | 18      | 16      | 02    | 1       | 0        | N/A  |
| 17    | 19      | 18      | 02    | 2       | 0        | N/A  |
| 18    | 16      | 17      | 02    | 17      | 0        | N/A  |
| 19    | 17      | 19      | 02    | 18      | 0        | N/A  |
| 20    | 21      | 20      | 03    | 3       | 0        | N/A  |
| 21    | 23      | 22      | 03    | 4       | 0        | N/A  |
| 22    | 20      | 21      | 03    | 19      | 0        | N/A  |
| 23    | 22      | 23      | 03    | 20      | 0        | N/A  |
| 24    | 25      | 24      | 04    | 5       | 0        | N/A  |
| 25    | 27      | 26      | 04    | 6       | 0        | N/A  |
| 26    | 24      | 25      | 04    | 21      | 0        | N/A  |
| 27    | 26      | 27      | 04    | 22      | 0        | N/A  |
| 28    | 29      | 28      | 05    | 7       | 0        | N/A  |
| 29    | 30      | 30      | 05    | 8       | 0        | N/A  |
| 30    | 28      | 29      | 05    | 23      | 0        | N/A  |
| 31    | 31      | 31      | 05    | 24      | 0        | N/A  |
| 32    | 33      | 32      | 06    | 9       | 0        | N/A  |
| 33    | 34      | 34      | 06    | 10      | 0        | N/A  |
| 34    | 32      | 33      | 06    | 25      | 0        | N/A  |
| 35    | 35      | 35      | 06    | 26      | 0        | N/A  |
| 36    | 38      | 36      | 07    | 11      | 0        | N/A  |
| 37    | 39      | 38      | 07    | 12      | 0        | N/A  |
| 38    | 36      | 37      | 07    | 27      | 0        | N/A  |
| 39    | 37      | 39      | 07    | 28      | 0        | N/A  |
| 40    | 43      | 40      | 08    | 13      | 0        | N/A  |
| 41    | 41      | 42      | 08    | 14      | 0        | N/A  |
| 42    | 40      | 41      | 08    | 29      | 0        | N/A  |
| 43    | 42      | 43      | 08    | 30      | 0        | N/A  |
| 44    | 44      | 44      | 09    | 15      | 0        | N/A  |
| 45    | 46      | 46      | 09    | 16      | 0        | N/A  |
| 46    | 45      | 45      | 09    | 31      | 0        | N/A  |
| 47    | 47      | 47      | 09    | 32      | 0        | N/A  |
| 48    | 48      | 48      | -     | -       | -        | N/A  |
| 49    | 49      | 49      | -     | -       | -        | N/A  |
| 50    | 50      | 50      | -     | -       | -        | N/A  |
=================================================================
>/usr/bin/bcmcmd phy info
======================================================
|                      PHY INFO Dump:                |
======================================================
| Port      | ID0    | ID1    | ADDR | Name          |
======================================================
| eth1(1)   | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/16 |
| eth2(2)   | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/17 |
| eth3(3)   | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/20 |
| eth4(4)   | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/21 |
| eth5(5)   | 0x600d | 0x8770 | 0x8  | TSCF16GEN3/24 |
| eth6(6)   | 0x600d | 0x8770 | 0x8  | TSCF16GEN3/25 |
| eth7(7)   | 0x600d | 0x8770 | 0x10 | TSCF16GEN3/28 |
| eth8(8)   | 0x600d | 0x8770 | 0x10 | TSCF16GEN3/29 |
| eth9(9)   | 0x600d | 0x8770 | 0x14 | TSCF16GEN3/32 |
| eth10(10) | 0x600d | 0x8770 | 0x14 | TSCF16GEN3/33 |
| eth11(11) | 0x600d | 0x8770 | 0x18 | TSCF16GEN3/36 |
| eth12(12) | 0x600d | 0x8770 | 0x18 | TSCF16GEN3/37 |
| eth13(13) | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/40 |
| eth14(14) | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/41 |
| eth15(15) | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/44 |
| eth16(16) | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/45 |
| eth17(17) | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/18 |
| eth18(18) | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/19 |
| eth19(19) | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/22 |
| eth20(20) | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/23 |
| eth21(21) | 0x600d | 0x8770 | 0x8  | TSCF16GEN3/26 |
| eth22(22) | 0x600d | 0x8770 | 0x8  | TSCF16GEN3/27 |
| eth23(23) | 0x600d | 0x8770 | 0x10 | TSCF16GEN3/30 |
| eth24(24) | 0x600d | 0x8770 | 0x10 | TSCF16GEN3/31 |
| eth25(25) | 0x600d | 0x8770 | 0x14 | TSCF16GEN3/34 |
| eth26(26) | 0x600d | 0x8770 | 0x14 | TSCF16GEN3/35 |
| eth27(27) | 0x600d | 0x8770 | 0x18 | TSCF16GEN3/38 |
| eth28(28) | 0x600d | 0x8770 | 0x18 | TSCF16GEN3/39 |
| eth29(29) | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/42 |
| eth30(30) | 0x600d | 0x8770 | 0x0  | TSCF16GEN3/43 |
| eth31(31) | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/46 |
| eth32(32) | 0x600d | 0x8770 | 0x4  | TSCF16GEN3/47 |
| eth33(33) | 0x600d | 0x8770 | 0x0  | TSCBHFLEXE/0  |
| eth34(34) | 0x600d | 0x8770 | 0x0  | TSCBHFLEXE/4  |
| eth35(35) | 0x600d | 0x8770 | 0x8  | TSCBHFLEXE/12 |
| eth36(36) | 0x600d | 0x8770 | 0x8  | TSCBHFLEXE/8  |
======================================================
>/usr/bin/bcmcmd linkscan
LiNKSCan: Linkscan enabled
LiNKSCan:   Software polling interval: 100000 usec
LiNKSCan:   Software Port BitMap 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000: none
LiNKSCan:   Hardware Port BitMap 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001e: xe1-xe4,xe32
LiNKSCan:   Disabled Port BitMap 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001effffffe0: ce,xe5-xe31
>/usr/bin/bcmcmd swstate lif_mngr global_lif_allocation symmetric_global_lif dump
lif_mngr_db[0]->global_lif_allocation.symmetric_global_lif: 
Resource :Ingress global lif (Advanced Algorithm - Yes)
| Number of entries : 3141632 | Number of used entries : 127 | First entry ID : 4096 |
 Grain size: 8192 | Number of grains : 384 | Tag size : 0 |Grain info (dumps only grains with allocated entries)

		     Grain 8 | Tag 0 | Number of elements 125 | Used Entries:  17384 | 17385 | 17386 | 17387 | 17388 | 17389 | 17390 | 17391 | 17392 | 17393 | 17394 | 17395 | 17396 | 17397 | 17398 | 17399 | 17400 | 17401 | 17402 | 17403 | 17404 | 17405 | 17406 | 17407 | 17408 | 17409 | 17410 | 17411 | 17412 | 17413 | 17414 | 17415 | 17416 | 17417 | 17418 | 17419 | 17420 | 17421 | 17422 | 17423 | 17424 | 17425 | 17426 | 17427 | 17428 | 17429 | 17430 | 17431 | 17432 | 17433 | 17434 | 17435 | 17436 | 17437 | 17438 | 17439 | 17440 | 17441 | 17442 | 17443 | 17444 | 17445 | 17446 | 17447 | 17448 | 17449 | 17450 | 17451 | 17452 | 17453 | 17454 | 17455 | 17456 | 17457 | 17458 | 17459 | 17460 | 17461 | 17462 | 17463 | 17464 | 17465 | 17466 | 17467 | 17468 | 17469 | 17470 | 17471 | 17472 | 17473 | 17474 | 17475 | 17476 | 17477 | 17478 | 17479 | 17480 | 17481 | 17482 | 17483 | 17484 | 17485 | 17486 | 17487 | 17488 | 17489 | 17490 | 17491 | 17492 | 17493 | 17494 | 17495 | 17496 | 17497 | 17498 | 17499 | 17500 | 17501 | 17502 | 17503 | 17504 | 17505 | 17506 | 17507 | 17508 |
		     Grain 30 | Tag 0 | Number of elements 1 | Used Entries:  82920 |
		     Grain 31 | Tag 0 | Number of elements 1 | Used Entries:  262128 |
>/usr/bin/bcmcmd swstate lif_mngr global_lif_allocation ingress_global_lif dump
lif_mngr_db[0]->global_lif_allocation.ingress_global_lif: 
Resource :Ingress global lif (Advanced Algorithm - Yes)
| Number of entries : 3141632 | Number of used entries : 126 | First entry ID : 4096 |
 Grain size: 8192 | Number of grains : 384 | Tag size : 0 |Grain info (dumps only grains with allocated entries)

		     Grain 30 | Tag 0 | Number of elements 125 | Used Entries:  17384 | 17385 | 17386 | 17387 | 17388 | 17389 | 17390 | 17391 | 17392 | 17393 | 17394 | 17395 | 17396 | 17397 | 17398 | 17399 | 17400 | 17401 | 17402 | 17403 | 17404 | 17405 | 17406 | 17407 | 17408 | 17409 | 17410 | 17411 | 17412 | 17413 | 17414 | 17415 | 17416 | 17417 | 17418 | 17419 | 17420 | 17421 | 17422 | 17423 | 17424 | 17425 | 17426 | 17427 | 17428 | 17429 | 17430 | 17431 | 17432 | 17433 | 17434 | 17435 | 17436 | 17437 | 17438 | 17439 | 17440 | 17441 | 17442 | 17443 | 17444 | 17445 | 17446 | 17447 | 17448 | 17449 | 17450 | 17451 | 17452 | 17453 | 17454 | 17455 | 17456 | 17457 | 17458 | 17459 | 17460 | 17461 | 17462 | 17463 | 17464 | 17465 | 17466 | 17467 | 17468 | 17469 | 17470 | 17471 | 17472 | 17473 | 17474 | 17475 | 17476 | 17477 | 17478 | 17479 | 17480 | 17481 | 17482 | 17483 | 17484 | 17485 | 17486 | 17487 | 17488 | 17489 | 17490 | 17491 | 17492 | 17493 | 17494 | 17495 | 17496 | 17497 | 17498 | 17499 | 17500 | 17501 | 17502 | 17503 | 17504 | 17505 | 17506 | 17507 | 17508 |
		     Grain 31 | Tag 0 | Number of elements 1 | Used Entries:  262128 |
>/usr/bin/bcmcmd swstate lif_mngr global_lif_allocation egress_global_lif dump
lif_mngr_db[0]->global_lif_allocation.egress_global_lif: 
Resource :Ingress global lif (Advanced Algorithm - Yes)
| Number of entries : 3141632 | Number of used entries : 127 | First entry ID : 4096 |
 Grain size: 8192 | Number of grains : 384 | Tag size : 0 |Grain info (dumps only grains with allocated entries)

		     Grain 8 | Tag 0 | Number of elements 125 | Used Entries:  17384 | 17385 | 17386 | 17387 | 17388 | 17389 | 17390 | 17391 | 17392 | 17393 | 17394 | 17395 | 17396 | 17397 | 17398 | 17399 | 17400 | 17401 | 17402 | 17403 | 17404 | 17405 | 17406 | 17407 | 17408 | 17409 | 17410 | 17411 | 17412 | 17413 | 17414 | 17415 | 17416 | 17417 | 17418 | 17419 | 17420 | 17421 | 17422 | 17423 | 17424 | 17425 | 17426 | 17427 | 17428 | 17429 | 17430 | 17431 | 17432 | 17433 | 17434 | 17435 | 17436 | 17437 | 17438 | 17439 | 17440 | 17441 | 17442 | 17443 | 17444 | 17445 | 17446 | 17447 | 17448 | 17449 | 17450 | 17451 | 17452 | 17453 | 17454 | 17455 | 17456 | 17457 | 17458 | 17459 | 17460 | 17461 | 17462 | 17463 | 17464 | 17465 | 17466 | 17467 | 17468 | 17469 | 17470 | 17471 | 17472 | 17473 | 17474 | 17475 | 17476 | 17477 | 17478 | 17479 | 17480 | 17481 | 17482 | 17483 | 17484 | 17485 | 17486 | 17487 | 17488 | 17489 | 17490 | 17491 | 17492 | 17493 | 17494 | 17495 | 17496 | 17497 | 17498 | 17499 | 17500 | 17501 | 17502 | 17503 | 17504 | 17505 | 17506 | 17507 | 17508 |
		     Grain 30 | Tag 0 | Number of elements 1 | Used Entries:  82920 |
		     Grain 31 | Tag 0 | Number of elements 1 | Used Entries:  262128 |
>/usr/bin/bcmcmd swstate mdb fec_hierarchy_info dump
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[0]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[1]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[2]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[3]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[4]: 0
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[5]: 0
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[6]: 0
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[7]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[8]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[9]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[10]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[11]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[12]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[13]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[14]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[15]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[16]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[17]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[18]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[19]: STRIDE detected. arithmetic progression in the next 7 cells (cells values will not display)
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[26]: 2
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[27]: 2
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[28]: 3
mdb_db_infos[0]->fec_hierarchy_info.fec_hierarchy_map[29]: 1
mdb_db_infos[0]->fec_hierarchy_info.fec_id_range_start[0]: 52430
mdb_db_infos[0]->fec_hierarchy_info.fec_id_range_start[1]: 380110
mdb_db_infos[0]->fec_hierarchy_info.fec_id_range_start[2]: 340788
mdb_db_infos[0]->fec_hierarchy_info.fec_id_range_size[0]: 39322
mdb_db_infos[0]->fec_hierarchy_info.fec_id_range_size[1]: 13106
mdb_db_infos[0]->fec_hierarchy_info.fec_id_range_size[2]: 26214
>/usr/bin/bcmcmd swstate dnx_mirror dump
dnx_mirror_db[0]->channel_to_egress_if[0][0]: 0
dnx_mirror_db[0]->channel_to_egress_if[0][1]: 32
dnx_mirror_db[0]->channel_to_egress_if[0][2]: 33
dnx_mirror_db[0]->channel_to_egress_if[0][3]: 34
dnx_mirror_db[0]->channel_to_egress_if[0][4]: 35
dnx_mirror_db[0]->channel_to_egress_if[0][5]: 36
dnx_mirror_db[0]->channel_to_egress_if[0][6]: 37
dnx_mirror_db[0]->channel_to_egress_if[0][7]: 38
dnx_mirror_db[0]->channel_to_egress_if[0][8]: 39
dnx_mirror_db[0]->channel_to_egress_if[0][9]: 40
dnx_mirror_db[0]->channel_to_egress_if[0][10]: 41
dnx_mirror_db[0]->channel_to_egress_if[0][11]: 42
dnx_mirror_db[0]->channel_to_egress_if[0][12]: 43
dnx_mirror_db[0]->channel_to_egress_if[0][13]: STRIDE detected. arithmetic progression in the next 24 cells (cells values will not display)
dnx_mirror_db[0]->channel_to_egress_if[0][37]: 0
dnx_mirror_db[0]->channel_to_egress_if[0][38]: 0
dnx_mirror_db[0]->channel_to_egress_if[0][39]: 0
dnx_mirror_db[0]->channel_to_egress_if[0][40]: 4
dnx_mirror_db[0]->channel_to_egress_if[0][41]: 1
dnx_mirror_db[0]->channel_to_egress_if[0][42]: 2
dnx_mirror_db[0]->channel_to_egress_if[0][43]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][44]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][45]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][46]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][47]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][48]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][49]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][50]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][51]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][52]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][53]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][54]: -1
dnx_mirror_db[0]->channel_to_egress_if[0][55]: STRIDE detected. arithmetic progression in the next 201 cells (cells values will not display)
dnx_mirror_db[0]->channel_to_egress_if[1][0-255]: -1
dnx_mirror_db[0]->egress_mirror_priority[0-1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010004000000000000000000000000000000000040640000001fffffffff
dnx_mirror_db[0]->snif_ingress_profiles_mirror: 
Resource :SNIF_INGRESS_PROFILES_MIRROR (Advanced Algorithm - No)
| Number of entries : 31 | Number of used entries : 0 | First entry ID : 1 |
dnx_mirror_db[0]->snif_ingress_profiles_snoop: 
Resource :SNIF_INGRESS_PROFILES_SNOOP (Advanced Algorithm - No)
| Number of entries : 31 | Number of used entries : 4 | First entry ID : 1 |
	Used Entries: 1 | 2 | 4 | 12 |
dnx_mirror_db[0]->snif_ingress_profiles_stat_sampling: 
Resource :SNIF_INGRESS_PROFILES_STAT_SAMPLING (Advanced Algorithm - No)
| Number of entries : 31 | Number of used entries : 0 | First entry ID : 1 |
dnx_mirror_db[0]->snif_egress_vlan_profiles_mirror[0-0]: 
 Template :SNIF_EGRESS_VLAN_PROFILES_MIRROR (Advanced Algorithm - No)| First profile:0: | Nof profiles:7: | Nof profiles in use:0: | Nof free profiles:7:|

dnx_mirror_db[0]->snif_ingress_vlan_profiles_mirror[0-0]: 
 Template :SNIF_INGRESS_VLAN_PROFILES_MIRROR (Advanced Algorithm - No)| First profile:0: | Nof profiles:6: | Nof profiles in use:0: | Nof free profiles:6:|

dnx_mirror_db[0]->mirror_on_drop_profile[0-0]: -1
>/usr/bin/bcmcmd mdb info
=============================
| MDB Profile               |
|   MDB profile: custom     |
|   MDB profile KAPS cfg: 2 |
=============================
============================================================================
|                           DBAL PHYSICAL TABLES                           |
============================================================================
| Table Name | Type          | Address capacity | Address Resolution[bits] |
============================================================================
| KAPS1      | KAPS (LPM)    | 524288           |                          |
| KAPS2      | KAPS (LPM)    | 0                |                          |
| ISEM1      | Exact Match   | 131072           | 30                       |
| ISEM2      | Exact Match   | 114688           | 30                       |
| ISEM3      | Exact Match   | 114688           | 30                       |
| INLIF1     | Direct Access | 98304            | 60                       |
| INLIF2     | Direct Access | 32768            | 60                       |
| INLIF3     | Direct Access | 32768            | 60                       |
| IVSI       | Direct Access | 21846            | 90                       |
| LEM        | Exact Match   | 1048576          | 30                       |
| IOEM1      | Exact Match   | 49152            | 30                       |
| IOEM2      | Exact Match   | 32768            | 30                       |
| MAP        | Direct Access | 65536            | 60                       |
| FEC1       | Direct Access | 19661            | 150                      |
| FEC2       | Direct Access | 6554             | 150                      |
| FEC3       | Direct Access | 13108            | 150                      |
| PPMC       | Exact Match   | 49152            | 30                       |
| GLEM1      | Exact Match   | 49152            | 30                       |
| GLEM2      | Exact Match   | 65536            | 30                       |
| EEDB1      | EEDB          | 49152            |                          |
| EEDB2      | EEDB          | 49152            |                          |
| EEDB3      | EEDB          | 49152            |                          |
| EEDB4      | EEDB          | 49152            |                          |
| EEDB5      | EEDB          | 16384            |                          |
| EEDB6      | EEDB          | 16384            |                          |
| EEDB7      | EEDB          | 16384            |                          |
| EEDB8      | EEDB          | 16384            |                          |
| EOEM1      | Exact Match   | 49152            | 30                       |
| EOEM2      | Exact Match   | 49152            | 30                       |
| ESEM       | Exact Match   | 49152            | 30                       |
| EVSI       | Direct Access | 32768            | 30                       |
| SEXEM1     | Exact Match   | 98304            | 30                       |
| SEXEM2     | Exact Match   | 163840           | 30                       |
| SEXEM3     | Exact Match   | 196608           | 30                       |
| LEXEM      | Exact Match   | 131072           | 30                       |
| RMEP_EM    | Exact Match   | 81920            | 30                       |
============================================================================
>/usr/bin/bcmcmd mdb info capacity
=============================
| MDB Profile               |
|   MDB profile: custom     |
|   MDB profile KAPS cfg: 2 |
=============================
=====================================================================================================================================================
| Capacity summary table                                                                                                                            |
|   EM tables capacity is presented as estimates in Expected(Pessimistic) format.                                                                   |
|   LPM(KAPS) tables capacity is presented as estimates in IPv4(32bits) and IPv6(128bits) entry sizes.                                              |
|   EEDB entry size is controlled by the outlif_physical_phase_data_granularity_XX soc property, capacities are for the current dynamic allocation. |
|   MAP (PMF-Direct) entry size is controlled by the map_payload_size_enum soc property.                                                            |
=====================================================================================================================================================
| Table Name | Entry bits 1:Capacity | Entry bits 2:Capacity | Entry bits 3:Capacity                                                                |
=====================================================================================================================================================
| KAPS1      | 32:378880             | 128:189440            |                                                                                      |
| KAPS2      | 32:0                  | 128:0                 |                                                                                      |
| ISEM1      | 30:127137 (127137)    | 60:63568 (62584)      | 120:0 (0)                                                                            |
| ISEM2      | 30:0 (0)              | 60:54475 (52426)      | 120:26622 (23633)                                                                    |
| ISEM3      | 30:0 (0)              | 60:55622 (54392)      | 120:27401 (26130)                                                                    |
| INLIF1     | 120:49152             | 180:32768             |                                                                                      |
| INLIF2     | 120:16384             | 180:10922             |                                                                                      |
| INLIF3     | 120:16384             | 180:10922             |                                                                                      |
| IVSI       | 90:21846              |                       |                                                                                      |
| LEM        | 60:508551 (508551)    | 120:254273 (246407)   | 240:124513 (117959)                                                                  |
| IOEM1      | 30:0 (0)              | 60:20889 (14745)      | 120:6021 (3931)                                                                      |
| IOEM2      | 30:0 (0)              | 60:13926 (9830)       | 120:4014 (2620)                                                                      |
| MAP        | 60:65536              |                       |                                                                                      |
| FEC1       | 75:39322              | 150:19661             |                                                                                      |
| FEC2       | 75:13108              | 150:6554              |                                                                                      |
| FEC3       | 75:26216              | 150:13108             |                                                                                      |
| PPMC       | 30:0 (0)              | 60:23346 (21624)      | 120:11058 (9216)                                                                     |
| GLEM1      | 30:45219 (36864)      | 60:0 (0)              | 120:0 (0)                                                                            |
| GLEM2      | 30:60292 (49152)      | 60:0 (0)              | 120:0 (0)                                                                            |
| EEDB1      | 60:49152              |                       |                                                                                      |
| EEDB2      | 60:49152              |                       |                                                                                      |
| EEDB3      | 60:49152              |                       |                                                                                      |
| EEDB4      | 60:49152              |                       |                                                                                      |
| EEDB5      | 60:16384              |                       |                                                                                      |
| EEDB6      | 60:16384              |                       |                                                                                      |
| EEDB7      | 60:16384              |                       |                                                                                      |
| EEDB8      | 60:16384              |                       |                                                                                      |
| EOEM1      | 30:0 (0)              | 60:20889 (14745)      | 120:6021 (3931)                                                                      |
| EOEM2      | 30:0 (0)              | 60:20889 (14745)      | 120:6021 (3931)                                                                      |
| ESEM       | 30:0 (0)              | 60:20889 (14745)      | 120:6021 (3931)                                                                      |
| EVSI       | 30:32768              |                       |                                                                                      |
| SEXEM1     | 30:90439 (73728)      | 60:44072 (34406)      | 120:17940 (12451)                                                                    |
| SEXEM2     | 30:150732 (122880)    | 60:74219 (58982)      | 120:31866 (22281)                                                                    |
| SEXEM3     | 30:180879 (147456)    | 60:90439 (73728)      | 120:41778 (29490)                                                                    |
| LEXEM      | 60:60292 (49152)      | 120:27852 (19660)     | 240:8028 (5242)                                                                      |
| RMEP_EM    | 30:0 (0)              | 60:37109 (29491)      | 120:15933 (11140)                                                                    |
=====================================================================================================================================================
>/usr/bin/bcmcmd diag counter g core=all
                                    ||                                               /\ 
                                    ||               Network Interface               ||
                                    \/                                               ||
=================================================================================================================================
|        |    Counter                         |    Value        |        |    Counter                         |    Value        |
=================================================================================================================================
| NIF_RX | TOTAL_DROPPED_EOPS                 | 0               | NIF_TX | TX_TOTAL_PACKTS                    | 382,007         |
|        | RX_TOTAL_PACKTS                    | 382,368         |        | TX_TOTAL_BYTES                     | 336,144,392     |
|        | RX_TOTAL_BYTES                     | 336,475,874     |        |                                    |                 |
---------------------------------------------------------------------------------------------------------------------------------
| IRE    | IN_CPU_PACKETS                     | 760             | ESB    | ESB_Q_CNT                          | 366,676         |
|        | IN_OLP_PACKETS                     | 0               | ----   | ---------------------------------- | --------------- |
|        | IN_NIF_PACKETS                     | 344,138         | EPNI   | DISCARD_CNT(ETPP Drops)            | 0               |
|        | IN_OAMP_PACKETS                    | 0               |        | IFC_TRANSACTIONS                   | 367,693         |
|        | IN_RCYH_PACKETS                    | 0               |        | MIRROR_TRANSACTIONS                | 0               |
|        | IN_RCYL_PACKETS                    | 0               |        | QUEUE_TRANSACTIONS                 | 367,687         |
|        | IN_SAT_PACKETS                     | 0               |        |                                    |                 |
|        | IN_EVENTOR_PACKETS                 | 0               |        |                                    |                 |
---------------------------------------------------------------------------------------------------------------------------------
| SPB    | IN_IRE_PACKETS                     | 335,338         | PQP    | VISIBILITY_PACKETS                 | 35,044          |
|        | OUT_CGM_REPORTS                    | 335,558         |        | MULTICAST_PACKETS                  | 0               |
|        | OUT_DDP_PACKETS                    | 0               |        | UNICAST_PACKETS                    | 336,731         |
|        | OUT_IPT_PACKETS                    | 335,491         |        | MULTICAST_DISCARD_PACKETS          | 0               |
|        | CRC_ERROR_PACKETS                  | 0               |        | UNICAST_DISCARD_PACKETS            | 177             |
|        | OUT_DDP_ERROR_PACKETS              | 0               | ----   | ---------------------------------- | --------------- |
|        | OUT_IPT_ERROR_PACKETS              | 0               | RQP    | IN_PRP_PACKETS                     | 336,785         |
|        | OUT_S2D_CRC_ERRORS                 | 0               |        | RQP_TDM_BYPASS_CELLS               | 0               |
| ----   | ---------------------------------- | --------------- |        | IPT_CELL_CNT                       | 1,417,647       |
| DDP    | IN_SPB_GOOD_PACKETS                | 0               |        | IRE_CELL_CNT                       | 0               |
|        | IN_SPB_ERROR_PACKETS               | 0               |        | TDM_CELL_CNT                       | 0               |
|        | CRC_ERROR_PACKETS                  | 0               |        | PRP_MC_DISCARD_PACKETS             | 0               |
|        | DRAM_CRC_FLIPPED_ERROR_PACKETS     | 0               |        | PRP_UC_DISCARD_PACKETS             | 0               |
|        | DRAM_CRC_ERROR_PACKETS             | 0               |        | PRP_TDM_DISCARD_PACKETS            | 0               |
|        | DRAM_DUMMY_TO_DISCARD_PACKETS      | 0               |        | EMR_DISCARD_PACKETS                | 0               |
|        | DRAM_GOOD_PACKETS                  | 0               |        | EMR_MULTICAST_HIGH                 | 0               |
|        | CPYDAT_ERROR_PACKETS               | 0               |        | EMR_MULTICAST_LOW                  | 0               |
|        | OUT_CGM_CPYDAT_REPORTS             | 0               |        | EMR_UNICAST                        | 336,994         |
| ----   | ---------------------------------- | --------------- |        | EMR_TDM                            | 0               |
| CGM    | QNUM_NOT_VALID_PKTS(IRPP Drops)    | 46              |        |                                    |                 |
|        | SRAM_DELETED_PACKETS               | 0               |        |                                    |                 |
|        | SRAM_DEQUEUE_TO_DRAM_PACKETS       | 0               |        |                                    |                 |
|        | SRAM_DEQUEUE_TO_FABRIC_PACKETS     | 0               |        |                                    |                 |
|        | SRAM_ENQUEUE_PACKETS               | 0               |        |                                    |                 |
|        | SRAM_ENQUEUE_REJECT_PACKETS        | 0               |        |                                    |                 |
|        | DRAM_DELETED_BUNDLES               | 0               |        |                                    |                 |
|        | DRAM_DEQUEUE_TO_FABRIC_BUNDLES     | 0               |        |                                    |                 |
| ----   | ---------------------------------- | --------------- |        |                                    |                 |
| IPT    | IN_CGM_COMMANDS                    | 345,472         |        |                                    |                 |
|        | IN_SPB_PACKETS                     | 345,368         |        |                                    |                 |
|        | IN_DDP_BUFFERS                     | 0               |        |                                    |                 |
|        | IN_ITPP_DISCARD_PACKETS            | 0               |        |                                    |                 |
=================================================================================================================================
=============================================================================
|                  Reason for dropped and rejected packets                  |
=============================================================================
| Block  | Reason                                                           |
=============================================================================
| CGM    | QNUM_NOT_VALID                                                   |
| ------ | ---------------------------------------------------------------- |
=============================================================================
                                    ||                                                /\ 
                                    ||                Fabric Interface                ||
                                    \/                                                ||
>/usr/bin/bcmcmd dbal table dump table=IN_AC_S_VLAN_DB

=========================================================================================================================
Entries dump table IN_AC_S_VLAN_DB
# | S_VID | VLAN_DOMAIN || IN_LIF | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
0 | 127 | 35 || 0xe7  | NONE | 
1 | 127 | 7 || 0xea  | NONE | 
2 | 127 | 21 || 0xed  | NONE | 
3 | 2 | 32 || 0xf0  | PRI_1ST | 
4 | 127 | 18 || 0xf3  | NONE | 
5 | 127 | 12 || 0xf6  | NONE | 
6 | 127 | 6 || 0xf9  | NONE | 
7 | 127 | 32 || 0xff  | NONE | 
8 | 127 | 8 || 0x102  | NONE | 
9 | 127 | 10 || 0x105  | NONE | 
10 | 3 | 32 || 0x10b  | PRI_1ST | 
11 | 127 | 34 || 0x10e  | NONE | 
12 | 127 | 9 || 0x111  | NONE | 
13 | 127 | 24 || 0x114  | NONE | 
14 | 127 | 36 || 0x117  | NONE | 
15 | 4090 | 3 || 0x11a  | PRI_1ST | 
16 | 4 | 32 || 0x11d  | PRI_1ST | 
17 | 127 | 5 || 0x120  | NONE | 
18 | 127 | 1 || 0x123  | NONE | 
19 | 127 | 26 || 0x126  | NONE | 
20 | 4090 | 2 || 0x12c  | PRI_1ST | 
21 | 127 | 31 || 0x12f  | NONE | 
22 | 127 | 11 || 0x132  | NONE | 
23 | 127 | 19 || 0x135  | NONE | 
24 | 127 | 33 || 0x138  | NONE | 
25 | 4090 | 4 || 0x13b  | PRI_1ST | 
26 | 127 | 13 || 0x13e  | NONE | 
27 | 127 | 28 || 0x141  | NONE | 
28 | 5 | 32 || 0x144  | PRI_1ST | 
29 | 127 | 22 || 0x147  | NONE | 
30 | 127 | 15 || 0x14a  | NONE | 
31 | 127 | 30 || 0x14d  | NONE | 
32 | 127 | 3 || 0x150  | NONE | 
33 | 127 | 23 || 0x153  | NONE | 
34 | 127 | 16 || 0x159  | NONE | 
35 | 127 | 27 || 0x15c  | NONE | 
36 | 4090 | 1 || 0x15f  | PRI_1ST | 
37 | 127 | 25 || 0x162  | NONE | 
38 | 127 | 29 || 0x165  | NONE | 
39 | 127 | 20 || 0x168  | NONE | 
40 | 127 | 17 || 0x16b  | NONE | 
41 | 127 | 4 || 0x16e  | NONE | 
42 | 127 | 14 || 0x171  | NONE | 
43 | 127 | 2 || 0x174  | NONE | 
44 | 4 | 3 || 0xfc  | PRI_1ST | 
45 | 4090 | 32 || 0xff  | NONE | 
46 | 3 | 2 || 0x108  | PRI_1ST | 
47 | 2 | 1 || 0x129  | PRI_1ST | 
48 | 5 | 4 || 0x156  | PRI_1ST | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 49

>/usr/bin/bcmcmd dbal table dump table=IN_AC_S_S_VLAN_DB

=========================================================================================================================
Entries dump table IN_AC_S_S_VLAN_DB
# | S_VID_1 | S_VID_2 | VLAN_DOMAIN || IN_LIF | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
0 | 2064 | 2048 | 66 || 0x8  | NONE | 
1 | 2065 | 2048 | 66 || 0xa  | PRI_1ST | 
2 | 2066 | 2048 | 66 || 0x17a  | NONE | 
3 | 2068 | 2048 | 66 || 0x17c  | PRI_1ST | 
4 | 2067 | 2048 | 66 || 0x17e  | PRI_1ST | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 5

>/usr/bin/bcmcmd dbal table dump table=VLAN_PORT_MATCH_KEY_SW

=========================================================================================================================
Entries dump table VLAN_PORT_MATCH_KEY_SW
# | CRITERIA | MATCH_PORT | ETH_TYPE | PCP_DEI_OUTER_VLAN | VID_OUTER_VLAN | VID_INNER_VLAN | PON_CHANNEL_ID || GPORT | 
-------------------------------------------------------------------------------------------------------------------------
0 | 2 | 1811939394 | 0 | 0 | 0 | 0 | 0 || 1149501424 | 
1 | 2 | 1811939397 | 0 | 0 | 0 | 0 | 0 || 1149501424 | 
2 | 2 | 1811939398 | 0 | 0 | 0 | 0 | 0 || 1149501424 | 
3 | 41 | 1811939394 | 0 | 0 | 2048 | 2064 | 0 || 1149256680 | 
4 | 25 | 1811939329 | 0 | 0 | 0 | 0 | 0 || 1149256796 | 
5 | 2 | 1811939329 | 0 | 0 | 0 | 0 | 0 || 1149256717 | 
6 | 25 | 1811939330 | 0 | 0 | 0 | 0 | 0 || 1149256801 | 
7 | 2 | 1811939330 | 0 | 0 | 0 | 0 | 0 || 1149256718 | 
8 | 25 | 1811939331 | 0 | 0 | 0 | 0 | 0 || 1149256802 | 
9 | 2 | 1811939331 | 0 | 0 | 0 | 0 | 0 || 1149256719 | 
10 | 25 | 1811939332 | 0 | 0 | 0 | 0 | 0 || 1149256803 | 
11 | 2 | 1811939332 | 0 | 0 | 0 | 0 | 0 || 1149256720 | 
12 | 25 | 1811939333 | 0 | 0 | 0 | 0 | 0 || 1149256721 | 
13 | 2 | 1811939333 | 0 | 0 | 0 | 0 | 0 || 1149256721 | 
14 | 25 | 1811939334 | 0 | 0 | 0 | 0 | 0 || 1149256722 | 
15 | 2 | 1811939334 | 0 | 0 | 0 | 0 | 0 || 1149256722 | 
16 | 25 | 1811939335 | 0 | 0 | 0 | 0 | 0 || 1149256723 | 
17 | 2 | 1811939335 | 0 | 0 | 0 | 0 | 0 || 1149256723 | 
18 | 25 | 1811939336 | 0 | 0 | 0 | 0 | 0 || 1149256724 | 
19 | 2 | 1811939336 | 0 | 0 | 0 | 0 | 0 || 1149256724 | 
20 | 25 | 1811939337 | 0 | 0 | 0 | 0 | 0 || 1149256725 | 
21 | 2 | 1811939337 | 0 | 0 | 0 | 0 | 0 || 1149256725 | 
22 | 25 | 1811939338 | 0 | 0 | 0 | 0 | 0 || 1149256726 | 
23 | 2 | 1811939338 | 0 | 0 | 0 | 0 | 0 || 1149256726 | 
24 | 25 | 1811939339 | 0 | 0 | 0 | 0 | 0 || 1149256727 | 
25 | 2 | 1811939339 | 0 | 0 | 0 | 0 | 0 || 1149256727 | 
26 | 25 | 1811939340 | 0 | 0 | 0 | 0 | 0 || 1149256728 | 
27 | 2 | 1811939340 | 0 | 0 | 0 | 0 | 0 || 1149256728 | 
28 | 25 | 1811939341 | 0 | 0 | 0 | 0 | 0 || 1149256729 | 
29 | 2 | 1811939341 | 0 | 0 | 0 | 0 | 0 || 1149256729 | 
30 | 25 | 1811939342 | 0 | 0 | 0 | 0 | 0 || 1149256730 | 
31 | 2 | 1811939342 | 0 | 0 | 0 | 0 | 0 || 1149256730 | 
32 | 25 | 1811939343 | 0 | 0 | 0 | 0 | 0 || 1149256731 | 
33 | 2 | 1811939343 | 0 | 0 | 0 | 0 | 0 || 1149256731 | 
34 | 25 | 1811939344 | 0 | 0 | 0 | 0 | 0 || 1149256732 | 
35 | 2 | 1811939344 | 0 | 0 | 0 | 0 | 0 || 1149256732 | 
36 | 25 | 1811939345 | 0 | 0 | 0 | 0 | 0 || 1149256733 | 
37 | 2 | 1811939345 | 0 | 0 | 0 | 0 | 0 || 1149256733 | 
38 | 25 | 1811939346 | 0 | 0 | 0 | 0 | 0 || 1149256734 | 
39 | 2 | 1811939346 | 0 | 0 | 0 | 0 | 0 || 1149256734 | 
40 | 25 | 1811939347 | 0 | 0 | 0 | 0 | 0 || 1149256735 | 
41 | 2 | 1811939347 | 0 | 0 | 0 | 0 | 0 || 1149256735 | 
42 | 25 | 1811939348 | 0 | 0 | 0 | 0 | 0 || 1149256736 | 
43 | 2 | 1811939348 | 0 | 0 | 0 | 0 | 0 || 1149256736 | 
44 | 25 | 1811939349 | 0 | 0 | 0 | 0 | 0 || 1149256737 | 
45 | 2 | 1811939349 | 0 | 0 | 0 | 0 | 0 || 1149256737 | 
46 | 25 | 1811939350 | 0 | 0 | 0 | 0 | 0 || 1149256738 | 
47 | 2 | 1811939350 | 0 | 0 | 0 | 0 | 0 || 1149256738 | 
48 | 25 | 1811939351 | 0 | 0 | 0 | 0 | 0 || 1149256739 | 
49 | 2 | 1811939351 | 0 | 0 | 0 | 0 | 0 || 1149256739 | 
50 | 25 | 1811939352 | 0 | 0 | 0 | 0 | 0 || 1149256740 | 
51 | 2 | 1811939352 | 0 | 0 | 0 | 0 | 0 || 1149256740 | 
52 | 25 | 1811939353 | 0 | 0 | 0 | 0 | 0 || 1149256741 | 
53 | 2 | 1811939353 | 0 | 0 | 0 | 0 | 0 || 1149256741 | 
54 | 25 | 1811939354 | 0 | 0 | 0 | 0 | 0 || 1149256742 | 
55 | 2 | 1811939354 | 0 | 0 | 0 | 0 | 0 || 1149256742 | 
56 | 25 | 1811939355 | 0 | 0 | 0 | 0 | 0 || 1149256743 | 
57 | 2 | 1811939355 | 0 | 0 | 0 | 0 | 0 || 1149256743 | 
58 | 25 | 1811939356 | 0 | 0 | 0 | 0 | 0 || 1149256744 | 
59 | 2 | 1811939356 | 0 | 0 | 0 | 0 | 0 || 1149256744 | 
60 | 25 | 1811939357 | 0 | 0 | 0 | 0 | 0 || 1149256745 | 
61 | 2 | 1811939357 | 0 | 0 | 0 | 0 | 0 || 1149256745 | 
62 | 25 | 1811939358 | 0 | 0 | 0 | 0 | 0 || 1149256746 | 
63 | 2 | 1811939358 | 0 | 0 | 0 | 0 | 0 || 1149256746 | 
64 | 25 | 1811939359 | 0 | 0 | 0 | 0 | 0 || 1149256747 | 
65 | 2 | 1811939359 | 0 | 0 | 0 | 0 | 0 || 1149256747 | 
66 | 25 | 1811939360 | 0 | 0 | 0 | 0 | 0 || 1149256748 | 
67 | 2 | 1811939360 | 0 | 0 | 0 | 0 | 0 || 1149256748 | 
68 | 25 | 1811939361 | 0 | 0 | 0 | 0 | 0 || 1149256749 | 
69 | 2 | 1811939361 | 0 | 0 | 0 | 0 | 0 || 1149256749 | 
70 | 25 | 1811939362 | 0 | 0 | 0 | 0 | 0 || 1149256750 | 
71 | 2 | 1811939362 | 0 | 0 | 0 | 0 | 0 || 1149256750 | 
72 | 25 | 1811939363 | 0 | 0 | 0 | 0 | 0 || 1149256751 | 
73 | 2 | 1811939363 | 0 | 0 | 0 | 0 | 0 || 1149256751 | 
74 | 25 | 1811939364 | 0 | 0 | 0 | 0 | 0 || 1149256752 | 
75 | 2 | 1811939364 | 0 | 0 | 0 | 0 | 0 || 1149256752 | 
76 | 3 | 1811939363 | 0 | 0 | 127 | 0 | 0 || 1149256790 | 
77 | 3 | 1811939335 | 0 | 0 | 127 | 0 | 0 || 1149256762 | 
78 | 3 | 1811939349 | 0 | 0 | 127 | 0 | 0 || 1149256776 | 
79 | 3 | 1811939360 | 0 | 0 | 2 | 0 | 0 || 1149256797 | 
80 | 3 | 1811939346 | 0 | 0 | 127 | 0 | 0 || 1149256773 | 
81 | 3 | 1811939340 | 0 | 0 | 127 | 0 | 0 || 1149256767 | 
82 | 3 | 1811939334 | 0 | 0 | 127 | 0 | 0 || 1149256761 | 
83 | 3 | 1811939360 | 0 | 0 | 127 | 0 | 0 || 1149256787 | 
84 | 3 | 1811939336 | 0 | 0 | 127 | 0 | 0 || 1149256763 | 
85 | 3 | 1811939338 | 0 | 0 | 127 | 0 | 0 || 1149256765 | 
86 | 3 | 1811939360 | 0 | 0 | 3 | 0 | 0 || 1149256798 | 
87 | 3 | 1811939362 | 0 | 0 | 127 | 0 | 0 || 1149256789 | 
88 | 3 | 1811939337 | 0 | 0 | 127 | 0 | 0 || 1149256764 | 
89 | 3 | 1811939352 | 0 | 0 | 127 | 0 | 0 || 1149256779 | 
90 | 3 | 1811939364 | 0 | 0 | 127 | 0 | 0 || 1149256791 | 
91 | 3 | 1811939331 | 0 | 0 | 4090 | 0 | 0 || 1149256794 | 
92 | 3 | 1811939360 | 0 | 0 | 4 | 0 | 0 || 1149256799 | 
93 | 3 | 1811939333 | 0 | 0 | 127 | 0 | 0 || 1149256760 | 
94 | 3 | 1811939329 | 0 | 0 | 127 | 0 | 0 || 1149256756 | 
95 | 3 | 1811939354 | 0 | 0 | 127 | 0 | 0 || 1149256781 | 
96 | 3 | 1811939330 | 0 | 0 | 4090 | 0 | 0 || 1149256793 | 
97 | 3 | 1811939359 | 0 | 0 | 127 | 0 | 0 || 1149256786 | 
98 | 3 | 1811939339 | 0 | 0 | 127 | 0 | 0 || 1149256766 | 
99 | 3 | 1811939347 | 0 | 0 | 127 | 0 | 0 || 1149256774 | 
100 | 3 | 1811939361 | 0 | 0 | 127 | 0 | 0 || 1149256788 | 
101 | 3 | 1811939332 | 0 | 0 | 4090 | 0 | 0 || 1149256795 | 
102 | 3 | 1811939341 | 0 | 0 | 127 | 0 | 0 || 1149256768 | 
103 | 3 | 1811939356 | 0 | 0 | 127 | 0 | 0 || 1149256783 | 
104 | 3 | 1811939360 | 0 | 0 | 5 | 0 | 0 || 1149256800 | 
105 | 3 | 1811939350 | 0 | 0 | 127 | 0 | 0 || 1149256777 | 
106 | 3 | 1811939343 | 0 | 0 | 127 | 0 | 0 || 1149256770 | 
107 | 3 | 1811939358 | 0 | 0 | 127 | 0 | 0 || 1149256785 | 
108 | 3 | 1811939331 | 0 | 0 | 127 | 0 | 0 || 1149256758 | 
109 | 3 | 1811939351 | 0 | 0 | 127 | 0 | 0 || 1149256778 | 
110 | 3 | 1811939344 | 0 | 0 | 127 | 0 | 0 || 1149256771 | 
111 | 3 | 1811939355 | 0 | 0 | 127 | 0 | 0 || 1149256782 | 
112 | 3 | 1811939329 | 0 | 0 | 4090 | 0 | 0 || 1149256792 | 
113 | 3 | 1811939353 | 0 | 0 | 127 | 0 | 0 || 1149256780 | 
114 | 3 | 1811939357 | 0 | 0 | 127 | 0 | 0 || 1149256784 | 
115 | 3 | 1811939348 | 0 | 0 | 127 | 0 | 0 || 1149256775 | 
116 | 3 | 1811939345 | 0 | 0 | 127 | 0 | 0 || 1149256772 | 
117 | 3 | 1811939332 | 0 | 0 | 127 | 0 | 0 || 1149256759 | 
118 | 3 | 1811939342 | 0 | 0 | 127 | 0 | 0 || 1149256769 | 
119 | 3 | 1811939330 | 0 | 0 | 127 | 0 | 0 || 1149256757 | 
120 | 3 | 1811939331 | 0 | 0 | 4 | 0 | 0 || 1149256802 | 
121 | 3 | 1811939360 | 0 | 0 | 4090 | 0 | 0 || 1149256787 | 
122 | 3 | 1811939330 | 0 | 0 | 3 | 0 | 0 || 1149256801 | 
123 | 3 | 1811939329 | 0 | 0 | 2 | 0 | 0 || 1149256796 | 
124 | 3 | 1811939332 | 0 | 0 | 5 | 0 | 0 || 1149256803 | 
125 | 41 | 1811939394 | 0 | 0 | 2048 | 2065 | 0 || 1149256753 | 
126 | 41 | 1811939394 | 0 | 0 | 2048 | 2066 | 0 || 1149256754 | 
127 | 41 | 1811939394 | 0 | 0 | 2048 | 2068 | 0 || 1149256804 | 
128 | 41 | 1811939394 | 0 | 0 | 2048 | 2067 | 0 || 1149256755 | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 129

>/usr/bin/bcmcmd dbal table dump table=EGRESS_VIRTUAL_GPORT_TO_MATCH_INFO_SW

=========================================================================================================================
Entries dump table EGRESS_VIRTUAL_GPORT_TO_MATCH_INFO_SW: Result type  ESEM_NATIVE_AC
# | GPORT || LOCAL_OUT_LIF | FODO_VSI | HW_RESULT_TYPE | STAT_EGRESS_ENABLE_FLAG_SET | IS_LIF_SCOPE | VLAN_DOMAIN | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table EGRESS_VIRTUAL_GPORT_TO_MATCH_INFO_SW: Result type  ESEM_AC
# | GPORT || FODO_VSI | OUTER_VLAN_ID | GPORT | VLAN_DOMAIN | HW_RESULT_TYPE | STAT_EGRESS_ENABLE_FLAG_SET | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table EGRESS_VIRTUAL_GPORT_TO_MATCH_INFO_SW: Result type  ESEM_NAMESPACE_VSI
# | GPORT || FODO_VSI | NETWORK_DOMAIN | HW_RESULT_TYPE | CREATED_BY_AC | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table EGRESS_VIRTUAL_GPORT_TO_MATCH_INFO_SW: Result type  ESEM_NAMESPACE_PORT
# | GPORT || GPORT | NAMESPACE | HW_RESULT_TYPE | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table EGRESS_VIRTUAL_GPORT_TO_MATCH_INFO_SW: Result type  ESEM_DEFAULT
# | GPORT || HW_RESULT_TYPE | 
-------------------------------------------------------------------------------------------------------------------------
0 | 1161822221 || 0 | 
1 | 1161822220 || 0 | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 2

>/usr/bin/bcmcmd swstate algo_lif_profile dump
algo_lif_profile_db[0]->in_lif_profile_l3_enablers: 
 Template :enablers vector table (Advanced Algorithm - No)| First profile:0: | Nof profiles:32: | Nof profiles in use:3: | Nof free profiles:29:|
| Profile ID:0: | Nof ref:135033: |
			      | Field Name : enabler vector MSB | Value : 0x00000000 |

			      | Field Name : enablers vector LSB | Value : 0x00000004 |
| Profile ID:1: | Nof ref:130: |
			      | Field Name : enabler vector MSB | Value : 0x0c3f0fc0 |

			      | Field Name : enablers vector LSB | Value : 0x0300c20c |
| Profile ID:2: | Nof ref:5: |
			      | Field Name : enabler vector MSB | Value : 0x0c3f0fc0 |

			      | Field Name : enablers vector LSB | Value : 0x0300c35c |

algo_lif_profile_db[0]->in_lif_lb_profile_enablers: 
 Template :in_lif_lb_profile enablers (Advanced Algorithm - No)| First profile:0: | Nof profiles:4: | Nof profiles in use:1: | Nof free profiles:3:|
| Profile ID:0: | Nof ref:4096: |
			      | Field Name : Layers Disable | Value : 0xffffffff |

algo_lif_profile_db[0]->in_lif_profile: 
 Template :in_lif_profile table (Advanced Algorithm - No)| First profile:0: | Nof profiles:8: | Nof profiles in use:2: | Nof free profiles:6:|
| Profile ID:0: | Nof ref:98178: |
			      | Field Name : routing enablers profile | Value : 0x00000000 |

			      | Field Name : rpf mode | Value : 0x00000000 |

			      | Field Name : cs_in_lif_profile | Value : 0x00000000 |

			      | Field Name : cs_in_lif_fwd_profile | Value : 0x00000000 |

			      | Field Name : da_not_found_dst_profile | Value : 0x00000000 |

			      | Field Name : mact_mode | Value : 0 |

			      | Field Name : l2_v4_mc_fwd_type | Value : 0 |

			      | Field Name : l2_v6_mc_fwd_type | Value : 0 |

			      | Field Name : oam_default_profile | Value : 0 |

			      | Field Name : icmpv6_trap_profile | Value : 0 |

			      | Field Name : icmpv4_trap_profile | Value : 0 |

			      | Field Name : l2cp_trap_profile | Value : 0 |

			      | Field Name : arp_trap_profile | Value : 0 |

			      | Field Name : igmp_trap_profile | Value : 0 |

			      | Field Name : dhcp_trap_profile | Value : 0 |

			      | Field Name : non_auth_8021x_trap_profile | Value : 0 |
| Profile ID:1: | Nof ref:126: |
			      | Field Name : routing enablers profile | Value : 0x00000001 |

			      | Field Name : rpf mode | Value : 0x00000000 |

			      | Field Name : cs_in_lif_profile | Value : 0x00000000 |

			      | Field Name : cs_in_lif_fwd_profile | Value : 0x00000000 |

			      | Field Name : da_not_found_dst_profile | Value : 0x00000000 |

			      | Field Name : mact_mode | Value : 0 |

			      | Field Name : l2_v4_mc_fwd_type | Value : 0 |

			      | Field Name : l2_v6_mc_fwd_type | Value : 0 |

			      | Field Name : oam_default_profile | Value : 0 |

			      | Field Name : icmpv6_trap_profile | Value : 0 |

			      | Field Name : icmpv4_trap_profile | Value : 0 |

			      | Field Name : l2cp_trap_profile | Value : 0 |

			      | Field Name : arp_trap_profile | Value : 0 |

			      | Field Name : igmp_trap_profile | Value : 0 |

			      | Field Name : dhcp_trap_profile | Value : 0 |

			      | Field Name : non_auth_8021x_trap_profile | Value : 0 |

algo_lif_profile_db[0]->eth_rif_profile: 
 Template :eth_rif_profile table (Advanced Algorithm - No)| First profile:0: | Nof profiles:32: | Nof profiles in use:3: | Nof free profiles:29:|
| Profile ID:0: | Nof ref:98295: |
			      | Field Name : routing enablers profile | Value : 0x00000000 |

			      | Field Name : rpf mode | Value : 0x00000000 |

			      | Field Name : cs_in_lif_profile | Value : 0x00000000 |

			      | Field Name : cs_in_lif_fwd_profile | Value : 0x00000000 |

			      | Field Name : da_not_found_dst_profile | Value : 0x00000000 |

			      | Field Name : mact_mode | Value : 0 |

			      | Field Name : l2_v4_mc_fwd_type | Value : 0 |

			      | Field Name : l2_v6_mc_fwd_type | Value : 0 |

			      | Field Name : oam_default_profile | Value : 0 |

			      | Field Name : icmpv6_trap_profile | Value : 0 |

			      | Field Name : icmpv4_trap_profile | Value : 0 |

			      | Field Name : l2cp_trap_profile | Value : 0 |

			      | Field Name : arp_trap_profile | Value : 0 |

			      | Field Name : igmp_trap_profile | Value : 0 |

			      | Field Name : dhcp_trap_profile | Value : 0 |

			      | Field Name : non_auth_8021x_trap_profile | Value : 0 |
| Profile ID:1: | Nof ref:5: |
			      | Field Name : routing enablers profile | Value : 0x00000002 |

			      | Field Name : rpf mode | Value : 0x00000000 |

			      | Field Name : cs_in_lif_profile | Value : 0x00000004 |

			      | Field Name : cs_in_lif_fwd_profile | Value : 0x00000000 |

			      | Field Name : da_not_found_dst_profile | Value : 0x00000000 |

			      | Field Name : mact_mode | Value : 0 |

			      | Field Name : l2_v4_mc_fwd_type | Value : 0 |

			      | Field Name : l2_v6_mc_fwd_type | Value : 0 |

			      | Field Name : oam_default_profile | Value : 0 |

			      | Field Name : icmpv6_trap_profile | Value : 0 |

			      | Field Name : icmpv4_trap_profile | Value : 0 |

			      | Field Name : l2cp_trap_profile | Value : 0 |

			      | Field Name : arp_trap_profile | Value : 0 |

			      | Field Name : igmp_trap_profile | Value : 0 |

			      | Field Name : dhcp_trap_profile | Value : 0 |

			      | Field Name : non_auth_8021x_trap_profile | Value : 0 |
| Profile ID:2: | Nof ref:4: |
			      | Field Name : routing enablers profile | Value : 0x00000001 |

			      | Field Name : rpf mode | Value : 0x00000000 |

			      | Field Name : cs_in_lif_profile | Value : 0x00000004 |

			      | Field Name : cs_in_lif_fwd_profile | Value : 0x00000000 |

			      | Field Name : da_not_found_dst_profile | Value : 0x00000000 |

			      | Field Name : mact_mode | Value : 0 |

			      | Field Name : l2_v4_mc_fwd_type | Value : 1 |

			      | Field Name : l2_v6_mc_fwd_type | Value : 0 |

			      | Field Name : oam_default_profile | Value : 0 |

			      | Field Name : icmpv6_trap_profile | Value : 0 |

			      | Field Name : icmpv4_trap_profile | Value : 0 |

			      | Field Name : l2cp_trap_profile | Value : 0 |

			      | Field Name : arp_trap_profile | Value : 0 |

			      | Field Name : igmp_trap_profile | Value : 0 |

			      | Field Name : dhcp_trap_profile | Value : 0 |

			      | Field Name : non_auth_8021x_trap_profile | Value : 0 |

algo_lif_profile_db[0]->in_lif_da_not_found_destination: 
 Template :flooding group profiles for unknown DA on inlif (Advanced Algorithm - No)| First profile:0: | Nof profiles:4: | Nof profiles in use:1: | Nof free profiles:3:|
| Profile ID:0: | Nof ref:131072: |
Default destinations for unknown unicast packets: destination = 0x00000000, offset = 0x00000000, add_vsi_dst = 0x1
Default destinations for unknown multicast packets: destination = 0x00000000, offset = 0x00000000, add_vsi_dst = 0x1
Default destinations for broadcast packets: destination = 0x00000000, offset = 0x00000000, add_vsi_dst = 0x1
algo_lif_profile_db[0]->etpp_out_lif_profile: 
 Template :out lif profile table (Advanced Algorithm - Yes)| First profile:0: | Nof profiles:64: | Nof profiles in use:5: | Nof free profiles:59:|
| Profile ID:0: | Nof ref:262107: |
			      | Field Name : out lif orientation | Value : 0x00000000 |

			      | Field Name : split horizon enable | Value : 0x00000001 |

			      | Field Name : oam lif profile | Value : 0x00000000 |
| Profile ID:1: | Nof ref:37: |
			      | Field Name : out lif orientation | Value : 0x00000001 |

			      | Field Name : split horizon enable | Value : 0x00000001 |

			      | Field Name : oam lif profile | Value : 0x00000000 |
| Profile ID:44: | Nof ref:256: |
			      | Field Name : out lif orientation | Value : 0x00000000 |

			      | Field Name : split horizon enable | Value : 0x00000001 |

			      | Field Name : oam lif profile | Value : 0x00000000 |
| Profile ID:52: | Nof ref:262144: |
			      | Field Name : out lif orientation | Value : 0x00000000 |

			      | Field Name : split horizon enable | Value : 0x00000001 |

			      | Field Name : oam lif profile | Value : 0x00000000 |
| Profile ID:56: | Nof ref:262144: |
			      | Field Name : out lif orientation | Value : 0x00000000 |

			      | Field Name : split horizon enable | Value : 0x00000001 |

			      | Field Name : oam lif profile | Value : 0x00000000 |

algo_lif_profile_db[0]->erpp_out_lif_profile: 
 Template :erpp out lif profile table (Advanced Algorithm - No)| First profile:0: | Nof profiles:8: | Nof profiles in use:2: | Nof free profiles:6:|
| Profile ID:0: | Nof ref:4092: |
			      | Field Name : TTL Scope Threshold | Value : 0x00000000 |
| Profile ID:1: | Nof ref:4: |
			      | Field Name : TTL Scope Threshold | Value : 0x00000001 |

>/usr/bin/bcmcmd pp info cct
>/usr/bin/bcmcmd pp info occ ing inlif
====================================================================================================================
| InLIF Ingress-PP profile                                                                                         |
|   Profile bits separation: ACL profile bits [6 : 6], Egress profile bits [5 : 3], Ingress profile bits = [2 : 0] |
====================================================================================================================
=========================================================================
|                                  Egress bits                          |
=========================================================================
| InLif   | Orientation | Inner | Outer | Same interface     | Preserve |
| Profile |             | DP    | DP    |                    | DSCP     |
=========================================================================
| x000xxx | 0           | 0     | 0     | DEVICE_SCOPE (0x0) | 0        |
-------------------------------------------------------------------------
| x001xxx | 1           | 0     | 0     | DEVICE_SCOPE (0x0) | 0        |
-------------------------------------------------------------------------
| x010xxx | 2           | 0     | 0     | DEVICE_SCOPE (0x0) | 0        |
-------------------------------------------------------------------------
| x011xxx | 3           | 0     | 0     | DEVICE_SCOPE (0x0) | 0        |
-------------------------------------------------------------------------
| x100xxx | 0           | 0     | 0     | SYSTEM_SCOPE (0x1) | 0        |
-------------------------------------------------------------------------
| x101xxx | 1           | 0     | 0     | SYSTEM_SCOPE (0x1) | 0        |
-------------------------------------------------------------------------
| x110xxx | 2           | 0     | 0     | SYSTEM_SCOPE (0x1) | 0        |
-------------------------------------------------------------------------
| x111xxx | 3           | 0     | 0     | SYSTEM_SCOPE (0x1) | 0        |
=========================================================================
========================================================================================================================================================
|                                                                         Ingress bits                                                      |
========================================================================================================================================================
| InLif   | Routing  | RPF mode      | L2TP    | ICMPV4  | ICMPV6  | ARP     | IGMP    | DHCP    | Non     | CS      | CS      | DA not      | OAM     |
| Profile | enablers |               | profile | profile | profile | Profile | Profile | Profile | auth    | InLif   | InLif   | found       | Default |
|         | profile  |               |         |         |         |         |         |         | 802tx   | VTT     | FWD     | destination | Profile |
|         |          |               |         |         |         |         |         |         | Profile | Profile | Profile | Profile     |         |
========================================================================================================================================================
| xxxx000 | 0        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------
| xxxx001 | 1        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------
| xxxx010 | 0        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------
| xxxx011 | 0        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------
| xxxx100 | 0        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------
| xxxx101 | 0        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------
| xxxx110 | 0        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------
| xxxx111 | 0        | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 0           | 0       |
========================================================================================================================================================
>/usr/bin/bcmcmd pp info occ ing vsi
Command:"vsi" is not supported for current device and/or configuration
>/usr/bin/bcmcmd pp info occ ing ethrif
===============================================================================================
| Ingress-PP VSI profile table                                                                |
|   Profile bits separation: ACL profile bits [6 : 5], Ingress ETH RIF profile bits = [4 : 0] |
===============================================================================================
============================================================================================================================================================================================
|                                                                                        ETH RIF profile                                                     |
============================================================================================================================================================================================
| ETH RIF | Routing  | IVL/SVL | MCv4       | MCv6       | RPF mode      | L2TP    | ICMPV4  | ICMPV6  | ARP     | IGMP    | DHCP    | Non     | CS      | CS      | DA not      | OAM     |
| Profile | Enablers | Lookup  | forwarding | forwarding |               | profile | profile | profile | Profile | Profile | Profile | auth    | InLif   | InLif   | found       | Default |
|         | Profile  | Mode    | type       | type       |               |         |         |         |         |         |         | 802tx   | VTT     | FWD     | destination | Profile |
|         |          |         |            |            |               |         |         |         |         |         |         | Profile | Profile | Profile | Profile     |         |
============================================================================================================================================================================================
| xx00001 | 2        | 0       | 0          | 0          | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 4       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| xx00010 | 1        | 0       | 1          | 0          | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 4       | 0       | 0           | 0       |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| xx00011 | 0        | 0       | 1          | 0          | DISABLE (0x0) | 0       | 0       | 0       | 0       | 0       | 0       | 0       | 4       | 0       | 0           | 0       |
============================================================================================================================================================================================
>/usr/bin/bcmcmd pp info occ egr erpp
==========================================================================================
| ERPP outlif profile                                                                    |
|   Profile bits separation: ACL profile bits = [3 : 3], ERPP RIF Profile bits = [2 : 0] |
==========================================================================================
==================================
| ERPP PP RIF Profile allocation |
==================================
| ERPP    | TTL                  |
| OutRif  | Threshold            |
| Profile |                      |
==================================
| x000    | 0                    |
----------------------------------
| x001    | 1                    |
----------------------------------
| x010    | 0                    |
----------------------------------
| x011    | 0                    |
----------------------------------
| x100    | 0                    |
----------------------------------
| x101    | 0                    |
----------------------------------
| x110    | 0                    |
----------------------------------
| x111    | 0                    |
==================================
>/usr/bin/bcmcmd pp info occ egr ettp
Command:"ettp" is not supported for current device and/or configuration
>/usr/bin/bcmcmd swstate algo_qos dump
algo_qos_db[0]->ingress_qos: 
Resource :INGRESS QOS (Advanced Algorithm - No)
| Number of entries : 1024 | Number of used entries : 4 | First entry ID : 0 |
	Used Entries: 0 | 1 | 16 | 63 |
algo_qos_db[0]->ingress_qos_ecn: 
Resource :INGRESS QOS ECN (Advanced Algorithm - No)
| Number of entries : 4 | Number of used entries : 1 | First entry ID : 1 |
	Used Entries: 1 |
algo_qos_db[0]->ingress_qos_phb_opcode: 
Resource :INGRESS QOS OPCODE (Advanced Algorithm - No)
| Number of entries : 256 | Number of used entries : 10 | First entry ID : 0 |
	Used Entries: 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
algo_qos_db[0]->ingress_qos_remark_opcode: 
Resource :INGRESS QOS OPCODE (Advanced Algorithm - No)
| Number of entries : 256 | Number of used entries : 10 | First entry ID : 0 |
	Used Entries: 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
algo_qos_db[0]->ingress_qos_ecn_opcode: 
Resource :INGRESS QOS OPCODE (Advanced Algorithm - No)
| Number of entries : 16 | Number of used entries : 1 | First entry ID : 1 |
	Used Entries: 1 |
algo_qos_db[0]->ingress_qos_policer: 
Resource :INGRESS QOS POLICER (Advanced Algorithm - No)
| Number of entries : 3 | Number of used entries : 0 | First entry ID : 1 |
algo_qos_db[0]->ingress_qos_vlan_pcp: 
Resource :INGRESS QOS VLAN PCP (Advanced Algorithm - No)
| Number of entries : 16 | Number of used entries : 2 | First entry ID : 0 |
	Used Entries: 0 | 8 |
algo_qos_db[0]->egress_qos: 
Resource :EGRESS QOS (Advanced Algorithm - No)
| Number of entries : 32 | Number of used entries : 3 | First entry ID : 0 |
	Used Entries: 0 | 1 | 8 |
algo_qos_db[0]->egress_qos_opcode: 
Resource :EGRESS QOS OPCODE (Advanced Algorithm - No)
| Number of entries : 32 | Number of used entries : 8 | First entry ID : 0 |
	Used Entries: 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
algo_qos_db[0]->egress_qos_mpls_php: 
Resource :EGRESS QOS MPLS PHP (Advanced Algorithm - No)
| Number of entries : 7 | Number of used entries : 0 | First entry ID : 1 |
algo_qos_db[0]->egress_qos_php_opcode: 
Resource :EGRESS QOS PHP OPCODE (Advanced Algorithm - No)
| Number of entries : 7 | Number of used entries : 0 | First entry ID : 1 |
algo_qos_db[0]->egress_qos_policer: 
Resource :EGRESS QOS POLICER (Advanced Algorithm - No)
| Number of entries : 8 | Number of used entries : 0 | First entry ID : 0 |
algo_qos_db[0]->egress_qos_oam_pcp_map: 
Resource :EGRESS QOS OAM PRIORITY MAP (Advanced Algorithm - No)
| Number of entries : 4 | Number of used entries : 0 | First entry ID : 0 |
algo_qos_db[0]->qos_egress_ttl_pipe_profile: 
 Template :EGRESS QOS TTL PIPE PROFILE TEMPLATE (Advanced Algorithm - No)| First profile:0: | Nof profiles:16: | Nof profiles in use:0: | Nof free profiles:16:|

algo_qos_db[0]->qos_ingress_propagation_profile: 
 Template :INGRESS PROPAGATION PROFILE TEMPLATE (Advanced Algorithm - No)| First profile:0: | Nof profiles:8: | Nof profiles in use:3: | Nof free profiles:5:|
| Profile ID:0: | Nof ref:135160: |
			      | Field Name : PHB | Value : 0 | Info: PHB |

			      | Field Name : REMARK | Value : 0 | Info: REMARK |

			      | Field Name : ECN | Value : 1 | Info: ECN |

			      | Field Name : TTL | Value : 0 | Info: TTL |
| Profile ID:1: | Nof ref:2: |
			      | Field Name : PHB | Value : 2 | Info: PHB |

			      | Field Name : REMARK | Value : 2 | Info: REMARK |

			      | Field Name : ECN | Value : 1 | Info: ECN |

			      | Field Name : TTL | Value : 2 | Info: TTL |
| Profile ID:2: | Nof ref:6: |
			      | Field Name : PHB | Value : 1 | Info: PHB |

			      | Field Name : REMARK | Value : 1 | Info: REMARK |

			      | Field Name : ECN | Value : 1 | Info: ECN |

			      | Field Name : TTL | Value : 1 | Info: TTL |

algo_qos_db[0]->qos_egress_network_qos_profile: 
 Template :EGRESS NETWORK_QOS PROFILE TEMPLATE (Advanced Algorithm - No)| First profile:0: | Nof profiles:64: | Nof profiles in use:0: | Nof free profiles:64:|

algo_qos_db[0]->egress_cos_profile: 
Resource :EGRESS QOS COS PROFILE (Advanced Algorithm - No)
| Number of entries : 15 | Number of used entries : 0 | First entry ID : 1 |
>/usr/bin/bcmcmd diag pp cos
==================================================================================================================================
|                                            Ingress qos mapping info through core_0                                             |
==================================================================================================================================
| QoS    | fwd_     | qos_     | qos_    | map control   | map mode          | source | opcode | mapped qos     | qos to ITM     |
| Type   | layer_   | layer_   | profile | type          | (explicit/mapped) | qos    |        | value          |                |
|        | index    | index    |         |               |                   | value  |        |                |                |
==================================================================================================================================
| ReMark | 0 (ETH1) | 0 (ETH1) | 16      | DEFAULT (0x0) | MAPPED            | 0x00   | 0x05   | 0x00 (NWK_QOS) | 0x00 (NWK_QOS) |
----------------------------------------------------------------------------------------------------------------------------------
| PHB    | 0 (ETH1) | 0 (ETH1) | 16      | DEFAULT (0x0) | MAPPED            | 0x00   | 0x05   | 0 (TC), 0 (DP) | 0 (TC), 0 (DP) |
==================================================================================================================================
==============================================================================================================
|                                   Egress qos mapping info through core_0                                   |
==============================================================================================================
| stage   | input      | remark_ | qos_model     | qos_var_type  | opcode | remark_or_   | qos_ | next       |
|         | (dp,nwk_   | profile |               |               |        | preserve     | var  | layer      |
|         | qos)       |         |               |               |        |              |      | (dp,nwk_   |
|         |            |         |               |               |        |              |      | qos)       |
==============================================================================================================
| Initial | -          | -       | -             | -             | -      | -            | -    | 0x00, 0x00 |
--------------------------------------------------------------------------------------------------------------
| Fwd     | 0x00, 0x00 | 0x08    | UNIFORM (0x0) | PCP_DEI (0x0) | 0x04   | REMARK (0x1) | 0x00 | 0x00, 0x00 |
--------------------------------------------------------------------------------------------------------------
| Enc1    | -          | -       | -             | -             | -      | -            | -    | -          |
--------------------------------------------------------------------------------------------------------------
| Enc2    | -          | -       | -             | -             | -      | -            | -    | -          |
--------------------------------------------------------------------------------------------------------------
| Enc3    | -          | -       | -             | -             | -      | -            | -    | -          |
--------------------------------------------------------------------------------------------------------------
| Enc4    | -          | -       | -             | -             | -      | -            | -    | -          |
--------------------------------------------------------------------------------------------------------------
| Enc5    | -          | -       | -             | -             | -      | -            | -    | -          |
==============================================================================================================
>/usr/bin/bcmcmd l2 info
L2 Opportunistic Learning: Opportunistic learn mode is OFF 
L2 Learning Mode: Ingress Centralized 
L2 Learning Limit Mode: VLAN
L2 Aging: Meta cycle time is 37 seconds 
>/usr/bin/bcmcmd l2 count
The number of MACT entries is: 159
>/usr/bin/bcmcmd l2 vsi
=======================================
|              VSI Properties         |
=======================================
| VSI | Learn Profile | Limit | Count |
=======================================
| 0   | 0             | -1    | 0     |
---------------------------------------
| 16  | 0             | -1    | 0     |
---------------------------------------
| 17  | 0             | -1    | 0     |
---------------------------------------
| 18  | 0             | -1    | 0     |
---------------------------------------
| 19  | 0             | -1    | 4     |
---------------------------------------
| 20  | 0             | -1    | 43    |
---------------------------------------
| 21  | 0             | -1    | 0     |
---------------------------------------
| 22  | 0             | -1    | 25    |
---------------------------------------
| 23  | 0             | -1    | 57    |
---------------------------------------
| 24  | 0             | -1    | 30    |
=======================================
>/usr/bin/bcmcmd swstate algo_l2 dump
algo_l2_db[0]->event_forwarding_profile: 
 Template :VSI forwarding profile template (Advanced Algorithm - No)| First profile:0: | Nof profiles:4: | Nof profiles in use:1: | Nof free profiles:3:|
| Profile ID:0: | Nof ref:1: |
			      | Field Name : Ack | Value : 2 | Info: Ack event distribution |

			      | Field Name : Delete | Value : 2 | Info: Delete event distribution |

			      | Field Name : Insert | Value : 2 | Info: Insert event distribution |

			      | Field Name : Learn | Value : 2 | Info: Learn event distribution |

			      | Field Name : Refresh | Value : 2 | Info: Refresh event distribution |

			      | Field Name : Transplant | Value : 2 | Info: Transplant event distribution |

algo_l2_db[0]->vsi_learning_profile: 
 Template :VSI learning profile template (Advanced Algorithm - No)| First profile:0: | Nof profiles:32: | Nof profiles in use:1: | Nof free profiles:31:|
| Profile ID:0: | Nof ref:21846: |
			      | Field Name : Aging profile | Value : 0 | Info: Aging profile |

			      | Field Name : Forwarding profile | Value : 0 | Info: Forwarding profile |

			      | Field Name : Limit | Value : 2097151 | Info: Limit |

			      | Field Name : Message enable | Value : 0 | Info: Message enable |

algo_l2_db[0]->vsi_aging_profile: 
 Template :VSI aging profile template (Advanced Algorithm - No)| First profile:0: | Nof profiles:32: | Nof profiles in use:1: | Nof free profiles:31:|
| Profile ID:0: | Nof ref:1: |
			      | Field Name : Ageout | Value : 0 | Info: Ageout age |

			      | Field Name : Delete | Value : 4294967295 | Info: Delete age |

			      | Field Name : Refresh | Value : 7 | Info: Refresh age |

>/usr/bin/bcmcmd swstate vlan dump
vlan_db[0]->vlan_info.default_vid: 1
vlan_db[0]->vsi: 
Resource :VSI (Advanced Algorithm - No)
| Number of entries : 21845 | Number of used entries : 9 | First entry ID : 1 |
	Used Entries: 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
vlan_db[0]->action_id_ingress: 
Resource :ACTION_ID_INGRESS (Advanced Algorithm - No)
| Number of entries : 128 | Number of used entries : 2 | First entry ID : 0 |
	Used Entries: 8 | 9 |
vlan_db[0]->action_id_egress: 
Resource :ACTION_ID_EGRESS (Advanced Algorithm - No)
| Number of entries : 128 | Number of used entries : 97 | First entry ID : 0 |
	Used Entries: 0 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 |
		      28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
		      53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 |
		      78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 |
vlan_db[0]->vlan_port_ingress_virtual_gport_id: 
Resource :VLAN-PORT INGRESS VIRTUAL GPORT ID (Advanced Algorithm - No)
| Number of entries : 32768 | Number of used entries : 0 | First entry ID : 0 |
vlan_db[0]->vlan_port_egress_virtual_gport_id: 
Resource :VLAN-PORT EGRESS VIRTUAL GPORT ID (Advanced Algorithm - No)
| Number of entries : 49152 | Number of used entries : 0 | First entry ID : 32768 |
vlan_db[0]->vlan_range_outer_profile: 
 Template :Vlan range outer (Advanced Algorithm - No)| First profile:0: | Nof profiles:32: | Nof profiles in use:1: | Nof free profiles:31:|
| Profile ID:0: | Nof ref:512: |keys ={[vlan range id]}, data = {vlan range low, vlan range high}

[ 0][   0,   0][ 1][   0,   0][ 2][   0,   0][ 3][   0,   0][ 4][   0,   0][ 5][   0,   0][ 6][   0,   0][ 7][   0,   0]
[ 8][   0,   0][ 9][   0,   0][10][   0,   0][11][   0,   0][12][   0,   0][13][   0,   0][14][   0,   0][15][   0,   0]
[16][   0,   0][17][   0,   0][18][   0,   0][19][   0,   0][20][   0,   0][21][   0,   0][22][   0,   0][23][   0,   0]
[24][   0,   0][25][   0,   0][26][   0,   0][27][   0,   0][28][   0,   0][29][   0,   0][30][   0,   0][31][   0,   0]
vlan_db[0]->vlan_range_inner_profile: 
 Template :Vlan range inner (Advanced Algorithm - No)| First profile:0: | Nof profiles:32: | Nof profiles in use:1: | Nof free profiles:31:|
| Profile ID:0: | Nof ref:512: |keys ={[vlan range id]}, data = {vlan range low, vlan range high}

[ 0][   0,   0][ 1][   0,   0][ 2][   0,   0][ 3][   0,   0][ 4][   0,   0][ 5][   0,   0][ 6][   0,   0][ 7][   0,   0]
[ 8][   0,   0][ 9][   0,   0][10][   0,   0][11][   0,   0][12][   0,   0][13][   0,   0][14][   0,   0][15][   0,   0]
[16][   0,   0][17][   0,   0][18][   0,   0][19][   0,   0][20][   0,   0][21][   0,   0][22][   0,   0][23][   0,   0]
[24][   0,   0][25][   0,   0][26][   0,   0][27][   0,   0][28][   0,   0][29][   0,   0][30][   0,   0][31][   0,   0]
>/usr/bin/bcmcmd dbal table dump table=MPLS_FWD

=========================================================================================================================
Entries dump table MPLS_FWD: Result type  FWD_DEST
# | ZERO_PADDING | MPLS_LABEL || DESTINATION | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table MPLS_FWD: Result type  FWD_DEST_EEI
# | ZERO_PADDING | MPLS_LABEL || DESTINATION | EEI | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table MPLS_FWD: Result type  FWD_DEST_EEI_STAT
# | ZERO_PADDING | MPLS_LABEL || DESTINATION | EEI | STAT_OBJECT_ID | STAT_OBJECT_CMD | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table MPLS_FWD: Result type  FWD_DEST_OUTLIF
# | ZERO_PADDING | MPLS_LABEL || DESTINATION | GLOB_OUT_LIF | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table MPLS_FWD: Result type  FWD_DEST_OUTLIF_STAT
# | ZERO_PADDING | MPLS_LABEL || DESTINATION | GLOB_OUT_LIF | STAT_OBJECT_ID | STAT_OBJECT_CMD | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0


=========================================================================================================================
Entries dump table MPLS_FWD: Result type  FWD_DEST_STAT
# | ZERO_PADDING | MPLS_LABEL || DESTINATION | STAT_OBJECT_ID | STAT_OBJECT_CMD | HITBIT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

>/usr/bin/bcmcmd swstate algo_mpls dump
algo_mpls_db[0]->termination_profile: 
 Template :TERMINATION PROFILE (Advanced Algorithm - No)| First profile:0: | Nof profiles:8: | Nof profiles in use:5: | Nof free profiles:3:|
| Profile ID:0: | Nof ref:1: |
			      | Field Name : labels_to_terminate | Value : 1 | Info: labels to terminate |

			      | Field Name : ttl_exp_label_index | Value : 0 | Info: ttl exp label index |

			      | Field Name : reject_ttl_0 | Value : 0 | Info: reject_ttl_0 |

			      | Field Name : reject_ttl_1 | Value : 0 | Info: reject_ttl_1 |

			      | Field Name : has_cw | Value : 0 | Info: has_cw |

			      | Field Name : expect_bos | Value : 0 | Info: expect_bos |

			      | Field Name : check_bos | Value : 0 | Info: check_bos |
| Profile ID:1: | Nof ref:1: |
			      | Field Name : labels_to_terminate | Value : 2 | Info: labels to terminate |

			      | Field Name : ttl_exp_label_index | Value : 0 | Info: ttl exp label index |

			      | Field Name : reject_ttl_0 | Value : 0 | Info: reject_ttl_0 |

			      | Field Name : reject_ttl_1 | Value : 0 | Info: reject_ttl_1 |

			      | Field Name : has_cw | Value : 0 | Info: has_cw |

			      | Field Name : expect_bos | Value : 0 | Info: expect_bos |

			      | Field Name : check_bos | Value : 0 | Info: check_bos |
| Profile ID:2: | Nof ref:1: |
			      | Field Name : labels_to_terminate | Value : 1 | Info: labels to terminate |

			      | Field Name : ttl_exp_label_index | Value : 0 | Info: ttl exp label index |

			      | Field Name : reject_ttl_0 | Value : 0 | Info: reject_ttl_0 |

			      | Field Name : reject_ttl_1 | Value : 0 | Info: reject_ttl_1 |

			      | Field Name : has_cw | Value : 1 | Info: has_cw |

			      | Field Name : expect_bos | Value : 0 | Info: expect_bos |

			      | Field Name : check_bos | Value : 0 | Info: check_bos |
| Profile ID:3: | Nof ref:1: |
			      | Field Name : labels_to_terminate | Value : 2 | Info: labels to terminate |

			      | Field Name : ttl_exp_label_index | Value : 0 | Info: ttl exp label index |

			      | Field Name : reject_ttl_0 | Value : 0 | Info: reject_ttl_0 |

			      | Field Name : reject_ttl_1 | Value : 0 | Info: reject_ttl_1 |

			      | Field Name : has_cw | Value : 1 | Info: has_cw |

			      | Field Name : expect_bos | Value : 0 | Info: expect_bos |

			      | Field Name : check_bos | Value : 0 | Info: check_bos |
| Profile ID:4: | Nof ref:1: |
			      | Field Name : labels_to_terminate | Value : 0 | Info: labels to terminate |

			      | Field Name : ttl_exp_label_index | Value : 0 | Info: ttl exp label index |

			      | Field Name : reject_ttl_0 | Value : 0 | Info: reject_ttl_0 |

			      | Field Name : reject_ttl_1 | Value : 0 | Info: reject_ttl_1 |

			      | Field Name : has_cw | Value : 0 | Info: has_cw |

			      | Field Name : expect_bos | Value : 0 | Info: expect_bos |

			      | Field Name : check_bos | Value : 0 | Info: check_bos |

algo_mpls_db[0]->push_profile: 
 Template :PUSH PROFILE (Advanced Algorithm - No)| First profile:1: | Nof profiles:7: | Nof profiles in use:0: | Nof free profiles:7:|

algo_mpls_db[0]->label_range_profile: 
Resource :MPLS Label Range Profile (Advanced Algorithm - No)
| Number of entries : 7 | Number of used entries : 0 | First entry ID : 1 |
>/usr/bin/bcmcmd swstate algo_failover dump
algo_failover_db[0]->fec_path_select: 
Resource :DNX_ALGO_FAILOVER_RES_FEC_PATH_SELECT (Advanced Algorithm - Yes)
| Number of entries : 262144 | Number of used entries : 3 | First entry ID : 0 |
 Grain size: 16384 | Number of grains : 16 | Tag size : 2 |Grain info (dumps only grains with allocated entries)
		     Grain 14 | Tag 0 | Number of elements 1 | Used Entries:  0 |
		     Grain 15 | Tag 0 | Number of elements 2 | Used Entries:  262142 | 262143 |
algo_failover_db[0]->ing_path_select: 
Resource :DNX_ALGO_FAILOVER_RES_ING_PATH_SELECT (Advanced Algorithm - No)
| Number of entries : 16384 | Number of used entries : 3 | First entry ID : 0 |
	Used Entries: 0 | 16380 | 16381 |
algo_failover_db[0]->egr_path_select: 
Resource :DNX_ALGO_FAILOVER_RES_EGR_PATH_SELECT (Advanced Algorithm - No)
| Number of entries : 131072 | Number of used entries : 3 | First entry ID : 0 |
	Used Entries: 0 | 131068 | 131069 |
>/usr/bin/bcmcmd dbal table dump table=FAILOVER_EGRESS_PATH_SELECT

=========================================================================================================================
Entries dump table FAILOVER_EGRESS_PATH_SELECT
# | PROTECTION_POINTER || PROTECTION_PATH | 
-------------------------------------------------------------------------------------------------------------------------
0 | 131068 || SECONDARY (0x1)  | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 1

>/usr/bin/bcmcmd dbal table dump table=FAILOVER_INGRESS_PATH_SELECT

=========================================================================================================================
Entries dump table FAILOVER_INGRESS_PATH_SELECT
# | PROTECTION_POINTER || PROTECTION_PATH | 
-------------------------------------------------------------------------------------------------------------------------
0 | 16380 || SECONDARY (0x1)  | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 1

>/usr/bin/bcmcmd dbal table dump table=FAILOVER_FACILITY_DESTINATION_STATUS

=========================================================================================================================
Entries dump table FAILOVER_FACILITY_DESTINATION_STATUS
# | SYSTEM_PORT || ENABLE | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

 NOTE, 0 entries found for this result type. but the default entry is non-standard (means that there are entries in HW different than 0
to see default entries use: dbal table dump table=xxx default

>/usr/bin/bcmcmd dbal table dump table=FAILOVER_FEC_PATH_SELECT

=========================================================================================================================
Entries dump table FAILOVER_FEC_PATH_SELECT
# | PROTECTION_POINTER || PROTECTION_PATH | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

>/usr/bin/bcmcmd dbal table dump table=FAILOVER_FEC_PATH_SELECT_CONFIG

=========================================================================================================================
Entries dump table FAILOVER_FEC_PATH_SELECT_CONFIG
# | | NO_PROTECTION_PTR | FACILITY_PROTECTION_PTR | FACILITY_ACCELERATED_MODE_ENABLE | FACILITY_LOGIC | FACILITY_TRAP_LOGIC | 
-------------------------------------------------------------------------------------------------------------------------
0 | | 262143 | 262142 | False  | 0xffff0000, 0x0, 0xaa2aaa2a, 0xf000f000, 0xffff0000, 0x0, 0x2a2a2a2a, 0x0, 0xffff0000, 0x0, 0xea2aea2a, 0xf000f000, 0xffff0000, 0x0, 0xaa2aaa2a, 0x0  | 0x0, 0x0, 0xc000c000, 0xf000f000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0  | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 1

>/usr/bin/bcmcmd dbal table dump table=FAILOVER_FEC_PATH_SELECT_BANK_CONFIG

=========================================================================================================================
Entries dump table FAILOVER_FEC_PATH_SELECT_BANK_CONFIG
# | BANK_ID || HIERARCHY_LEVEL | 
-------------------------------------------------------------------------------------------------------------------------
0 | 15 || NO_HIERARCHY (0x3)  | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 1

>/usr/bin/bcmcmd swstate algo_l3 rif_alloc dump
algo_l3_db[0]->rif_alloc.rif_res_manager: 
Resource :LIF local outlif (Advanced Algorithm - Yes)
| Number of entries : 4095 | Number of used entries : 5 | First entry ID : 1 |
 Grain size: 2 | Number of grains : 2048 | Tag size : 1 |Grain info (dumps only grains with allocated entries)

		     Grain 7 | Tag 0 | Number of elements 1 | Used Entries:  16 |
		     Grain 8 | Tag 0 | Number of elements 2 | Used Entries:  17 | 18 |
		     Grain 9 | Tag 0 | Number of elements 2 | Used Entries:  19 | 20 |

>/usr/bin/bcmcmd l3 egr alloc
======================================================
|             FEC MDB cluster allocation             |
======================================================
| Hierarchy ID | Range allocation                    |
======================================================
| 1            | Range 52430 to 91751 (39322 FECs)   |
|              | 0 allocated                         |
|              | 39322 free                          |
------------------------------------------------------
| 2            | Range 380110 to 393215 (13106 FECs) |
|              | 0 allocated                         |
|              | 13106 free                          |
------------------------------------------------------
| 3            | Range 340788 to 367001 (26214 FECs) |
|              | 5 allocated                         |
|              | 26209 free                          |
======================================================
>/usr/bin/bcmcmd l3 ecmp alloc
====================================================================
|                       ECMP bank allocation                       |
====================================================================
| Bank ID | Hierarchy    | Allocated/Total | Reserved for failover |
====================================================================
| 0       | NO hierarchy | 0/2047          | N/A                   |
--------------------------------------------------------------------
| 1       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 2       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 3       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 4       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 5       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 6       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 7       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 8       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 9       | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 10      | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 11      | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 12      | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 13      | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 14      | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 15      | NO hierarchy | 0/2048          | N/A                   |
--------------------------------------------------------------------
| 16      | NO hierarchy | 0/2048          | No                    |
--------------------------------------------------------------------
| 17      | NO hierarchy | 0/2048          | No                    |
--------------------------------------------------------------------
| 18      | NO hierarchy | 0/2048          | No                    |
--------------------------------------------------------------------
| 19      | NO hierarchy | 0/2048          | No                    |
====================================================================
>/usr/bin/bcmcmd l3 ecmp dump
>/usr/bin/bcmcmd dbal table dump table=IPV4_UNICAST_PRIVATE_LPM_FORWARD_2

=========================================================================================================================
Entries dump table IPV4_UNICAST_PRIVATE_LPM_FORWARD_2
# | VRF | IPV4 || KAPS_RESULT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

>/usr/bin/bcmcmd dbal table dump table=IPV4_UNICAST_PRIVATE_LPM_FORWARD

=========================================================================================================================
Entries dump table IPV4_UNICAST_PRIVATE_LPM_FORWARD
# | VRF | IPV4 || KAPS_RESULT | 
-------------------------------------------------------------------------------------------------------------------------
0 | 1 mask: 0xffff | 10.11.118.251 (0xa0b76fb)  mask: 0xffffffff || FEC 340788 (340788) | 
1 | 1 mask: 0xffff | 10.11.118.0 (0xa0b7600)  mask: 0xfffffe00 || FEC 340789 (340789) | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 2

>/usr/bin/bcmcmd dbal table dump table=IPV6_UNICAST_PRIVATE_LPM_FORWARD_2

=========================================================================================================================
Entries dump table IPV6_UNICAST_PRIVATE_LPM_FORWARD_2
# | ZERO_PADDING | VRF | IPV6 || KAPS_RESULT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

>/usr/bin/bcmcmd dbal table dump table=IPV6_UNICAST_PRIVATE_LPM_FORWARD

=========================================================================================================================
Entries dump table IPV6_UNICAST_PRIVATE_LPM_FORWARD
# | ZERO_PADDING | VRF | IPV6 || KAPS_RESULT | 
-------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

>/usr/bin/bcmcmd swstate multicast dump
multicast_db[0]->mcdb: 
Resource :MCDB (Advanced Algorithm - Yes)
| Number of entries : 65535 | Number of used entries : 51 | First entry ID : 0 |
	Used Entries: 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
		      25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 |
		      50 |
multicast_db[0]->group_is_tdm: 
Resource :MULTICAST_GROUP_IS_TDM (Advanced Algorithm - No)
| Number of entries : 16384 | Number of used entries : 0 | First entry ID : 0 |
>/usr/bin/bcmcmd pp info load disp
============================================================================================
|                     Legend - For table of 'reserved labels', below.                      |
============================================================================================
| column name           | description                                                      |
============================================================================================
| Label indication      | Bit map of 16 bits. Each bit corresponds to a reserved label. If |
|                       | set then this label is included in the search                    |
--------------------------------------------------------------------------------------------
| Force layer           | Bit map of 16 bits. Each bit corresponds to a reserved label. If |
|                       | set then this label is included in the search even if terminated |
--------------------------------------------------------------------------------------------
| Next label indication | Bit map of 16 bits. Each bit corresponds to a reserved label. If |
|                       | set then the label following this label is included in the       |
|                       | search even if terminated                                        |
--------------------------------------------------------------------------------------------
| Next label valid      | Currently, this bitmaps should just be equal to 'Next label      |
|                       | indication'                                                      |
============================================================================================
===============================================================================
| Setup for handling of MPLS reserved labels - LOAD_BALANCING_RESERVED_LABELS |
===============================================================================
| Label      | Force  | Next label | Next                                     |
| indication | layer  | indication | label                                    |
|            |        |            | valid                                    |
===============================================================================
| 0x0000     | 0x0000 | 0xFFFF     | 0xFFFF                                   |
===============================================================================
============================================================================================
|                   Legend - For table of 'mpls identification', below.                    |
============================================================================================
| column name           | description                                                      |
============================================================================================
| Identification bitmap | Bit map of 32 bits. Each bit corresponds to identification of    |
|                       | MPLS protocol within the 5-bits protocol identifiers list        |
============================================================================================
========================================================================================================================================================================
|                                              Bitmap of MPLS protocol identifiers - MPLS_LAYER_IDENTIFICATION_BITMAP_CFG                                              |
========================================================================================================================================================================
| Identification | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
| bit            |   |   |   |   |   |   |   |   |   |   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
========================================================================================================================================================================
| Value          | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 1  | 0  | 0  | 0  | 0  |
========================================================================================================================================================================
=========================================================================
| Legend - For table of clients and corresponding crc functions, below. |
=========================================================================
| column name              | description                                |
=========================================================================
| NwkHashConfig            | CRC function for network load balancing    |
-------------------------------------------------------------------------
| TrunkHashConfig          | CRC function for LAG                       |
-------------------------------------------------------------------------
| ECMPHashConfig           | CRC function for first ECMP hierarchy      |
-------------------------------------------------------------------------
| ECMPSecondHierHashConfig | CRC function for second ECMP hierarchy     |
-------------------------------------------------------------------------
| ECMPThirdHierHashConfig  | CRC function for Third ECMP hierarchy      |
=========================================================================
================================================================================================================================
|                                            Load balancing clients and corresponding crc functions.                           |
|     plus selection of LS or MS 16 bits out of 32 assigned per layer.                                                         |
|   Handling Tables LOAD_BALANCING_CRC_SELECTION_HL_TCAM and                                                                   |
|   LOAD_BALANCING_CLIET_FWD_BIT_SEL.                                                                                          |
|   The last row displays an 8-bits bitmap. It indicates whether specified                                                     |
|   client would use the LS 16 bits (0) or the MS 16 bits of each of the                                                       |
|   8 record layers. There are 32 bits per record layer                                                                        |
================================================================================================================================
| Logical client name  | NwkHashConfig | TrunkHashConfig | ECMPHashConfig | ECMPSecondHierHashConfig | ECMPThirdHierHashConfig |
================================================================================================================================
| Physical client id   | 0             | 1               | 2              | 3                        | 4                       |
| crc function id      | 0x10039       | 0x1203d         | 0x1015d        | 0x10939                  | 0x109e7                 |
| Select LS/MS 16-bits | 0x0000        | 0x0000          | 0x0000         | 0x0000                   | 0x0000                  |
================================================================================================================================
==============================================================================
|            Legend - For table of crc_seed_per_function, below.             |
==============================================================================
| column name                | description                                   |
==============================================================================
| Identifier of crc function | Seed for crc calculation. variable of 16 bits |
==============================================================================
========================================================================================
|   Load balancing crc functions and corresponding seeds - LOAD_BALANCING_CRC_SEEDS    |
========================================================================================
| crc function | 0      | 1      | 2      | 3      | 4      | 5      | 6      | 7      |
| id           |        |        |        |        |        |        |        |        |
========================================================================================
| 16-bits seed | 0x0000 | 0x0000 | 0x0000 | 0x0000 | 0x0000 | 0x0000 | 0x0000 | 0x0000 |
========================================================================================
============================================================================================
| Legend - For table of general crc seeds for MPLS label collection and for parser, below. |
============================================================================================
| column name  | description                                                               |
============================================================================================
| MPLS_STACK_0 | Seed for the CRC32 function on label collection and compression           |
|              | for first MPLS stack                                                      |
--------------------------------------------------------------------------------------------
| MPLS_STACK_1 | Seed for the CRC32 function on label collection and compression           |
|              | for second MPLS stack                                                     |
--------------------------------------------------------------------------------------------
| PARSER       | Seed for the CRC32 function on data collection and compression            |
|              | for parser                                                                |
============================================================================================
===================================================================
| Load balancing general crc seeds - LOAD_BALANCING_GENERAL_SEEDS |
===================================================================
|              | MPLS_STACK_| MPLS_STACK_| PARSER                 |
|              | 0          | 1          |                        |
===================================================================
| 32-bits seed | 0x00000000 | 0x00000000 | 0x00000000             |
===================================================================
>/usr/bin/bcmcmd pp info fec

=========================================================================================================================
No Protection FECs Hierarchy 0, (Both Cores)
FEC_Id | Stat_Id | Stat_Cmd | Dest | MC_RPF_Mode | EEI | Hierarch_TM_Flow | Glob_Out_LIF | Glob_Out_LIF_2nd | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

=========================================================================================================================
Protection FECs Hierarchy 0, (Both Cores)
FEC_Id | Inst | Protect | Stat_Id | Stat_Cmd | Dest | MC_RPF_Mode | EEI | Hierarch_TM_Flow | Glob_Out_LIF | Glob_Out_LIF_2nd | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

=========================================================================================================================
No Protection FECs Hierarchy 1, (Both Cores)
FEC_Id | Stat_Id | Stat_Cmd | Dest | MC_RPF_Mode | EEI | Hierarch_TM_Flow | Glob_Out_LIF | Glob_Out_LIF_2nd | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

=========================================================================================================================
Protection FECs Hierarchy 1, (Both Cores)
FEC_Id | Inst | Protect | Stat_Id | Stat_Cmd | Dest | MC_RPF_Mode | EEI | Hierarch_TM_Flow | Glob_Out_LIF | Glob_Out_LIF_2nd | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0

=========================================================================================================================
No Protection FECs Hierarchy 2, (Both Cores)
FEC_Id | Stat_Id | Stat_Cmd | Dest | MC_RPF_Mode | EEI | Hierarch_TM_Flow | Glob_Out_LIF | Glob_Out_LIF_2nd | 
340788 | - | - | INGRESS_TRAP_DEST 1814 | 3 | - | - | - | - | 
340789 | - | - | INGRESS_TRAP_DEST 18c8 | 3 | - | - | - | - | 
340790 | - | - | INGRESS_TRAP_DEST 18c9 | 3 | - | - | - | - | 
340791 | - | - | FLOW_ID 7ffff | 3 | - | - | - | - | 
340804 | - | - | FLOW_ID 7ffff | - | - | - | 82920 | - | 

-------------------------------------------------------------------------------------------------------------------------
Total Entries: 5

=========================================================================================================================
Protection FECs Hierarchy 2, (Both Cores)
FEC_Id | Inst | Protect | Stat_Id | Stat_Cmd | Dest | MC_RPF_Mode | EEI | Hierarch_TM_Flow | Glob_Out_LIF | Glob_Out_LIF_2nd | 
-------------------------------------------------------------------------------------------------------------------------
Total Entries: 0
>/usr/bin/bcmcmd trap list pre
============================================================================================================
|                                     IRPP predefined traps configured                                     |
============================================================================================================
| bcmRxTrap                          | Trap id (HW code) | Snoop strength | Forward strength | Strengtless |
============================================================================================================
| LinkLayerSaMulticast               | 0x3               | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| LinkLayerSaEqualsDa                | 0x4               | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| LinkLayerVlanTagDiscard            | 0x6               | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| Default                            | 0x9               | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| UnknownDest                        | 0xa               | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| EgressTrapped2ndPass               | 0xb               | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| MplsUnknownLabel                   | 0xc               | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| MyMacAndIpDisabled                 | 0x14              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ArpReply                           | 0x16              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| MyMAcAndUnknownL3                  | 0x17              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| MplsUnexpectedNoBos                | 0x22              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| MplsTunnelTerminationTtl0          | 0x23              | 0              | 13               | FALSE       |
------------------------------------------------------------------------------------------------------------
| MplsTunnelTerminationTtl1          | 0x24              | 0              | 13               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedMplsControlWordTrap      | 0x25              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| StpStateBlock                      | 0x27              | 0              | 11               | FALSE       |
------------------------------------------------------------------------------------------------------------
| StpStateLearn                      | 0x28              | 0              | 11               | FALSE       |
------------------------------------------------------------------------------------------------------------
| Failover1Plus1Fail                 | 0x2c              | 2              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop0                    | 0x30              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop6                    | 0x31              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedVlanTagDiscard           | 0x33              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedSaMulticast              | 0x3c              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedSaEqualsDa               | 0x3d              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4VersionError         | 0x40              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4ChecksumError        | 0x41              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4HeaderLengthError    | 0x42              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4TotalLengthError     | 0x43              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4Ttl0                 | 0x44              | 0              | 11               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4HasOptions           | 0x45              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4Ttl1                 | 0x46              | 0              | 11               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4SipEqualDip          | 0x47              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4DipZero              | 0x48              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv4SipIsMc              | 0x49              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| Ipv6HopCount0                      | 0x4b              | 0              | 11               | FALSE       |
------------------------------------------------------------------------------------------------------------
| Ipv6HopCount1                      | 0x4c              | 0              | 11               | FALSE       |
------------------------------------------------------------------------------------------------------------
| TerminatedIpv6LocalLinkDestination | 0x52              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop1                    | 0x5b              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop2                    | 0x5c              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop3                    | 0x5d              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop4                    | 0x5e              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop5                    | 0x5f              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop7                    | 0x61              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop8                    | 0x62              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop9                    | 0x63              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop10                   | 0x64              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop11                   | 0x65              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop12                   | 0x66              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop13                   | 0x67              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4VersionError         | 0x68              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4ChecksumError        | 0x69              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4HeaderLengthError    | 0x6a              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4TotalLengthError     | 0x6b              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4Ttl0                 | 0x6c              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4HasOptions           | 0x6d              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4Ttl1                 | 0x6e              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4SipEqualDip          | 0x6f              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4DipZero              | 0x70              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv4SipIsMc              | 0x71              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv6Ttl0                 | 0x73              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv6Ttl1                 | 0x74              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| ForwardingIpv6LocalLinkDestination | 0x7a              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| MplsForwardingTtl0                 | 0x81              | 0              | 13               | FALSE       |
------------------------------------------------------------------------------------------------------------
| MplsForwardingTtl1                 | 0x82              | 0              | 13               | FALSE       |
------------------------------------------------------------------------------------------------------------
| L2Learn0                           | 0x90              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| L2Learn1                           | 0x91              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| L2Learn2                           | 0x92              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| L2Learn3                           | 0x93              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| 1588                               | 0x98              | 0              | 12               | FALSE       |
------------------------------------------------------------------------------------------------------------
| 1588Discard                        | 0x99              | 0              | 15               | FALSE       |
------------------------------------------------------------------------------------------------------------
| OamLevel                           | 0xa2              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| SameInterface                      | 0xa3              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop14                   | 0xa4              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| EgTxFieldSnoop15                   | 0xa5              | 0              | 0                | FALSE       |
------------------------------------------------------------------------------------------------------------
| UcLooseRpfFail                     | 0xa6              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| OamPerformanceEthAccelerated       | 0xa9              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamPerformanceY1731MplsTp          | 0xaa              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamPerformanceY1731Pwe             | 0xab              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamPassive                         | 0xac              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| DfltDroppedPacket                  | 0xaf              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| UcStrictRpfFail                    | 0xc2              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| McExplicitRpfFail                  | 0xc3              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| McUseSipRpfFail                    | 0xc4              | 0              | 4                | FALSE       |
------------------------------------------------------------------------------------------------------------
| OamEthAccelerated                  | 0xe0              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamY1731MplsTp                     | 0xe1              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamY1731Pwe                        | 0xe2              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamBfdIpv4                         | 0xe3              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamBfdMpls                         | 0xe4              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamBfdPwe                          | 0xe5              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| OamBfdIpv6                         | 0xe8              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| BfdOamDownMEP                      | 0xfd              | N/A            | N/A              | TRUE        |
------------------------------------------------------------------------------------------------------------
| SnoopOamPacket                     | 0xfe              | N/A            | N/A              | TRUE        |
============================================================================================================
======================================================================
|                  ETPP predefined traps configured                  |
======================================================================
| bcmRxTrap             | Forward Action Profile | Trap id (Encoded) |
======================================================================
| EgTxOamUpMEPOamp      | 0x4                    | 0xf00             |
----------------------------------------------------------------------
| EgTxOamUpMEPDest1     | 0x5                    | 0xf41             |
----------------------------------------------------------------------
| EgTxOamUpMEPDest2     | 0x6                    | 0xf82             |
----------------------------------------------------------------------
| EgTxOamPassive        | 0x5                    | 0xf44             |
----------------------------------------------------------------------
| EgTxOamLevel          | 0x5                    | 0xf43             |
----------------------------------------------------------------------
| EgTxOamReflector      | 0x3                    | 0xec5             |
----------------------------------------------------------------------
| EgTxIfaEgressMetadata | 0x0                    | 0xe06             |
======================================================================
>/usr/bin/bcmcmd trap list user
======================================
| IRPP User-defined traps configured |
======================================
| USER_DEFINED_#  | Trap id (HW id)  |
======================================
| USER_DEFINED_0  | 0x2a             |
--------------------------------------
| USER_DEFINED_1  | 0x2b             |
--------------------------------------
| USER_DEFINED_2  | 0x19             |
--------------------------------------
| USER_DEFINED_3  | 0x2d             |
--------------------------------------
| USER_DEFINED_4  | 0x1a             |
--------------------------------------
| USER_DEFINED_5  | 0x2f             |
--------------------------------------
| USER_DEFINED_6  | 0x1b             |
--------------------------------------
| USER_DEFINED_7  | 0xb2             |
--------------------------------------
| USER_DEFINED_8  | 0x1c             |
--------------------------------------
| USER_DEFINED_9  | 0xb4             |
--------------------------------------
| USER_DEFINED_10 | 0xb5             |
--------------------------------------
| USER_DEFINED_11 | 0xb6             |
--------------------------------------
| USER_DEFINED_12 | 0xb7             |
--------------------------------------
| USER_DEFINED_13 | 0xb8             |
--------------------------------------
| USER_DEFINED_14 | 0xb9             |
--------------------------------------
| USER_DEFINED_15 | 0xba             |
--------------------------------------
| USER_DEFINED_16 | 0xbb             |
--------------------------------------
| USER_DEFINED_17 | 0xbc             |
--------------------------------------
| USER_DEFINED_18 | 0xbd             |
--------------------------------------
| USER_DEFINED_19 | 0xbe             |
--------------------------------------
| USER_DEFINED_20 | 0x1d             |
--------------------------------------
| USER_DEFINED_21 | 0xc7             |
--------------------------------------
| USER_DEFINED_22 | 0xc8             |
--------------------------------------
| USER_DEFINED_23 | 0xc9             |
--------------------------------------
| USER_DEFINED_24 | 0xca             |
--------------------------------------
| USER_DEFINED_25 | 0xcb             |
--------------------------------------
| USER_DEFINED_26 | 0xcc             |
--------------------------------------
| USER_DEFINED_27 | 0xcd             |
--------------------------------------
| USER_DEFINED_28 | 0xce             |
--------------------------------------
| USER_DEFINED_59 | 0xf0             |
======================================
======================================
| ERPP User-defined traps configured |
======================================
| Trap id | Forward Action Profile   |
======================================
| DEFAULT | 0                        |
--------------------------------------
| 0x801   | 1                        |
--------------------------------------
| 0x802   | 2                        |
--------------------------------------
| 0x803   | 3                        |
======================================
======================================
| ETPP User-defined traps configured |
======================================
| Trap id | Forward Action Profile   |
======================================
| DEFAULT | 0                        |
--------------------------------------
| DROP    | 1                        |
--------------------------------------
| 0xc03   | 3                        |
======================================
>/usr/bin/bcmcmd trap list app
=============================================================================================================
|                                     ERPP application traps configured                                     |
=============================================================================================================
| bcmRxTrap                | Forward action profile | Trap id (Encoded) | Forward strength | Snoop strength |
=============================================================================================================
| EgHairPinFilter          | 0x1                    | 0x801             | 13               | 0              |
-------------------------------------------------------------------------------------------------------------
| EgSplitHorizonFilter     | 0x0                    | 0x800             | 0                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgUnknownDa              | 0x0                    | 0x800             | 0                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgDiscardFrameTypeFilter | 0x0                    | 0x800             | 0                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgIpmcTtlErr             | 0x1                    | 0x801             | 4                | 0              |
-------------------------------------------------------------------------------------------------------------
| DssStacking              | 0x1                    | 0x801             | 4                | 0              |
-------------------------------------------------------------------------------------------------------------
| LagMulticast             | 0x1                    | 0x801             | 4                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgInvalidDestPort        | 0x1                    | 0x801             | 4                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgIpv4Ttl0               | 0x2                    | 0x802             | 12               | 0              |
-------------------------------------------------------------------------------------------------------------
| EgIpv4Ttl1               | 0x1                    | 0x801             | 4                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgRqpDiscard             | 0x1                    | 0x801             | 4                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgTdmDiscard             | 0x0                    | 0x800             | 0                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgExcludeSrc             | 0x1                    | 0x801             | 4                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgGlemPpTrap             | 0x0                    | 0x800             | 0                | 0              |
-------------------------------------------------------------------------------------------------------------
| EgGlemNonePpTrap         | 0x0                    | 0x800             | 0                | 0              |
=============================================================================================================
=================================================================================================================
|                                       ETPP application traps configured                                       |
=================================================================================================================
| bcmRxTrap                    | Forward action profile | Trap id (Encoded) | Forward strength | Snoop strength |
=================================================================================================================
| EgTxStpStateFail             | 0x1                    | 0xc01             | 13               | 0              |
-----------------------------------------------------------------------------------------------------------------
| EgTxProtectionPathUnexpected | 0x1                    | 0xc01             | 13               | 0              |
-----------------------------------------------------------------------------------------------------------------
| EgTxPortNotVlanMember        | 0x1                    | 0xc01             | 4                | 0              |
-----------------------------------------------------------------------------------------------------------------
| EgTxDiscardFrameTypeFilter   | 0x0                    | 0xc00             | 0                | 0              |
-----------------------------------------------------------------------------------------------------------------
| EgTxSplitHorizonFilter       | 0x1                    | 0xc01             | 13               | 0              |
-----------------------------------------------------------------------------------------------------------------
| EgTxLatency                  | 0x0                    | 0xc00             | 0                | 0              |
-----------------------------------------------------------------------------------------------------------------
| EgTxMetering                 | 0x0                    | 0xc00             | 0                | 0              |
-----------------------------------------------------------------------------------------------------------------
| EgTxGlem                     | 0x0                    | 0xc00             | 0                | 0              |
=================================================================================================================
>/usr/bin/bcmcmd trap map pre block=ETPP
================================================================================================================================
|                                                  ETPP predefined traps Map                                                   |
================================================================================================================================
| bcmRxTrap             | Description                                             | Forward Action Profile | Trap id (Encoded) |
================================================================================================================================
| EgTxOamUpMEPOamp      | ETPP trap for OAM Up MEPs with destination OAMP         | 0x4                    | 0xf00             |
--------------------------------------------------------------------------------------------------------------------------------
| EgTxOamUpMEPDest1     | ETPP trap for OAM Up MEPs with configurable destination | 0x5                    | 0xf41             |
--------------------------------------------------------------------------------------------------------------------------------
| EgTxOamUpMEPDest2     | ETPP trap for OAM Up MEPs with configurable destination | 0x6                    | 0xf82             |
--------------------------------------------------------------------------------------------------------------------------------
| EgTxOamPassive        | ETPP trap for OAM passive error                         | 0x5                    | 0xf44             |
--------------------------------------------------------------------------------------------------------------------------------
| EgTxOamLevel          | ETPP trap for OAM MD-level error                        | 0x5                    | 0xf43             |
--------------------------------------------------------------------------------------------------------------------------------
| EgTxOamReflector      | ETPP trap for OAM Up MEP LBM reply through reflector    | 0x3                    | 0xec5             |
--------------------------------------------------------------------------------------------------------------------------------
| EgTxIfaEgressMetadata | ETPP trap for IFA Egress Node with metadata mirroring   | 0x0                    | 0xe06             |
================================================================================================================================
>/usr/bin/bcmcmd trap mtu prof
=================================================================================================
|                                         MTU Profile info                                      |
=================================================================================================
| ID | MTU Profile | Compressed Layer Type | MTU Value | Action Profile                         |
=================================================================================================
| 9  | 1           | 1                     | 1500      | Trap_ID: 3075, Fwd_Str: 12, Snp_Str: 0 |
-------------------------------------------------------------------------------------------------
| 10 | 1           | 2                     | 1500      | Trap_ID: DROP, Fwd_Str: 1, Snp_Str: 0  |
-------------------------------------------------------------------------------------------------
| 15 | 1           | 7                     | 1522      | Trap_ID: DROP, Fwd_Str: 1, Snp_Str: 0  |
=================================================================================================
>/usr/bin/bcmcmd trap last info block=all core=all
>/usr/bin/bcmcmd field key info type=by_half_key valid=yes
Command:"info" is not supported for current device and/or configuration
>/usr/bin/bcmcmd field key info type=by_bit_range valid=yes
Command:"info" is not supported for current device and/or configuration
>/usr/bin/bcmcmd field fem info by_fg
==========================================================
| Active-only actions - SWSTATE for FEM id: from 0 to 15 |
==========================================================
| fem_ | fg_ | input  | ignore  | map   | encoded        |
| id   | id  | offset | actions | index | actions        |
==========================================================
| 0    | 3   | 96     | 0xFC    | 0     |                |
|      |     |        |         | 0     | 0x01010060     |
|      |     |        |         | 1     | 0x01010060     |
|      |     |        |         | 2     | ---            |
|      |     |        |         | 3     | ---            |
| 2    | 0   | 32     | 0xFE    | 0     |                |
|      |     |        |         | 0     | 0x0101002B     |
|      |     |        |         | 1     | ---            |
|      |     |        |         | 2     | ---            |
|      |     |        |         | 3     | ---            |
|      | 3   | 32     | 0xFD    | 1     |                |
|      |     |        |         | 0     | ---            |
|      |     |        |         | 1     | 0x0101002B     |
|      |     |        |         | 2     | ---            |
|      |     |        |         | 3     | ---            |
| 3    | 0   | 32     | 0xFE    | 0     |                |
|      |     |        |         | 0     | 0x01010027     |
|      |     |        |         | 1     | ---            |
|      |     |        |         | 2     | ---            |
|      |     |        |         | 3     | ---            |
|      | 3   | 0      | 0xFE    | 1     |                |
|      |     |        |         | 0     | 0x01010027     |
|      |     |        |         | 1     | ---            |
|      |     |        |         | 2     | ---            |
|      |     |        |         | 3     | ---            |
| 4    | 0   | 32     | 0xFE    | 0     |                |
|      |     |        |         | 0     | 0x01010012     |
|      |     |        |         | 1     | ---            |
|      |     |        |         | 2     | ---            |
|      |     |        |         | 3     | ---            |
==========================================================
>/usr/bin/bcmcmd field fem info by_cont
=============================================================================
|                Legend - For table of FEM contexts, below.                 |
=============================================================================
| column | description                                                      |
| name   |                                                                  |
=============================================================================
| FM     | FEM                                                              |
| ID     | FEM identifier                                                   |
| KSL    | FEM key select (dbal_enum_value_field_field_pmf_a_fem_key_select_|
|        | e). If set to '--' then FEM is not active                        |
| PRG    | FEM program (dnx_field_fem_program_t). One of four               |
| RFLG   | Booelan flag of 'replace' ('override') feature. If non-zero then |
|        | 'TCAM' is meaningful                                             |
| TCAM   | Identifier of the TCAM result to take the LS 16 bits from.       |
|        | Range: 0 - 7                                                     |
=============================================================================
================================================================================================
|                    Active-only contexts - HW for context id: from 0 to 63                    |
================================================================================================
| Ctxt | Field | FM | FM | FM | FM | FM | FM | FM | FM | FM | FM | FM | FM | FM | FM | FM | FM |
|      |       | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  | 9  | 10 | 11 | 12 | 13 | 14 | 15 |
================================================================================================
| 49   | ID    | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  | 9  | 10 | 11 | 12 | 13 | 14 | 15 |
|      | KSL   | 46 | -- | 42 | 40 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
|      | PRG   | 0  | 0  | 1  | 1  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | RFLG  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | TCAM  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
------------------------------------------------------------------------------------------------
| 51   | ID    | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  | 9  | 10 | 11 | 12 | 13 | 14 | 15 |
|      | KSL   | -- | -- | 42 | 42 | 42 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
|      | PRG   | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | RFLG  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | TCAM  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
------------------------------------------------------------------------------------------------
| 61   | ID    | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  | 9  | 10 | 11 | 12 | 13 | 14 | 15 |
|      | KSL   | 46 | -- | 42 | 40 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
|      | PRG   | 0  | 0  | 1  | 1  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | RFLG  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | TCAM  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
------------------------------------------------------------------------------------------------
| 62   | ID    | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  | 9  | 10 | 11 | 12 | 13 | 14 | 15 |
|      | KSL   | 46 | -- | 42 | 40 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
|      | PRG   | 0  | 0  | 1  | 1  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | RFLG  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | TCAM  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
------------------------------------------------------------------------------------------------
| 63   | ID    | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  | 9  | 10 | 11 | 12 | 13 | 14 | 15 |
|      | KSL   | -- | -- | 42 | 42 | 42 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
|      | PRG   | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | RFLG  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
|      | TCAM  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  |
================================================================================================
>/usr/bin/bcmcmd field fem info cond
========================================
| Remarks -                            |
========================================
| For table of FEM conditions, below,  |
| all elements which are marked        |
| 'invalid', are meaningless           |
========================================
==============================================================
| Active-only fem_programs - HW for fem program: from 0 to 3 |
==============================================================
| FEM | FEM     | Condition | Valid | Map  | Action          |
| id  | program |           |       | data |                 |
|     |         |           |       |      | index           |
==============================================================
|     |         |           |       |      |                 |
| 0   | 0       |           |       |      |                 |
|     |         | 0         | NO    | 0x0  | 0               |
|     |         | 1         | YES   | 0x0  | 0               |
|     |         | 2         | NO    | 0x0  | 0               |
|     |         | 3         | YES   | 0x0  | 1               |
|     |         | 4         | NO    | 0x0  | 0               |
|     |         | 5         | YES   | 0x0  | 0               |
|     |         | 6         | NO    | 0x0  | 0               |
|     |         | 7         | YES   | 0x0  | 1               |
|     |         | 8         | NO    | 0x0  | 0               |
|     |         | 9         | YES   | 0x0  | 0               |
|     |         | 10        | NO    | 0x0  | 0               |
|     |         | 11        | YES   | 0x0  | 1               |
|     |         | 12        | NO    | 0x0  | 0               |
|     |         | 13        | YES   | 0x0  | 0               |
|     |         | 14        | NO    | 0x0  | 0               |
|     |         | 15        | YES   | 0x0  | 1               |
| 2   | 0       |           |       |      |                 |
|     |         | 0         | NO    | 0x0  | 0               |
|     |         | 1         | NO    | 0x0  | 0               |
|     |         | 2         | YES   | 0x0  | 0               |
|     |         | 3         | YES   | 0x0  | 0               |
|     |         | 4         | NO    | 0x0  | 0               |
|     |         | 5         | NO    | 0x0  | 0               |
|     |         | 6         | YES   | 0x0  | 0               |
|     |         | 7         | YES   | 0x0  | 0               |
|     |         | 8         | NO    | 0x0  | 0               |
|     |         | 9         | NO    | 0x0  | 0               |
|     |         | 10        | YES   | 0x0  | 0               |
|     |         | 11        | YES   | 0x0  | 0               |
|     |         | 12        | NO    | 0x0  | 0               |
|     |         | 13        | NO    | 0x0  | 0               |
|     |         | 14        | YES   | 0x0  | 0               |
|     |         | 15        | YES   | 0x0  | 0               |
| 2   | 1       |           |       |      |                 |
|     |         | 0         | NO    | 0x0  | 1               |
|     |         | 1         | NO    | 0x0  | 1               |
|     |         | 2         | NO    | 0x0  | 1               |
|     |         | 3         | NO    | 0x0  | 1               |
|     |         | 4         | YES   | 0x0  | 1               |
|     |         | 5         | YES   | 0x0  | 1               |
|     |         | 6         | YES   | 0x0  | 1               |
|     |         | 7         | YES   | 0x0  | 1               |
|     |         | 8         | NO    | 0x0  | 1               |
|     |         | 9         | NO    | 0x0  | 1               |
|     |         | 10        | NO    | 0x0  | 1               |
|     |         | 11        | NO    | 0x0  | 1               |
|     |         | 12        | YES   | 0x0  | 1               |
|     |         | 13        | YES   | 0x0  | 1               |
|     |         | 14        | YES   | 0x0  | 1               |
|     |         | 15        | YES   | 0x0  | 1               |
| 3   | 0       |           |       |      |                 |
|     |         | 0         | NO    | 0x0  | 0               |
|     |         | 1         | YES   | 0x0  | 0               |
|     |         | 2         | NO    | 0x0  | 0               |
|     |         | 3         | YES   | 0x0  | 0               |
|     |         | 4         | NO    | 0x0  | 0               |
|     |         | 5         | YES   | 0x0  | 0               |
|     |         | 6         | NO    | 0x0  | 0               |
|     |         | 7         | YES   | 0x0  | 0               |
|     |         | 8         | NO    | 0x0  | 0               |
|     |         | 9         | YES   | 0x0  | 0               |
|     |         | 10        | NO    | 0x0  | 0               |
|     |         | 11        | YES   | 0x0  | 0               |
|     |         | 12        | NO    | 0x0  | 0               |
|     |         | 13        | YES   | 0x0  | 0               |
|     |         | 14        | NO    | 0x0  | 0               |
|     |         | 15        | YES   | 0x0  | 0               |
| 3   | 1       |           |       |      |                 |
|     |         | 0         | NO    | 0x0  | 0               |
|     |         | 1         | NO    | 0x0  | 0               |
|     |         | 2         | YES   | 0x0  | 0               |
|     |         | 3         | YES   | 0x0  | 0               |
|     |         | 4         | NO    | 0x0  | 0               |
|     |         | 5         | NO    | 0x0  | 0               |
|     |         | 6         | YES   | 0x0  | 0               |
|     |         | 7         | YES   | 0x0  | 0               |
|     |         | 8         | NO    | 0x0  | 0               |
|     |         | 9         | NO    | 0x0  | 0               |
|     |         | 10        | YES   | 0x0  | 0               |
|     |         | 11        | YES   | 0x0  | 0               |
|     |         | 12        | NO    | 0x0  | 0               |
|     |         | 13        | NO    | 0x0  | 0               |
|     |         | 14        | YES   | 0x0  | 0               |
|     |         | 15        | YES   | 0x0  | 0               |
| 4   | 0       |           |       |      |                 |
|     |         | 0         | YES   | 0x0  | 0               |
|     |         | 1         | YES   | 0x0  | 0               |
|     |         | 2         | YES   | 0x0  | 0               |
|     |         | 3         | YES   | 0x0  | 0               |
|     |         | 4         | YES   | 0x0  | 0               |
|     |         | 5         | YES   | 0x0  | 0               |
|     |         | 6         | YES   | 0x0  | 0               |
|     |         | 7         | YES   | 0x0  | 0               |
|     |         | 8         | YES   | 0x0  | 0               |
|     |         | 9         | YES   | 0x0  | 0               |
|     |         | 10        | YES   | 0x0  | 0               |
|     |         | 11        | YES   | 0x0  | 0               |
|     |         | 12        | YES   | 0x0  | 0               |
|     |         | 13        | YES   | 0x0  | 0               |
|     |         | 14        | YES   | 0x0  | 0               |
|     |         | 15        | NO    | 0x0  | 0               |
==============================================================
>/usr/bin/bcmcmd field fem info act
=========================================================================================
|                       Legend - For table of FEM actions, below.                       |
=========================================================================================
| column name        | description                                                      |
=========================================================================================
| Action index       | Index of 'action' within all 4 'actions' available per 'fem_id'  |
-----------------------------------------------------------------------------------------
| Fem program *      | Indication on whether specified fem program has, on at least one |
|                    | of its 'conditions', a pointer to 'action index'                 |
-----------------------------------------------------------------------------------------
| Action type value  | Numerical value of action, as stored on HW (and as specified in  |
|                    | the spec                                                         |
-----------------------------------------------------------------------------------------
| Action type string | String descriptor of action, as stored on corresponding DBAL     |
|                    | enum                                                             |
-----------------------------------------------------------------------------------------
| Bit index          | Index of the bit, within hardware, for which one of a few        |
|                    | descriptors is selected by the user.                             |
|                    | Note that there are 4 bits for 'fem_id' 0/1 and 24 bits for the  |
|                    | others                                                           |
-----------------------------------------------------------------------------------------
| Bit desc           | Indication on how HW is instructed to handle this bit:           |
|                    | 'Ix' stands for 'For bit-index, take value from bit x on input   |
|                    | 32 bits (x may be 0 - 31)',                                      |
|                    | 'Cx' stands for 'For bit-index, take constant value x as stored  |
|                    | by caller (x may be 0 or 1)',                                    |
|                    | 'Dx' stands for 'For bit-index, take value from bit x fon 4-bits |
|                    | map-data (x may be 0 - 3)',                                      |
|                    | '--' stands for 'For bit-index, descriptor is 'invalid' (E.g.,   |
|                    | bit5 on fem_id 0)                                                |
=========================================================================================
=======================================================================================================================
|                             Active-only fem actions - HW actions for fem: from 0 to 15                              |
=======================================================================================================================
| FEM | Action | Action | Action type string          | Adder | Fem     | Fem     | Fem     | Fem     | Bit   | Bit   |
| id  | index  | type   |                             |       | program | program | program | program | index | desc. |
|     |        | value  |                             |       | 0       | 1       | 2       | 3       |       |       |
=======================================================================================================================
|     |        |        |                             |       |         |         |         |         |       |       |
| 0   |        |        |                             |       |         |         |         |         |       |       |
|     | 0      | 96     | SYSTEM_HEADER_PROFILE_INDEX | --    | V       | --      | --      | --      |       |       |
|     |        |        |                             |       |         |         |         |         | 0     | C0    |
|     |        |        |                             |       |         |         |         |         | 1     | C0    |
|     |        |        |                             |       |         |         |         |         | 2     | C1    |
|     |        |        |                             |       |         |         |         |         | 3     | C0    |
|     |        |        |                             |       |         |         |         |         | 4     | --    |
|     |        |        |                             |       |         |         |         |         | 5     | --    |
|     |        |        |                             |       |         |         |         |         | 6     | --    |
|     |        |        |                             |       |         |         |         |         | 7     | --    |
|     |        |        |                             |       |         |         |         |         | 8     | --    |
|     |        |        |                             |       |         |         |         |         | 9     | --    |
|     |        |        |                             |       |         |         |         |         | 10    | --    |
|     |        |        |                             |       |         |         |         |         | 11    | --    |
|     |        |        |                             |       |         |         |         |         | 12    | --    |
|     |        |        |                             |       |         |         |         |         | 13    | --    |
|     |        |        |                             |       |         |         |         |         | 14    | --    |
|     |        |        |                             |       |         |         |         |         | 15    | --    |
|     |        |        |                             |       |         |         |         |         | 16    | --    |
|     |        |        |                             |       |         |         |         |         | 17    | --    |
|     |        |        |                             |       |         |         |         |         | 18    | --    |
|     |        |        |                             |       |         |         |         |         | 19    | --    |
|     |        |        |                             |       |         |         |         |         | 20    | --    |
|     |        |        |                             |       |         |         |         |         | 21    | --    |
|     |        |        |                             |       |         |         |         |         | 22    | --    |
|     |        |        |                             |       |         |         |         |         | 23    | --    |
|     | 1      | 96     | SYSTEM_HEADER_PROFILE_INDEX | --    | V       | --      | --      | --      |       |       |
|     |        |        |                             |       |         |         |         |         | 0     | C0    |
|     |        |        |                             |       |         |         |         |         | 1     | C1    |
|     |        |        |                             |       |         |         |         |         | 2     | C0    |
|     |        |        |                             |       |         |         |         |         | 3     | C0    |
|     |        |        |                             |       |         |         |         |         | 4     | --    |
|     |        |        |                             |       |         |         |         |         | 5     | --    |
|     |        |        |                             |       |         |         |         |         | 6     | --    |
|     |        |        |                             |       |         |         |         |         | 7     | --    |
|     |        |        |                             |       |         |         |         |         | 8     | --    |
|     |        |        |                             |       |         |         |         |         | 9     | --    |
|     |        |        |                             |       |         |         |         |         | 10    | --    |
|     |        |        |                             |       |         |         |         |         | 11    | --    |
|     |        |        |                             |       |         |         |         |         | 12    | --    |
|     |        |        |                             |       |         |         |         |         | 13    | --    |
|     |        |        |                             |       |         |         |         |         | 14    | --    |
|     |        |        |                             |       |         |         |         |         | 15    | --    |
|     |        |        |                             |       |         |         |         |         | 16    | --    |
|     |        |        |                             |       |         |         |         |         | 17    | --    |
|     |        |        |                             |       |         |         |         |         | 18    | --    |
|     |        |        |                             |       |         |         |         |         | 19    | --    |
|     |        |        |                             |       |         |         |         |         | 20    | --    |
|     |        |        |                             |       |         |         |         |         | 21    | --    |
|     |        |        |                             |       |         |         |         |         | 22    | --    |
|     |        |        |                             |       |         |         |         |         | 23    | --    |
| 2   |        |        |                             |       |         |         |         |         |       |       |
|     | 0      | 43     | GLOB_OUT_LIF_0              | 0     | V       | --      | --      | --      |       |       |
|     |        |        |                             |       |         |         |         |         | 0     | I2    |
|     |        |        |                             |       |         |         |         |         | 1     | I3    |
|     |        |        |                             |       |         |         |         |         | 2     | I4    |
|     |        |        |                             |       |         |         |         |         | 3     | I5    |
|     |        |        |                             |       |         |         |         |         | 4     | I6    |
|     |        |        |                             |       |         |         |         |         | 5     | I7    |
|     |        |        |                             |       |         |         |         |         | 6     | I8    |
|     |        |        |                             |       |         |         |         |         | 7     | I9    |
|     |        |        |                             |       |         |         |         |         | 8     | I10   |
|     |        |        |                             |       |         |         |         |         | 9     | I11   |
|     |        |        |                             |       |         |         |         |         | 10    | I12   |
|     |        |        |                             |       |         |         |         |         | 11    | I13   |
|     |        |        |                             |       |         |         |         |         | 12    | I14   |
|     |        |        |                             |       |         |         |         |         | 13    | I15   |
|     |        |        |                             |       |         |         |         |         | 14    | I16   |
|     |        |        |                             |       |         |         |         |         | 15    | I17   |
|     |        |        |                             |       |         |         |         |         | 16    | I18   |
|     |        |        |                             |       |         |         |         |         | 17    | I19   |
|     |        |        |                             |       |         |         |         |         | 18    | I20   |
|     |        |        |                             |       |         |         |         |         | 19    | I21   |
|     |        |        |                             |       |         |         |         |         | 20    | I22   |
|     |        |        |                             |       |         |         |         |         | 21    | I23   |
|     |        |        |                             |       |         |         |         |         | 22    | C0    |
|     |        |        |                             |       |         |         |         |         | 23    | C0    |
|     | 1      | 43     | GLOB_OUT_LIF_0              | 0     | --      | V       | --      | --      |       |       |
|     |        |        |                             |       |         |         |         |         | 0     | I3    |
|     |        |        |                             |       |         |         |         |         | 1     | I4    |
|     |        |        |                             |       |         |         |         |         | 2     | I5    |
|     |        |        |                             |       |         |         |         |         | 3     | I6    |
|     |        |        |                             |       |         |         |         |         | 4     | I7    |
|     |        |        |                             |       |         |         |         |         | 5     | I8    |
|     |        |        |                             |       |         |         |         |         | 6     | I9    |
|     |        |        |                             |       |         |         |         |         | 7     | I10   |
|     |        |        |                             |       |         |         |         |         | 8     | I11   |
|     |        |        |                             |       |         |         |         |         | 9     | I12   |
|     |        |        |                             |       |         |         |         |         | 10    | I13   |
|     |        |        |                             |       |         |         |         |         | 11    | I14   |
|     |        |        |                             |       |         |         |         |         | 12    | I15   |
|     |        |        |                             |       |         |         |         |         | 13    | I16   |
|     |        |        |                             |       |         |         |         |         | 14    | I17   |
|     |        |        |                             |       |         |         |         |         | 15    | I18   |
|     |        |        |                             |       |         |         |         |         | 16    | I19   |
|     |        |        |                             |       |         |         |         |         | 17    | I20   |
|     |        |        |                             |       |         |         |         |         | 18    | I21   |
|     |        |        |                             |       |         |         |         |         | 19    | I22   |
|     |        |        |                             |       |         |         |         |         | 20    | I23   |
|     |        |        |                             |       |         |         |         |         | 21    | I24   |
|     |        |        |                             |       |         |         |         |         | 22    | C0    |
|     |        |        |                             |       |         |         |         |         | 23    | C0    |
| 3   |        |        |                             |       |         |         |         |         |       |       |
|     | 0      | 39     | MIRROR_DATA                 | 0     | V       | V       | --      | --      |       |       |
|     |        |        |                             |       |         |         |         |         | 0     | C0    |
|     |        |        |                             |       |         |         |         |         | 1     | C0    |
|     |        |        |                             |       |         |         |         |         | 2     | C0    |
|     |        |        |                             |       |         |         |         |         | 3     | C0    |
|     |        |        |                             |       |         |         |         |         | 4     | C0    |
|     |        |        |                             |       |         |         |         |         | 5     | C1    |
|     |        |        |                             |       |         |         |         |         | 6     | C1    |
|     |        |        |                             |       |         |         |         |         | 7     | C1    |
|     |        |        |                             |       |         |         |         |         | 8     | C1    |
|     |        |        |                             |       |         |         |         |         | 9     | C0    |
|     |        |        |                             |       |         |         |         |         | 10    | C0    |
|     |        |        |                             |       |         |         |         |         | 11    | C0    |
|     |        |        |                             |       |         |         |         |         | 12    | C0    |
|     |        |        |                             |       |         |         |         |         | 13    | C0    |
|     |        |        |                             |       |         |         |         |         | 14    | C0    |
|     |        |        |                             |       |         |         |         |         | 15    | C0    |
|     |        |        |                             |       |         |         |         |         | 16    | C0    |
|     |        |        |                             |       |         |         |         |         | 17    | C0    |
|     |        |        |                             |       |         |         |         |         | 18    | C0    |
|     |        |        |                             |       |         |         |         |         | 19    | C0    |
|     |        |        |                             |       |         |         |         |         | 20    | C0    |
|     |        |        |                             |       |         |         |         |         | 21    | C0    |
|     |        |        |                             |       |         |         |         |         | 22    | C0    |
|     |        |        |                             |       |         |         |         |         | 23    | C0    |
| 4   |        |        |                             |       |         |         |         |         |       |       |
|     | 0      | 18     | FWD_TRAP                    | 0     | V       | --      | --      | --      |       |       |
|     |        |        |                             |       |         |         |         |         | 0     | C1    |
|     |        |        |                             |       |         |         |         |         | 1     | C0    |
|     |        |        |                             |       |         |         |         |         | 2     | C0    |
|     |        |        |                             |       |         |         |         |         | 3     | C1    |
|     |        |        |                             |       |         |         |         |         | 4     | C0    |
|     |        |        |                             |       |         |         |         |         | 5     | C0    |
|     |        |        |                             |       |         |         |         |         | 6     | C0    |
|     |        |        |                             |       |         |         |         |         | 7     | C0    |
|     |        |        |                             |       |         |         |         |         | 8     | C0    |
|     |        |        |                             |       |         |         |         |         | 9     | C1    |
|     |        |        |                             |       |         |         |         |         | 10    | C1    |
|     |        |        |                             |       |         |         |         |         | 11    | C1    |
|     |        |        |                             |       |         |         |         |         | 12    | C1    |
|     |        |        |                             |       |         |         |         |         | 13    | C0    |
|     |        |        |                             |       |         |         |         |         | 14    | C0    |
|     |        |        |                             |       |         |         |         |         | 15    | C0    |
|     |        |        |                             |       |         |         |         |         | 16    | C0    |
|     |        |        |                             |       |         |         |         |         | 17    | C0    |
|     |        |        |                             |       |         |         |         |         | 18    | C0    |
|     |        |        |                             |       |         |         |         |         | 19    | C0    |
|     |        |        |                             |       |         |         |         |         | 20    | C0    |
|     |        |        |                             |       |         |         |         |         | 21    | C0    |
|     |        |        |                             |       |         |         |         |         | 22    | C0    |
|     |        |        |                             |       |         |         |         |         | 23    | C0    |
=======================================================================================================================
>/usr/bin/bcmcmd field cont list
==========================================================================================================================================
|                                                                       CONTEXT                                                      |
==========================================================================================================================================
| CTX ID  | Stage       | Name                | Presel IDs                 | Presel(Value, Mask, Arg)               | Mode               |
==========================================================================================================================================
| 0       | IngressPMF1 | Default_Ctx         | 127                        | Always Hit                             | CMP1.D, HASH.E     |
------------------------------------------------------------------------------------------------------------------------------------------
| 4       | IngressPMF1 | DFLT                | 61                         | Ptch(0, 0x7, N/A)                      | N/A                |
------------------------------------------------------------------------------------------------------------------------------------------
| 5       | IngressPMF1 | IPv6                | 60                         | ForwardingLayerIndex(1, 0x7, N/A),     | N/A                |
|         |             |                     |                            | ForwardingType(Ip6, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 6       | IngressPMF1 | IPv4                | 59                         | ForwardingLayerIndex(1, 0x7, N/A),     | N/A                |
|         |             |                     |                            | ForwardingType(Ip4, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 11      | IngressPMF1 | IPv6PtpRxTrapCode   | 54                         | ForwardingLayerIndex(1, 0x7, N/A),     | N/A                |
|         |             |                     |                            | RxTrapCode(152, 0x1FF, N/A),           |                    |
|         |             |                     |                            | ForwardingType(Ip6, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 12      | IngressPMF1 | IPv4PtpRxTrapCode   | 53                         | ForwardingLayerIndex(1, 0x7, N/A),     | N/A                |
|         |             |                     |                            | RxTrapCode(152, 0x1FF, N/A),           |                    |
|         |             |                     |                            | ForwardingType(Ip4, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 13      | IngressPMF1 | L2|MPLS             | 52                         | ForwardingLayerIndex(3, 0x7, N/A),     | N/A                |
|         |             |                     |                            | ForwardingType(Mpls, 0x1F, -1/7),      |                    |
|         |             |                     |                            | ForwardingType(Eth, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 17      | IngressPMF1 | MPLS                | 48                         | ForwardingLayerIndex(2, 0x7, N/A),     | N/A                |
|         |             |                     |                            | ForwardingType(Mpls, 0x1F, -1/7),      |                    |
|         |             |                     |                            | ForwardingType(Mpls, 0x1F, 0)          |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 19      | IngressPMF1 | IPv4|MPLS           | 46                         | ForwardingLayerIndex(3, 0x7, N/A),     | N/A                |
|         |             |                     |                            | ForwardingType(Mpls, 0x1F, -1/7),      |                    |
|         |             |                     |                            | ForwardingType(Ip4, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 20      | IngressPMF1 | InjL2               | 45                         | Ptch(7, 0x7, N/A),                     | N/A                |
|         |             |                     |                            | ForwardingType(Eth, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 21      | IngressPMF1 | InjIPv4             | 44                         | Ptch(2, 0x7, N/A),                     | N/A                |
|         |             |                     |                            | ForwardingType(Ip4, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 22      | IngressPMF1 | InjIPv6             | 43                         | Ptch(2, 0x7, N/A),                     | N/A                |
|         |             |                     |                            | ForwardingType(Ip6, 0x1F, 0)           |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 28      | IngressPMF1 | InPortType          | 37                         | PortClassPacketProcessing(6, 0x7, N/A) | N/A                |
------------------------------------------------------------------------------------------------------------------------------------------
| 49      | IngressPMF1 | ITMH_PPH_FHEI_IPMF1 | 39, 116                    | ForwardingType(Tm, 0x1F, 0),           | CMP1.D, CMP2.D     |
|         |             |                     |                            | ForwardingLayerQualifier(1, 0x1, 0),   |                    |
|         |             |                     |                            | ForwardingLayerQualifier(32, 0x30,     |                    |
|         |             |                     |                            | 2/-6)                                  |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 51      | IngressPMF1 | ITMH_1588_TSH_IPMF1 | 40, 118                    | ForwardingType(Tm, 0x1F, 0),           | N/A                |
|         |             |                     |                            | ForwardingLayerQualifier(2, 0x7, 1/-7) |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 62      | IngressPMF1 | ITMH_PPH_IPMF1      | 41, 125                    | ForwardingType(Tm, 0x1F, 0),           | CMP1.D             |
|         |             |                     |                            | ForwardingLayerQualifier(1, 0x1, 0),   |                    |
|         |             |                     |                            | ForwardingLayerQualifier(0, 0x30,      |                    |
|         |             |                     |                            | 2/-6)                                  |                    |
------------------------------------------------------------------------------------------------------------------------------------------
| 63      | IngressPMF1 | ITMH_IPMF1          | 42, 126                    | ForwardingType(Tm, 0x1F, 0)            | N/A                |
------------------------------------------------------------------------------------------------------------------------------------------
| 0       | IngressPMF2 | Default_Ctx         | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 0    |
------------------------------------------------------------------------------------------------------------------------------------------
| 4       | IngressPMF2 | DFLT                | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 4    |
------------------------------------------------------------------------------------------------------------------------------------------
| 5       | IngressPMF2 | IPv6                | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 5    |
------------------------------------------------------------------------------------------------------------------------------------------
| 6       | IngressPMF2 | IPv4                | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 6    |
------------------------------------------------------------------------------------------------------------------------------------------
| 11      | IngressPMF2 | IPv6PtpRxTrapCode   | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 11   |
------------------------------------------------------------------------------------------------------------------------------------------
| 12      | IngressPMF2 | IPv4PtpRxTrapCode   | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 12   |
------------------------------------------------------------------------------------------------------------------------------------------
| 13      | IngressPMF2 | L2|MPLS             | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 13   |
------------------------------------------------------------------------------------------------------------------------------------------
| 17      | IngressPMF2 | MPLS                | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 17   |
------------------------------------------------------------------------------------------------------------------------------------------
| 19      | IngressPMF2 | IPv4|MPLS           | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 19   |
------------------------------------------------------------------------------------------------------------------------------------------
| 20      | IngressPMF2 | InjL2               | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 20   |
------------------------------------------------------------------------------------------------------------------------------------------
| 21      | IngressPMF2 | InjIPv4             | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 21   |
------------------------------------------------------------------------------------------------------------------------------------------
| 22      | IngressPMF2 | InjIPv6             | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 22   |
------------------------------------------------------------------------------------------------------------------------------------------
| 28      | IngressPMF2 | InPortType          | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 28   |
------------------------------------------------------------------------------------------------------------------------------------------
| 49      | IngressPMF2 | ITMH_PPH_FHEI_IPMF1 | 116                        | CompareKeysResult0(2, 0x7, N/A)        | Cascading_Ctx 49   |
------------------------------------------------------------------------------------------------------------------------------------------
| 51      | IngressPMF2 | ITMH_1588_TSH_IPMF1 | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 51   |
------------------------------------------------------------------------------------------------------------------------------------------
| 61      | IngressPMF2 | ITMH_PPH_FHEI_Vlan  | 120                        | CompareKeysResult1(2, 0x7, N/A)        | Cascading_Ctx 49   |
------------------------------------------------------------------------------------------------------------------------------------------
| 62      | IngressPMF2 | ITMH_PPH_IPMF1      | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 62   |
------------------------------------------------------------------------------------------------------------------------------------------
| 63      | IngressPMF2 | ITMH_IPMF1          | No hit - iPMF1 ctx chosen! | -                                      | Cascading_Ctx 63   |
------------------------------------------------------------------------------------------------------------------------------------------
| 0       | IngressPMF3 | Default_Ctx         | 127                        | Always Hit                             | N/A                |
------------------------------------------------------------------------------------------------------------------------------------------
| 62      | IngressPMF3 | ITMH_PPH_IPMF3      | 111, 112, 126              | ContextId(62, 0x3F, N/A)               | N/A                |
------------------------------------------------------------------------------------------------------------------------------------------
| 0       | Egress      | Default_Ctx         | 127                        | Always Hit                             | N/A                |
------------------------------------------------------------------------------------------------------------------------------------------
| 1       | Egress      | Eg                  | 64                         |                                        | N/A                |
------------------------------------------------------------------------------------------------------------------------------------------
| 1 (AT)  | External    | L2                  | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 7 (AT)  | External    | Mpls                | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 12 (AT) | External    | TrafficManagement   | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 15 (AT) | External    | Ip4UcastRpf         | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 16 (AT) | External    | Ip6UcastRpf         | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 17 (AT) | External    | Ip4McastRpf         | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 19 (AT) | External    | Ip6McastRpf         | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 45 (AT) | External    | Vip4                | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 46 (AT) | External    | Vip6                | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 47 (AT) | External    | Vip4Direct          | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 48 (AT) | External    | Vip6Direct          | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 49 (AT) | External    | Srv6Endpoint        | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 50 (AT) | External    | Srv6UsidEndpoint    | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
------------------------------------------------------------------------------------------------------------------------------------------
| 51 (AT) | External    | Srv6GsidEndpoint    | No hit - FWD ctx chosen!   | -                                      | Predefined Apptype |
==========================================================================================================================================
>/usr/bin/bcmcmd field qual user
====================================================================================================
|                                  FIELD_User_Defined_Qualifiers                                   |
====================================================================================================
| Qualifier | Name                                 | Size | FG / Context (mode)                    |
| ID        |                                      |      |                                        |
====================================================================================================
| 0         | pph_type_qual                        | 2    | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 1         | dp_dst_snp_tc_qual                   | 31   | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 2         | ext_exist_qual                       | 1    | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 3         | out_lif_dst_qual                     | 22   | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 4         | ase_inj_qual                         | 1    | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 5         | mirror_qual                          | 1    | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 6         | itmh_oam_valid_bit                   | 1    | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 7         | itmh_fbr_hdr_set                     | 4    | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 8         | itmh_fwd_l_idx                       | 3    | FG: 0 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 9         | ase_offset_1588                      | 8    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 10        | ts_encapsulation_1588                | 1    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 11        | ts_command_1588                      | 2    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 12        | use_ingress_time_stamp_1588          | 1    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 13        | ase_type_qual_1588                   | 1    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 14        | tsh_inj_q_1588                       | 1    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 15        | itmh_fwd_l_idx_1588                  | 3    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 16        | time_stamp_valid_qual                | 1    | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 17        | time_stamp_qual                      | 32   | FG: 1 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 18        | itmh_fbr_hdr_set_qual                | 4    | FG: 2 / "ITMH"                         |
----------------------------------------------------------------------------------------------------
| 19        | lif_extension_q_pph                  | 3    | CTX: 62 / "ITMH_PPH_IPMF1 (CMP1)"      |
----------------------------------------------------------------------------------------------------
| 20        | key_gen_var_q_pph                    | 3    | CTX: 62 / "ITMH_PPH_IPMF1 (CMP1)"      |
----------------------------------------------------------------------------------------------------
| 21        | fhei_trap_type_q_pph                 | 4    | CTX: 49 / "ITMH_PPH_FHEI_IPMF1 (CMP1)" |
----------------------------------------------------------------------------------------------------
| 22        | lif_extension_trap_q_pph             | 3    | CTX: 49 / "ITMH_PPH_FHEI_IPMF1 (CMP1)" |
----------------------------------------------------------------------------------------------------
| 23        | key_gen_var_trap_q_pph               | 7    | CTX: 49 / "ITMH_PPH_FHEI_IPMF1 (CMP1)" |
----------------------------------------------------------------------------------------------------
| 24        | fhei_vlan_type_q_pph                 | 1    | CTX: 49 / "ITMH_PPH_FHEI_IPMF1 (CMP2)" |
----------------------------------------------------------------------------------------------------
| 25        | lif_extension_vlan_q_pph             | 3    | CTX: 49 / "ITMH_PPH_FHEI_IPMF1 (CMP2)" |
----------------------------------------------------------------------------------------------------
| 26        | key_gen_var_vlan_q_pph               | 4    | CTX: 49 / "ITMH_PPH_FHEI_IPMF1 (CMP2)" |
----------------------------------------------------------------------------------------------------
| 27        | tc_sn_dst_dp_mr_pph_q_pph            | 34   | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 28        | ext_exist_q_pph                      | 1    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 29        | out_lif_dst_q_pph                    | 22   | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 30        | ase_inj_q_pph                        | 1    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 31        | time_stamp_q_pph                     | 32   | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 32        | L2CP part1                           | 32   | FG: 7 / "System L2CP"                  |
----------------------------------------------------------------------------------------------------
| 33        | L2CP part2                           | 32   | FG: 7 / "System L2CP"                  |
----------------------------------------------------------------------------------------------------
| 34        | LSP-ping UDP port                    | 16   |                                        |
----------------------------------------------------------------------------------------------------
| 35        | LSP-ping DIP                         | 8    |                                        |
----------------------------------------------------------------------------------------------------
| 36        | LSP-ping IP proto                    | 8    |                                        |
----------------------------------------------------------------------------------------------------
| 37        | PWE inner DMAC1                      | 32   |                                        |
----------------------------------------------------------------------------------------------------
| 38        | PWE inner DMAC2                      | 16   |                                        |
----------------------------------------------------------------------------------------------------
| 39        | PWE inner etype                      | 16   |                                        |
----------------------------------------------------------------------------------------------------
| 40        | PWE inner IP proto                   | 8    |                                        |
----------------------------------------------------------------------------------------------------
| 41        | PWE inner DIP                        | 32   |                                        |
----------------------------------------------------------------------------------------------------
| 42        | PWE inner L4 src port                | 16   |                                        |
----------------------------------------------------------------------------------------------------
| 43        | PWE inner L4 dst port                | 16   |                                        |
----------------------------------------------------------------------------------------------------
| 44        | PHP upper proto                      | 4    |                                        |
----------------------------------------------------------------------------------------------------
| 45        | PWE learn-info                       | 24   |                                        |
----------------------------------------------------------------------------------------------------
| 46        | FEC index                            | 24   |                                        |
----------------------------------------------------------------------------------------------------
| 47        | Learn FEC index                      | 24   |                                        |
----------------------------------------------------------------------------------------------------
| 48        | Meter/Stat ID                        | 16   | FG: 6 / "InLifMeter (DIRECT)"          |
----------------------------------------------------------------------------------------------------
| 49        | L3 ACL profile                       | 6    | FG: 10 / "Acl IPv6"                    |
|           |                                      |      | FG: 11 / "Acl IPv4"                    |
----------------------------------------------------------------------------------------------------
| 50        | L2 ACL profile                       | 2    |                                        |
----------------------------------------------------------------------------------------------------
| 51        | ICMP type                            | 8    | FG: 10 / "Acl IPv6"                    |
|           |                                      |      | FG: 11 / "Acl IPv4"                    |
----------------------------------------------------------------------------------------------------
| 52        | fwd_trap_code_zero_q_pph             | 9    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 53        | fwd_str_res_bit_q_1                  | 3    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 54        | fwd_str_q_pph                        | 1    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 55        | oam_stamp_offset_q_pph               | 8    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 56        | oam_offset_q_pph                     | 8    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 57        | oam_sub_type_q_pph                   | 4    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 58        | oam_mep_q_pph                        | 1    | FG: 3 / "ITMH_PPH-OAM_TSH"             |
----------------------------------------------------------------------------------------------------
| 59        | pars_offset_valid_q_pph              | 1    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 60        | parsing_offset_q_pph                 | 7    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 61        | FHEI type                            | 4    | FG: 4 / "Egress Rules"                 |
----------------------------------------------------------------------------------------------------
| 62        | Ethertype (improved)                 | 16   | FG: 7 / "System L2CP"                  |
|           |                                      |      | FG: 8 / "System L3CP"                  |
|           |                                      |      | FG: 9 / "Acl"                          |
----------------------------------------------------------------------------------------------------
| 63        | In-LIF (18bits)                      | 18   | FG: 7 / "System L2CP"                  |
----------------------------------------------------------------------------------------------------
| 64        | Inner TPID                           | 16   | FG: 9 / "Acl"                          |
----------------------------------------------------------------------------------------------------
| 65        | Inner VID                            | 12   | FG: 9 / "Acl"                          |
----------------------------------------------------------------------------------------------------
| 66        | Inner PCP                            | 3    | FG: 9 / "Acl"                          |
----------------------------------------------------------------------------------------------------
| 67        | pars_type_valid_q_pph                | 1    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 68        | parsing_type_q_pph                   | 5    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 69        | Slow Protocol Sub-Type               | 8    | FG: 4 / "Egress Rules"                 |
----------------------------------------------------------------------------------------------------
| 70        | In PP port (9bits)                   | 9    | FG: 7 / "System L2CP"                  |
----------------------------------------------------------------------------------------------------
| 71        | In AC LIF                            | 19   | FG: 12 / "QosFlow"                     |
----------------------------------------------------------------------------------------------------
| 72        | adj_size_layer_idx_egr_prs_idx_q_pph | 7    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 73        | ttl_set_q                            | 8    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 74        | in_lif_profile_q_pph                 | 8    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 75        | fwd_additional_info_q_pph            | 4    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 76        | NWK_QoS_q_pph                        | 8    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 77        | End_Of_Pkt_Edit_q_pph                | 3    | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 78        | in_lif_0_q_pph                       | 22   | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 79        | fwd_domain_q_pph                     | 18   | FG: 15 / "ITMH_PPH-PPH"                |
----------------------------------------------------------------------------------------------------
| 80        | 1bitCmpResult_q_pph                  | 1    | FG: 16 / "ITMH_PPH-FHEI_Trap"          |
----------------------------------------------------------------------------------------------------
| 81        | fwd_trap_code_q_pph                  | 9    | FG: 16 / "ITMH_PPH-FHEI_Trap"          |
----------------------------------------------------------------------------------------------------
| 82        | fwd_str_res_bit_q_2                  | 3    | FG: 16 / "ITMH_PPH-FHEI_Trap"          |
----------------------------------------------------------------------------------------------------
| 83        | fwd_str_q                            | 1    | FG: 16 / "ITMH_PPH-FHEI_Trap"          |
----------------------------------------------------------------------------------------------------
| 84        | fwd_qualifier_q_pph                  | 19   | FG: 16 / "ITMH_PPH-FHEI_Trap"          |
----------------------------------------------------------------------------------------------------
| 85        | fhei_bridge_5B_innerVlan_q_pph       | 16   | FG: 17 / "ITMH_PPH-FHEI_Vlan"          |
----------------------------------------------------------------------------------------------------
| 86        | fhei_bridge_5B_Vact_outV_q_pph       | 23   | FG: 17 / "ITMH_PPH-FHEI_Vlan"          |
----------------------------------------------------------------------------------------------------
| 87        | sys_hdr_const_q_pph                  | 24   | FG: 17 / "ITMH_PPH-FHEI_Vlan"          |
====================================================================================================
>/usr/bin/bcmcmd field act user
====================================================================================================================================================
|                                                            FIELD_User_Defined_actions                                                      |
====================================================================================================================================================
| Action | Name                                | Stage           | Size | Prefix | Prefix | Base action            | FG Id/Name                    |
| ID     |                                     |                 |      | size   | Value  |                        |                               |
====================================================================================================================================================
| 92     | NwkQos                              | IngressPMF1     | 3    | 5      | 0x0    | NetworkQos             | FG: 7 / "System L2CP"         |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 0      | snoop_data_act                      | IngressPMF2     | 5    | 15     | 0x7f   | SnoopRaw               | FG: 0 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 4      | destination_act                     | IngressPMF2     | 21   | 11     | 0x0    | Forward                | FG: 0 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 5      | ext_exist_act                       | IngressPMF2     | 1    | 31     | 0x0    | Void                   | FG: 0 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 6      | out_lif_act                         | IngressPMF2     | 22   | 10     | 0x0    | Void                   | FG: 0 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 7      | udh3_1bit_ase_act                   | IngressPMF2     | 1    | 31     | 0x0    | UDHData3               | FG: 0 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 8      | mirror_command_act                  | IngressPMF2     | 1    | 31     | 0x0    | Void                   | FG: 0 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 9      | fwd_act_str_act                     | IngressPMF2     | 4    | 28     | 0x0    | Void                   | FG: 0 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 10     | tsh_with_flow_id_valid_bit_act_1588 | IngressPMF2     | 1    | 23     | 0x0    | LatencyFlowIdRaw       | FG: 1 / "ITMH"                |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 11     | snoop_data_a_pph                    | IngressPMF2     | 5    | 15     | 0x7f   | SnoopRaw               | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 12     | destination_a_pph                   | IngressPMF2     | 21   | 11     | 0x0    | Forward                | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 13     | mirror_command_a_pph                | IngressPMF2     | 1    | 31     | 0x0    | Void                   | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 14     | ext_exist_a_pph                     | IngressPMF2     | 1    | 31     | 0x0    | Void                   | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 15     | out_lif_a_pph                       | IngressPMF2     | 22   | 10     | 0x0    | Void                   | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 16     | udh3_1bit_ase_a_pph                 | IngressPMF2     | 1    | 31     | 0x0    | UDHData2               | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 17     | fwd_str_a_pph                       | IngressPMF2     | 13   | 19     | 0x0    | TrapRaw                | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 18     | lr_qual_a_pph                       | IngressPMF2     | 16   | 16     | 0x0    | Void                   | FG: 3 / "ITMH_PPH-OAM_TSH"    |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 19     | pars_start_sys_adjust_a_pph         | IngressPMF2     | 21   | 11     | 0x0    | Container              | FG: 15 / "ITMH_PPH-PPH"       |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 55     | Stat2FpMeter                        | IngressPMF2     | 16   | 4      | 0x0    | StatId2                | FG: 6 / "InLifMeter (DIRECT)" |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 56     | Stat6FpStat                         | IngressPMF2     | 16   | 4      | 0x0    | StatId6                | FG: 6 / "InLifMeter (DIRECT)" |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 20     | parsing_start_offset_a_pph          | IngressPMF3     | 8    | 0      | 0x0    | ParsingStartOffsetRaw  | FG: 18 / "ITMH_PPH_IPMF3"     |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 21     | act_s_h_adjust_size_a_pph           | IngressPMF3     | 1    | 6      | 0x0    | SystemHeaderSizeAdjust | FG: 18 / "ITMH_PPH_IPMF3"     |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 22     | zero_action_a_pph                   | IngressPMF3     | 11   | 21     | 0x0    | Void                   | FG: 18 / "ITMH_PPH_IPMF3"     |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 1      | UDA_PPMC_OUTLIF_0                   | EgressExtension | 22   | 1      | 0x1    | OutVport0Raw           | ACE: 1 / "PPMC_SINGLE_OUTLIF" |
|        |                                     |                 |      |        |        |                        | ACE: 2 / "PPMC_DOUBLE_OUTLIF" |
|        |                                     |                 |      |        |        |                        | ACE: 3 / "PPMC_TRIPLE_OUTLIF" |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 2      | UDA_PPMC_OUTLIF_1                   | EgressExtension | 22   | 1      | 0x1    | OutVport1Raw           | ACE: 2 / "PPMC_DOUBLE_OUTLIF" |
|        |                                     |                 |      |        |        |                        | ACE: 3 / "PPMC_TRIPLE_OUTLIF" |
----------------------------------------------------------------------------------------------------------------------------------------------------
| 3      | UDA_PPMC_OUTLIF_2                   | EgressExtension | 22   | 1      | 0x1    | OutVport2Raw           | ACE: 3 / "PPMC_TRIPLE_OUTLIF" |
====================================================================================================================================================
>/usr/bin/bcmcmd field sys info stage=IPMF1
Command:"sys" is not supported for current device and/or configuration
>/usr/bin/bcmcmd field sys info stage=IPMF2
Command:"sys" is not supported for current device and/or configuration
>/usr/bin/bcmcmd field sys info stage=IPMF3
Command:"sys" is not supported for current device and/or configuration
>/usr/bin/bcmcmd field sys info stage=EPMF
Command:"sys" is not supported for current device and/or configuration
>/usr/bin/bcmcmd field sys head
Command:"sys" is not supported for current device and/or configuration
>/usr/bin/bcmcmd field grp list
===============================================================================
|                                     FIELD_GROUP                             |
===============================================================================
| FG | Name                | Type              | Stage       | Key  | Payload |
| ID |                     |                   |             | Size | Size    |
===============================================================================
| 5  | Misc                | TCAM              | IngressPMF1 | 160  | 64      |
-------------------------------------------------------------------------------
| 7  | System L2CP         | TCAM              | IngressPMF1 | 160  | 64      |
-------------------------------------------------------------------------------
| 8  | System L3CP         | TCAM              | IngressPMF1 | 160  | 64      |
-------------------------------------------------------------------------------
| 12 | QosFlow             | TCAM              | IngressPMF1 | 160  | 64      |
-------------------------------------------------------------------------------
| 13 | L3 Injection        | TCAM              | IngressPMF1 | 80   | 32      |
-------------------------------------------------------------------------------
| 14 | L2 Injection        | TCAM              | IngressPMF1 | 80   | 32      |
-------------------------------------------------------------------------------
| 27 | RcyTrapInPortType   | TCAM              | IngressPMF1 | 160  | 64      |
-------------------------------------------------------------------------------
| 28 | IEEE1588(PTP)       | TCAM              | IngressPMF1 | 160  | 64      |
-------------------------------------------------------------------------------
| 0  | ITMH                | DIRECT_EXTRACTION | IngressPMF2 | 70   | 70      |
-------------------------------------------------------------------------------
| 1  | ITMH                | DIRECT_EXTRACTION | IngressPMF2 | 50   | 50      |
-------------------------------------------------------------------------------
| 2  | ITMH                | DIRECT_EXTRACTION | IngressPMF2 | 4    | 4       |
-------------------------------------------------------------------------------
| 3  | ITMH_PPH-OAM_TSH    | DIRECT_EXTRACTION | IngressPMF2 | 140  | 140     |
-------------------------------------------------------------------------------
| 6  | InLifMeter (DIRECT) | DIRECT_TABLE_MDB  | IngressPMF2 | N/A  | N/A     |
-------------------------------------------------------------------------------
| 9  | Acl                 | TCAM              | IngressPMF2 | 320  | 128     |
-------------------------------------------------------------------------------
| 10 | Acl IPv6            | TCAM              | IngressPMF2 | 320  | 128     |
-------------------------------------------------------------------------------
| 11 | Acl IPv4            | TCAM              | IngressPMF2 | 320  | 128     |
-------------------------------------------------------------------------------
| 15 | ITMH_PPH-PPH        | DIRECT_EXTRACTION | IngressPMF2 | 92   | 92      |
-------------------------------------------------------------------------------
| 16 | ITMH_PPH-FHEI_Trap  | DIRECT_EXTRACTION | IngressPMF2 | 33   | 33      |
-------------------------------------------------------------------------------
| 17 | ITMH_PPH-FHEI_Vlan  | DIRECT_EXTRACTION | IngressPMF2 | 63   | 63      |
-------------------------------------------------------------------------------
| 38 | Host Termination    | TCAM              | IngressPMF2 | 160  | 64      |
-------------------------------------------------------------------------------
| 18 | ITMH_PPH_IPMF3      | DIRECT_EXTRACTION | IngressPMF3 | 32   | 32      |
-------------------------------------------------------------------------------
| 4  | Egress Rules        | TCAM              | Egress      | 160  | 64      |
===============================================================================
>/usr/bin/bcmcmd field grp info group=3
============================================================================
|                          FIELD GROUP Full Info                           |
============================================================================
| ID | Name             | Type              | Stage       | Key  | Payload |
|    |                  |                   |             | Size | Size    |
============================================================================
| 3  | ITMH_PPH-OAM_TSH | DIRECT_EXTRACTION | IngressPMF2 | 140  | 140     |
============================================================================
============================
|      Contexts for FG 3   |
============================
| ID | Name                |
============================
| 49 | ITMH_PPH_FHEI_IPMF1 |
----------------------------
| 61 | ITMH_PPH_FHEI_Vlan  |
----------------------------
| 62 | ITMH_PPH_IPMF1      |
============================
=====================================================================================================================
|                                                 Key & Payload Info                                                |
=====================================================================================================================
| Qualifier                 | Qual | Qual |   | Action               | Base Action                | Action | Action |
|                           | Size | Lsb  |   |                      |                            | Size   | Lsb    |
=====================================================================================================================
| tc_sn_dst_dp_mr_pph_q_pph | 34   | 0    |   | TC                   | N/A                        | 3      | 0      |
|                           |      |      |   | snoop_data_a_pph     | SNOOP_DATA (UDA ID: 11)    | 5      | 3      |
|                           |      |      |   | destination_a_pph    | DST_DATA (UDA ID: 12)      | 21     | 8      |
|                           |      |      |   | DP                   | N/A                        | 2      | 29     |
|                           |      |      |   | mirror_command_a_pph | VOID (UDA ID: 13)          | 1      | 31     |
|                           |      |      |   | PPH_TYPE             | N/A                        | 2      | 32     |
---------------------------------------------------------------------------------------------------------------------
| ext_exist_q_pph           | 1    | 34   |   | ext_exist_a_pph      | VOID (UDA ID: 14)          | 1      | 34     |
---------------------------------------------------------------------------------------------------------------------
| out_lif_dst_q_pph         | 22   | 35   |   | out_lif_a_pph        | VOID (UDA ID: 15)          | 22     | 35     |
---------------------------------------------------------------------------------------------------------------------
| ase_inj_q_pph             | 1    | 57   |   | udh3_1bit_ase_a_pph  | USER_HEADER_3 (UDA ID: 16) | 1      | 57     |
---------------------------------------------------------------------------------------------------------------------
| time_stamp_q_pph          | 32   | 58   |   | INGRESS_TIME_STAMP   | N/A                        | 32     | 58     |
---------------------------------------------------------------------------------------------------------------------
| fwd_trap_code_zero_q_pph  | 9    | 90   |   | fwd_str_a_pph        | FWD_TRAP (UDA ID: 17)      | 13     | 90     |
| fwd_str_res_bit_q_1       | 3    | 99   |   |                      |                            |        |        |
| fwd_str_q_pph             | 1    | 102  |   |                      |                            |        |        |
---------------------------------------------------------------------------------------------------------------------
| oam_stamp_offset_q_pph    | 8    | 103  |   | OAM_DATA             | N/A                        | 21     | 103    |
| oam_offset_q_pph          | 8    | 111  |   |                      |                            |        |        |
| oam_sub_type_q_pph        | 4    | 119  |   |                      |                            |        |        |
| oam_mep_q_pph             | 1    | 123  |   |                      |                            |        |        |
---------------------------------------------------------------------------------------------------------------------
| LAYER_QUALIFIER           | 16   | 124  |   | lr_qual_a_pph        | VOID (UDA ID: 18)          | 16     | 124    |
=====================================================================================================================
>/usr/bin/bcmcmd field grp info group=5
===================================================
|              FIELD GROUP Full Info              |
===================================================
| ID | Name | Type | Stage       | Key  | Payload |
|    |      |      |             | Size | Size    |
===================================================
| 5  | Misc | TCAM | IngressPMF1 | 160  | 64      |
===================================================
==========================
|     Contexts for FG 5  |
==========================
| ID | Name              |
==========================
| 4  | DFLT              |
--------------------------
| 5  | IPv6              |
--------------------------
| 6  | IPv4              |
--------------------------
| 11 | IPv6PtpRxTrapCode |
--------------------------
| 12 | IPv4PtpRxTrapCode |
==========================
===========================================================================================
|                                    Key & Payload Info                                   |
===========================================================================================
| Qualifier                | Qual | Qual |   | Action          | Base   | Action | Action |
|                          | Size | Lsb  |   |                 | Action | Size   | Lsb    |
===========================================================================================
| IN_PORT                  | 10   | 0    |   | STATISTICS_ID_1 | N/A    | 20     | 11     |
-------------------------------------------------------------------------------------------
| SRC_SYS_PORT             | 16   | 10   |   | DST_DATA        | N/A    | 32     | 32     |
-------------------------------------------------------------------------------------------
| FWD_ACTION_DESTINATION   | 21   | 26   |   |                 |        |        |        |
-------------------------------------------------------------------------------------------
| L4_DST_PORT              | 16   | 47   |   |                 |        |        |        |
-------------------------------------------------------------------------------------------
| IPV4_PROTOCOL            | 8    | 63   |   |                 |        |        |        |
-------------------------------------------------------------------------------------------
| GLOB_IN_LIF_0            | 22   | 71   |   |                 |        |        |        |
-------------------------------------------------------------------------------------------
| FWD_ACTION_CPU_TRAP_CODE | 9    | 93   |   |                 |        |        |        |
-------------------------------------------------------------------------------------------
| PMF_OAM_ID               | 19   | 102  |   |                 |        |        |        |
===========================================================================================
===========================================
|                FG 5 Bank Info           |
===========================================
| Access  | Bank IDs   | Prefix  | Prefix |
| Profile |            |         | Size   |
===========================================
| 5       | core_0: 1  | 0b00000 | 5      |
|         | core_1:    |         |        |
|         | N/A        |         |        |
===========================================
=========================================
|                FG Entry Info          |
=========================================
| Banks       | ID 1       | Total      |
=========================================
| Nof entries | core_0: 3  | core_0: 3  |
|             | core_1:    | core_1:    |
|             | N/A        | N/A        |
=========================================
>/usr/bin/bcmcmd field grp info group=6
==============================================================================
|                           FIELD GROUP Full Info                            |
==============================================================================
| ID | Name                | Type             | Stage       | Key  | Payload |
|    |                     |                  |             | Size | Size    |
==============================================================================
| 6  | InLifMeter (DIRECT) | DIRECT_TABLE_MDB | IngressPMF2 | 16   | 46      |
==============================================================================
==========================
|     Contexts for FG 6  |
==========================
| ID | Name              |
==========================
| 4  | DFLT              |
--------------------------
| 5  | IPv6              |
--------------------------
| 6  | IPv4              |
--------------------------
| 11 | IPv6PtpRxTrapCode |
--------------------------
| 12 | IPv4PtpRxTrapCode |
==========================
=======================================================================================================
|                                          Key & Payload Info                                         |
=======================================================================================================
| Qualifier     | Qual | Qual |   | Action           | Base Action                  | Action | Action |
|               | Size | Lsb  |   |                  |                              | Size   | Lsb    |
=======================================================================================================
| Meter/Stat ID | 16   | 0    |   | STATISTICS_ATR_2 | N/A                          | 5      | 75     |
-------------------------------------------------------------------------------------------------------
|               |      |      |   | Stat2FpMeter     | STATISTICS_ID_2 (UDA ID: 55) | 16     | 81     |
-------------------------------------------------------------------------------------------------------
|               |      |      |   | STATISTICS_ATR_6 | N/A                          | 5      | 98     |
-------------------------------------------------------------------------------------------------------
|               |      |      |   | Stat6FpStat      | STATISTICS_ID_6 (UDA ID: 56) | 16     | 104    |
=======================================================================================================
>/usr/bin/bcmcmd field grp info group=10
=======================================================
|                FIELD GROUP Full Info                |
=======================================================
| ID | Name     | Type | Stage       | Key  | Payload |
|    |          |      |             | Size | Size    |
=======================================================
| 10 | Acl IPv6 | TCAM | IngressPMF2 | 320  | 128     |
=======================================================
==========================
|    Contexts for FG 10  |
==========================
| ID | Name              |
==========================
| 5  | IPv6              |
--------------------------
| 11 | IPv6PtpRxTrapCode |
==========================
===================================================================================
|                                Key & Payload Info                               |
===================================================================================
| Qualifier        | Qual | Qual |   | Action          | Base   | Action | Action |
|                  | Size | Lsb  |   |                 | Action | Size   | Lsb    |
===================================================================================
| IPV6_SIP_HIGH    | 64   | 0    |   | STATISTICS_ID_0 | N/A    | 20     | 48     |
-----------------------------------------------------------------------------------
| IPV6_SIP_LOW     | 64   | 64   |   | DST_DATA        | N/A    | 32     | 69     |
-----------------------------------------------------------------------------------
| IPV6_DIP_HIGH    | 64   | 128  |   | CONGESTION_INFO | N/A    | 3      | 102    |
-----------------------------------------------------------------------------------
| IPV6_DIP_LOW     | 64   | 192  |   | GLOB_OUT_LIF_0  | N/A    | 22     | 106    |
-----------------------------------------------------------------------------------
| IPV6_NEXT_HEADER | 8    | 256  |   |                 |        |        |        |
-----------------------------------------------------------------------------------
| L4_SRC_PORT      | 16   | 264  |   |                 |        |        |        |
-----------------------------------------------------------------------------------
| L4_DST_PORT      | 16   | 280  |   |                 |        |        |        |
-----------------------------------------------------------------------------------
| TCP_CTL          | 6    | 296  |   |                 |        |        |        |
-----------------------------------------------------------------------------------
| L3 ACL profile   | 6    | 302  |   |                 |        |        |        |
-----------------------------------------------------------------------------------
| ICMP type        | 8    | 308  |   |                 |        |        |        |
===================================================================================
=============================================
|                FG 10 Bank Info            |
=============================================
| Access  | Bank IDs      | Prefix | Prefix |
| Profile |               |        | Size   |
=============================================
| 23      | core_0: 2, 3  | 0b0010 | 4      |
|         | core_1: N/A   |        |        |
=============================================
======================================================
|                       FG Entry Info                |
======================================================
| Banks       | ID 2       | ID 3       | Total      |
======================================================
| Nof entries | core_0: 0  | core_0: 0  | core_0: 0  |
|             | core_1:    | core_1:    | core_1:    |
|             | N/A        | N/A        | N/A        |
======================================================
>/usr/bin/bcmcmd field grp info group=11
=======================================================
|                FIELD GROUP Full Info                |
=======================================================
| ID | Name     | Type | Stage       | Key  | Payload |
|    |          |      |             | Size | Size    |
=======================================================
| 11 | Acl IPv4 | TCAM | IngressPMF2 | 320  | 128     |
=======================================================
==========================
|    Contexts for FG 11  |
==========================
| ID | Name              |
==========================
| 6  | IPv4              |
--------------------------
| 12 | IPv4PtpRxTrapCode |
==========================
=====================================================================================
|                                 Key & Payload Info                                |
=====================================================================================
| Qualifier          | Qual | Qual |   | Action          | Base   | Action | Action |
|                    | Size | Lsb  |   |                 | Action | Size   | Lsb    |
=====================================================================================
| IPV4_SIP           | 32   | 0    |   | STATISTICS_ID_0 | N/A    | 20     | 48     |
-------------------------------------------------------------------------------------
| IPV4_DIP           | 32   | 32   |   | DST_DATA        | N/A    | 32     | 69     |
-------------------------------------------------------------------------------------
| IPV4_PROTOCOL      | 8    | 64   |   | CONGESTION_INFO | N/A    | 3      | 102    |
-------------------------------------------------------------------------------------
| L4_SRC_PORT        | 16   | 72   |   | GLOB_OUT_LIF_0  | N/A    | 22     | 106    |
-------------------------------------------------------------------------------------
| L4_DST_PORT        | 16   | 88   |   |                 |        |        |        |
-------------------------------------------------------------------------------------
| TCP_CTL            | 6    | 104  |   |                 |        |        |        |
-------------------------------------------------------------------------------------
| IPV4_TOS           | 8    | 110  |   |                 |        |        |        |
-------------------------------------------------------------------------------------
| IPV4_IS_FRAGMENTED | 1    | 118  |   |                 |        |        |        |
-------------------------------------------------------------------------------------
| L3 ACL profile     | 6    | 119  |   |                 |        |        |        |
-------------------------------------------------------------------------------------
| ICMP type          | 8    | 125  |   |                 |        |        |        |
=====================================================================================
==============================================
|                 FG 11 Bank Info            |
==============================================
| Access  | Bank IDs      | Prefix  | Prefix |
| Profile |               |         | Size   |
==============================================
| 25      | core_0: 2, 3  | 0b00110 | 5      |
|         | core_1: N/A   |         |        |
==============================================
======================================================
|                       FG Entry Info                |
======================================================
| Banks       | ID 2       | ID 3       | Total      |
======================================================
| Nof entries | core_0: 0  | core_0: 0  | core_0: 0  |
|             | core_1:    | core_1:    | core_1:    |
|             | N/A        | N/A        | N/A        |
======================================================
>/usr/bin/bcmcmd field grp info group=0
================================================================
|                    FIELD GROUP Full Info                     |
================================================================
| ID | Name | Type              | Stage       | Key  | Payload |
|    |      |                   |             | Size | Size    |
================================================================
| 0  | ITMH | DIRECT_EXTRACTION | IngressPMF2 | 70   | 70      |
================================================================
============================
|      Contexts for FG 0   |
============================
| ID | Name                |
============================
| 51 | ITMH_1588_TSH_IPMF1 |
----------------------------
| 63 | ITMH_IPMF1          |
============================
=================================================================================================================================
|                                                       Key & Payload Info                                                      |
=================================================================================================================================
| Qualifier           | Qual | Qual |   | Action                                  | Base Action               | Action | Action |
|                     | Size | Lsb  |   |                                         |                           | Size   | Lsb    |
=================================================================================================================================
| pph_type_qual       | 2    | 0    |   | PPH_TYPE                                | N/A                       | 2      | 0      |
---------------------------------------------------------------------------------------------------------------------------------
| dp_dst_snp_tc_qual  | 31   | 2    |   | TC                                      | N/A                       | 3      | 2      |
|                     |      |      |   | snoop_data_act                          | SNOOP_DATA (UDA ID: 0)    | 5      | 5      |
|                     |      |      |   | destination_act                         | DST_DATA (UDA ID: 4)      | 21     | 10     |
|                     |      |      |   | DP                                      | N/A                       | 2      | 31     |
---------------------------------------------------------------------------------------------------------------------------------
| ext_exist_qual      | 1    | 33   |   | ext_exist_act                           | VOID (UDA ID: 5)          | 1      | 33     |
---------------------------------------------------------------------------------------------------------------------------------
| out_lif_dst_qual    | 22   | 34   |   | out_lif_act                             | VOID (UDA ID: 6)          | 22     | 34     |
---------------------------------------------------------------------------------------------------------------------------------
| ase_inj_qual        | 1    | 56   |   | udh3_1bit_ase_act                       | USER_HEADER_4 (UDA ID: 7) | 1      | 56     |
---------------------------------------------------------------------------------------------------------------------------------
| mirror_qual         | 1    | 57   |   | mirror_command_act                      | VOID (UDA ID: 8)          | 1      | 57     |
---------------------------------------------------------------------------------------------------------------------------------
| FWD_ACTION_STRENGTH | 4    | 58   |   | fwd_act_str_act                         | VOID (UDA ID: 9)          | 4      | 58     |
---------------------------------------------------------------------------------------------------------------------------------
| itmh_oam_valid_bit  | 1    | 62   |   | SYSTEM_HEADER_PROFILE_INDEX + condition | N/A                       | 5      | 63     |
| itmh_fbr_hdr_set    | 4    | 63   |   |                                         |                           |        |        |
---------------------------------------------------------------------------------------------------------------------------------
| itmh_fwd_l_idx      | 3    | 67   |   | FWD_LAYER_INDEX                         | N/A                       | 3      | 67     |
=================================================================================================================================
>/usr/bin/bcmcmd field grp info group=7
==========================================================
|                 FIELD GROUP Full Info                  |
==========================================================
| ID | Name        | Type | Stage       | Key  | Payload |
|    |             |      |             | Size | Size    |
==========================================================
| 7  | System L2CP | TCAM | IngressPMF1 | 160  | 64      |
==========================================================
==========================
|     Contexts for FG 7  |
==========================
| ID | Name              |
==========================
| 4  | DFLT              |
--------------------------
| 5  | IPv6              |
--------------------------
| 6  | IPv4              |
--------------------------
| 11 | IPv6PtpRxTrapCode |
--------------------------
| 12 | IPv4PtpRxTrapCode |
--------------------------
| 20 | InjL2             |
==========================
==================================================================================================
|                                        Key & Payload Info                                      |
==================================================================================================
| Qualifier              | Qual | Qual |   | Action     | Base Action          | Action | Action |
|                        | Size | Lsb  |   |            |                      | Size   | Lsb    |
==================================================================================================
| MAC_DST                | 48   | 0    |   | DST_DATA   | N/A                  | 32     | 3      |
--------------------------------------------------------------------------------------------------
| INCOMING_TAG_STRUCTURE | 5    | 48   |   | SNOOP_DATA | N/A                  | 20     | 36     |
--------------------------------------------------------------------------------------------------
| In PP port (9bits)     | 9    | 53   |   | TC         | N/A                  | 3      | 57     |
--------------------------------------------------------------------------------------------------
| L2CP part1             | 32   | 62   |   | NwkQos     | NWK_QOS (UDA ID: 92) | 3      | 61     |
--------------------------------------------------------------------------------------------------
| L2CP part2             | 32   | 94   |   |            |                      |        |        |
--------------------------------------------------------------------------------------------------
| Ethertype (improved)   | 16   | 126  |   |            |                      |        |        |
--------------------------------------------------------------------------------------------------
| In-LIF (18bits)        | 18   | 142  |   |            |                      |        |        |
==================================================================================================
==========================================
|                FG 7 Bank Info          |
==========================================
| Access  | Bank IDs   | Prefix | Prefix |
| Profile |            |        | Size   |
==========================================
| 7       | core_0: 5  | 0b0    | 0      |
|         | core_1:    |        |        |
|         | N/A        |        |        |
==========================================
=============================================
|                  FG Entry Info            |
=============================================
| Banks       | ID 5         | Total        |
=============================================
| Nof entries | core_0: 144  | core_0: 144  |
|             | core_1: N/A  | core_1: N/A  |
=============================================
>/usr/bin/bcmcmd field grp info group=8
==========================================================
|                 FIELD GROUP Full Info                  |
==========================================================
| ID | Name        | Type | Stage       | Key  | Payload |
|    |             |      |             | Size | Size    |
==========================================================
| 8  | System L3CP | TCAM | IngressPMF1 | 160  | 64      |
==========================================================
========================
| Contexts for FG 8    |
========================
| ID | Name            |
========================
| 4  | DFLT            |
------------------------
| 5  | IPv6            |
------------------------
| 6  | IPv4            |
========================
==================================================================================
|                                Key & Payload Info                              |
==================================================================================
| Qualifier            | Qual | Qual |   | Action     | Base   | Action | Action |
|                      | Size | Lsb  |   |            | Action | Size   | Lsb    |
==================================================================================
| PMF_ETH_RIF_PROFILE  | 2    | 0    |   | DST_DATA   | N/A    | 32     | 11     |
----------------------------------------------------------------------------------
| MAC_DST              | 48   | 2    |   | SNOOP_DATA | N/A    | 20     | 44     |
----------------------------------------------------------------------------------
| IPV4_DIP             | 32   | 50   |   |            |        |        |        |
----------------------------------------------------------------------------------
| IPV4_PROTOCOL        | 8    | 82   |   |            |        |        |        |
----------------------------------------------------------------------------------
| L4_DST_PORT          | 16   | 90   |   |            |        |        |        |
----------------------------------------------------------------------------------
| L4_SRC_PORT          | 16   | 106  |   |            |        |        |        |
----------------------------------------------------------------------------------
| LAYER_TYPES          | 5    | 122  |   |            |        |        |        |
----------------------------------------------------------------------------------
| Ethertype (improved) | 16   | 127  |   |            |        |        |        |
==================================================================================
===========================================
|                FG 8 Bank Info           |
===========================================
| Access  | Bank IDs   | Prefix  | Prefix |
| Profile |            |         | Size   |
===========================================
| 11      | core_0: 4  | 0b00001 | 5      |
|         | core_1:    |         |        |
|         | N/A        |         |        |
===========================================
===========================================
|                 FG Entry Info           |
===========================================
| Banks       | ID 4        | Total       |
===========================================
| Nof entries | core_0: 13  | core_0: 13  |
|             | core_1: N/A | core_1: N/A |
===========================================
>/usr/bin/bcmcmd field grp info group=9
===================================================
|              FIELD GROUP Full Info              |
===================================================
| ID | Name | Type | Stage       | Key  | Payload |
|    |      |      |             | Size | Size    |
===================================================
| 9  | Acl  | TCAM | IngressPMF2 | 320  | 128     |
===================================================
========================
| Contexts for FG 9    |
========================
| ID | Name            |
========================
| 4  | DFLT            |
========================
=========================================================================================
|                                   Key & Payload Info                                  |
=========================================================================================
| Qualifier              | Qual | Qual |   | Action          | Base   | Action | Action |
|                        | Size | Lsb  |   |                 | Action | Size   | Lsb    |
=========================================================================================
| GLOB_IN_LIF_0          | 22   | 0    |   | STATISTICS_ID_0 | N/A    | 20     | 48     |
-----------------------------------------------------------------------------------------
| MAC_SRC                | 48   | 22   |   | DST_DATA        | N/A    | 32     | 69     |
-----------------------------------------------------------------------------------------
| MAC_DST                | 48   | 70   |   | CONGESTION_INFO | N/A    | 3      | 102    |
-----------------------------------------------------------------------------------------
| VLAN_TPID              | 16   | 118  |   | GLOB_OUT_LIF_0  | N/A    | 22     | 106    |
-----------------------------------------------------------------------------------------
| VLAN_ID                | 12   | 134  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| VLAN_PRI               | 3    | 146  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| INCOMING_TAG_STRUCTURE | 5    | 149  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| IPV4_SIP               | 32   | 154  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| IPV4_DIP               | 32   | 186  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| IPV4_PROTOCOL          | 8    | 218  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| L4_SRC_PORT            | 16   | 226  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| L4_DST_PORT            | 16   | 242  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| IPV4_TOS               | 8    | 258  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| FWD_ACTION_STRENGTH    | 4    | 266  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| Ethertype (improved)   | 16   | 270  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| Inner TPID             | 16   | 286  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| Inner VID              | 12   | 302  |   |                 |        |        |        |
-----------------------------------------------------------------------------------------
| Inner PCP              | 3    | 314  |   |                 |        |        |        |
=========================================================================================
=============================================
|                 FG 9 Bank Info            |
=============================================
| Access  | Bank IDs      | Prefix | Prefix |
| Profile |               |        | Size   |
=============================================
| 21      | core_0: 2, 3  | 0b000  | 3      |
|         | core_1: N/A   |        |        |
=============================================
======================================================
|                       FG Entry Info                |
======================================================
| Banks       | ID 2       | ID 3       | Total      |
======================================================
| Nof entries | core_0: 2  | core_0: 0  | core_0: 2  |
|             | core_1:    | core_1:    | core_1:    |
|             | N/A        | N/A        | N/A        |
======================================================
>/usr/bin/bcmcmd field grp info group=2
================================================================
|                    FIELD GROUP Full Info                     |
================================================================
| ID | Name | Type              | Stage       | Key  | Payload |
|    |      |                   |             | Size | Size    |
================================================================
| 2  | ITMH | DIRECT_EXTRACTION | IngressPMF2 | 4    | 4       |
================================================================
========================
| Contexts for FG 2    |
========================
| ID | Name            |
========================
| 63 | ITMH_IPMF1      |
========================
====================================================================================================
|                                         Key & Payload Info                                       |
====================================================================================================
| Qualifier             | Qual | Qual |   | Action                      | Base   | Action | Action |
|                       | Size | Lsb  |   |                             | Action | Size   | Lsb    |
====================================================================================================
| itmh_fbr_hdr_set_qual | 4    | 0    |   | SYSTEM_HEADER_PROFILE_INDEX | N/A    | 4      | 0      |
====================================================================================================
>/usr/bin/bcmcmd field entry list grp=3

Field Group Type DIRECT_EXTRACTION is not supported by Entry Info diagnostic!! 

>/usr/bin/bcmcmd field entry list grp=5
==========================================
| FG ID 5 (TCAM) | CORE ID 0 | BANK ID 1 |
==========================================
| Number of Free Entries: 2037           |
|       Used Entry IDs:                  |
==========================================
| 0x0002EC, 0x0002EB, 0x000000           |
==========================================
>/usr/bin/bcmcmd field entry list grp=6

Please use DBAL diagnostics instead to query on entries of Field groups of type DIRECT_TABLE_MDB, DBAL table name: InLifMeter (DIRECT)

>/usr/bin/bcmcmd field entry list grp=10
==============================================
| FG ID 10 (TCAM) | CORE ID 0 | BANK ID 2, 3 |
==============================================
| Number                                     |
| of Free                                    |
| Entries:                                   |
| 2044                                       |
|   Used                                     |
| Entry                                      |
| IDs:                                       |
==============================================
|                                            |
==============================================
>/usr/bin/bcmcmd field entry list grp=11
==============================================
| FG ID 11 (TCAM) | CORE ID 0 | BANK ID 2, 3 |
==============================================
| Number                                     |
| of Free                                    |
| Entries:                                   |
| 2044                                       |
|   Used                                     |
| Entry                                      |
| IDs:                                       |
==============================================
|                                            |
==============================================
>/usr/bin/bcmcmd field entry list grp=7
====================================================================
|              FG ID 7 (TCAM) | CORE ID 0 | BANK ID 5              |
====================================================================
| Number of Free Entries: 1760       Used Entry IDs:               |
====================================================================
| 0x002BEA, 0x002C3E, 0x002C92, 0x002CE6, 0x002D3A, 0x002D8E,      |
| 0x002DE2, 0x002E36, 0x002E8A, 0x002EDE, 0x002F32, 0x002F86,      |
| 0x002FDA, 0x00302E, 0x003082, 0x0030D6, 0x00312A, 0x00317E,      |
| 0x0031D2, 0x003226, 0x00327A, 0x0032CE, 0x003322, 0x003376,      |
| 0x0033CA, 0x00341E, 0x003472, 0x0034C6, 0x00351A, 0x00356E,      |
| 0x0035C2, 0x003616, 0x00366A, 0x0036BE, 0x003712, 0x003766,      |
| 0x002008, 0x00205C, 0x0020B0, 0x002104, 0x002158, 0x0021AC,      |
| 0x002200, 0x002254, 0x0022A8, 0x0022FC, 0x002350, 0x0023A4,      |
| 0x0023F8, 0x00244C, 0x0024A0, 0x0024F4, 0x002548, 0x00259C,      |
| 0x0025F0, 0x002644, 0x002698, 0x0026EC, 0x002740, 0x002794,      |
| 0x0027E8, 0x00283C, 0x002890, 0x0028E4, 0x002938, 0x00298C,      |
| 0x0029E0, 0x002A34, 0x002A88, 0x002ADC, 0x002B30, 0x002B84,      |
| 0x002003, 0x002004, 0x002057, 0x002058, 0x0020AB, 0x0020AC,      |
| 0x0020FF, 0x002100, 0x002153, 0x002154, 0x0021A7, 0x0021A8,      |
| 0x0021FB, 0x0021FC, 0x00224F, 0x002250, 0x0022A3, 0x0022A4,      |
| 0x0022F7, 0x0022F8, 0x00234B, 0x00234C, 0x00239F, 0x0023A0,      |
| 0x0023F3, 0x0023F4, 0x002447, 0x002448, 0x00249B, 0x00249C,      |
| 0x0024EF, 0x0024F0, 0x002543, 0x002544, 0x002597, 0x002598,      |
| 0x0025EB, 0x0025EC, 0x00263F, 0x002640, 0x002693, 0x002694,      |
| 0x0026E7, 0x0026E8, 0x00273B, 0x00273C, 0x00278F, 0x002790,      |
| 0x0027E3, 0x0027E4, 0x002837, 0x002838, 0x00288B, 0x00288C,      |
| 0x0028DF, 0x0028E0, 0x002933, 0x002934, 0x002987, 0x002988,      |
| 0x0029DB, 0x0029DC, 0x002A2F, 0x002A30, 0x002A83, 0x002A84,      |
| 0x002AD7, 0x002AD8, 0x002B2B, 0x002B2C, 0x002B7F, 0x002B80       |
====================================================================
>/usr/bin/bcmcmd field entry list grp=8
====================================================================
|              FG ID 8 (TCAM) | CORE ID 0 | BANK ID 4              |
====================================================================
| Number of Free Entries: 2018       Used Entry IDs:               |
====================================================================
| 0x0000E8, 0x0000E9, 0x0000EA, 0x0000EB, 0x0000EC, 0x0000ED,      |
| 0x0000EE, 0x0000EF, 0x0000F0, 0x0000F6, 0x0000F7, 0x0000F8,      |
| 0x0000F9                                                         |
====================================================================
>/usr/bin/bcmcmd field entry list grp=9
=============================================
| FG ID 9 (TCAM) | CORE ID 0 | BANK ID 2, 3 |
=============================================
| Number of Free                            |
| Entries: 2044                             |
|  Used Entry IDs:                          |
=============================================
| 0x000001, 0x000002                        |
=============================================
>/usr/bin/bcmcmd field entry list grp=2

Field Group Type DIRECT_EXTRACTION is not supported by Entry Info diagnostic!! 

>/usr/bin/bcmcmd field last info core=all

******************************
*      CORE ID 0            *
******************************


******************************
*           IPMF1            *
******************************
============================================
|          Context Selection Info          |
============================================
| Presel Id             | N/A              |
============================================
| Context Id/Name       | 4 /"DFLT"        |
--------------------------------------------
| System Header Profile | FTMH_TSH_PPH_UDH |
============================================
================================================================================================
|                                         Field Group Info                                     |
================================================================================================
| FG Id/Name      | FG   | Key | Raw Data                                   | Hit | Entry Id   |
|                 | Type | Id  |                                            |     |            |
================================================================================================
| 5/"Misc"        | TCAM | A   | 0x000000000128248120222f837a5fb0000c008020 | Yes | N/A        |
------------------------------------------------------------------------------------------------
| 7/"System L2CP" | TCAM | B   | 0x1117420011400176000082000403dc2c6e7e85e6 | No  | No Entries |
------------------------------------------------------------------------------------------------
| 8/"System L3CP" | TCAM | C   | 0x000004000406efd2fc18282de532e1a7d159283c | No  | No Entries |
------------------------------------------------------------------------------------------------
| 12/"QosFlow"    | TCAM | D   | 0x0000000000000000000000000000000445f00083 | No  | No Entries |
================================================================================================
==========================================================================================================================================
|                                             Key Info & Performed Actions for FG ID 5 (HIT)                                             |
==========================================================================================================================================
| Qual Type                | Key      |   | FES/  | Action Type     | Base   | Valid   | Payload    | Signal Value                       |
|                          | Value    |   | FEM   |                 | Action |         | Value      |                                    |
|                          |          |   |       |                 | (ID)   |         |            |                                    |
==========================================================================================================================================
| IN_PORT                  | 0x0020   |   | FES 0 | STATISTICS_ID_1 | N/A    | Invalid | 0x000000   | Stats_Objects_Resolved.2: 0x000000 |
------------------------------------------------------------------------------------------------------------------------------------------
| SRC_SYS_PORT             | 0x0020   |   | FES 1 | DST_DATA        | N/A    | Invalid | 0x00000000 | Fwd_Action_Dst.type: 0x18          |
|                          |          |   |       |                 |        |         |            | Fwd_Action_Dst.value: 0x0003       |
------------------------------------------------------------------------------------------------------------------------------------------
| FWD_ACTION_DESTINATION   | 0x0c0003 |   |       |                 |        |         |            |                                    |
------------------------------------------------------------------------------------------------------------------------------------------
| L4_DST_PORT              | 0xf4bf   |   |       |                 |        |         |            |                                    |
------------------------------------------------------------------------------------------------------------------------------------------
| IPV4_PROTOCOL            | 0x06     |   |       |                 |        |         |            |                                    |
------------------------------------------------------------------------------------------------------------------------------------------
| GLOB_IN_LIF_0            | 0x00445f |   |       |                 |        |         |            |                                    |
------------------------------------------------------------------------------------------------------------------------------------------
| FWD_ACTION_CPU_TRAP_CODE | 0x0009   |   |       |                 |        |         |            |                                    |
------------------------------------------------------------------------------------------------------------------------------------------
| PMF_OAM_ID               | 0x04a092 |   |       |                 |        |         |            |                                    |
==========================================================================================================================================
=========================================================================================================
|                           Key Info & Performed Actions for FG ID 7 (NO HIT)                           |
=========================================================================================================
| Qual Type              | Key Value      |   | FES/  | Action     | Base    | Valid | Payload | Signal |
|                        |                |   | FEM   | Type       | Action  |       | Value   | Value  |
|                        |                |   |       |            | (ID)    |       |         |        |
=========================================================================================================
| MAC_DST                | 0xdc2c6e7e85e6 |   | FES 6 | DST_DATA   | N/A     | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
| INCOMING_TAG_STRUCTURE | 0x03           |   | FES 7 | SNOOP_DATA | N/A     | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
| In PP port (9bits)     | 0x0020         |   | FES 8 | TC         | N/A     | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
| L2CP part1             | 0x00020800     |   | FES 9 | NwkQos     | NWK_QOS | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
| L2CP part2             | 0x450005d8     |   |       |            |         |       |         |        |
---------------------------------------------------------------------------------------------------------
| Ethertype (improved)   | 0x0800         |   |       |            |         |       |         |        |
---------------------------------------------------------------------------------------------------------
| In-LIF (18bits)        | 0x00445d       |   |       |            |         |       |         |        |
=========================================================================================================
=======================================================================================================
|                          Key Info & Performed Actions for FG ID 8 (NO HIT)                          |
=======================================================================================================
| Qual Type            | Key Value      |   | FES/   | Action     | Base   | Valid | Payload | Signal |
|                      |                |   | FEM    | Type       | Action |       | Value   | Value  |
|                      |                |   |        |            | (ID)   |       |         |        |
=======================================================================================================
| PMF_ETH_RIF_PROFILE  | 0x00           |   | FES 16 | DST_DATA   | N/A    | N/A   | N/A     | N/A    |
-------------------------------------------------------------------------------------------------------
| MAC_DST              | 0xb869f4564a0f |   | FES 21 | SNOOP_DATA | N/A    | N/A   | N/A     | N/A    |
-------------------------------------------------------------------------------------------------------
| IPV4_DIP             | 0x0a0b794c     |   |        |            |        |       |         |        |
-------------------------------------------------------------------------------------------------------
| IPV4_PROTOCOL        | 0x06           |   |        |            |        |       |         |        |
-------------------------------------------------------------------------------------------------------
| L4_DST_PORT          | 0xf4bf         |   |        |            |        |       |         |        |
-------------------------------------------------------------------------------------------------------
| L4_SRC_PORT          | 0x01bb         |   |        |            |        |       |         |        |
-------------------------------------------------------------------------------------------------------
| LAYER_TYPES          | 0x01           |   |        |            |        |       |         |        |
-------------------------------------------------------------------------------------------------------
| Ethertype (improved) | 0x0800         |   |        |            |        |       |         |        |
=======================================================================================================
=========================================================================================================
|                          Key Info & Performed Actions for FG ID 12 (NO HIT)                           |
=========================================================================================================
| Qual Type              | Key      |   | FES/   | Action Type      | Base   | Valid | Payload | Signal |
|                        | Value    |   | FEM    |                  | Action |       | Value   | Value  |
|                        |          |   |        |                  | (ID)   |       |         |        |
=========================================================================================================
| INCOMING_TAG_STRUCTURE | 0x03     |   | FES 22 | STATISTICS_ID_1  | N/A    | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
| VLAN_ID                | 0x0004   |   | FES 23 | STATISTICS_ID_6  | N/A    | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
| TC                     | 0x00     |   | FES 24 | STATISTICS_ATR_2 | N/A    | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
| In AC LIF              | 0x00445f |   | FES 25 | STATISTICS_ATR_1 | N/A    | N/A   | N/A     | N/A    |
---------------------------------------------------------------------------------------------------------
|                        |          |   | FES 26 | STATISTICS_ATR_6 | N/A    | N/A   | N/A     | N/A    |
=========================================================================================================

******************************
*           IPMF2            *
******************************
=================================
|    Context Selection Info     |
=================================
| Presel Id       | N/A         |
=================================
| Context Id/Name | 4 /"DFLT"   |
---------------------------------
| Bytes to Remove | 0 + 0 bytes |
=================================
====================================================================================================================
|                                                   Field Group Info                                               |
====================================================================================================================
| FG Id/Name              | FG Type          | Key | Raw Data                                   | Hit | Entry Id   |
|                         |                  | Id  |                                            |     |            |
====================================================================================================================
| 6/"InLifMeter (DIRECT)" | DIRECT_TABLE_MDB | H   | 0x0007c00000000000000000000000000000000000 | Yes |            |
--------------------------------------------------------------------------------------------------------------------
| 9/"Acl"                 | TCAM             | F   | 0x0c6000a0401d134a2b093ef7899e529b4640445d | No  | No Entries |
|                         |                  | G   | 0x09400200020000000143a7e0185c75d410282de3 |     |            |
====================================================================================================================
Mismatch between STATISTICS_ATR_2 action values, result 0x0, entry payload 0x1
 Mismatch between Stat2FpMeter action values, result 0x0, entry payload 0x1
 Mismatch between STATISTICS_ATR_6 action values, result 0x0, entry payload 0x1
 Mismatch between Stat6FpStat action values, result 0x0, entry payload 0xF
 =================================================================================================================================================================
|                                                        Key Info & Performed Actions for FG ID 6 (HIT)                                                     |
=================================================================================================================================================================
| Qual Type     | Packet     | Entry Key  |   | FES/  | Action Type      | Base Action (ID)     | Valid/         | Entry Payload Value                 | Signal |
|               | Value      | Value      |   | FEM   |                  |                      | Condition      |                                     | Value  |
|               |            |            |   | Id    |                  |                      | bit            |                                     |        |
=================================================================================================================================================================
| Meter/Stat ID | 0x0000007C | 0x0000007C |   | FES 2 | STATISTICS_ATR_2 | N/A                  | 0 (valid if 1) | Stats_Objects_Atr.3.Is_Meter: 0x00  |        |
|               |            |            |   |       |                  |                      |                | Stats_Objects_Atr.3.Is_LM: 0x00     |        |
|               |            |            |   |       |                  |                      |                | Stats_Objects_Atr.3.Type: 0x00      |        |
|               |            |            |   |       |                  |                      |                | Stats_Objects_Atr.3.Valid: 0x00     |        |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
|               |            |            |   | FES 3 | Stat2FpMeter     | STATISTICS_ID_2 (55) | 0 (valid if 1) | Stats_Objects_Resolved.3: 0x000000  |        |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
|               |            |            |   | FES 4 | STATISTICS_ATR_6 | N/A                  | 0 (valid if 1) | Stats_Objects_Atr.7.Is_Meter: 0x00  |        |
|               |            |            |   |       |                  |                      |                | Stats_Objects_Atr.7.Is_LM: 0x00     |        |
|               |            |            |   |       |                  |                      |                | Stats_Objects_Atr.7.Type: 0x00      |        |
|               |            |            |   |       |                  |                      |                | Stats_Objects_Atr.7.Valid: 0x00     |        |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
|               |            |            |   | FES 5 | Stat6FpStat      | STATISTICS_ID_6 (56) | 0 (valid if 1) | Stats_Objects_Resolved.7: 0x000007  |        |
=================================================================================================================================================================
==============================================================================================================
|                             Key Info & Performed Actions for FG ID 9 (NO HIT)                              |
==============================================================================================================
| Qual Type              | Key Value      |   | FES/   | Action Type     | Base   | Valid | Payload | Signal |
|                        |                |   | FEM    |                 | Action |       | Value   | Value  |
|                        |                |   |        |                 | (ID)   |       |         |        |
==============================================================================================================
| GLOB_IN_LIF_0          | 0x00445d       |   | FES 20 | STATISTICS_ID_0 | N/A    | N/A   | N/A     | N/A    |
--------------------------------------------------------------------------------------------------------------
| MAC_SRC                | 0xde26794a6d19 |   | FES 17 | DST_DATA        | N/A    | N/A   | N/A     | N/A    |
--------------------------------------------------------------------------------------------------------------
| MAC_DST                | 0x744d28ac24fb |   | FES 18 | CONGESTION_INFO | N/A    | N/A   | N/A     | N/A    |
--------------------------------------------------------------------------------------------------------------
| VLAN_TPID              | 0x8100         |   | FES 19 | GLOB_OUT_LIF_0  | N/A    | N/A   | N/A     | N/A    |
--------------------------------------------------------------------------------------------------------------
| VLAN_ID                | 0x0002         |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| VLAN_PRI               | 0x00           |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| INCOMING_TAG_STRUCTURE | 0x03           |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| IPV4_SIP               | 0x0a0b78c3     |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| IPV4_DIP               | 0x171d7504     |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| IPV4_PROTOCOL          | 0x06           |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| L4_SRC_PORT            | 0xe9f8         |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| L4_DST_PORT            | 0x0050         |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| IPV4_TOS               | 0x00           |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| FWD_ACTION_STRENGTH    | 0x00           |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| Ethertype (improved)   | 0x0800         |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| Inner TPID             | 0x0800         |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| Inner VID              | 0x0500         |   |        |                 |        |       |         |        |
--------------------------------------------------------------------------------------------------------------
| Inner PCP              | 0x02           |   |        |                 |        |       |         |        |
==============================================================================================================

******************************
*           IPMF3            *
******************************
======================================
|       Context Selection Info       |
======================================
| Presel Id       | N/A              |
======================================
| Context Id/Name | 0 /"Default_Ctx" |
======================================

No attached Field Groups were found for context 0 !!!


No key info and performed actions were found, to be presented!! 


******************************
*           EPMF            *
******************************
=============================
|  Context Selection Info   |
=============================
| Presel Id       | N/A     |
=============================
| Context Id/Name | 1 /"Eg" |
=============================
=================================================================================================
|                                         Field Group Info                                      |
=================================================================================================
| FG Id/Name       | FG   | Key | Raw Data                                   | Hit | Entry Id   |
|                  | Type | Id  |                                            |     |            |
=================================================================================================
| 4/"Egress Rules" | TCAM | B   | 0x00000040801040445fde26794a6d190003000020 | No  | No Entries |
=================================================================================================
========================================================================================================================
|                                  Key Info & Performed Actions for FG ID 4 (NO HIT)                                   |
========================================================================================================================
| Qual Type                | Key Value      |   | FES/  | Action Type              | Base   | Valid | Payload | Signal |
|                          |                |   | FEM   |                          | Action |       | Value   | Value  |
|                          |                |   |       |                          | (ID)   |       |         |        |
========================================================================================================================
| PP_PORT_PMF_PROFILE      | 0x000020       |   | FES 0 | PP_DSP                   | N/A    | N/A   | N/A     | N/A    |
------------------------------------------------------------------------------------------------------------------------
| SRC_SYS_PORT             | 0x0003         |   | FES 1 | CUD_OUTLIF_OR_MCDB_PTR   | N/A    | N/A   | N/A     | N/A    |
------------------------------------------------------------------------------------------------------------------------
| MAC_DST                  | 0xde26794a6d19 |   | FES 2 | FWD_ACTION_PROFILE_INDEX | N/A    | N/A   | N/A     | N/A    |
------------------------------------------------------------------------------------------------------------------------
| GLOB_OUT_LIF_0           | 0x00445f       |   | FES 3 | DISCARD                  | N/A    | N/A   | N/A     | N/A    |
------------------------------------------------------------------------------------------------------------------------
| LAYER_TYPES              | 0x01           |   | FES 4 | PMF_COUNTER_0_PTR        | N/A    | N/A   | N/A     | N/A    |
------------------------------------------------------------------------------------------------------------------------
| FHEI_SIZE                | 0x02           |   | FES 5 | MIRROR_PROFILE           | N/A    | N/A   | N/A     | N/A    |
------------------------------------------------------------------------------------------------------------------------
| FTMH_TM_ACTION_TYPE      | 0x00           |   |       |                          |        |       |         |        |
------------------------------------------------------------------------------------------------------------------------
| ETHERTYPE                | 0x8100         |   |       |                          |        |       |         |        |
------------------------------------------------------------------------------------------------------------------------
| FWD_ACTION_PROFILE_INDEX | 0x00           |   |       |                          |        |       |         |        |
------------------------------------------------------------------------------------------------------------------------
| FHEI type                | 0x00           |   |       |                          |        |       |         |        |
------------------------------------------------------------------------------------------------------------------------
| Slow Protocol Sub-Type   | 0x00           |   |       |                          |        |       |         |        |
========================================================================================================================
0:diag_dnx_field_last_cb:  Error 'Internal error' indicated, Last Info diag failed! Look above for 'Mismatch' prints.
>/usr/bin/bcmcmd tm lag core=all
================================================================================================
|                                                 Lag info                                     |
================================================================================================
| Pool | Max Groups | Max Members | Group | PSC                    | System port | Is Disabled |
================================================================================================
| 0    | 256        | 64          | 1     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 2     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 3     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 4     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 5     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 6     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 7     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 8     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 9     | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 10    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 11    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 12    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 13    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 14    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 15    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 16    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 17    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 18    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 19    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 20    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 21    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 22    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 23    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 24    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 25    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 26    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 27    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 28    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 29    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 30    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 31    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 32    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 33    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 34    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 35    | BCM_TRUNK_PSC_PORTFLOW |             |             |
|      |            |             | 36    | BCM_TRUNK_PSC_PORTFLOW |             |             |
------------------------------------------------------------------------------------------------
| 1    | 256        | 64          |       |                        |             |             |
================================================================================================
>/usr/bin/bcmcmd diag cosq non
No content for table:"MAX VOQ OCCUPANCY: Core 0"
>/usr/bin/bcmcmd tm ing queue non core=all
No content for table:"MAX VOQ OCCUPANCY: Core 0"
>/usr/bin/bcmcmd tm ing queue mapping core=all
=====================================================================================
|                               Ingress Queue Mapping                               |
=====================================================================================
| System Port | Core ID | Base Queue | Master Sysport | Dest Fap | Dest FTMH PP DSP |
=====================================================================================
| 1           | ALL     | 32         | 1              | 0        | 1                |
| 2           | ALL     | 40         | 2              | 0        | 2                |
| 3           | ALL     | 48         | 3              | 0        | 3                |
| 4           | ALL     | 56         | 4              | 0        | 4                |
| 5           | ALL     | 64         | 5              | 0        | 5                |
| 6           | ALL     | 72         | 6              | 0        | 6                |
| 7           | ALL     | 80         | 7              | 0        | 7                |
| 8           | ALL     | 88         | 8              | 0        | 8                |
| 9           | ALL     | 96         | 9              | 0        | 9                |
| 10          | ALL     | 104        | 10             | 0        | 10               |
| 11          | ALL     | 112        | 11             | 0        | 11               |
| 12          | ALL     | 120        | 12             | 0        | 12               |
| 13          | ALL     | 128        | 13             | 0        | 13               |
| 14          | ALL     | 136        | 14             | 0        | 14               |
| 15          | ALL     | 144        | 15             | 0        | 15               |
| 16          | ALL     | 152        | 16             | 0        | 16               |
| 17          | ALL     | 160        | 17             | 0        | 17               |
| 18          | ALL     | 168        | 18             | 0        | 18               |
| 19          | ALL     | 176        | 19             | 0        | 19               |
| 20          | ALL     | 184        | 20             | 0        | 20               |
| 21          | ALL     | 192        | 21             | 0        | 21               |
| 22          | ALL     | 200        | 22             | 0        | 22               |
| 23          | ALL     | 208        | 23             | 0        | 23               |
| 24          | ALL     | 216        | 24             | 0        | 24               |
| 25          | ALL     | 224        | 25             | 0        | 25               |
| 26          | ALL     | 232        | 26             | 0        | 26               |
| 27          | ALL     | 240        | 27             | 0        | 27               |
| 28          | ALL     | 248        | 28             | 0        | 28               |
| 29          | ALL     | 256        | 29             | 0        | 29               |
| 30          | ALL     | 264        | 30             | 0        | 30               |
| 31          | ALL     | 272        | 31             | 0        | 31               |
| 32          | ALL     | 280        | 32             | 0        | 32               |
| 33          | ALL     | 288        | 33             | 0        | 33               |
| 34          | ALL     | 296        | 34             | 0        | 34               |
| 35          | ALL     | 304        | 35             | 0        | 35               |
| 36          | ALL     | 312        | 36             | 0        | 36               |
| 60          | ALL     | 504        | 60             | 0        | 0                |
| 66          | ALL     | 552        | 66             | 0        | 66               |
| 69          | ALL     | 576        | 69             | 0        | 69               |
| 70          | ALL     | 584        | 70             | 0        | 70               |
| 76          | ALL     | 632        | 76             | 0        | 76               |
| 78          | ALL     | 648        | 78             | 0        | 78               |
| 218         | ALL     | 1768       | 218            | 0        | 218              |
| 232         | ALL     | 1880       | 232            | 0        | 232              |
| 240         | ALL     | 1944       | 240            | 0        | 240              |
=====================================================================================
>/usr/bin/bcmcmd tm ing local_to_sys core=all
============================================
|    Local Port to System Port Mapping     |
============================================
| Local Port | System Port | Port Name     |
============================================
| 0          | 60          | cpu0          |
| 1          | 1           | eth1          |
| 2          | 2           | eth2          |
| 3          | 3           | eth3          |
| 4          | 4           | eth4          |
| 5          | 5           | eth5          |
| 6          | 6           | eth6          |
| 7          | 7           | eth7          |
| 8          | 8           | eth8          |
| 9          | 9           | eth9          |
| 10         | 10          | eth10         |
| 11         | 11          | eth11         |
| 12         | 12          | eth12         |
| 13         | 13          | eth13         |
| 14         | 14          | eth14         |
| 15         | 15          | eth15         |
| 16         | 16          | eth16         |
| 17         | 17          | eth17         |
| 18         | 18          | eth18         |
| 19         | 19          | eth19         |
| 20         | 20          | eth20         |
| 21         | 21          | eth21         |
| 22         | 22          | eth22         |
| 23         | 23          | eth23         |
| 24         | 24          | eth24         |
| 25         | 25          | eth25         |
| 26         | 26          | eth26         |
| 27         | 27          | eth27         |
| 28         | 28          | eth28         |
| 29         | 29          | eth29         |
| 30         | 30          | eth30         |
| 31         | 31          | eth31         |
| 32         | 32          | eth32         |
| 33         | 33          | eth33         |
| 34         | 34          | eth34         |
| 35         | 35          | eth35         |
| 36         | 36          | eth36         |
| 66         | 66          | cpu66         |
| 69         | 69          | cpu69         |
| 70         | 70          | cpu70         |
| 71         | 32767       | rcy71         |
| 76         | 76          | rcy76         |
| 78         | 78          | rcy78         |
| 100        | 32767       | rcy_mirror100 |
| 101        | 32767       | rcy_mirror101 |
| 102        | 32767       | rcy_mirror102 |
| 103        | 32767       | rcy_mirror103 |
| 104        | 32767       | rcy_mirror104 |
| 105        | 32767       | rcy_mirror105 |
| 106        | 32767       | rcy_mirror106 |
| 107        | 32767       | rcy_mirror107 |
| 108        | 32767       | rcy_mirror108 |
| 109        | 32767       | rcy_mirror109 |
| 110        | 32767       | rcy_mirror110 |
| 111        | 32767       | rcy_mirror111 |
| 112        | 32767       | rcy_mirror112 |
| 113        | 32767       | rcy_mirror113 |
| 114        | 32767       | rcy_mirror114 |
| 115        | 32767       | rcy_mirror115 |
| 116        | 32767       | rcy_mirror116 |
| 117        | 32767       | rcy_mirror117 |
| 118        | 32767       | rcy_mirror118 |
| 119        | 32767       | rcy_mirror119 |
| 120        | 32767       | rcy_mirror120 |
| 121        | 32767       | rcy_mirror121 |
| 122        | 32767       | rcy_mirror122 |
| 123        | 32767       | rcy_mirror123 |
| 124        | 32767       | rcy_mirror124 |
| 125        | 32767       | rcy_mirror125 |
| 126        | 32767       | rcy_mirror126 |
| 127        | 32767       | rcy_mirror127 |
| 128        | 32767       | rcy_mirror128 |
| 129        | 32767       | rcy_mirror129 |
| 130        | 32767       | rcy_mirror130 |
| 131        | 32767       | rcy_mirror131 |
| 132        | 32767       | rcy_mirror132 |
| 133        | 32767       | rcy_mirror133 |
| 134        | 32767       | rcy_mirror134 |
| 135        | 32767       | rcy_mirror135 |
| 136        | 32767       | rcy_mirror136 |
| 137        | 32767       | rcy_mirror137 |
| 138        | 32767       | rcy_mirror138 |
| 139        | 32767       | rcy_mirror139 |
| 140        | 32767       | rcy_mirror140 |
| 141        | 32767       | rcy_mirror141 |
| 142        | 32767       | rcy_mirror142 |
| 143        | 32767       | rcy_mirror143 |
| 144        | 32767       | rcy_mirror144 |
| 145        | 32767       | rcy_mirror145 |
| 146        | 32767       | rcy_mirror146 |
| 147        | 32767       | rcy_mirror147 |
| 148        | 32767       | rcy_mirror148 |
| 149        | 32767       | rcy_mirror149 |
| 218        | 218         | sat218        |
| 232        | 232         | oamp232       |
| 240        | 240         | olp240        |
============================================
>/usr/bin/bcmcmd tm ing reass core=all
===================================================================================================================
|                                                Reassembly Context                                               |
===================================================================================================================
| Port | Core | IN TM Port | Reassembly Context - priority 0 | Reassembly Context - priority 1 | Port Termination |
===================================================================================================================
| 0    | 0    | 0          | 0                               | -                               | 0                |
| 1    | 0    | 1          | 1                               | 255                             | 1                |
| 2    | 0    | 2          | 2                               | 255                             | 2                |
| 3    | 0    | 3          | 3                               | 255                             | 3                |
| 4    | 0    | 4          | 4                               | 255                             | 4                |
| 5    | 0    | 5          | 5                               | 255                             | 5                |
| 6    | 0    | 6          | 6                               | 255                             | 6                |
| 7    | 0    | 7          | 7                               | 255                             | 7                |
| 8    | 0    | 8          | 8                               | 255                             | 8                |
| 9    | 0    | 9          | 9                               | 255                             | 9                |
| 10   | 0    | 10         | 10                              | 255                             | 10               |
| 11   | 0    | 11         | 11                              | 255                             | 11               |
| 12   | 0    | 12         | 12                              | 255                             | 12               |
| 13   | 0    | 13         | 13                              | 255                             | 13               |
| 14   | 0    | 14         | 14                              | 255                             | 14               |
| 15   | 0    | 15         | 15                              | 255                             | 15               |
| 16   | 0    | 16         | 16                              | 255                             | 16               |
| 17   | 0    | 17         | 17                              | 255                             | 17               |
| 18   | 0    | 18         | 18                              | 255                             | 18               |
| 19   | 0    | 19         | 19                              | 255                             | 19               |
| 20   | 0    | 20         | 20                              | 255                             | 20               |
| 21   | 0    | 21         | 21                              | 255                             | 21               |
| 22   | 0    | 22         | 22                              | 255                             | 22               |
| 23   | 0    | 23         | 23                              | 255                             | 23               |
| 24   | 0    | 24         | 24                              | 255                             | 24               |
| 25   | 0    | 25         | 25                              | 255                             | 25               |
| 26   | 0    | 26         | 26                              | 255                             | 26               |
| 27   | 0    | 27         | 27                              | 255                             | 27               |
| 28   | 0    | 28         | 28                              | 255                             | 28               |
| 29   | 0    | 29         | 29                              | 255                             | 29               |
| 30   | 0    | 30         | 30                              | 255                             | 30               |
| 31   | 0    | 31         | 31                              | 255                             | 31               |
| 32   | 0    | 32         | 32                              | 255                             | 32               |
| 33   | 0    | 33         | 33                              | 255                             | 33               |
| 34   | 0    | 34         | 34                              | 255                             | 34               |
| 35   | 0    | 35         | 35                              | 255                             | 35               |
| 36   | 0    | 36         | 36                              | 255                             | 36               |
| 66   | 0    | 66         | 0                               | -                               | 66               |
| 69   | 0    | 69         | 0                               | -                               | 69               |
| 70   | 0    | 70         | 0                               | -                               | 70               |
| 71   | 0    | 71         | 37                              | -                               | 71               |
| 76   | 0    | 76         | 37                              | -                               | 76               |
| 78   | 0    | 78         | 37                              | -                               | 78               |
| 100  | 0    | 100        | 42                              | 43                              | 100              |
| 101  | 0    | 101        | 44                              | 45                              | 101              |
| 102  | 0    | 102        | 46                              | 47                              | 102              |
| 103  | 0    | 103        | 48                              | 49                              | 103              |
| 104  | 0    | 104        | 50                              | 51                              | 104              |
| 105  | 0    | 105        | 52                              | 53                              | 105              |
| 106  | 0    | 106        | 54                              | 55                              | 106              |
| 107  | 0    | 107        | 56                              | 57                              | 107              |
| 108  | 0    | 108        | 58                              | 59                              | 108              |
| 109  | 0    | 109        | 60                              | 61                              | 109              |
| 110  | 0    | 110        | 62                              | 63                              | 110              |
| 111  | 0    | 111        | 64                              | 65                              | 111              |
| 112  | 0    | 112        | 66                              | 67                              | 112              |
| 113  | 0    | 113        | 68                              | 69                              | 113              |
| 114  | 0    | 114        | 70                              | 71                              | 114              |
| 115  | 0    | 115        | 72                              | 73                              | 115              |
| 116  | 0    | 116        | 74                              | 75                              | 116              |
| 117  | 0    | 117        | 76                              | 77                              | 117              |
| 118  | 0    | 118        | 78                              | 79                              | 118              |
| 119  | 0    | 119        | 80                              | 81                              | 119              |
| 120  | 0    | 120        | 82                              | 83                              | 120              |
| 121  | 0    | 121        | 84                              | 85                              | 121              |
| 122  | 0    | 122        | 86                              | 87                              | 122              |
| 123  | 0    | 123        | 88                              | 89                              | 123              |
| 124  | 0    | 124        | 90                              | 91                              | 124              |
| 125  | 0    | 125        | 92                              | 93                              | 125              |
| 126  | 0    | 126        | 94                              | 95                              | 126              |
| 127  | 0    | 127        | 96                              | 97                              | 127              |
| 128  | 0    | 128        | 98                              | 99                              | 128              |
| 129  | 0    | 129        | 100                             | 101                             | 129              |
| 130  | 0    | 130        | 102                             | 103                             | 130              |
| 131  | 0    | 131        | 104                             | 105                             | 131              |
| 132  | 0    | 132        | 106                             | 107                             | 132              |
| 133  | 0    | 133        | 108                             | 109                             | 133              |
| 134  | 0    | 134        | 110                             | 111                             | 134              |
| 135  | 0    | 135        | 112                             | 113                             | 135              |
| 136  | 0    | 136        | 114                             | 115                             | 136              |
| 137  | 0    | 137        | 42                              | 43                              | 137              |
| 138  | 0    | 138        | 42                              | 43                              | 138              |
| 139  | 0    | 139        | 42                              | 43                              | 139              |
| 140  | 0    | 140        | 116                             | 117                             | 140              |
| 141  | 0    | 141        | 118                             | 119                             | 141              |
| 142  | 0    | 142        | 120                             | 121                             | 142              |
| 143  | 0    | 143        | 255                             | 255                             | 143              |
| 144  | 0    | 144        | 255                             | 255                             | 144              |
| 145  | 0    | 145        | 255                             | 255                             | 145              |
| 146  | 0    | 146        | 255                             | 255                             | 146              |
| 147  | 0    | 147        | 255                             | 255                             | 147              |
| 148  | 0    | 148        | 255                             | 255                             | 148              |
| 149  | 0    | 149        | 255                             | 255                             | 149              |
| 218  | 0    | 218        | 39                              | -                               | 218              |
| 232  | 0    | 232        | 40                              | -                               | 232              |
| 240  | 0    | 240        | 41                              | -                               | 240              |
===================================================================================================================
>/usr/bin/bcmcmd tm ing cong core=all
======================================
|          Ingress Congestion        |
======================================
| Resource                  | Core 0 |
======================================
| Free DRAM BDBs            | 65521  |
--------------------------------------
| Minimum Free DRAM BDBs    | 65521  |
--------------------------------------
| Free SRAM Buffers         | 32768  |
--------------------------------------
| Minimum Free SRAM Buffers | 32712  |
--------------------------------------
| Free SRAM PDBs            | 16345  |
--------------------------------------
| Minimum Free SRAM PDBs    | 16319  |
======================================
>/usr/bin/bcmcmd tm ing port core=all
===============================================================================================================
|                                               Ingress Port Drop                                             |
===============================================================================================================
| port | PRD Port Type | PRD Priority | Sch Priority | FIFO Size(in entries) | Threshold     | PRD Drop count |
===============================================================================================================
| 1    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 2    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 3    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 4    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 5    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 6    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 7    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 8    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 9    | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 10   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 11   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 12   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 13   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 14   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 15   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 16   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 17   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 18   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 19   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 20   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 21   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 22   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 23   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 24   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 25   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 26   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 27   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 28   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 29   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 30   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 31   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 32   | ETH           | 0,1,2,3      | Low          | 32                    | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 33   | ETH           | 0,1,2,3      | Low          | 256                   | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 34   | ETH           | 0,1,2,3      | Low          | 256                   | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 35   | ETH           | 0,1,2,3      | Low          | 256                   | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
| 36   | ETH           | 0,1,2,3      | Low          | 256                   | 0 - unlimited | 0              |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 1 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 2 - unlimited |                |
---------------------------------------------------------------------------------------------------------------
|      |               |              |              |                       | 3 - unlimited |                |
===============================================================================================================
>/usr/bin/bcmcmd tm ing comp core=all
===============================================================================
|                                        Ingress Compensation - General       |
|   For more information select compensation type - sch/crps/stif.            |
===============================================================================
| Compensation component | ID  | Enabled                | Delta Value [Bytes] |
===============================================================================
| Header Truncate        |  -- | SCH/CRPS/STIF specific |  --                 |
-------------------------------------------------------------------------------
| IRPP Delta             |  -- | True                   | Automatic           |
-------------------------------------------------------------------------------
| Queue                  |  -- | SCH/CRPS/STIF specific |  --                 |
-------------------------------------------------------------------------------
| Input Port             |  -- | SCH/CRPS/STIF specific |  --                 |
-------------------------------------------------------------------------------
| Header Append Profile  |  -- | SCH/CRPS/STIF specific |  --                 |
===============================================================================

*Note that configured compensation values affect all Compensation types
(SCH/CRPS/STIF) which have enabled that compensation component.

>/usr/bin/bcmcmd tm ing system_red res core=all
=======================================================================================================
|                                     Resource to RED-Q-Size Map                                      |
=======================================================================================================
| Resource    | RED Index 0 | Thr 0 | RED Index 1 | Thr 1 | RED Index 2 | Thr 2 | RED Index 3 | Thr 3 |
=======================================================================================================
| OCB PDBs    | 0           | 0     | 0           | 0     | 0           | 0     | 0           | 16383 |
| OCB Buffers | 0           | 0     | 0           | 0     | 0           | 0     | 0           | 32767 |
| DRAM BDBs   | 0           | 0     | 0           | 0     | 0           | 0     | 0           | 65535 |
=======================================================================================================
>/usr/bin/bcmcmd tm ing system_red stat core=all
=====================================
|          System RED Status        |
=====================================
| Current RED Index | Max RED Index |
=====================================
| 0                 | 0             |
=====================================
>/usr/bin/bcmcmd tm ing vsq res core=all
========================================================================================
|                              Core 0 Resource Allocation                              |
========================================================================================
| Parameter        | Bytes                   | OCB Buffers    | OCB Packet Descriptors |
========================================================================================
| Nominal Headroom | 0                       | 0              | 0                      |
| (Max Headroom)   | 0                       | 0              | 0                      |
| Pool 0           | 2147483392              | 32752          | 65520                  |
| Pool 1           | 0                       | 0              | 0                      |
| Reserved         | 0                       | 0              | 0                      |
| Maximal          | 2147483647 (0x7fffffff) | 32767 (0x7fff) | 65535 (0xffff)         |
| Unused           | 0                       | 0              | 0                      |
========================================================================================
>/usr/bin/bcmcmd tm ing vsq count group=e core=all
=====================================
| VSQ: E Core: 0 counter statistics |
=====================================
| Counter name          | Value     |
=====================================
| SRAM Enqueued packets | 1616580   |
| SRAM Rejected packets | 259       |
=====================================
>/usr/bin/bcmcmd tm ing vsq count group=f core=all
=====================================
| VSQ: F Core: 0 counter statistics |
=====================================
| Counter name          | Value     |
=====================================
| SRAM Enqueued packets | 11153     |
| SRAM Rejected packets | 1         |
=====================================
>/usr/bin/bcmcmd tm ing vsq non_empty group=e core=all
=========================================================================================================================================================================================================================
|                                                                                              MAX VSQ E OCCUPANCY: Core 0                                                     |
=========================================================================================================================================================================================================================
| VSQ ID | Guaranteed | Shared  | Headroom | Guaranteed | Shared  | Headroom || Guaranteed | Shared   | Headroom | Guaranteed | Shared   | Headroom || Guaranteed | Shared | Headroom | Guaranteed | Shared | Headroom ||
|        | Pool 0     | Pool 0  | Pool 0   | Pool 1     | Pool 1  | Pool 1   || Pool 0     | Pool 0   | Pool 0   | Pool 1     | Pool 1   | Pool 1   || Pool 0     | Pool 0 | Pool 0   | Pool 1     | Pool 1 | Pool 1   ||
|        | [Bytes]    | [Bytes] | [Bytes]  | [Bytes]    | [Bytes] | [Bytes]  || [OCB       | [OCB     | [OCB     | [OCB       | [OCB     | [OCB     || [OCB PDS]  | [OCB   | [OCB     | [OCB PDS]  | [OCB   | [OCB     ||
|        |            |         |          |            |         |          || Buffers]   | Buffers] | Buffers] | Buffers]   | Buffers] | Buffers] ||            | PDS]   | PDS]     |            | PDS]   | PDS]     ||
=========================================================================================================================================================================================================================
| 63     | 0          | 1568    | 0        | 0          | 0       | 0        || 0          | 0        | 0        | 0          | 0        | 0        || 0          | 0      | 0        | 0          | 0      | 0        ||
=========================================================================================================================================================================================================================
>/usr/bin/bcmcmd tm ing vsq non_empty group=f core=all
No content for table:"MAX VSQ F OCCUPANCY: Core 0"
>/usr/bin/bcmcmd tm ing rate cgm core=all
========================================================
|      Ingress CGM Rate on All Queues on core(0)       |
========================================================
| No. | Counter                         | Rate  | Unit |
========================================================
| 0   | SRAM Enqueued packets           | 10    | kpps |
| 1   | SRAM Rejected packets           | 0     | kpps |
| 2   | SRAM to DRAM Dequeued packets   | 0     | kpps |
| 3   | SRAM to Fabric Dequeued packets | 10    | kpps |
| 4   | SRAM Deleted packets            | 0     | kpps |
| 5   | SRAM Enqueued bytes             | 69681 | kbps |
| 6   | SRAM Discarded bytes            | 1     | kbps |
| 7   | SRAM Deleted bytes              | 0     | kbps |
| 8   | SRAM to DRAM Dequeued bytes     | 0     | kbps |
| 9   | SSRAM to fabric Dequeued bytes  | 69681 | kbps |
========================================================
>/usr/bin/bcmcmd tm ing rate ipt core=all
=================================================
|         Ingress IPT Rate on core (0)          |
=================================================
| No. | Counter                   | Rate | Unit |
=================================================
| 0   | Packet from CGM Count     | 0    | kpps |
| 1   | Packet from SPB Count     | 11   | kpps |
| 2   | ITPP Discard Packet Count | 0    | kpps |
=================================================
>/usr/bin/bcmcmd tm ing rate sqm core=all
=============================================
|       Ingress SQM Rate on core (0)        |
=============================================
| No. | Counter               | Rate | Unit |
=============================================
| 0   | EN-QUEUE Packet Count | 13   | kpps |
| 1   | DE-QUEUE Packet Count | 13   | kpps |
=============================================
>/usr/bin/bcmcmd tm ing rate ire core=all
=======================================================
|            Ingress IRE Rate on core (0)             |
=======================================================
| No. | Counter                         | Rate | Unit |
=======================================================
| 0   | NIF Packet Count                | 16   | kpps |
| 1   | RCYH Packet Count               | 0    | kpps |
| 2   | RCYL Packet Count               | 0    | kpps |
| 3   | CPU Packet Count                | 0    | kpps |
| 4   | OLP Packet Count                | 0    | kpps |
| 5   | OAMP Packet Count               | 0    | kpps |
| 6   | Register Interface Packet Count | 0    | kpps |
=======================================================
>/usr/bin/bcmcmd tm egr shaper core=all
===============================================================================================
|                                             EGQ shaping                                     |
===============================================================================================
| Port | EGQ Port rate [Kbps] | Core | EGQ IF | Nof Qpairs | Channelized | EGQ IF rate [Kbps] |
===============================================================================================
| 0    | 2525034              | 0    | 0      | 2          | yes         | 10100135           |
| 1    | 10201153             | 0    | 32     | 2          | no          | unlimited          |
| 2    | 10201153             | 0    | 33     | 2          | no          | unlimited          |
| 3    | 10201153             | 0    | 34     | 2          | no          | unlimited          |
| 4    | 10201153             | 0    | 35     | 2          | no          | unlimited          |
| 5    | 10201153             | 0    | 36     | 2          | no          | unlimited          |
| 6    | 10201153             | 0    | 37     | 2          | no          | unlimited          |
| 7    | 10201153             | 0    | 38     | 2          | no          | unlimited          |
| 8    | 10201153             | 0    | 39     | 2          | no          | unlimited          |
| 9    | 10201153             | 0    | 40     | 2          | no          | unlimited          |
| 10   | 10201153             | 0    | 41     | 2          | no          | unlimited          |
| 11   | 10201153             | 0    | 42     | 2          | no          | unlimited          |
| 12   | 10201153             | 0    | 43     | 2          | no          | unlimited          |
| 13   | 10201153             | 0    | 44     | 2          | no          | unlimited          |
| 14   | 10201153             | 0    | 45     | 2          | no          | unlimited          |
| 15   | 10201153             | 0    | 46     | 2          | no          | unlimited          |
| 16   | 10201153             | 0    | 47     | 2          | no          | unlimited          |
| 17   | 10201153             | 0    | 48     | 2          | no          | unlimited          |
| 18   | 10201153             | 0    | 49     | 2          | no          | unlimited          |
| 19   | 10201153             | 0    | 50     | 2          | no          | unlimited          |
| 20   | 10201153             | 0    | 51     | 2          | no          | unlimited          |
| 21   | 10201153             | 0    | 52     | 2          | no          | unlimited          |
| 22   | 10201153             | 0    | 53     | 2          | no          | unlimited          |
| 23   | 10201153             | 0    | 54     | 2          | no          | unlimited          |
| 24   | 10201153             | 0    | 55     | 2          | no          | unlimited          |
| 25   | 10201153             | 0    | 56     | 2          | no          | unlimited          |
| 26   | 10201153             | 0    | 57     | 2          | no          | unlimited          |
| 27   | 10201153             | 0    | 58     | 2          | no          | unlimited          |
| 28   | 10201153             | 0    | 59     | 2          | no          | unlimited          |
| 29   | 10201153             | 0    | 60     | 2          | no          | unlimited          |
| 30   | 10201153             | 0    | 61     | 2          | no          | unlimited          |
| 31   | 10201153             | 0    | 62     | 2          | no          | unlimited          |
| 32   | 10201153             | 0    | 63     | 2          | no          | unlimited          |
| 33   | 102010098            | 0    | 64     | 2          | no          | unlimited          |
| 34   | 102010098            | 0    | 65     | 2          | no          | unlimited          |
| 35   | 102010098            | 0    | 66     | 2          | no          | unlimited          |
| 36   | 102010098            | 0    | 67     | 2          | no          | unlimited          |
| 66   | 2525034              | 0    | 0      | 8          | yes         | 10100135           |
| 69   | 2525034              | 0    | 0      | 2          | yes         | 10100135           |
| 70   | 2525034              | 0    | 0      | 2          | yes         | 10100135           |
| 71   | 3366712              | 0    | 4      | 2          | yes         | 10100135           |
| 76   | 3366712              | 0    | 4      | 2          | yes         | 10100135           |
| 78   | 3366712              | 0    | 4      | 2          | yes         | 10100135           |
| 218  | 10100113             | 0    | 1      | 2          | no          | unlimited          |
| 232  | 10100113             | 0    | 2      | 2          | no          | unlimited          |
| 240  | 10100135             | 0    | 3      | 2          | yes         | 10100135           |
===============================================================================================
>/usr/bin/bcmcmd tm egr comp core=all
===============================
|        EGQ Compensation     |
===============================
| Port | Compensation [Bytes] |
===============================
| 0    | 24                   |
| 1    | 24                   |
| 2    | 24                   |
| 3    | 24                   |
| 4    | 24                   |
| 5    | 24                   |
| 6    | 24                   |
| 7    | 24                   |
| 8    | 24                   |
| 9    | 24                   |
| 10   | 24                   |
| 11   | 24                   |
| 12   | 24                   |
| 13   | 24                   |
| 14   | 24                   |
| 15   | 24                   |
| 16   | 24                   |
| 17   | 24                   |
| 18   | 24                   |
| 19   | 24                   |
| 20   | 24                   |
| 21   | 24                   |
| 22   | 24                   |
| 23   | 24                   |
| 24   | 24                   |
| 25   | 24                   |
| 26   | 24                   |
| 27   | 24                   |
| 28   | 24                   |
| 29   | 24                   |
| 30   | 24                   |
| 31   | 24                   |
| 32   | 24                   |
| 33   | 24                   |
| 34   | 24                   |
| 35   | 24                   |
| 36   | 24                   |
| 66   | 24                   |
| 69   | 24                   |
| 70   | 24                   |
| 71   | 24                   |
| 76   | 24                   |
| 78   | 24                   |
| 218  | 24                   |
| 232  | 24                   |
| 240  | 24                   |
===============================
>/usr/bin/bcmcmd tm egr cong core=all
No content for table:"ECGM Resources Per Core - Current Value"
No content for table:"ECGM Resources Per Element - Current Value"
=================================================================
|        ECGM Resources Per Service Pool - Current Value        |
=================================================================
| Core | Service Pool | PDs | DBs | Reserved PDs | Reserved DBs |
=================================================================
| 0    | 0            | 0   | 0   | 472          | 1200         |
| 0    | 1            | 0   | 0   | 472          | 1200         |
=================================================================
No content for table:"ECGM Resources Per Service Pool Per TC - Current Value"
====================================================================
|               ECGM Resources Per Core - Max Value                |
====================================================================
| Core | total PDs | UC PDs | MC PDs | total DBs | UC DBs | MC DBs |
====================================================================
| 0    | 33        | 33     | 0      | 62        | 62     | 0      |
====================================================================
========================================================================
|                ECGM Resources Per Element - Max Value                |
========================================================================
| Core | Element Type | Element ID | UC PDs | MC PDs | UC DBs | MC DBs |
========================================================================
| 0    | Interface    | 0          | 40     | 0      | 41     | 0      |
| 0    | Interface    | 3          | 1      | 0      | 1      | 0      |
| 0    | Interface    | 32         | 6      | 0      | 38     | 0      |
| 0    | Interface    | 33         | 5      | 0      | 35     | 0      |
| 0    | Interface    | 34         | 6      | 0      | 42     | 0      |
| 0    | Interface    | 35         | 5      | 0      | 42     | 0      |
| 0    | Interface    | 36         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 37         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 38         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 39         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 40         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 41         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 42         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 43         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 44         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 45         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 46         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 47         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 48         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 49         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 50         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 51         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 52         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 53         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 54         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 55         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 56         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 57         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 58         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 59         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 60         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 61         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 62         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 63         | 40     | 0      | 81     | 0      |
| 0    | Interface    | 64         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 65         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 66         | 1      | 0      | 2      | 0      |
| 0    | Interface    | 67         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 1          | 6      | 0      | 38     | 0      |
| 0    | Logical Port | 2          | 5      | 0      | 35     | 0      |
| 0    | Logical Port | 3          | 6      | 0      | 42     | 0      |
| 0    | Logical Port | 4          | 5      | 0      | 42     | 0      |
| 0    | Logical Port | 5          | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 6          | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 7          | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 8          | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 9          | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 10         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 11         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 12         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 13         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 14         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 15         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 16         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 17         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 18         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 19         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 20         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 21         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 22         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 23         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 24         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 25         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 26         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 27         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 28         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 29         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 30         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 31         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 32         | 40     | 0      | 81     | 0      |
| 0    | Logical Port | 33         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 34         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 35         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 36         | 1      | 0      | 2      | 0      |
| 0    | Logical Port | 66         | 40     | 0      | 41     | 0      |
| 0    | Logical Port | 240        | 1      | 0      | 1      | 0      |
| 0    | Queue        | 9          | 6      | 0      | 38     | 0      |
| 0    | Queue        | 11         | 5      | 0      | 35     | 0      |
| 0    | Queue        | 13         | 6      | 0      | 42     | 0      |
| 0    | Queue        | 15         | 5      | 0      | 42     | 0      |
| 0    | Queue        | 17         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 19         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 21         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 23         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 25         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 27         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 29         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 31         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 33         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 35         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 37         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 39         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 41         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 43         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 45         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 47         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 49         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 51         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 53         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 55         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 57         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 59         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 61         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 63         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 65         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 67         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 69         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 71         | 40     | 0      | 81     | 0      |
| 0    | Queue        | 73         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 75         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 77         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 79         | 1      | 0      | 2      | 0      |
| 0    | Queue        | 83         | 40     | 0      | 41     | 0      |
| 0    | Queue        | 105        | 1      | 0      | 1      | 0      |
========================================================================
No content for table:"ECGM Resources Per Service Pool - Max Value"
No content for table:"ECGM Resources Per Service Pool Per TC - Max Value"
No content for table:"ECGM to SCH Global FC Indications"
No content for table:"ECGM to SCH per Interface FC Indications"
No content for table:"ECGM to SCH per Q-pair FC Indications"
>/usr/bin/bcmcmd tm egr rate rqp core=all
===================================================
|           Egress RQP Rate on core (0)           |
===================================================
| No. | Coutner                     | Rate | Unit |
===================================================
| 0   | EMR_UNICAST_PACKET_COUNTER  | 10   | Kpps |
| 1   | EMR_MC_HIGH_PACKET_COUNTER  | 0    | Kpps |
| 2   | EMR_MC_LOW_PACKET_COUNTER   | 0    | Kpps |
| 3   | EMR_DISCARDS_PACKET_COUNTER | 0    | Kpps |
| 4   | EMR_TDM_PACKET_COUNTER      | 0    | Kpps |
| 5   | PRP_PACKET_IN_CNT           | 10   | Kpps |
| 6   | PRP_PACKET_GOOD_UC_CNT      | 10   | Kpps |
| 7   | PRP_PACKET_GOOD_MC_CNT      | 0    | Kpps |
| 8   | PRP_PACKET_GOOD_TDM_CNT     | 0    | Kpps |
| 9   | PRP_PACKET_DISCARD_UC_CNT   | 0    | Kpps |
| 10  | PRP_PACKET_DISCARD_MC_CNT   | 0    | Kpps |
| 11  | PRP_PACKET_DISCARD_TDM_CNT  | 0    | Kpps |
| 12  | PRP_SOP_DISCARD_UC_CNT      | 0    | Kpps |
| 13  | PRP_SOP_DISCARD_MC_CNT      | 0    | Kpps |
| 14  | PRP_SOP_DISCARD_TDM_CNT     | 0    | Kpps |
| 15  | PRP_TDM_BYPASS_PACKET_CNT   | 0    | Kpps |
===================================================
>/usr/bin/bcmcmd tm egr rate pqp
==================================================================
|                  Egress PQP Rate on core (0)                   |
==================================================================
| No. | Coutner                                  | Rate   | Unit |
==================================================================
| 0   | PQP_ENQ_PACKET_COUNTER                   | 18     | Kpps |
| 1   | PQP_ENQ_BYTES_COUNTER                    | 150658 | Kbps |
| 2   | PQP_DEQ_UNICAST_PACKET_COUNTER           | 18     | Kpps |
| 3   | PQP_DEQ_MULTICAST_PACKET_COUNTER         | 0      | Kpps |
| 4   | PQP_DEQ_DISCARD_UNICAST_PACKET_COUNTER   | 0      | Kpps |
| 5   | PQP_DEQ_DISCARD_MULTICAST_PACKET_COUNTER | 0      | Kpps |
| 6   | PQP_DEQ_UNICAST_BYTES_COUNTER            | 150641 | Kbps |
| 7   | PQP_DEQ_MULTICAST_BYTES_COUNTER          | 0      | Kbps |
==================================================================
>/usr/bin/bcmcmd tm egr rate epeport
==================================================
|          Egress EPEP Rate on core(0)           |
==================================================
| No. | Coutner                   | Rate  | Unit |
==================================================
| 0   | EPNI_Q_CNT_PACKET         | 9     | Kpps |
| 1   | EPNI_DISC_CNT_PACKET      | 0     | Kpps |
| 2   | EPNI_FRWD_DISC_CNT_PACKET | 0     | Kpps |
| 3   | EPNI_Q_CNT_BYTE           | 61077 | Kbps |
| 4   | EPNI_DISC_CNT_BYTE        | 0     | Kbps |
| 5   | EPNI_FRWD_DISC_CNT_BYTE   | 0     | Kbps |
==================================================
>/usr/bin/bcmcmd tm egr rate epni core=all
=========================================================
|            Egress EPNI Rate on the device             |
=========================================================
| Core | No. | Coutner                   | Rate  | Unit |
=========================================================
| 0    | 0   | EPNI_Q_CNT_PACKET         | 14    | Kpps |
|      | 1   | EPNI_IFC_CNT_PACKET       | 14    | Kpps |
|      | 2   | EPNI_MIRR_CNT_PACKET      | 0     | Kpps |
|      | 3   | EPNI_DISC_CNT_PACKET      | 0     | Kpps |
|      | 4   | EPNI_FRWD_DISC_CNT_PACKET | 0     | Kpps |
|      | 5   | EPNI_Q_CNT_BYTE           | 67574 | Kbps |
|      | 6   | EPNI_IFC_CNT_BYTE         | 67574 | Kbps |
|      | 7   | EPNI_MIRR_CNT_BYTE        | 0     | Kbps |
|      | 8   | EPNI_DISC_CNT_BYTE        | 0     | Kbps |
|      | 9   | EPNI_FRWD_DISC_CNT_BYTE   | 0     | Kbps |
=========================================================
>/usr/bin/bcmcmd tm egr rate egq
=================================================================
|                Egress Queuing Rate on core (0)                |
=================================================================
| No. | Coutner                                  | Rate  | Unit |
=================================================================
| 0   | EMR_UNICAST_PACKET_COUNTER               | 10    | Kpps |
| 1   | EMR_MC_HIGH_PACKET_COUNTER               | 0     | Kpps |
| 2   | EMR_MC_LOW_PACKET_COUNTER                | 0     | Kpps |
| 3   | EMR_DISCARDS_PACKET_COUNTER              | 0     | Kpps |
| 4   | EMR_TDM_PACKET_COUNTER                   | 0     | Kpps |
| 5   | PRP_PACKET_IN_CNT                        | 10    | Kpps |
| 6   | PRP_PACKET_GOOD_UC_CNT                   | 10    | Kpps |
| 7   | PRP_PACKET_GOOD_MC_CNT                   | 0     | Kpps |
| 8   | PRP_PACKET_GOOD_TDM_CNT                  | 0     | Kpps |
| 9   | PRP_PACKET_DISCARD_UC_CNT                | 0     | Kpps |
| 10  | PRP_PACKET_DISCARD_MC_CNT                | 0     | Kpps |
| 11  | PRP_PACKET_DISCARD_TDM_CNT               | 0     | Kpps |
| 12  | PRP_SOP_DISCARD_UC_CNT                   | 0     | Kpps |
| 13  | PRP_SOP_DISCARD_MC_CNT                   | 0     | Kpps |
| 14  | PRP_SOP_DISCARD_TDM_CNT                  | 0     | Kpps |
| 15  | PRP_TDM_BYPASS_PACKET_CNT                | 0     | Kpps |
| 16  | PQP_ENQ_PACKET_COUNTER                   | 13    | Kpps |
| 17  | PQP_ENQ_BYTES_COUNTER                    | 99579 | Kbps |
| 18  | PQP_DEQ_UNICAST_PACKET_COUNTER           | 13    | Kpps |
| 19  | PQP_DEQ_MULTICAST_PACKET_COUNTER         | 0     | Kpps |
| 20  | PQP_DEQ_DISCARD_UNICAST_PACKET_COUNTER   | 0     | Kpps |
| 21  | PQP_DEQ_DISCARD_MULTICAST_PACKET_COUNTER | 0     | Kpps |
| 22  | PQP_DEQ_UNICAST_BYTES_COUNTER            | 99564 | Kbps |
| 23  | PQP_DEQ_MULTICAST_BYTES_COUNTER          | 0     | Kbps |
| 24  | EPNI_Q_CNT_PACKET                        | 12    | Kpps |
| 25  | EPNI_DISC_CNT_PACKET                     | 0     | Kpps |
| 26  | EPNI_FRWD_DISC_CNT_PACKET                | 0     | Kpps |
| 27  | EPNI_Q_CNT_BYTE                          | 65404 | Kbps |
| 28  | EPNI_DISC_CNT_BYTE                       | 0     | Kbps |
| 29  | EPNI_FRWD_DISC_CNT_BYTE                  | 0     | Kbps |
=================================================================
>/usr/bin/bcmcmd tm egr rate int core=all
===============================================================================
|                         Rate Measure per Interface                          |
===============================================================================
| Port | Core | EGQ IF | Utilization Rate [Percent] | Utilization Rate [Mbps] |
===============================================================================
| 0    | 0    | 0      |   0.0%                     | 0                       |
| 1    | 0    | 32     |   0.0%                     | 0                       |
| 2    | 0    | 33     |   0.0%                     | 0                       |
| 3    | 0    | 34     |   0.0%                     | 0                       |
| 4    | 0    | 35     |   0.0%                     | 0                       |
| 5    | 0    | 36     |   0.0%                     | 0                       |
| 6    | 0    | 37     |   0.0%                     | 0                       |
| 7    | 0    | 38     |   0.0%                     | 0                       |
| 8    | 0    | 39     |   0.0%                     | 0                       |
| 9    | 0    | 40     |   0.0%                     | 0                       |
| 10   | 0    | 41     |   0.0%                     | 0                       |
| 11   | 0    | 42     |   0.0%                     | 0                       |
| 12   | 0    | 43     |   0.0%                     | 0                       |
| 13   | 0    | 44     |   0.0%                     | 0                       |
| 14   | 0    | 45     |   0.0%                     | 0                       |
| 15   | 0    | 46     |   0.0%                     | 0                       |
| 16   | 0    | 47     |   0.0%                     | 0                       |
| 17   | 0    | 48     |   0.0%                     | 0                       |
| 18   | 0    | 49     |   0.0%                     | 0                       |
| 19   | 0    | 50     |   0.0%                     | 0                       |
| 20   | 0    | 51     |   0.0%                     | 0                       |
| 21   | 0    | 52     |   0.0%                     | 0                       |
| 22   | 0    | 53     |   0.0%                     | 0                       |
| 23   | 0    | 54     |   0.0%                     | 0                       |
| 24   | 0    | 55     |   0.0%                     | 0                       |
| 25   | 0    | 56     |   0.0%                     | 0                       |
| 26   | 0    | 57     |   0.0%                     | 0                       |
| 27   | 0    | 58     |   0.0%                     | 0                       |
| 28   | 0    | 59     |   0.0%                     | 0                       |
| 29   | 0    | 60     |   0.0%                     | 0                       |
| 30   | 0    | 61     |   0.0%                     | 0                       |
| 31   | 0    | 62     |   0.0%                     | 0                       |
| 32   | 0    | 63     |   0.0%                     | 0                       |
| 33   | 0    | 64     |   0.0%                     | 0                       |
| 34   | 0    | 65     |   0.0%                     | 0                       |
| 35   | 0    | 66     |   0.0%                     | 0                       |
| 36   | 0    | 67     |   0.0%                     | 0                       |
| 66   | 0    | 0      |   0.0%                     | 0                       |
| 69   | 0    | 0      |   0.0%                     | 0                       |
| 70   | 0    | 0      |   0.0%                     | 0                       |
| 71   | 0    | 4      |   0.0%                     | 0                       |
| 76   | 0    | 4      |   0.0%                     | 0                       |
| 78   | 0    | 4      |   0.0%                     | 0                       |
| 218  | 0    | 1      |   0.0%                     | 0                       |
| 232  | 0    | 2      |   0.0%                     | 0                       |
| 240  | 0    | 3      |   0.0%                     | 0                       |
===============================================================================
>/usr/bin/bcmcmd tm sched conn ing core=all
=========================================================================
|                  E2E Scheduler connections - Ingress                  |
=========================================================================
| VOQ ID | NOF VOQs | Core |      | Remote VOQ Connector | Remote Modid |
=========================================================================
| 32     | 8        | 0    | ---> | 40                   | 0            |
| 40     | 8        | 0    | ---> | 48                   | 0            |
| 48     | 8        | 0    | ---> | 56                   | 0            |
| 56     | 8        | 0    | ---> | 64                   | 0            |
| 64     | 8        | 0    | ---> | 72                   | 0            |
| 72     | 8        | 0    | ---> | 80                   | 0            |
| 80     | 8        | 0    | ---> | 88                   | 0            |
| 88     | 8        | 0    | ---> | 96                   | 0            |
| 96     | 8        | 0    | ---> | 104                  | 0            |
| 104    | 8        | 0    | ---> | 112                  | 0            |
| 112    | 8        | 0    | ---> | 120                  | 0            |
| 120    | 8        | 0    | ---> | 128                  | 0            |
| 128    | 8        | 0    | ---> | 136                  | 0            |
| 136    | 8        | 0    | ---> | 144                  | 0            |
| 144    | 8        | 0    | ---> | 152                  | 0            |
| 152    | 8        | 0    | ---> | 160                  | 0            |
| 160    | 8        | 0    | ---> | 168                  | 0            |
| 168    | 8        | 0    | ---> | 176                  | 0            |
| 176    | 8        | 0    | ---> | 184                  | 0            |
| 184    | 8        | 0    | ---> | 192                  | 0            |
| 192    | 8        | 0    | ---> | 200                  | 0            |
| 200    | 8        | 0    | ---> | 208                  | 0            |
| 208    | 8        | 0    | ---> | 216                  | 0            |
| 216    | 8        | 0    | ---> | 224                  | 0            |
| 224    | 8        | 0    | ---> | 232                  | 0            |
| 232    | 8        | 0    | ---> | 240                  | 0            |
| 240    | 8        | 0    | ---> | 248                  | 0            |
| 248    | 8        | 0    | ---> | 256                  | 0            |
| 256    | 8        | 0    | ---> | 264                  | 0            |
| 264    | 8        | 0    | ---> | 272                  | 0            |
| 272    | 8        | 0    | ---> | 280                  | 0            |
| 280    | 8        | 0    | ---> | 288                  | 0            |
| 288    | 8        | 0    | ---> | 296                  | 0            |
| 296    | 8        | 0    | ---> | 304                  | 0            |
| 304    | 8        | 0    | ---> | 312                  | 0            |
| 312    | 8        | 0    | ---> | 320                  | 0            |
| 504    | 8        | 0    | ---> | 32                   | 0            |
| 552    | 8        | 0    | ---> | 1072                 | 0            |
| 576    | 8        | 0    | ---> | 1096                 | 0            |
| 584    | 8        | 0    | ---> | 1104                 | 0            |
| 632    | 8        | 0    | ---> | 1152                 | 0            |
| 648    | 8        | 0    | ---> | 1168                 | 0            |
| 1768   | 8        | 0    | ---> | 3312                 | 0            |
| 1880   | 8        | 0    | ---> | 3424                 | 0            |
| 1944   | 8        | 0    | ---> | 3488                 | 0            |
| 2056   | 8        | 0    | ---> | 5616                 | 0            |
=========================================================================
>/usr/bin/bcmcmd tm sched conn egr core=all
================================================================================
|                      E2E Scheduler connections - Egress                      |
================================================================================
| VOQ Connector | NOF VOQ Connectors | Core | #    | Remote VOQ | Remote Modid |
================================================================================
| 32            | 8                  | 0    | ---> | 504        | 0            |
| 40            | 8                  | 0    | ---> | 32         | 0            |
| 48            | 8                  | 0    | ---> | 40         | 0            |
| 56            | 8                  | 0    | ---> | 48         | 0            |
| 64            | 8                  | 0    | ---> | 56         | 0            |
| 72            | 8                  | 0    | ---> | 64         | 0            |
| 80            | 8                  | 0    | ---> | 72         | 0            |
| 88            | 8                  | 0    | ---> | 80         | 0            |
| 96            | 8                  | 0    | ---> | 88         | 0            |
| 104           | 8                  | 0    | ---> | 96         | 0            |
| 112           | 8                  | 0    | ---> | 104        | 0            |
| 120           | 8                  | 0    | ---> | 112        | 0            |
| 128           | 8                  | 0    | ---> | 120        | 0            |
| 136           | 8                  | 0    | ---> | 128        | 0            |
| 144           | 8                  | 0    | ---> | 136        | 0            |
| 152           | 8                  | 0    | ---> | 144        | 0            |
| 160           | 8                  | 0    | ---> | 152        | 0            |
| 168           | 8                  | 0    | ---> | 160        | 0            |
| 176           | 8                  | 0    | ---> | 168        | 0            |
| 184           | 8                  | 0    | ---> | 176        | 0            |
| 192           | 8                  | 0    | ---> | 184        | 0            |
| 200           | 8                  | 0    | ---> | 192        | 0            |
| 208           | 8                  | 0    | ---> | 200        | 0            |
| 216           | 8                  | 0    | ---> | 208        | 0            |
| 224           | 8                  | 0    | ---> | 216        | 0            |
| 232           | 8                  | 0    | ---> | 224        | 0            |
| 240           | 8                  | 0    | ---> | 232        | 0            |
| 248           | 8                  | 0    | ---> | 240        | 0            |
| 256           | 8                  | 0    | ---> | 248        | 0            |
| 264           | 8                  | 0    | ---> | 256        | 0            |
| 272           | 8                  | 0    | ---> | 264        | 0            |
| 280           | 8                  | 0    | ---> | 272        | 0            |
| 288           | 8                  | 0    | ---> | 280        | 0            |
| 296           | 8                  | 0    | ---> | 288        | 0            |
| 304           | 8                  | 0    | ---> | 296        | 0            |
| 312           | 8                  | 0    | ---> | 304        | 0            |
| 320           | 8                  | 0    | ---> | 312        | 0            |
| 1072          | 8                  | 0    | ---> | 552        | 0            |
| 1096          | 8                  | 0    | ---> | 576        | 0            |
| 1104          | 8                  | 0    | ---> | 584        | 0            |
| 1152          | 8                  | 0    | ---> | 632        | 0            |
| 1168          | 8                  | 0    | ---> | 648        | 0            |
| 3312          | 8                  | 0    | ---> | 1768       | 0            |
| 3424          | 8                  | 0    | ---> | 1880       | 0            |
| 3488          | 8                  | 0    | ---> | 1944       | 0            |
| 5616          | 8                  | 0    | ---> | 2056       | 0            |
================================================================================
>/usr/bin/bcmcmd tm sched gport core=all
=======================================================================
|                             VOQs gport info                         |
=======================================================================
| TM gport   | NOF | Type                | Modid | FTMH PP DSP | Base |
|            | COS |                     |       |             | VOQ  |
=======================================================================
| 0x241c0020 | 8   | Unicast Queue Group | 0     | 1           | 32   |
| 0x241c0028 | 8   | Unicast Queue Group | 0     | 2           | 40   |
| 0x241c0030 | 8   | Unicast Queue Group | 0     | 3           | 48   |
| 0x241c0038 | 8   | Unicast Queue Group | 0     | 4           | 56   |
| 0x241c0040 | 8   | Unicast Queue Group | 0     | 5           | 64   |
| 0x241c0048 | 8   | Unicast Queue Group | 0     | 6           | 72   |
| 0x241c0050 | 8   | Unicast Queue Group | 0     | 7           | 80   |
| 0x241c0058 | 8   | Unicast Queue Group | 0     | 8           | 88   |
| 0x241c0060 | 8   | Unicast Queue Group | 0     | 9           | 96   |
| 0x241c0068 | 8   | Unicast Queue Group | 0     | 10          | 104  |
| 0x241c0070 | 8   | Unicast Queue Group | 0     | 11          | 112  |
| 0x241c0078 | 8   | Unicast Queue Group | 0     | 12          | 120  |
| 0x241c0080 | 8   | Unicast Queue Group | 0     | 13          | 128  |
| 0x241c0088 | 8   | Unicast Queue Group | 0     | 14          | 136  |
| 0x241c0090 | 8   | Unicast Queue Group | 0     | 15          | 144  |
| 0x241c0098 | 8   | Unicast Queue Group | 0     | 16          | 152  |
| 0x241c00a0 | 8   | Unicast Queue Group | 0     | 17          | 160  |
| 0x241c00a8 | 8   | Unicast Queue Group | 0     | 18          | 168  |
| 0x241c00b0 | 8   | Unicast Queue Group | 0     | 19          | 176  |
| 0x241c00b8 | 8   | Unicast Queue Group | 0     | 20          | 184  |
| 0x241c00c0 | 8   | Unicast Queue Group | 0     | 21          | 192  |
| 0x241c00c8 | 8   | Unicast Queue Group | 0     | 22          | 200  |
| 0x241c00d0 | 8   | Unicast Queue Group | 0     | 23          | 208  |
| 0x241c00d8 | 8   | Unicast Queue Group | 0     | 24          | 216  |
| 0x241c00e0 | 8   | Unicast Queue Group | 0     | 25          | 224  |
| 0x241c00e8 | 8   | Unicast Queue Group | 0     | 26          | 232  |
| 0x241c00f0 | 8   | Unicast Queue Group | 0     | 27          | 240  |
| 0x241c00f8 | 8   | Unicast Queue Group | 0     | 28          | 248  |
| 0x241c0100 | 8   | Unicast Queue Group | 0     | 29          | 256  |
| 0x241c0108 | 8   | Unicast Queue Group | 0     | 30          | 264  |
| 0x241c0110 | 8   | Unicast Queue Group | 0     | 31          | 272  |
| 0x241c0118 | 8   | Unicast Queue Group | 0     | 32          | 280  |
| 0x241c0120 | 8   | Unicast Queue Group | 0     | 33          | 288  |
| 0x241c0128 | 8   | Unicast Queue Group | 0     | 34          | 296  |
| 0x241c0130 | 8   | Unicast Queue Group | 0     | 35          | 304  |
| 0x241c0138 | 8   | Unicast Queue Group | 0     | 36          | 312  |
| 0x241c01f8 | 8   | Unicast Queue Group | 0     | 0           | 504  |
| 0x241c0228 | 8   | Unicast Queue Group | 0     | 66          | 552  |
| 0x241c0240 | 8   | Unicast Queue Group | 0     | 69          | 576  |
| 0x241c0248 | 8   | Unicast Queue Group | 0     | 70          | 584  |
| 0x241c0278 | 8   | Unicast Queue Group | 0     | 76          | 632  |
| 0x241c0288 | 8   | Unicast Queue Group | 0     | 78          | 648  |
| 0x241c06e8 | 8   | Unicast Queue Group | 0     | 218         | 1768 |
| 0x241c0758 | 8   | Unicast Queue Group | 0     | 232         | 1880 |
| 0x241c0798 | 8   | Unicast Queue Group | 0     | 240         | 1944 |
| 0x241c0808 | 8   | Unicast Queue Group | 0     | 66          | 2056 |
=======================================================================
=============================================================
|                       Flows gport info                    |
=============================================================
| Gport      | NOF | Type                    | Core | Flow  |
|            | COS |                         |      | ID    |
=============================================================
| 0xc4000020 | 8   | Scheduler VOQ Connector | 0    | 32    |
| 0xc4000028 | 8   | Scheduler VOQ Connector | 0    | 40    |
| 0xc4000030 | 8   | Scheduler VOQ Connector | 0    | 48    |
| 0xc4000038 | 8   | Scheduler VOQ Connector | 0    | 56    |
| 0xc4000040 | 8   | Scheduler VOQ Connector | 0    | 64    |
| 0xc4000048 | 8   | Scheduler VOQ Connector | 0    | 72    |
| 0xc4000050 | 8   | Scheduler VOQ Connector | 0    | 80    |
| 0xc4000058 | 8   | Scheduler VOQ Connector | 0    | 88    |
| 0xc4000060 | 8   | Scheduler VOQ Connector | 0    | 96    |
| 0xc4000068 | 8   | Scheduler VOQ Connector | 0    | 104   |
| 0xc4000070 | 8   | Scheduler VOQ Connector | 0    | 112   |
| 0xc4000078 | 8   | Scheduler VOQ Connector | 0    | 120   |
| 0xc4000080 | 8   | Scheduler VOQ Connector | 0    | 128   |
| 0xc4000088 | 8   | Scheduler VOQ Connector | 0    | 136   |
| 0xc4000090 | 8   | Scheduler VOQ Connector | 0    | 144   |
| 0xc4000098 | 8   | Scheduler VOQ Connector | 0    | 152   |
| 0xc40000a0 | 8   | Scheduler VOQ Connector | 0    | 160   |
| 0xc40000a8 | 8   | Scheduler VOQ Connector | 0    | 168   |
| 0xc40000b0 | 8   | Scheduler VOQ Connector | 0    | 176   |
| 0xc40000b8 | 8   | Scheduler VOQ Connector | 0    | 184   |
| 0xc40000c0 | 8   | Scheduler VOQ Connector | 0    | 192   |
| 0xc40000c8 | 8   | Scheduler VOQ Connector | 0    | 200   |
| 0xc40000d0 | 8   | Scheduler VOQ Connector | 0    | 208   |
| 0xc40000d8 | 8   | Scheduler VOQ Connector | 0    | 216   |
| 0xc40000e0 | 8   | Scheduler VOQ Connector | 0    | 224   |
| 0xc40000e8 | 8   | Scheduler VOQ Connector | 0    | 232   |
| 0xc40000f0 | 8   | Scheduler VOQ Connector | 0    | 240   |
| 0xc40000f8 | 8   | Scheduler VOQ Connector | 0    | 248   |
| 0xc4000100 | 8   | Scheduler VOQ Connector | 0    | 256   |
| 0xc4000108 | 8   | Scheduler VOQ Connector | 0    | 264   |
| 0xc4000110 | 8   | Scheduler VOQ Connector | 0    | 272   |
| 0xc4000118 | 8   | Scheduler VOQ Connector | 0    | 280   |
| 0xc4000120 | 8   | Scheduler VOQ Connector | 0    | 288   |
| 0xc4000128 | 8   | Scheduler VOQ Connector | 0    | 296   |
| 0xc4000130 | 8   | Scheduler VOQ Connector | 0    | 304   |
| 0xc4000138 | 8   | Scheduler VOQ Connector | 0    | 312   |
| 0xc4000140 | 8   | Scheduler VOQ Connector | 0    | 320   |
| 0xc4000430 | 8   | Scheduler VOQ Connector | 0    | 1072  |
| 0xc4000448 | 8   | Scheduler VOQ Connector | 0    | 1096  |
| 0xc4000450 | 8   | Scheduler VOQ Connector | 0    | 1104  |
| 0xc4000480 | 8   | Scheduler VOQ Connector | 0    | 1152  |
| 0xc4000490 | 8   | Scheduler VOQ Connector | 0    | 1168  |
| 0xc4000cf0 | 8   | Scheduler VOQ Connector | 0    | 3312  |
| 0xc4000d60 | 8   | Scheduler VOQ Connector | 0    | 3424  |
| 0xc4000da0 | 8   | Scheduler VOQ Connector | 0    | 3488  |
| 0xc40015f0 | 8   | Scheduler VOQ Connector | 0    | 5616  |
| 0x3400b801 | 1   | Scheduler HR            | 0    | 47105 |
| 0x3400b805 | 1   | Scheduler HR            | 0    | 47109 |
| 0x3400b809 | 1   | Scheduler HR            | 0    | 47113 |
| 0x3400b80d | 1   | Scheduler HR            | 0    | 47117 |
| 0x3400b811 | 1   | Scheduler HR            | 0    | 47121 |
| 0x3400b815 | 1   | Scheduler HR            | 0    | 47125 |
| 0x3400b821 | 1   | Scheduler HR            | 0    | 47137 |
| 0x3400b825 | 1   | Scheduler HR            | 0    | 47141 |
| 0x3400b829 | 1   | Scheduler HR            | 0    | 47145 |
| 0x3400b82d | 1   | Scheduler HR            | 0    | 47149 |
| 0x3400b831 | 1   | Scheduler HR            | 0    | 47153 |
| 0x3400b835 | 1   | Scheduler HR            | 0    | 47157 |
| 0x3400b839 | 1   | Scheduler HR            | 0    | 47161 |
| 0x3400b83d | 1   | Scheduler HR            | 0    | 47165 |
| 0x3400b841 | 1   | Scheduler HR            | 0    | 47169 |
| 0x3400b845 | 1   | Scheduler HR            | 0    | 47173 |
| 0x3400b849 | 1   | Scheduler HR            | 0    | 47177 |
| 0x3400b84d | 1   | Scheduler HR            | 0    | 47181 |
| 0x3400b851 | 1   | Scheduler HR            | 0    | 47185 |
| 0x3400b855 | 1   | Scheduler HR            | 0    | 47189 |
| 0x3400b859 | 1   | Scheduler HR            | 0    | 47193 |
| 0x3400b85d | 1   | Scheduler HR            | 0    | 47197 |
| 0x3400b861 | 1   | Scheduler HR            | 0    | 47201 |
| 0x3400b865 | 1   | Scheduler HR            | 0    | 47205 |
| 0x3400b869 | 1   | Scheduler HR            | 0    | 47209 |
| 0x3400b86d | 1   | Scheduler HR            | 0    | 47213 |
| 0x3400b871 | 1   | Scheduler HR            | 0    | 47217 |
| 0x3400b875 | 1   | Scheduler HR            | 0    | 47221 |
| 0x3400b879 | 1   | Scheduler HR            | 0    | 47225 |
| 0x3400b87d | 1   | Scheduler HR            | 0    | 47229 |
| 0x3400b881 | 1   | Scheduler HR            | 0    | 47233 |
| 0x3400b885 | 1   | Scheduler HR            | 0    | 47237 |
| 0x3400b889 | 1   | Scheduler HR            | 0    | 47241 |
| 0x3400b88d | 1   | Scheduler HR            | 0    | 47245 |
| 0x3400b891 | 1   | Scheduler HR            | 0    | 47249 |
| 0x3400b895 | 1   | Scheduler HR            | 0    | 47253 |
| 0x3400b899 | 1   | Scheduler HR            | 0    | 47257 |
| 0x3400b89d | 1   | Scheduler HR            | 0    | 47261 |
| 0x3400b8a1 | 1   | Scheduler HR            | 0    | 47265 |
| 0x3400b8a5 | 1   | Scheduler HR            | 0    | 47269 |
| 0x3400b8a9 | 1   | Scheduler HR            | 0    | 47273 |
| 0x3400b8ad | 1   | Scheduler HR            | 0    | 47277 |
| 0x3400b8b1 | 1   | Scheduler HR            | 0    | 47281 |
| 0x3400b8b5 | 1   | Scheduler HR            | 0    | 47285 |
| 0x3400b8b9 | 1   | Scheduler HR            | 0    | 47289 |
| 0x3400b8bd | 1   | Scheduler HR            | 0    | 47293 |
| 0x3400b8c1 | 1   | Scheduler HR            | 0    | 47297 |
| 0x3400b8c5 | 1   | Scheduler HR            | 0    | 47301 |
| 0x3400b8c9 | 1   | Scheduler HR            | 0    | 47305 |
| 0x3400b8cd | 1   | Scheduler HR            | 0    | 47309 |
| 0x3400b8d1 | 1   | Scheduler HR            | 0    | 47313 |
| 0x3400b8d5 | 1   | Scheduler HR            | 0    | 47317 |
| 0x3400b8d9 | 1   | Scheduler HR            | 0    | 47321 |
| 0x3400b8dd | 1   | Scheduler HR            | 0    | 47325 |
| 0x3400b8e1 | 1   | Scheduler HR            | 0    | 47329 |
| 0x3400b8e5 | 1   | Scheduler HR            | 0    | 47333 |
| 0x3400b8e9 | 1   | Scheduler HR            | 0    | 47337 |
| 0x3400b8ed | 1   | Scheduler HR            | 0    | 47341 |
| 0x3400b8f1 | 1   | Scheduler HR            | 0    | 47345 |
| 0x3400b8f5 | 1   | Scheduler HR            | 0    | 47349 |
| 0x3400b8f9 | 1   | Scheduler HR            | 0    | 47353 |
| 0x3400b8fd | 1   | Scheduler HR            | 0    | 47357 |
| 0x3400b901 | 1   | Scheduler HR            | 0    | 47361 |
| 0x3400b905 | 1   | Scheduler HR            | 0    | 47365 |
| 0x3400b909 | 1   | Scheduler HR            | 0    | 47369 |
| 0x3400b90d | 1   | Scheduler HR            | 0    | 47373 |
| 0x3400b911 | 1   | Scheduler HR            | 0    | 47377 |
| 0x3400b915 | 1   | Scheduler HR            | 0    | 47381 |
| 0x3400b919 | 1   | Scheduler HR            | 0    | 47385 |
| 0x3400b91d | 1   | Scheduler HR            | 0    | 47389 |
| 0x3400b921 | 1   | Scheduler HR            | 0    | 47393 |
| 0x3400b925 | 1   | Scheduler HR            | 0    | 47397 |
| 0x3400b929 | 1   | Scheduler HR            | 0    | 47401 |
| 0x3400b92d | 1   | Scheduler HR            | 0    | 47405 |
| 0x3400b931 | 1   | Scheduler HR            | 0    | 47409 |
| 0x3400b935 | 1   | Scheduler HR            | 0    | 47413 |
| 0x3400b939 | 1   | Scheduler HR            | 0    | 47417 |
| 0x3400b93d | 1   | Scheduler HR            | 0    | 47421 |
| 0x3400b941 | 1   | Scheduler HR            | 0    | 47425 |
| 0x3400b945 | 1   | Scheduler HR            | 0    | 47429 |
| 0x3400b949 | 1   | Scheduler HR            | 0    | 47433 |
| 0x3400b94d | 1   | Scheduler HR            | 0    | 47437 |
| 0x3400b951 | 1   | Scheduler HR            | 0    | 47441 |
| 0x3400b955 | 1   | Scheduler HR            | 0    | 47445 |
| 0x3400b959 | 1   | Scheduler HR            | 0    | 47449 |
| 0x3400b95d | 1   | Scheduler HR            | 0    | 47453 |
| 0x3400b961 | 1   | Scheduler HR            | 0    | 47457 |
| 0x3400b965 | 1   | Scheduler HR            | 0    | 47461 |
| 0x3400b969 | 1   | Scheduler HR            | 0    | 47465 |
| 0x3400b96d | 1   | Scheduler HR            | 0    | 47469 |
| 0x3400b971 | 1   | Scheduler HR            | 0    | 47473 |
| 0x3400b975 | 1   | Scheduler HR            | 0    | 47477 |
| 0x3400b981 | 1   | Scheduler HR            | 0    | 47489 |
| 0x3400b985 | 1   | Scheduler HR            | 0    | 47493 |
| 0x3400b989 | 1   | Scheduler HR            | 0    | 47497 |
| 0x3400b98d | 1   | Scheduler HR            | 0    | 47501 |
| 0x3400b9a1 | 1   | Scheduler HR            | 0    | 47521 |
| 0x3400b9a5 | 1   | Scheduler HR            | 0    | 47525 |
=============================================================
>/usr/bin/bcmcmd tm sched group band core=all
=====================================
| Core 0 - Current BandWidth [Kbps] |
=====================================
| Group 0 | Group 1 | Group 2       |
=====================================
| 10362   | 26980   | 64246         |
=====================================
>/usr/bin/bcmcmd tm snif all enabled_only=1 core=all
================================================================
|      Showing TM attributes of Snoop command(profile) 1       |
================================================================
| ATTRIBUTES                                      | CORE 0     |
================================================================
| Ingress Attributes:                             |            |
----------------------------------------------------------------
| Destination                                     | 0xc0042    |
| LAG Load Balancing Key Overwrite                | 0x0        |
| LAG Load Balancing Key                          | 0x0        |
| Traffic Class Overwrite                         | 0x1        |
| Traffic Class                                   | 0x4        |
| Drop Precedence Overwrite                       | 0x0        |
| Drop Precedence                                 | 0x0        |
| Crop enabled                                    | 0x0        |
| Drop Snif if forward copy is dropped            | 0x0        |
| Drop forward copy if Snif is dropped            | 0x0        |
| In PP Port Overwrite                            | 0x0        |
| In PP Port                                      | 0x0        |
| ST VSQ pointer Overwrite                        | 0x0        |
| ST VSQ pointer                                  | 0x0        |
| Admit Profile Overwrite                         | 0x0        |
| Admit Profile                                   | 0x0        |
| Snif Probability                                | 0xffffff   |
| DSP Ext Destination                             | 0x0        |
| DSP Ext Destination Stamp Enable                | 0x0        |
| Remove System Headers                           | 0x0        |
| Keerp Incoming System Headers                   | 0x0        |
| SNIF Append Mode                                | 0x0        |
| TM Action Type                                  | 0x1        |
| TM Action Type Mask                             | 0x3        |
| Is Multicast                                    | 0x0        |
| Is Multicast Mask                               | 0x1        |
| Multicast Outlif                                | 0x0        |
| Multicast Outlif Mask                           | 0x0        |
| FTMH Stacking Ext Offset                        | 0x0        |
| Application Ext Stamp Enable                    | 0x0        |
| Application Ext Offset                          | 0x0        |
| Application Ext Type                            | 0x0        |
----------------------------------------------------------------
| Egress Attributes:                              |            |
----------------------------------------------------------------
| Enable                                          | 0x1        |
| Snif Egress Probability                         | 0xffffffff |
| Snif Recycle Priority                           | 0x1        |
| Append original headers to Snif copy            | 0x0        |
| Snif Crop Enabled                               | 0x0        |
| Snif Recycle command                            | 0x1        |
| Snoop Strength                                  | 0x3        |
----------------------------------------------------------------
| Counting Attributes:                            |            |
----------------------------------------------------------------
| External Stat Data Valid Overwrite              | 0x0        |
| External Stat Data Valid                        | 0x0        |
| External Stat Data Opcode Overwrite             | 0x0        |
| External Stat Data Opcode type id for stat id 0 | 0x0        |
| External Stat Data Opcode type id for stat id 1 | 0x0        |
| External Stat Data Opcode type id for stat id 2 | 0x0        |
| External Stat Data Opcode type id for stat id 3 | 0x0        |
| External Stat Data Overwrite                    | 0x0        |
| External Stat Data ID 0                         | 0x0        |
| External Stat Data ID 1                         | 0x0        |
| External Stat Data ID 2                         | 0x0        |
| External Stat Data ID 3                         | 0x0        |
| Internal Stat Object Valid Overwrite            | 0x0        |
| Internal Stat Object Valid                      | 0x0        |
| Internal Stat Object ID Overwrite               | 0x0        |
| Internal Stat Object ID                         | 0x0        |
| Internal Stat Object Type Overwrite             | 0x0        |
| Internal Stat Object Type                       | 0x0        |
| Internal Stat Object Meta Data Overwrite        | 0x0        |
| Internal Stat Object Meta Data                  | 0x0        |
================================================================
======================================================================================================================
|                                 Showing TM attributes of Snoop command(profile) 2                                  |
======================================================================================================================
| ATTRIBUTES                                      | CORE 0                                                           |
======================================================================================================================
| Ingress Attributes:                             |                                                                  |
----------------------------------------------------------------------------------------------------------------------
| Destination                                     | 0xc0042                                                          |
| LAG Load Balancing Key Overwrite                | 0x0                                                              |
| LAG Load Balancing Key                          | 0x0                                                              |
| Traffic Class Overwrite                         | 0x0                                                              |
| Traffic Class                                   | 0x0                                                              |
| Drop Precedence Overwrite                       | 0x0                                                              |
| Drop Precedence                                 | 0x0                                                              |
| Crop enabled                                    | 0x0                                                              |
| Drop Snif if forward copy is dropped            | 0x0                                                              |
| Drop forward copy if Snif is dropped            | 0x0                                                              |
| In PP Port Overwrite                            | 0x0                                                              |
| In PP Port                                      | 0x0                                                              |
| ST VSQ pointer Overwrite                        | 0x0                                                              |
| ST VSQ pointer                                  | 0x0                                                              |
| Admit Profile Overwrite                         | 0x0                                                              |
| Admit Profile                                   | 0x0                                                              |
| Snif Probability                                | 0xffffff                                                         |
| DSP Ext Destination                             | 0x0                                                              |
| DSP Ext Destination Stamp Enable                | 0x0                                                              |
| Remove System Headers                           | 0x1                                                              |
| Keerp Incoming System Headers                   | 0x0                                                              |
| SNIF Append Mode                                | 0x1                                                              |
| New System Header                               | 0000002100080000026000000000000000000000000000000007fa0002000000 |
|                                                 | 000000000000000000000000000000000000000000000000                 |
| Header Size                                     | 0x23                                                             |
| PPH FHEI Ext Stamp Enable                       | 0x1                                                              |
| PPH FHEI Ext Offset                             | 0x22                                                             |
| TM Action Type                                  | 0x0                                                              |
| TM Action Type Mask                             | 0x0                                                              |
| Is Multicast                                    | 0x0                                                              |
| Is Multicast Mask                               | 0x0                                                              |
| Multicast Outlif                                | 0x0                                                              |
| Multicast Outlif Mask                           | 0x0                                                              |
| FTMH Stacking Ext Offset                        | 0x0                                                              |
| Application Ext Stamp Enable                    | 0x0                                                              |
| Application Ext Offset                          | 0x0                                                              |
| Application Ext Type                            | 0x0                                                              |
----------------------------------------------------------------------------------------------------------------------
| Egress Attributes:                              |                                                                  |
----------------------------------------------------------------------------------------------------------------------
| Enable                                          | 0x1                                                              |
| Snif Egress Probability                         | 0xffffffff                                                       |
| Snif Recycle Priority                           | 0x1                                                              |
| Append original headers to Snif copy            | 0x1                                                              |
| Snif Crop Enabled                               | 0x0                                                              |
| Snif Recycle command                            | 0x2                                                              |
| Snoop Strength                                  | 0x3                                                              |
----------------------------------------------------------------------------------------------------------------------
| Counting Attributes:                            |                                                                  |
----------------------------------------------------------------------------------------------------------------------
| External Stat Data Valid Overwrite              | 0x0                                                              |
| External Stat Data Valid                        | 0x0                                                              |
| External Stat Data Opcode Overwrite             | 0x0                                                              |
| External Stat Data Opcode type id for stat id 0 | 0x0                                                              |
| External Stat Data Opcode type id for stat id 1 | 0x0                                                              |
| External Stat Data Opcode type id for stat id 2 | 0x0                                                              |
| External Stat Data Opcode type id for stat id 3 | 0x0                                                              |
| External Stat Data Overwrite                    | 0x0                                                              |
| External Stat Data ID 0                         | 0x0                                                              |
| External Stat Data ID 1                         | 0x0                                                              |
| External Stat Data ID 2                         | 0x0                                                              |
| External Stat Data ID 3                         | 0x0                                                              |
| Internal Stat Object Valid Overwrite            | 0x0                                                              |
| Internal Stat Object Valid                      | 0x0                                                              |
| Internal Stat Object ID Overwrite               | 0x0                                                              |
| Internal Stat Object ID                         | 0x0                                                              |
| Internal Stat Object Type Overwrite             | 0x0                                                              |
| Internal Stat Object Type                       | 0x0                                                              |
| Internal Stat Object Meta Data Overwrite        | 0x0                                                              |
| Internal Stat Object Meta Data                  | 0x0                                                              |
======================================================================================================================
================================================================
|      Showing TM attributes of Snoop command(profile) 4       |
================================================================
| ATTRIBUTES                                      | CORE 0     |
================================================================
| Ingress Attributes:                             |            |
----------------------------------------------------------------
| Destination                                     | 0xc0042    |
| LAG Load Balancing Key Overwrite                | 0x0        |
| LAG Load Balancing Key                          | 0x0        |
| Traffic Class Overwrite                         | 0x1        |
| Traffic Class                                   | 0x4        |
| Drop Precedence Overwrite                       | 0x0        |
| Drop Precedence                                 | 0x0        |
| Crop enabled                                    | 0x0        |
| Drop Snif if forward copy is dropped            | 0x0        |
| Drop forward copy if Snif is dropped            | 0x0        |
| In PP Port Overwrite                            | 0x0        |
| In PP Port                                      | 0x0        |
| ST VSQ pointer Overwrite                        | 0x0        |
| ST VSQ pointer                                  | 0x0        |
| Admit Profile Overwrite                         | 0x0        |
| Admit Profile                                   | 0x0        |
| Snif Probability                                | 0xffffff   |
| DSP Ext Destination                             | 0x0        |
| DSP Ext Destination Stamp Enable                | 0x0        |
| Remove System Headers                           | 0x0        |
| Keerp Incoming System Headers                   | 0x0        |
| SNIF Append Mode                                | 0x0        |
| TM Action Type                                  | 0x1        |
| TM Action Type Mask                             | 0x3        |
| Is Multicast                                    | 0x0        |
| Is Multicast Mask                               | 0x1        |
| Multicast Outlif                                | 0x0        |
| Multicast Outlif Mask                           | 0x0        |
| FTMH Stacking Ext Offset                        | 0x0        |
| Application Ext Stamp Enable                    | 0x0        |
| Application Ext Offset                          | 0x0        |
| Application Ext Type                            | 0x0        |
----------------------------------------------------------------
| Egress Attributes:                              |            |
----------------------------------------------------------------
| Enable                                          | 0x1        |
| Snif Egress Probability                         | 0xffffffff |
| Snif Recycle Priority                           | 0x1        |
| Append original headers to Snif copy            | 0x0        |
| Snif Crop Enabled                               | 0x0        |
| Snif Recycle command                            | 0x4        |
| Snoop Strength                                  | 0x3        |
----------------------------------------------------------------
| Counting Attributes:                            |            |
----------------------------------------------------------------
| External Stat Data Valid Overwrite              | 0x0        |
| External Stat Data Valid                        | 0x0        |
| External Stat Data Opcode Overwrite             | 0x0        |
| External Stat Data Opcode type id for stat id 0 | 0x0        |
| External Stat Data Opcode type id for stat id 1 | 0x0        |
| External Stat Data Opcode type id for stat id 2 | 0x0        |
| External Stat Data Opcode type id for stat id 3 | 0x0        |
| External Stat Data Overwrite                    | 0x0        |
| External Stat Data ID 0                         | 0x0        |
| External Stat Data ID 1                         | 0x0        |
| External Stat Data ID 2                         | 0x0        |
| External Stat Data ID 3                         | 0x0        |
| Internal Stat Object Valid Overwrite            | 0x0        |
| Internal Stat Object Valid                      | 0x0        |
| Internal Stat Object ID Overwrite               | 0x0        |
| Internal Stat Object ID                         | 0x0        |
| Internal Stat Object Type Overwrite             | 0x0        |
| Internal Stat Object Type                       | 0x0        |
| Internal Stat Object Meta Data Overwrite        | 0x0        |
| Internal Stat Object Meta Data                  | 0x0        |
================================================================
==============================================================
|     Showing TM attributes of Snoop command(profile) 12     |
==============================================================
| ATTRIBUTES                                      | CORE 0   |
==============================================================
| Ingress Attributes:                             |          |
--------------------------------------------------------------
| Destination                                     | 0xc0042  |
| LAG Load Balancing Key Overwrite                | 0x0      |
| LAG Load Balancing Key                          | 0x0      |
| Traffic Class Overwrite                         | 0x1      |
| Traffic Class                                   | 0x4      |
| Drop Precedence Overwrite                       | 0x0      |
| Drop Precedence                                 | 0x0      |
| Crop enabled                                    | 0x0      |
| Drop Snif if forward copy is dropped            | 0x0      |
| Drop forward copy if Snif is dropped            | 0x0      |
| In PP Port Overwrite                            | 0x0      |
| In PP Port                                      | 0x0      |
| ST VSQ pointer Overwrite                        | 0x0      |
| ST VSQ pointer                                  | 0x0      |
| Admit Profile Overwrite                         | 0x0      |
| Admit Profile                                   | 0x0      |
| Snif Probability                                | 0xffffff |
| DSP Ext Destination                             | 0x0      |
| DSP Ext Destination Stamp Enable                | 0x0      |
| Remove System Headers                           | 0x0      |
| Keerp Incoming System Headers                   | 0x0      |
| SNIF Append Mode                                | 0x0      |
| TM Action Type                                  | 0x1      |
| TM Action Type Mask                             | 0x3      |
| Is Multicast                                    | 0x0      |
| Is Multicast Mask                               | 0x1      |
| Multicast Outlif                                | 0x0      |
| Multicast Outlif Mask                           | 0x0      |
| FTMH Stacking Ext Offset                        | 0x0      |
| Application Ext Stamp Enable                    | 0x0      |
| Application Ext Offset                          | 0x0      |
| Application Ext Type                            | 0x0      |
--------------------------------------------------------------
| Counting Attributes:                            |          |
--------------------------------------------------------------
| External Stat Data Valid Overwrite              | 0x0      |
| External Stat Data Valid                        | 0x0      |
| External Stat Data Opcode Overwrite             | 0x0      |
| External Stat Data Opcode type id for stat id 0 | 0x0      |
| External Stat Data Opcode type id for stat id 1 | 0x0      |
| External Stat Data Opcode type id for stat id 2 | 0x0      |
| External Stat Data Opcode type id for stat id 3 | 0x0      |
| External Stat Data Overwrite                    | 0x0      |
| External Stat Data ID 0                         | 0x0      |
| External Stat Data ID 1                         | 0x0      |
| External Stat Data ID 2                         | 0x0      |
| External Stat Data ID 3                         | 0x0      |
| Internal Stat Object Valid Overwrite            | 0x0      |
| Internal Stat Object Valid                      | 0x0      |
| Internal Stat Object ID Overwrite               | 0x0      |
| Internal Stat Object ID                         | 0x0      |
| Internal Stat Object Type Overwrite             | 0x0      |
| Internal Stat Object Type                       | 0x0      |
| Internal Stat Object Meta Data Overwrite        | 0x0      |
| Internal Stat Object Meta Data                  | 0x0      |
==============================================================
>/usr/bin/bcmcmd show int
======================================================================================================
|                                                        Interrupt                                   |
======================================================================================================
| Interrupt Name#                                               | ID   | UnMask(Enable) | On | Count |
======================================================================================================
| SPB_REASSEMBLY_ReassemblyErrorGeneralMop[0]                   | 102  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesHeaderSizeErrInt[0]                            | 145  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesQualifierSizeErrInt2[0]                        | 152  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesQualifierSizeErrInt3[0]                        | 153  | 0              | 1  | 0     |
| ETPPA_ETPPA_PesQualifierSizeErrInt4[0]                        | 154  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_SrcEqualDestInt[0]                          | 190  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesHeaderSizeErrInt[0]                    | 235  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt2[0]                | 249  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt3[0]                | 250  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt4[0]                | 251  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_PesQualifierSizeErrInt5[0]                | 252  | 0              | 1  | 0     |
| ERPP_ERPP_DISCARD_2_DiscardInt[0]                             | 255  | 0              | 1  | 0     |
| TCAM_TcamQueryFailureValid[0]                                 | 322  | 0              | 1  | 0     |
| IPPE_QualifierSizeError2[0]                                   | 430  | 0              | 1  | 0     |
| IPPE_QualifierSizeError7[0]                                   | 435  | 0              | 1  | 0     |
| IPPE_QualifierSizeError8[0]                                   | 436  | 0              | 1  | 0     |
| IPPE_QualifierSizeError9[0]                                   | 437  | 0              | 1  | 0     |
| IPPE_QualifierSizeError10[0]                                  | 438  | 0              | 1  | 0     |
| IPPE_QualifierSizeError11[0]                                  | 439  | 0              | 1  | 0     |
| CDU_TxFifoOverflowInt[0]                                      | 453  | 0              | 1  | 0     |
| CDU_TxFifoOverflowInt[1]                                      | 453  | 0              | 1  | 0     |
| SCH_SmpFullLevel1[0]                                          | 657  | 0              | 1  | 0     |
| ETPPB_ETPPB_PortMtuTrapInt[0]                                 | 679  | 0              | 1  | 0     |
| ETPPB_BTC_PopBeforeFifoReady[0]                               | 691  | 0              | 1  | 0     |
| IRE_NIF_ERROR_NifErrDataArrived[0]                            | 914  | 0              | 1  | 0     |
| IPPD_SameInteraceInt[0]                                       | 987  | 0              | 1  | 0     |
| ECGM_DroppedUcPdInt[0]                                        | 1038 | 0              | 1  | 0     |
| CRPS_DMA_0_FULLNESS_Dma0NotEmptyEvent[0]                      | 1186 | 0              | 1  | 0     |
| CRPS_DMA_1_FULLNESS_Dma1NotEmptyEvent[0]                      | 1189 | 0              | 1  | 0     |
| CLU_TxFifoOverflowInt[0]                                      | 1303 | 0              | 1  | 0     |
| CLU_TxFifoOverflowInt[1]                                      | 1303 | 0              | 1  | 0     |
| CLU_TxFifoOverflowInt[2]                                      | 1303 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_0[0] | 1313 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_1[0] | 1314 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_4[0] | 1317 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_5[0] | 1318 | 0              | 1  | 0     |
| CLU_LINK_STATUS_CHANGE_LinkStatusChangeInterruptRegister_7[2] | 1320 | 0              | 1  | 0     |
| MDB_Lem_EmpPulseScanDone[0]                                   | 1434 | 0              | 1  | 0     |
======================================================================================================
>/usr/bin/bcmcmd show counter full
=========================================================================================================
|                                                Full counters                                          |
=========================================================================================================
| Port  | Counter Name                           | Counter Value      | Diff from last call | Rate      |
=========================================================================================================
| eth1  | RX 64-byte frame                       | 34,789,544         | 34,789,544          | 0         |
| eth1  | RX 65 to 127 byte frame                | 8,124,312,035      | 8,124,312,035       | 724       |
| eth1  | RX 128 to 255 byte frame               | 811,521,006        | 811,521,006         | 73        |
| eth1  | RX 256 to 511 byte frame               | 782,384,725        | 782,384,725         | 53        |
| eth1  | RX 512 to 1023 byte frame              | 340,941,881        | 340,941,881         | 77        |
| eth1  | RX 1024 to 1518 byte frame             | 1,776,611,388      | 1,776,611,388       | 391       |
| eth1  | RX 1519 to 1522 byte frame             | 530,468,392        | 530,468,392         | 2         |
| eth1  | RX 1519 to 2047 byte frame             | 530,468,392        | 530,468,392         | 2         |
| eth1  | RX BC frame                            | 5,928,100          | 5,928,100           | 0         |
| eth1  | RX RPROG0 frame                        | 6,390,129,039      | 6,390,129,039       | 405       |
| eth1  | RX RPROG1 frame                        | 1,018,123,290      | 1,018,123,290       | 276       |
| eth1  | RX RPROG2 frame                        | 598,755,221        | 598,755,221         | 26        |
| eth1  | RX RPROG3 frame                        | 152,094,029        | 152,094,029         | 18        |
| eth1  | RX all packets frame                   | 12,401,028,971     | 12,401,028,971      | 1,320     |
| eth1  | RX good frame                          | 12,401,018,116     | 12,401,018,116      | 1,320     |
| eth1  | RX UC frame                            | 12,383,673,539     | 12,383,673,539      | 1,320     |
| eth1  | RX MC frame                            | 11,416,477         | 11,416,477          | 0         |
| eth1  | RX out-of-range length frame           | 10,855             | 10,855              | 0         |
| eth1  | RX single and double VLAN tagged frame | 12,401,028,971     | 12,401,028,971      | 1,320     |
| eth1  | RX promiscuous frame                   | 11,853,205,156     | 11,853,205,156      | 1,318     |
| eth1  | TX 64-byte frame                       | 357,342,748        | 357,342,748         | 26        |
| eth1  | TX 65 to 127 byte frame                | 3,465,096,665      | 3,465,096,665       | 576       |
| eth1  | TX 128 to 255 byte frame               | 364,726,689        | 364,726,689         | 65        |
| eth1  | TX 256 to 511 byte frame               | 279,255,688        | 279,255,688         | 103       |
| eth1  | TX 512 to 1023 byte frame              | 397,289,195        | 397,289,195         | 296       |
| eth1  | TX 1024 to 1518 byte frame             | 11,760,196,109     | 11,760,196,109      | 403       |
| eth1  | TX 1519 to 1522 byte frame             | 8,534,427,593      | 8,534,427,593       | 333       |
| eth1  | TX 1519 to 2047 byte frame             | 8,534,427,593      | 8,534,427,593       | 333       |
| eth1  | TX Broadcast frame                     | 2,680,495          | 2,680,495           | 0         |
| eth1  | TX all packets frame                   | 25,158,334,687     | 25,158,334,687      | 1,802     |
| eth1  | TX good frame                          | 25,158,334,687     | 25,158,334,687      | 1,802     |
| eth1  | TX UC frame                            | 25,154,094,853     | 25,154,094,853      | 1,802     |
| eth1  | TX MC frame                            | 1,559,339          | 1,559,339           | 0         |
| eth1  | TX single and double VLAN tagged frame | 25,157,771,037     | 25,157,771,037      | 1,800     |
| eth1  | RX Byte frame                          | 4,663,754,494,184  | 4,663,754,494,184   | 714,173   |
| eth1  | TX Byte frame                          | 30,900,422,351,973 | 30,900,422,351,973  | 1,361,098 |
| eth2  | RX 64-byte frame                       | 30,294,197         | 30,294,197          | 0         |
| eth2  | RX 65 to 127 byte frame                | 3,590,461,196      | 3,590,461,196       | 138       |
| eth2  | RX 128 to 255 byte frame               | 360,584,177        | 360,584,177         | 111       |
| eth2  | RX 256 to 511 byte frame               | 127,436,183        | 127,436,183         | 2         |
| eth2  | RX 512 to 1023 byte frame              | 147,791,707        | 147,791,707         | 2         |
| eth2  | RX 1024 to 1518 byte frame             | 541,703,677        | 541,703,677         | 8         |
| eth2  | RX 1519 to 1522 byte frame             | 388,846,375        | 388,846,375         | 0         |
| eth2  | RX 1519 to 2047 byte frame             | 388,846,375        | 388,846,375         | 0         |
| eth2  | RX BC frame                            | 3,515,088          | 3,515,088           | 4         |
| eth2  | RX RPROG0 frame                        | 2,580,917,320      | 2,580,917,320       | 107       |
| eth2  | RX RPROG1 frame                        | 607,288,283        | 607,288,283         | 14        |
| eth2  | RX RPROG2 frame                        | 324,115,459        | 324,115,459         | 10        |
| eth2  | RX RPROG3 frame                        | 108,434,331        | 108,434,331         | 8         |
| eth2  | RX all packets frame                   | 5,187,117,513      | 5,187,117,513       | 262       |
| eth2  | RX good frame                          | 5,187,117,180      | 5,187,117,180       | 262       |
| eth2  | RX UC frame                            | 5,178,921,665      | 5,178,921,665       | 253       |
| eth2  | RX MC frame                            | 4,680,427          | 4,680,427           | 6         |
| eth2  | RX out-of-range length frame           | 333                | 333                 | 0         |
| eth2  | RX single and double VLAN tagged frame | 5,187,117,513      | 5,187,117,513       | 260       |
| eth2  | RX promiscuous frame                   | 4,790,075,290      | 4,790,075,290       | 251       |
| eth2  | TX 64-byte frame                       | 276,215,700        | 276,215,700         | 14        |
| eth2  | TX 65 to 127 byte frame                | 1,308,271,672      | 1,308,271,672       | 97        |
| eth2  | TX 128 to 255 byte frame               | 266,404,395        | 266,404,395         | 116       |
| eth2  | TX 256 to 511 byte frame               | 164,761,847        | 164,761,847         | 4         |
| eth2  | TX 512 to 1023 byte frame              | 205,262,655        | 205,262,655         | 2         |
| eth2  | TX 1024 to 1518 byte frame             | 5,718,230,877      | 5,718,230,877       | 10        |
| eth2  | TX 1519 to 1522 byte frame             | 3,781,927,073      | 3,781,927,073       | 134       |
| eth2  | TX 1519 to 2047 byte frame             | 3,781,927,073      | 3,781,927,073       | 134       |
| eth2  | TX Broadcast frame                     | 2,161,828          | 2,161,828           | 0         |
| eth2  | TX all packets frame                   | 11,721,074,219     | 11,721,074,219      | 377       |
| eth2  | TX good frame                          | 11,721,074,219     | 11,721,074,219      | 377       |
| eth2  | TX UC frame                            | 11,717,353,220     | 11,717,353,220      | 377       |
| eth2  | TX MC frame                            | 1,559,171          | 1,559,171           | 0         |
| eth2  | TX single and double VLAN tagged frame | 11,720,510,570     | 11,720,510,570      | 369       |
| eth2  | RX Byte frame                          | 1,823,823,936,947  | 1,823,823,936,947   | 44,790    |
| eth2  | TX Byte frame                          | 14,268,706,628,625 | 14,268,706,628,625  | 240,435   |
| eth3  | RX 64-byte frame                       | 64,321,847         | 64,321,847          | 49        |
| eth3  | RX 65 to 127 byte frame                | 8,762,553,479      | 8,762,553,479       | 1,160     |
| eth3  | RX 128 to 255 byte frame               | 805,156,145        | 805,156,145         | 185       |
| eth3  | RX 256 to 511 byte frame               | 616,247,340        | 616,247,340         | 112       |
| eth3  | RX 512 to 1023 byte frame              | 365,304,178        | 365,304,178         | 85        |
| eth3  | RX 1024 to 1518 byte frame             | 2,401,429,770      | 2,401,429,770       | 71        |
| eth3  | RX 1519 to 1522 byte frame             | 807,604,799        | 807,604,799         | 387       |
| eth3  | RX 1519 to 2047 byte frame             | 807,604,799        | 807,604,799         | 387       |
| eth3  | RX BC frame                            | 7,212,563          | 7,212,563           | 0         |
| eth3  | RX RPROG0 frame                        | 6,302,214,815      | 6,302,214,815       | 533       |
| eth3  | RX RPROG1 frame                        | 1,576,044,572      | 1,576,044,572       | 132       |
| eth3  | RX RPROG2 frame                        | 767,153,701        | 767,153,701         | 513       |
| eth3  | RX RPROG3 frame                        | 181,462,244        | 181,462,244         | 41        |
| eth3  | RX all packets frame                   | 13,822,617,564     | 13,822,617,564      | 2,058     |
| eth3  | RX good frame                          | 13,821,704,537     | 13,821,704,537      | 2,058     |
| eth3  | RX UC frame                            | 13,804,995,500     | 13,804,995,500      | 2,058     |
| eth3  | RX MC frame                            | 9,496,474          | 9,496,474           | 0         |
| eth3  | RX out-of-range length frame           | 913,027            | 913,027             | 0         |
| eth3  | RX single and double VLAN tagged frame | 13,822,617,564     | 13,822,617,564      | 2,054     |
| eth3  | RX promiscuous frame                   | 12,997,390,793     | 12,997,390,793      | 1,671     |
| eth3  | TX 64-byte frame                       | 632,242,744        | 632,242,744         | 87        |
| eth3  | TX 65 to 127 byte frame                | 3,748,015,578      | 3,748,015,578       | 868       |
| eth3  | TX 128 to 255 byte frame               | 652,648,568        | 652,648,568         | 71        |
| eth3  | TX 256 to 511 byte frame               | 445,424,141        | 445,424,141         | 34        |
| eth3  | TX 512 to 1023 byte frame              | 564,391,560        | 564,391,560         | 93        |
| eth3  | TX 1024 to 1518 byte frame             | 11,559,636,964     | 11,559,636,964      | 4,250     |
| eth3  | TX 1519 to 1522 byte frame             | 12,234,894,372     | 12,234,894,372      | 73        |
| eth3  | TX 1519 to 2047 byte frame             | 12,234,894,372     | 12,234,894,372      | 73        |
| eth3  | TX Broadcast frame                     | 2,590,214          | 2,590,214           | 0         |
| eth3  | TX all packets frame                   | 29,837,253,941     | 29,837,253,941      | 5,490     |
| eth3  | TX good frame                          | 29,837,253,942     | 29,837,253,942      | 5,491     |
| eth3  | TX UC frame                            | 29,833,104,442     | 29,833,104,442      | 5,493     |
| eth3  | TX MC frame                            | 1,559,287          | 1,559,287           | 0         |
| eth3  | TX single and double VLAN tagged frame | 29,836,690,336     | 29,836,690,336      | 5,549     |
| eth3  | RX Byte frame                          | 5,952,373,674,054  | 5,952,373,674,054   | 923,319   |
| eth3  | TX Byte frame                          | 36,191,032,191,638 | 36,191,032,191,638  | 5,840,913 |
| eth4  | RX 64-byte frame                       | 35,688,751         | 35,688,751          | 0         |
| eth4  | RX 65 to 127 byte frame                | 4,318,116,719      | 4,318,116,719       | 351       |
| eth4  | RX 128 to 255 byte frame               | 813,064,501        | 813,064,501         | 178       |
| eth4  | RX 256 to 511 byte frame               | 139,955,483        | 139,955,483         | 24        |
| eth4  | RX 512 to 1023 byte frame              | 173,956,138        | 173,956,138         | 22        |
| eth4  | RX 1024 to 1518 byte frame             | 1,808,248,210      | 1,808,248,210       | 124       |
| eth4  | RX 1519 to 1522 byte frame             | 290,163,589        | 290,163,589         | 4         |
| eth4  | RX 1519 to 2047 byte frame             | 290,163,589        | 290,163,589         | 4         |
| eth4  | RX BC frame                            | 4,657,238          | 4,657,238           | 2         |
| eth4  | RX RPROG0 frame                        | 2,977,739,842      | 2,977,739,842       | 300       |
| eth4  | RX RPROG1 frame                        | 643,277,555        | 643,277,555         | 22        |
| eth4  | RX RPROG2 frame                        | 348,329,144        | 348,329,144         | 10        |
| eth4  | RX RPROG3 frame                        | 384,458,929        | 384,458,929         | 18        |
| eth4  | RX all packets frame                   | 7,579,193,391      | 7,579,193,391       | 700       |
| eth4  | RX good frame                          | 7,576,349,332      | 7,576,349,332       | 700       |
| eth4  | RX UC frame                            | 7,566,525,803      | 7,566,525,803       | 699       |
| eth4  | RX MC frame                            | 5,166,291          | 5,166,291           | 0         |
| eth4  | RX out-of-range length frame           | 2,844,059          | 2,844,059           | 0         |
| eth4  | RX single and double VLAN tagged frame | 7,579,193,391      | 7,579,193,391       | 700       |
| eth4  | RX promiscuous frame                   | 7,276,362,214      | 7,276,362,214       | 695       |
| eth4  | TX 64-byte frame                       | 314,722,942        | 314,722,942         | 53        |
| eth4  | TX 65 to 127 byte frame                | 2,015,568,086      | 2,015,568,086       | 166       |
| eth4  | TX 128 to 255 byte frame               | 540,880,550        | 540,880,550         | 154       |
| eth4  | TX 256 to 511 byte frame               | 315,353,060        | 315,353,060         | 75        |
| eth4  | TX 512 to 1023 byte frame              | 501,855,382        | 501,855,382         | 85        |
| eth4  | TX 1024 to 1518 byte frame             | 4,950,783,191      | 4,950,783,191       | 8         |
| eth4  | TX 1519 to 1522 byte frame             | 5,276,665,661      | 5,276,665,661       | 669       |
| eth4  | TX 1519 to 2047 byte frame             | 5,276,665,661      | 5,276,665,661       | 669       |
| eth4  | TX Broadcast frame                     | 3,408,357          | 3,408,357           | 0         |
| eth4  | TX all packets frame                   | 13,915,828,873     | 13,915,828,873      | 1,208     |
| eth4  | TX good frame                          | 13,915,828,873     | 13,915,828,873      | 1,206     |
| eth4  | TX UC frame                            | 13,910,861,282     | 13,910,861,282      | 1,206     |
| eth4  | TX MC frame                            | 1,559,234          | 1,559,234           | 0         |
| eth4  | TX single and double VLAN tagged frame | 13,915,265,224     | 13,915,265,224      | 1,204     |
| eth4  | RX Byte frame                          | 3,733,588,702,030  | 3,733,588,702,030   | 267,026   |
| eth4  | TX Byte frame                          | 15,943,491,910,059 | 15,943,491,910,059  | 1,142,411 |
| eth32 | RX NIF BIP error count                 | 191                | 191                 | 0         |
| eth32 | RX 64-byte frame                       | 1,602,894,669      | 1,602,894,669       | 107       |
| eth32 | RX 65 to 127 byte frame                | 10,107,413,557     | 10,107,413,557      | 1,127     |
| eth32 | RX 128 to 255 byte frame               | 1,824,115,295      | 1,824,115,295       | 302       |
| eth32 | RX 256 to 511 byte frame               | 1,203,791,265      | 1,203,791,265       | 158       |
| eth32 | RX 512 to 1023 byte frame              | 1,668,798,968      | 1,668,798,968       | 288       |
| eth32 | RX 1024 to 1518 byte frame             | 33,988,845,319     | 33,988,845,319      | 4,017     |
| eth32 | RX 1519 to 1522 byte frame             | 29,827,914,941     | 29,827,914,941      | 584       |
| eth32 | RX 1519 to 2047 byte frame             | 29,827,916,162     | 29,827,916,162      | 584       |
| eth32 | RX BC frame                            | 25,916,373         | 25,916,373          | 4         |
| eth32 | RX RPROG0 frame                        | 8,567,018,614      | 8,567,018,614       | 870       |
| eth32 | RX RPROG1 frame                        | 875,097,111        | 875,097,111         | 105       |
| eth32 | RX RPROG2 frame                        | 762,367,866        | 762,367,866         | 99        |
| eth32 | RX RPROG3 frame                        | 1,505,824,635      | 1,505,824,635       | 158       |
| eth32 | RX all packets frame                   | 80,223,775,239     | 80,223,775,239      | 6,581     |
| eth32 | RX good frame                          | 80,223,772,263     | 80,223,772,263      | 6,583     |
| eth32 | RX UC frame                            | 80,192,269,648     | 80,192,269,648      | 6,581     |
| eth32 | RX MC frame                            | 5,586,243          | 5,586,243           | 0         |
| eth32 | RX FCS error frame                     | 2,969              | 2,969               | 0         |
| eth32 | RX code error frame                    | 210                | 210                 | 0         |
| eth32 | RX jabber frame                        | 8                  | 8                   | 0         |
| eth32 | RX single and double VLAN tagged frame | 80,199,856,035     | 80,199,856,035      | 6,591     |
| eth32 | RX promiscuous frame                   | 50,364,354,715     | 50,364,354,715      | 6,003     |
| eth32 | RX fragment frame                      | 2                  | 2                   | 0         |
| eth32 | RX RUNT frame                          | 6                  | 6                   | 0         |
| eth32 | TX 65 to 127 byte frame                | 24,678,693,517     | 24,678,693,517      | 1,667     |
| eth32 | TX 128 to 255 byte frame               | 2,592,727,605      | 2,592,727,605       | 373       |
| eth32 | TX 256 to 511 byte frame               | 1,662,054,505      | 1,662,054,505       | 128       |
| eth32 | TX 512 to 1023 byte frame              | 1,026,976,144      | 1,026,976,144       | 142       |
| eth32 | TX 1024 to 1518 byte frame             | 6,527,992,903      | 6,527,992,903       | 257       |
| eth32 | TX 1519 to 1522 byte frame             | 2,017,083,239      | 2,017,083,239       | 337       |
| eth32 | TX 1519 to 2047 byte frame             | 2,017,083,239      | 2,017,083,239       | 337       |
| eth32 | TX Broadcast frame                     | 21,563,276         | 21,563,276          | 0         |
| eth32 | TX all packets frame                   | 38,505,527,922     | 38,505,527,922      | 2,918     |
| eth32 | TX good frame                          | 38,505,527,922     | 38,505,527,922      | 2,918     |
| eth32 | TX UC frame                            | 38,448,802,677     | 38,448,802,677      | 2,918     |
| eth32 | TX MC frame                            | 35,161,969         | 35,161,969          | 0         |
| eth32 | TX single and double VLAN tagged frame | 38,504,964,206     | 38,504,964,206      | 2,918     |
| eth32 | RX Byte frame                          | 97,271,134,936,082 | 97,271,134,936,082  | 6,619,760 |
| eth32 | RX Runt Byte frame                     | 208                | 208                 | 0         |
| eth32 | TX Byte frame                          | 16,124,709,614,650 | 16,124,709,614,650  | 1,228,160 |
=========================================================================================================
>/usr/bin/bcmcmd show counter nz
#############
# NIF Ports #
#############
===============================================================================================
|                                             RX COUNTERS                                     |
===============================================================================================
| Port | snmpIfHCInUcastPkts | snmpIfInNUcastPkts | snmpIfInErrors | snmpEtherStatsRXNoErrors |
===============================================================================================
| 1    | 12,383,674,448      | 17,344,577         | 0              | 12,401,029,880           |
-----------------------------------------------------------------------------------------------
| 2    | 5,178,921,870       | 8,195,515          | 0              | 5,187,117,718            |
-----------------------------------------------------------------------------------------------
| 3    | 13,804,997,767      | 16,709,037         | 0              | 13,822,619,830           |
-----------------------------------------------------------------------------------------------
| 4    | 7,566,526,306       | 9,823,533          | 0              | 7,579,193,898            |
-----------------------------------------------------------------------------------------------
| 32   | 80,192,280,687      | 31,502,616         | 2,983          | 80,223,783,303           |
===============================================================================================
==================================================================================================
|                                               TX COUNTERS                                      |
==================================================================================================
| Port | snmpIfHCOutUcastPkts | snmpIfOutNUcastPkts | snmpIfOutErrors | snmpEtherStatsTXNoErrors |
==================================================================================================
| 1    | 25,154,097,059       | 4,239,834           | 0               | 25,158,336,893           |
--------------------------------------------------------------------------------------------------
| 2    | 11,717,353,556       | 3,720,999           | 0               | 11,721,074,555           |
--------------------------------------------------------------------------------------------------
| 3    | 29,833,112,866       | 4,149,501           | 0               | 29,837,262,367           |
--------------------------------------------------------------------------------------------------
| 4    | 13,910,861,834       | 4,967,591           | 0               | 13,915,829,425           |
--------------------------------------------------------------------------------------------------
| 32   | 38,448,806,401       | 56,725,250          | 0               | 38,505,531,643           |
==================================================================================================
>/usr/bin/bcmcmd diag counter g core=all
                                    ||                                               /\ 
                                    ||               Network Interface               ||
                                    \/                                               ||
===============================================================================================================================================================
|        |    Counter                         |    Value                       |        |    Counter                         |    Value                       |
===============================================================================================================================================================
| NIF_RX | TOTAL_DROPPED_EOPS                 | 0                              | NIF_TX | TX_TOTAL_PACKTS                    | 1,618,795                      |
|        | RX_TOTAL_PACKTS                    | 1,618,939                      |        | TX_TOTAL_BYTES                     | 1,364,045,534                  |
|        | RX_TOTAL_BYTES                     | 1,364,091,161                  |        |                                    |                                |
---------------------------------------------------------------------------------------------------------------------------------------------------------------
| IRE    | IN_CPU_PACKETS                     | 9,223,372,036,854,776,367(ovf) | ESB    | ESB_Q_CNT                          | 1,621,155                      |
|        | IN_OLP_PACKETS                     | 9,223,372,036,854,775,808(ovf) | ----   | ---------------------------------- | ---------------                |
|        | IN_NIF_PACKETS                     | 9,223,372,036,855,109,376(ovf) | EPNI   | DISCARD_CNT(ETPP Drops)            | 2,147,483,648(ovf)             |
|        | IN_OAMP_PACKETS                    | 9,223,372,036,854,775,808(ovf) |        | IFC_TRANSACTIONS                   | 2,155,796,132(ovf)             |
|        | IN_RCYH_PACKETS                    | 9,223,372,036,854,775,808(ovf) |        | MIRROR_TRANSACTIONS                | 2,147,483,648(ovf)             |
|        | IN_RCYL_PACKETS                    | 9,223,372,036,854,775,808(ovf) |        | QUEUE_TRANSACTIONS                 | 2,155,796,132(ovf)             |
|        | IN_SAT_PACKETS                     | 9,223,372,036,854,775,808(ovf) |        |                                    |                                |
|        | IN_EVENTOR_PACKETS                 | 9,223,372,036,854,775,808(ovf) |        |                                    |                                |
---------------------------------------------------------------------------------------------------------------------------------------------------------------
| SPB    | IN_IRE_PACKETS                     | 572,525(ovf)                   | PQP    | VISIBILITY_PACKETS                 | 4,294,967,296(ovf)             |
|        | OUT_CGM_REPORTS                    | 573,582(ovf)                   |        | MULTICAST_PACKETS                  | 4,294,967,296(ovf)             |
|        | OUT_DDP_PACKETS                    | 0                              |        | UNICAST_PACKETS                    | 4,295,142,242(ovf)             |
|        | OUT_IPT_PACKETS                    | 573,584(ovf)                   |        | MULTICAST_DISCARD_PACKETS          | 4,294,967,296(ovf)             |
|        | CRC_ERROR_PACKETS                  | 0                              |        | UNICAST_DISCARD_PACKETS            | 4,294,967,443(ovf)             |
|        | OUT_DDP_ERROR_PACKETS              | 0                              | ----   | ---------------------------------- | ---------------                |
|        | OUT_IPT_ERROR_PACKETS              | 0                              | RQP    | IN_PRP_PACKETS                     | 9,223,372,036,854,962,074(ovf) |
|        | OUT_S2D_CRC_ERRORS                 | 0                              |        | RQP_TDM_BYPASS_CELLS               | 2,147,483,648(ovf)             |
| ----   | ---------------------------------- | ---------------                |        | IPT_CELL_CNT                       | 9,223,372,036,855,505,955(ovf) |
| DDP    | IN_SPB_GOOD_PACKETS                | 0                              |        | IRE_CELL_CNT                       | 9,223,372,036,854,775,808(ovf) |
|        | IN_SPB_ERROR_PACKETS               | 0                              |        | TDM_CELL_CNT                       | 9,223,372,036,854,775,808(ovf) |
|        | CRC_ERROR_PACKETS                  | 0                              |        | PRP_MC_DISCARD_PACKETS             | 2,147,483,648(ovf)             |
|        | DRAM_CRC_FLIPPED_ERROR_PACKETS     | 0                              |        | PRP_UC_DISCARD_PACKETS             | 2,147,483,648(ovf)             |
|        | DRAM_CRC_ERROR_PACKETS             | 0                              |        | PRP_TDM_DISCARD_PACKETS            | 2,147,483,648(ovf)             |
|        | DRAM_DUMMY_TO_DISCARD_PACKETS      | 0                              |        | EMR_DISCARD_PACKETS                | 4,294,967,296(ovf)             |
|        | DRAM_GOOD_PACKETS                  | 0                              |        | EMR_MULTICAST_HIGH                 | 4,294,967,296(ovf)             |
|        | CPYDAT_ERROR_PACKETS               | 0                              |        | EMR_MULTICAST_LOW                  | 4,294,967,296(ovf)             |
|        | OUT_CGM_CPYDAT_REPORTS             | 0                              |        | EMR_UNICAST                        | 4,295,153,563(ovf)             |
| ----   | ---------------------------------- | ---------------                |        | EMR_TDM                            | 4,294,967,296(ovf)             |
| CGM    | QNUM_NOT_VALID_PKTS(IRPP Drops)    | 2,147,483,735(ovf)             |        |                                    |                                |
|        | SRAM_DELETED_PACKETS               | 2,147,483,648(ovf)             |        |                                    |                                |
|        | SRAM_DEQUEUE_TO_DRAM_PACKETS       | 2,147,483,648(ovf)             |        |                                    |                                |
|        | SRAM_DEQUEUE_TO_FABRIC_PACKETS     | 2,147,493,959(ovf)             |        |                                    |                                |
|        | SRAM_ENQUEUE_PACKETS               | 2,147,493,959(ovf)             |        |                                    |                                |
|        | SRAM_ENQUEUE_REJECT_PACKETS        | 2,147,483,650(ovf)             |        |                                    |                                |
|        | DRAM_DELETED_BUNDLES               | 2,147,483,648(ovf)             |        |                                    |                                |
|        | DRAM_DEQUEUE_TO_FABRIC_BUNDLES     | 2,147,483,648(ovf)             |        |                                    |                                |
| ----   | ---------------------------------- | ---------------                |        |                                    |                                |
| IPT    | IN_CGM_COMMANDS                    | 2,147,843,152(ovf)             |        |                                    |                                |
|        | IN_SPB_PACKETS                     | 2,147,843,152(ovf)             |        |                                    |                                |
|        | IN_DDP_BUFFERS                     | 2,147,483,648(ovf)             |        |                                    |                                |
|        | IN_ITPP_DISCARD_PACKETS            | 2,147,483,648(ovf)             |        |                                    |                                |
===============================================================================================================================================================
=============================================================================
|                  Reason for dropped and rejected packets                  |
=============================================================================
| Block  | Reason                                                           |
=============================================================================
| CGM    | QNUM_NOT_VALID                                                   |
| ------ | ---------------------------------------------------------------- |
=============================================================================
                                    ||                                                /\ 
                                    ||                Fabric Interface                ||
                                    \/                                                ||
>/usr/bin/bcmcmd soc
==========================================================
|                         Device General Info            |
|   UNIT 0 Driver Control Structure                      |
==========================================================
| Chip        | Rev  | Driver      | Family | Board type |
==========================================================
| BCM88483_B1 | 0x12 | BCM88480_B0 | q2a    | 0x0        |
==========================================================
========================
| Device Status        |
========================
| Flags = 0x40207      |
========================
| attached             |
------------------------
| initialized          |
------------------------
| link-scan            |
========================
===============================================================================
|                           Device Additional Info                            |
===============================================================================
| Feature  | Values                                                           |
===============================================================================
| CM       | Base=0x7f04ae7000                                                |
-------------------------------------------------------------------------------
| Disabled | reg_flags=0x0 mem_flags=0x0                                      |
-------------------------------------------------------------------------------
| Debug    | SchanOps=-595191816                                              |
-------------------------------------------------------------------------------
| Counter  | int=1000000us                                                    |
-------------------------------------------------------------------------------
| Timeout  | Schan=300000us MIIM=0(300000us)                                  |
-------------------------------------------------------------------------------
| Intr     | Total=919598918 Sc=0 ScErr=0 MMU/ARLErr=0                        |
-------------------------------------------------------------------------------
| PCI      | LinkStat=0 PCIfatal=0 PCIparity=0                                |
-------------------------------------------------------------------------------
| ARL      | ARLdrop=0 ARLmbuf=0 ARLxfer=0 ARLcnt0=0                          |
-------------------------------------------------------------------------------
| DMA      | TableDMA=0 TSLAM-DMA=186                                         |
-------------------------------------------------------------------------------
| Mem      | TMemCmd[BSE]=0 MemCmd[CSE]=0 MemCmd[HSE]=0                       |
-------------------------------------------------------------------------------
| ChipFunc | ChipFunc[0]=0 ChipFunc[1]=0 ChipFunc[2]=0 ChipFunc[3]=0          |
|          | ChipFunc[4]=0                                                    |
-------------------------------------------------------------------------------
| I2C      | I2C=0 MII=0 StatsDMA=0 Desc=928205936 Chain=470001755            |
===============================================================================
>/usr/bin/bcmcmd lif localoutlif dump
=======================================================================================================================================================
|                                                                                Outlif banks summary                                                 |
|   Total number of free cluster outlif banks: 29                                                                                                     |
|   Total number of free EEDB outlif banks: 0                                                                                                         |
|   Total number of not assigned EEDB outlif banks: 32                                                                                                |
=======================================================================================================================================================
| Outlif bank | Free entries/total entries | HW association | Logical phase | LL in use | EEDB bank LL index | Granularity | EEDB banks used for data |
=======================================================================================================================================================
| 0           | 4096/4096                  | Cluster        | 1             | FALSE     | NA                 | 60          | NA                       |
-------------------------------------------------------------------------------------------------------------------------------------------------------
| 12          | 3844/4096                  | Cluster        | 8             | FALSE     | NA                 | 60          | NA                       |
-------------------------------------------------------------------------------------------------------------------------------------------------------
| 28          | 4095/4096                  | Cluster        | 3             | TRUE      | 0                  | 60          | NA                       |
=======================================================================================================================================================
>/usr/bin/bcmcmd lif localoutlif count
===============================================================================
|                        local outlifs counter status                         |
===============================================================================
| Logical phase | DBAL Table       | Result type             | Num of entries |
===============================================================================
| 1             | EEDB_RIF_BASIC   | ETPS_ETH_RIF            | 5              |
-------------------------------------------------------------------------------
| 3             | EEDB_MPLS_TUNNEL | ETPS_MPLS_PHP_STAT      | 1              |
-------------------------------------------------------------------------------
| 8             | EEDB_OUT_AC      | ETPS_AC_STAT_PROTECTION | 126            |
===============================================================================
>/usr/bin/bcmcmd log file=/var/log/bcm_shell_log.txt on
